Fan-out double-sided packaging structure and preparation method of fan-out double-sided packaging structure

Abstract

The embodiment of the present invention provides a fan-out double-sided packaging structure and a preparation method of the fan-out double-sided packaging structure, which relates to the field of semiconductor packaging technology. The fan-out double-sided packaging structure includes a first carrier, a first chip, a first plastic package, a second carrier, a second chip, a second plastic package, a wiring combination layer and a packaging device. The first carrier and the second carrier are bonded to each other, and the first chip is mounted on the first carrier, and the second chip and the packaging device are mounted on the second carrier, thereby realizing a double-sided fan-out packaging structure. At the same time, a first wiring layer is provided in the first carrier, and a second wiring layer is provided in the second carrier. Double-sided packaging is realized by two carriers, thereby greatly improving the wiring density, realizing higher density wiring requirements, and helping to increase the number of chip stacking. At the same time, plastic sealing is realized by two carriers respectively, which can play a better supporting role and can slow down the problem of plastic sealing warping, thereby slowing down the delamination problem.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging technology, and in particular to a fan-out double-sided packaging structure and a method for preparing the fan-out double-sided packaging structure. Background Art

[0002] With the rapid development of the semiconductor industry, fan-out wafer level package (FOWLP) packaging structure is widely used in the semiconductor industry. Generally, a single chip is cut from the wafer and then packaged on a carrier wafer. The main advantages are high-density integration, small package product size, superior product performance, and fast signal transmission frequency. Fan-out technology mainly realizes multi-pin output and small output pin spacing. The traditional fan-out packaging product structure mainly forms a packaging structure on the front and back sides of the same substrate. Since there are multiple packaging materials in the double-sided packaging structure formed on the substrate, and the materials used for different packaging bodies are different, the CTE coefficients between the materials are different. During the reliability test, the product has warping problems, which leads to the problem of easy delamination between the plastic package and the chip surface, and the delamination between the plastic package and the substrate, affecting the quality of the device. At the same time, due to the use of the same substrate for plastic packaging, the wiring density of the substrate is limited, and it is impossible to achieve higher wiring density requirements. Summary of the invention

[0003] The purpose of the present invention includes, for example, providing a fan-out double-sided packaging structure, a preparation method and method of a fan-out double-sided packaging structure, which can alleviate the plastic packaging warping problem and delamination problem, and at the same time can greatly improve the wiring density, improve the chip wiring integration, and thereby increase the number of chip stacking.

[0004] The embodiments of the present invention can be implemented as follows:

[0005] In a first aspect, the present invention provides a fan-out double-sided packaging structure, comprising:

[0006] The first carrier board;

[0007] A first chip mounted on a surface of one side of the first carrier;

[0008] A first plastic package body disposed on the first carrier and covering the first chip;

[0009] A second carrier board attached to the other side surface of the first carrier board;

[0010] A second chip mounted on a surface of one side of the second carrier;

[0011] A second plastic package body disposed on the second carrier board and covering the second chip;

[0012] A wiring assembly layer is arranged on a side of the second plastic package body away from the second carrier board;

[0013] and a packaged device mounted on the other side surface of the second carrier;

[0014] Among them, the first carrier board is provided with a makeshift groove that passes through to the second carrier board, the third chip is arranged in the makeshift groove, the first carrier board is provided with a first wiring layer, the second carrier board is provided with a second wiring layer, the first wiring layer and the second wiring layer are electrically connected, the first chip is electrically connected to the first wiring layer, the second chip is electrically connected to the second wiring layer, and the wiring combination layer is electrically connected to the second wiring layer.

[0015] In an optional embodiment, the packaged device includes a third chip, the third chip is mounted on a surface of the second carrier board on a side away from the second chip, and the third chip is electrically connected to the second wiring layer.

[0016] In an optional embodiment, the fan-out double-sided packaging structure further includes a third plastic package, which is disposed on a surface of the second carrier away from the wiring assembly layer and in the clearance groove, and the third plastic package covers the outside of the third chip.

[0017] In an optional embodiment, a conductive column is further provided in the second plastic package, one end of the conductive column extends to the second carrier board and is electrically connected to the second wiring layer, and the other end of the conductive column extends to the wiring assembly layer and is electrically connected to the wiring assembly layer.

[0018] In an optional embodiment, the first chip is flipped on the first carrier, a first conductive bump is provided on the first chip, a first solder pad is provided on a surface of the first carrier away from the second carrier, the first solder pad is electrically connected to the first wiring layer, and the first conductive bump is bonded to the first solder pad.

[0019] In an optional embodiment, the second chip is flipped on the second carrier, a second conductive bump is provided on the second chip, a second solder pad is provided on a surface of the second carrier away from the first carrier, the second solder pad is electrically connected to the second wiring layer, and the second conductive bump is bonded to the second solder pad.

[0020] In an optional embodiment, the third chip is flipped on the second carrier, a third conductive bump is arranged on the third chip, a third solder pad is arranged on a surface of the second carrier away from the second plastic package body, the third solder pad is electrically connected to the second wiring layer, and the third conductive bump is bonded to the third solder pad.

[0021] In an optional embodiment, the wiring combination layer includes a first dielectric layer, a first metal layer, a second dielectric layer, a second metal layer and a first solder ball, the first dielectric layer covers the surface of the second plastic package, the first metal layer is arranged in the first dielectric layer and is electrically connected to the conductive column, the second dielectric layer covers the surface of the first dielectric layer, the second metal layer is arranged in the second dielectric layer and is electrically connected to the first metal layer, and the first solder ball is arranged on a side of the second dielectric layer away from the second plastic package and is electrically connected to the second metal layer.

[0022] In an optional embodiment, there are multiple second chips, each of which is provided with a second conductive bump, and at least one second chip is mounted on the second carrier so that the corresponding second conductive bump is bonded to the first dielectric layer, a third wiring layer is further provided in the first dielectric layer, a conductive layer is further provided in the second dielectric layer, and a second solder ball is further provided on the second dielectric layer, the third wiring layer is electrically connected to the second conductive bump bonded to the first dielectric layer, the conductive layer is electrically connected to the third wiring layer, the second solder ball is electrically connected to the conductive layer, and the third wiring layer is electrically isolated from the first metal layer so that the third wiring layer is separately wired in the first dielectric layer.

[0023] In an optional embodiment, the packaged device includes a first heat sink, the first heat sink is attached to the second carrier, the first plastic package is wrapped around the first heat sink, and a side of the first heat sink away from the second carrier is exposed to the first plastic package.

[0024] In an optional embodiment, a second heat sink is further provided on the second carrier, the second heat sink is attached to a side surface of the second carrier away from the first carrier, the second plastic package is covered outside the second heat sink, and the second heat sink and the packaged device are correspondingly arranged on both side surfaces of the second carrier.

[0025] In a second aspect, the present invention provides a method for preparing a fan-out double-sided packaging structure, which is used to prepare the fan-out double-sided packaging structure as described in any one of the aforementioned embodiments, and the preparation method comprises:

[0026] Mounting a first chip on a surface of one side of the first carrier board;

[0027] forming a first plastic package covering the first chip on the first carrier;

[0028] Laying a second carrier plate on the other side surface of the first carrier plate;

[0029] Cutting grooves on the first plastic package body and the first carrier board to form a clearance groove and expose the second carrier board;

[0030] Mounting a packaged device in the recess;

[0031] forming a third plastic package body covering the packaged device in the recess;

[0032] Mounting a second chip on the second carrier board;

[0033] forming a second plastic package covering the second chip on the second carrier;

[0034] forming a wiring assembly layer on the second plastic package body;

[0035] Among them, a first wiring layer is arranged in the first carrier board, a second wiring layer is arranged in the second carrier board, the first wiring layer and the second wiring layer are electrically connected, the first chip is electrically connected to the first wiring layer, the second chip is electrically connected to the second wiring layer, and the wiring combination layer is electrically connected to the second wiring layer.

[0036] In a third aspect, the present invention provides a method for preparing a fan-out double-sided packaging structure, which is used to prepare the fan-out double-sided packaging structure as described in any one of the aforementioned embodiments, and the preparation method comprises:

[0037] Laying a second carrier plate on one side surface of the first carrier plate;

[0038] Cutting a groove on the first carrier board to form a clearance groove and expose the second carrier board;

[0039] Mounting a first chip on the first carrier board;

[0040] Mounting a packaged device on the second carrier board in the recess;

[0041] A first plastic package is formed in the first carrier board and the clearance groove to cover the first chip and the packaging device at the same time;

[0042] Mounting a second chip on a side of the second carrier away from the first chip;

[0043] forming a second plastic package covering the second chip on the second carrier;

[0044] forming a wiring assembly layer on a side of the second plastic package body away from the second carrier board;

[0045] A first wiring layer is provided in the first carrier board, a second wiring layer is provided in the second carrier board, the first wiring layer and the second wiring layer are electrically connected, the first chip is electrically connected to the first wiring layer, the second chip is electrically connected to the second wiring layer, and the wiring combination layer is electrically connected to the second wiring layer.

[0046] The beneficial effects of the embodiments of the present invention include, for example:

[0047] The embodiment of the present invention provides a fan-out double-sided packaging structure, wherein a first carrier plate and a second carrier plate are bonded to each other, and a first chip is mounted on the first carrier plate, and a second chip and a packaged device are mounted on the second carrier plate, thereby realizing a double-sided fan-out packaging structure. At the same time, a first wiring layer is provided in the first carrier plate, and a second wiring layer is provided in the second carrier plate. Double-sided packaging is realized by two carrier plates, thereby greatly improving the wiring density, realizing a higher density wiring requirement, and helping to increase the number of chip stacks. At the same time, plastic sealing is realized by two carrier plates respectively, which can play a better supporting role, and can alleviate the problem of plastic sealing warping, thereby alleviating the problem of delamination. Compared with the prior art, the present invention can alleviate the problem of plastic sealing warping and delamination, and at the same time can greatly improve the wiring density, improve the chip wiring integration, and thus increase the number of chip stacks. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0049] Figure 1 A schematic diagram of a fan-out double-sided packaging structure provided by a first embodiment of the present invention;

[0050] Figures 2 to 8 A process flow chart of a method for preparing a fan-out double-sided packaging structure provided by the first embodiment of the present invention;

[0051] Fig. 9 A schematic diagram of a fan-out double-sided packaging structure provided by a second embodiment of the present invention;

[0052] Figures 10 to 18 A process flow chart of a method for preparing a fan-out double-sided packaging structure provided in accordance with a second embodiment of the present invention;

[0053] Fig.19A schematic diagram of a fan-out double-sided packaging structure provided by a third embodiment of the present invention;

[0054] Fig. 20 A schematic diagram of a fan-out double-sided packaging structure provided by a fourth embodiment of the present invention;

[0055] Fig.21 A schematic diagram of a fan-out double-sided packaging structure provided in accordance with a fifth embodiment of the present invention.

[0056] Icon: 100-fan-out double-sided packaging structure; 110-first carrier; 111-first wiring layer; 113-gap groove; 115-first pad; 120-first chip; 121-first plastic package; 123-first conductive bump; 130-second carrier; 131-second wiring layer; 133-second pad; 135-third pad; 140-second chip; 141-second plastic package; 143-conductive column; 145-second conductive bump; 150-wiring combination layer; 151-first dielectric layer; 152-first metal layer; 153-second dielectric layer; 154-second metal layer; 155-first solder ball; 156-third wiring layer; 157-conductive layer; 158-second solder ball; 160-third chip; 161-third conductive bump; 163-third plastic package; 170-first heat sink; 180-second heat sink. DETAILED DESCRIPTION

[0057] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0058] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0059] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0060] In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear to indicate an orientation or position relationship, they are based on the orientation or position relationship shown in the accompanying drawings, or are the orientation or position relationship in which the product of the invention is usually placed when used. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0061] In addition, the terms “first”, “second”, etc., if used, are merely used to distinguish between the descriptions and should not be understood as indicating or implying relative importance.

[0062] As disclosed in the background technology, the existing double-sided packaging structure usually uses the same substrate for double-sided packaging, and the wiring density of a single substrate is limited, and it is impossible to achieve higher density wiring requirements. At the same time, the support of a single substrate is weak. For the case of double-sided plastic packaging, due to the different materials used for different packaging bodies, it is easy to have warping problems, which in turn leads to stratification problems between the plastic packaging body and the chip surface, and between the plastic packaging body and the substrate, affecting the quality of the device. In addition, the existing double-sided packaging structure cannot achieve reverse placement of the chip on the same side, which greatly limits the chip mounting method and the wiring method of the circuit layer, and the wiring flexibility is low.

[0063] In order to solve the above problems, the present invention provides a novel fan-out double-sided packaging structure and a preparation method thereof. It should be noted that the features in the embodiments of the present invention can be combined with each other without conflict.

[0064] First embodiment

[0065] Please refer to Figure 1 This embodiment provides a fan-out double-sided packaging structure 100, which can alleviate the plastic packaging warping problem and delamination problem, and at the same time can greatly improve the wiring density, improve the chip wiring integration, and thus increase the number of chip stacking.

[0066] The fan-out double-sided packaging structure 100 provided in this embodiment includes a first carrier 110, a first chip 120, a first plastic package 121, a second carrier 130, a second chip 140, a second plastic package 141, a wiring assembly layer 150 and a packaging device. The first chip 120 is mounted on a side surface of the first carrier 110, the first plastic package 121 is arranged on the first carrier 110 and covers the first chip 120, the second carrier 130 is attached to the other side surface of the first carrier 110, the second chip 140 is mounted on a side surface of the second carrier 130 away from the first carrier 110, and the packaging device is mounted on the second carrier On the other side surface of the board 130, the second plastic package body 141 covers the second chip 140 and the packaged device, wherein a make way groove 113 penetrating to the second carrier board 130 is provided on the first carrier board 110, and the packaged device is arranged in the make way groove 113. A first wiring layer 111 is provided in the first carrier board 110, and a second wiring layer 131 is provided in the second carrier board 130. The first wiring layer 111 and the second wiring layer 131 are electrically connected, the first chip 120 is electrically connected to the first wiring layer 111, the second chip 140 is electrically connected to the second wiring layer 131, and the wiring combination layer 150 is electrically connected to the second wiring layer 131.

[0067] In this embodiment, the clearance groove 113 extends to the edge of the device, so that the width of the first carrier 110 is smaller than the width of the second carrier 130. Preferably, the width of the first carrier 110 is half the width of the second carrier 130, so that the installation space of the packaged device is the same as the installation space of the first chip 120, which is conducive to uniform mounting.

[0068] In this embodiment, the packaged device includes a third chip 160, which is mounted on a side surface of the second carrier 130 away from the second chip 140, and the third chip 160 is electrically connected to the second wiring layer 131. Specifically, the third chip 160 is spaced apart from the first chip 120, and the third chip 160 is mounted on the second carrier 130 in the clearance groove 113, the first chip 120 is mounted on the first carrier 110, and the first carrier 110 and the second carrier 130 are electrically connected through internal circuits.

[0069] In this embodiment, there are two second chips 140, and the two second chips 140 are spaced apart on a side surface of the second carrier 130 away from the first carrier 110, wherein the widths of the first chip 120, the second chip 140 and the third chip 160 are substantially the same, and the two second chips 140 correspond to the third chip 160 and the first chip 120, respectively, so that the chips are symmetrically arranged on both sides of the carrier, realizing a double-sided fan-out packaging structure.

[0070] In this embodiment, a conductive column 143 is further provided in the second plastic package 141, one end of the conductive column 143 extends to the second carrier 130 and is electrically connected to the second wiring layer 131, and the other end of the conductive column 143 extends to the wiring assembly layer 150 and is electrically connected to the wiring assembly layer 150. Specifically, conductive columns 143 are provided on both sides of each second chip 140, and the conductive columns 143 can be copper columns and penetrate the second plastic package 141, so that the upper wiring assembly layer 150 can be electrically connected to the second wiring layer 131 in the second carrier 130.

[0071] It should be noted that in this embodiment, a plurality of connection pads are disposed on a side of the second carrier 130 away from the first carrier 110 , the connection pads are electrically connected to the second wiring layer 131 , and the conductive pillars 143 are disposed on the connection pads to achieve electrical connection.

[0072] In this embodiment, the first chip 120 is flipped on the first carrier 110, a first conductive bump 123 is provided on the first chip 120, a first pad 115 is provided on a surface of the first carrier 110 away from the second carrier 130, the first pad 115 is electrically connected to the first wiring layer 111, and the first conductive bump 123 is bonded to the first pad 115. Specifically, the first chip 120 is electrically connected through a flip-chip structure, which can further reduce the space required for its installation, and is conducive to miniaturization of the product.

[0073] In this embodiment, the second chip 140 is flip-mounted on the second carrier 130, a second conductive bump 145 is disposed on the second chip 140, a second pad 133 is disposed on a surface of the second carrier 130 away from the first carrier 110, the second pad 133 is electrically connected to the second wiring layer 131, and the second conductive bump 145 is bonded to the second pad 133. Specifically, the plurality of second chips 140 are flip-mounted on the second carrier 130, and the second chips 140 are electrically connected through a flip-mount structure, which can further reduce the space required for their installation, is conducive to the miniaturization of the product, and can also avoid interference between the wire bonding structure and the conductive column 143 to affect their electrical connection characteristics.

[0074] In this embodiment, the third chip 160 is flipped on the second carrier 130, a third conductive bump 161 is provided on the third chip 160, a third pad 135 is provided on the side surface of the second carrier 130 away from the second plastic package 141, the third pad 135 is electrically connected to the second wiring layer 131, and the third conductive bump 161 is bonded to the third pad 135. Specifically, the third chip 160 is flipped on the second carrier 130 in the clearance groove 113, and the electrical connection is achieved through the flip-chip structure, which can further reduce the installation space required, which is conducive to the miniaturization of the product, and also avoids the wire bonding being exposed to the first plastic package 121, which can make the height of the first plastic package 121 lower, which is conducive to the reduction of the height of the device.

[0075] In this embodiment, the wiring combination layer 150 includes a first dielectric layer 151, a first metal layer 152, a second dielectric layer 153, a second metal layer 154 and a first solder ball 155. The first dielectric layer 151 covers the surface of the second plastic package 141, the first metal layer 152 is arranged in the first dielectric layer 151 and is electrically connected to the conductive column 143, the second dielectric layer 153 covers the surface of the first dielectric layer 151, the second metal layer 154 is arranged in the second dielectric layer 153 and is electrically connected to the first metal layer 152, and the first solder ball 155 is arranged on the side of the second dielectric layer 153 away from the second plastic package 141, and is electrically connected to the second metal layer 154. Specifically, after forming the second plastic package 141, a fan-out wiring structure can be completed on the surface of the second plastic package 141, that is, the first dielectric layer 151, the first metal layer 152, the second dielectric layer 153, the second metal layer 154 and the first solder ball 155 are prepared in sequence, thereby realizing a fan-out packaging structure, wherein the basic structure and preparation method of the wiring combination layer 150 are consistent with the conventional fan-out wiring structure. For matters not mentioned in this embodiment, reference can be made to the existing fan-out packaging structure.

[0076] This embodiment also provides a method for preparing a fan-out double-sided packaging structure 100, which is used to prepare the aforementioned fan-out double-sided packaging structure 100, and the preparation method comprises the following steps:

[0077] S1: attaching the second carrier board 130 to one side surface of the first carrier board 110 .

[0078] Specifically, see Figure 2, provide a first carrier board 110 and a second carrier board 130 that have been pre-wired, and attach the first carrier board 110 and the second carrier board 130 together, wherein the first carrier board 110 and the second carrier board 130 are connected by lines, and can be electrically connected by surface pad welding, that is, the first carrier board 110 is provided with a first wiring layer 111, the second carrier board 130 is provided with a second wiring layer 131, and the first wiring layer 111 and the second wiring layer 131 are electrically connected. Preferably, solder paste, adhesive or cu-cu pad high temperature annealing welding can be used to perform welding and bonding between the first carrier board 110 and the second carrier board 130.

[0079] S2: cutting a groove on the first carrier board 110 to form a clearance groove 113 and expose the second carrier board 130 .

[0080] Specifically, see Figure 3 The first carrier board 110 in a preset area can be removed by an etching process or a laser cutting process to complete the grooving and expose the second carrier board 130 .

[0081] S3 : mounting the first chip 120 on the first carrier 110 .

[0082] Specifically, see Figure 4 The first chip 120 can be mounted in a preset area of ​​the first carrier 110. Specifically, the first chip 120 can be flipped on the first carrier 110, and the electrical connection between the first chip 120 and the first wiring layer 111 is achieved through the bonding between the first conductive bump 123 and the first pad 115.

[0083] S4 : mounting the third chip 160 on the second carrier board 130 in the clearance groove 113 .

[0084] Specifically, see Figure 4 Step S3 and step S4 can be performed simultaneously, and the third chip 160 can be flip-chip mounted on the second carrier 130 in the make way groove 113 area, and the electrical connection between the third chip 160 and the second wiring layer 131 can be achieved through the bonding between the third conductive bump 161 and the third pad 135.

[0085] S5: forming a first plastic package 121 in the first carrier board 110 and the recess 113 to cover the first chip 120 and the third chip 160 at the same time.

[0086] Specifically, see Figure 5 After the first chip 120 and the third chip 160 are mounted, a plastic encapsulation process can be performed to form a first plastic encapsulation body 121 on the first carrier 110 and the second carrier 130 in the area of ​​the recess 113 . The first plastic encapsulation body 121 simultaneously covers the first chip 120 and the third chip 160 .

[0087] S6 : Mounting the second chip 140 on a side of the second carrier 130 away from the first chip 120 .

[0088] Specifically, see Figure 6 , the package structure of the first plastic package 121 is turned over, and the second chip 140 is mounted on the second carrier 130. Here, the second chip 140 is flipped on the second carrier 130, and is electrically connected to the second wiring layer 131 through the bonding of the second conductive bump 145 and the second pad 133. At the same time, the second chip 140 needs to correspond to the first chip 120 and the third chip 160 respectively.

[0089] S7 : forming a second plastic package 141 on the second carrier 130 to cover the second chip 140 .

[0090] Specifically, see Figure 7 A second plastic packaging body 141 is formed on the second carrier board 130 by using a plastic packaging process, and the second plastic packaging body 141 covers the second chip 140 .

[0091] S8 : forming a wiring assembly layer 150 on a side of the second plastic package body 141 away from the second carrier 130 .

[0092] Specifically, see Figure 8 After the preparation of the second plastic package 141 is completed, it is first necessary to groove the second plastic package 141 and electroplate a copper layer to form a conductive column 143, which is located on both sides of the second chip 140, and then spin-coat a dielectric material, or deposit a dielectric material, such as by a physical vapor deposition process (PVD) or a chemical vapor deposition process (CVD) to form a first dielectric layer 151, and then pattern the first dielectric layer 151, expose and develop to form a patterned opening, and electroplate a metal material, such as copper, in the opening to form a first metal layer 152 and complete wiring, wherein the first metal layer 152 is connected to the top of the conductive column 143. Then, a dielectric material is deposited again on the surface of the first dielectric layer 151 to form a second dielectric layer 153, and then grooves are made in the second dielectric layer 153, and metal materials, such as copper, are electroplated in the opening grooves to form a second metal layer 154, which serves as a pad structure and is electrically connected to the first metal layer 152. Then, the UBM layer is prepared on the second metal layer 154, and finally, the ball planting process is completed on the second metal layer 154 by steel screen printing or ball planting to form the first solder ball 155. The material of the first solder ball 155 can be SnAg, SnAgCu, etc. The dielectric material can be silicon nitride, silicon oxynitride, polyimide, benzocyclobutene, etc.

[0093] After the preparation of the first solder balls 155 is completed, the cutting process is performed again to form a final product.

[0094] In summary, the fan-out double-sided packaging structure 100 and its preparation method provided in this embodiment are to bond the first carrier 110 and the second carrier 130 to each other, and mount the first chip 120 on the first carrier 110, and mount the second chip 140 and the packaged device on the second carrier 130, thereby realizing a double-sided fan-out packaging structure. At the same time, the first carrier 110 is provided with a first wiring layer 111, and the second carrier 130 is provided with a second wiring layer 131. Double-sided packaging is realized by two carriers, thereby greatly improving the wiring density, realizing higher density wiring requirements, and helping to increase the number of chip stacking. At the same time, plastic sealing is realized by two carriers respectively, which can play a better supporting role, and can alleviate the problem of plastic sealing warping, thereby alleviating the problem of delamination. The fan-out double-sided packaging structure 100 provided in this embodiment can alleviate the problem of plastic sealing warping and delamination, and at the same time can greatly improve the wiring density, improve the chip wiring integration, and thus increase the number of chip stacking.

[0095] Second embodiment

[0096] See also Fig. 9 This embodiment provides a fan-out double-sided packaging structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brief description, for parts not mentioned in this embodiment, reference may be made to the corresponding contents in the first embodiment.

[0097] The fan-out double-sided packaging structure 100 provided in this embodiment includes a first carrier 110, a first chip 120, a first plastic package 121, a second carrier 130, a second chip 140, a second plastic package 141, a third plastic package 163, a wiring assembly layer 150 and a packaging device. The first chip 120 is mounted on a side surface of the first carrier 110, the first plastic package 121 is arranged on the first carrier 110 and covers the first chip 120, the second carrier 130 is attached to the other side surface of the first carrier 110, the second chip 140 is mounted on a side surface of the second carrier 130 away from the first carrier 110, and the packaging device is mounted on On the other side surface of the second carrier 130, the second plastic package 141 covers the second chip 140 and the packaged device, wherein the first carrier 110 is provided with a clearance groove 113 penetrating to the second carrier 130, the third chip 160 is arranged in the clearance groove 113, the first carrier 110 is provided with a first wiring layer 111, the second carrier 130 is provided with a second wiring layer 131, the first wiring layer 111 and the second wiring layer 131 are electrically connected, the first chip 120 is electrically connected to the first wiring layer 111, the second chip 140 is electrically connected to the second wiring layer 131, and the wiring assembly layer 150 is electrically connected to the second wiring layer 131. The third plastic package 163 is arranged on a side surface of the second carrier 130 away from the wiring assembly layer 150, and is located in the clearance groove 113, and the third plastic package 163 covers the third chip 160.

[0098] It should be noted that, in this embodiment, the first plastic packaging body 121 is only located on the first carrier 110 and covers the first chip 120. A third plastic packaging body 163 is arranged on the second carrier 130 in the clearance groove 113. The third plastic packaging body 163 covers the third chip 160. The first plastic packaging body 121 and the third plastic packaging body 163 are formed successively, which can further alleviate the warping problem.

[0099] In this embodiment, a surface of the first plastic package body 121 away from the second carrier 130 is flush with a surface of the third plastic package body 163 away from the second carrier 130, and the side walls of the first plastic package body 121 and the third plastic package body 163 are joined to each other, so that an integral plastic package structure can be formed after molding, which is conducive to the miniaturization of the product.

[0100] This embodiment further provides a method for preparing a fan-out double-sided packaging structure 100, which is used to prepare the fan-out double-sided packaging structure 100 mentioned above in this embodiment, and the method comprises the following steps:

[0101] S1: mounting a first chip 120 on a surface of one side of a first carrier board 110 .

[0102] Specifically, see Fig.10A first carrier board 110 with completed wiring is provided, and a first chip 120 is mounted on the first carrier board 110, wherein the first chip 120 is flipped on the first carrier board 110. A first wiring layer 111 is provided in the first carrier board 110, and the first chip 120 is electrically connected to the first wiring layer 111.

[0103] S2: forming a first plastic package 121 on the first carrier 110 and covering the first chip 120 .

[0104] Specifically, see Fig.11 After the first chip 120 is mounted, a first plastic packaging body 121 is formed on the first carrier 110 by using a plastic packaging process. The first plastic packaging body 121 covers the first chip 120 .

[0105] S3 : attaching the second carrier board 130 to the other side surface of the first carrier board 110 .

[0106] Specifically, see Fig.12 , the second carrier 130 is attached to the surface of the first carrier 110 away from the first plastic package 121, the second carrier 130 is wired in advance, and is provided with a second wiring layer 131, and the first carrier 110 and the second carrier 130 are electrically connected through pad bonding, that is, the first wiring layer 111 and the second wiring layer 131 are electrically connected. Preferably, solder paste, adhesive or cu-cu pad high temperature annealing welding method can be used to perform welding bonding between the first carrier 110 and the second carrier 130.

[0107] S4: Grooving the first plastic package body 121 and the first carrier board to form a clearance groove 113 and expose the second carrier board.

[0108] Specifically, see Fig.13 The first plastic package 121 and the mounting area of ​​the first carrier can be removed by etching or laser cutting to form a clearance groove 113 on the first carrier. At this time, the first plastic package 121 can protect the first chip 120, and the second carrier can serve as a supporting member to play a supporting role.

[0109] S5: mounting the third chip 160 in the recess 113 .

[0110] Specifically, see Fig.14 The third chip 160 is mounted on the surface of the second carrier board 130 in the recess 113 . The third chip 160 is flipped on the second carrier board 130 , and the third chip 160 is electrically connected to the second wiring layer 131 .

[0111] S6: forming a third plastic package body 163 encapsulating the packaged device in the recess 113 .

[0112] Specifically, see Fig.15 After the third chip 160 is mounted, a third plastic encapsulation body 163 is formed in the recess 113 by a plastic encapsulation process, wherein the first plastic encapsulation body 121 and the third plastic encapsulation body 163 jointly cover the surfaces of the first carrier 110 and the second carrier 130. Moreover, since the first plastic encapsulation body 121 and the third plastic encapsulation body 163 are prepared separately, the stress on the first carrier 110 and the second carrier 130 can be further balanced, the warping phenomenon can be reduced, and the delamination problem can be avoided.

[0113] It should be noted that the first plastic packaging body 121 and the third plastic packaging body 163 are prepared separately here, which can solve the stress dispersion problem. At the same time, the first plastic packaging body 121 and the third plastic packaging body 163 can select the same or different plastic packaging materials according to the warping degree of the double-sided packaging structure, so as to balance the warping degree of the entire double-sided packaging structure. For example, if the left side is warped, a plastic packaging material with a small CTE deformation is used to balance it.

[0114] S7 : mounting the second chip 140 on the second carrier 130 .

[0115] Specifically, see Fig.16 After the third plastic package 163 is prepared, the package structure is turned over, and then the second chip 140 is mounted on the surface of the second carrier 130 away from the first carrier 110 , and the second chip 140 is electrically connected to the second wiring layer 131 .

[0116] S8 : forming a second plastic package 141 on the second carrier 130 to cover the second chip 140 .

[0117] Specifically, see Fig.17 After the second chip 140 is mounted, a second plastic package 141 is formed on the second carrier 130 again, and the second plastic package 141 covers the second chip 140 .

[0118] S9 : forming a wiring assembly layer 150 on the second plastic package body 141 .

[0119] Specifically, see Fig.18 After the second plastic package 141 is prepared, a wiring assembly layer 150 is formed on the surface of the second plastic package 141. The wiring assembly layer 150 is electrically connected to the second wiring layer 131. The specific process is the same as that of the first embodiment.

[0120] In summary, the present embodiment provides a fan-out double-sided packaging structure 100 and a preparation method thereof, wherein the first carrier 110 and the second carrier 130 are bonded to each other, and the first chip 120 is mounted on the first carrier 110, and the second chip 140 and the packaged device are mounted on the second carrier 130, thereby realizing a double-sided fan-out packaging structure. At the same time, a first wiring layer 111 is provided in the first carrier 110, and a second wiring layer 131 is provided in the second carrier 130. Double-sided packaging is realized by two carriers, thereby greatly improving the wiring density, realizing higher density wiring requirements, and helping to increase the number of chip stacking. At the same time, plastic sealing is realized by two carriers respectively, which can play a better supporting role, and can alleviate the problem of plastic sealing warping, thereby alleviating the problem of delamination. The present embodiment provides a fan-out double-sided packaging structure 100, which can alleviate the problem of plastic sealing warping and delamination, and at the same time can greatly improve the wiring density, improve the chip wiring integration, and thus increase the number of chip stacking. In addition, since the first plastic package body 121 and the third plastic package body 163 are prepared separately, the stress on the first carrier plate 110 and the second carrier plate 130 can be further balanced, the warping phenomenon is reduced, and the delamination problem is avoided.

[0121] Third embodiment

[0122] See also Fig.19 This embodiment provides a fan-out double-sided packaging structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brief description, for parts not mentioned in this embodiment, reference may be made to the corresponding contents in the first embodiment.

[0123] In this embodiment, there are multiple second chips 140, each of which is provided with a second conductive bump 145. At least one second chip 140 is mounted on the second carrier 130 so that the corresponding second conductive bump 145 is bonded to the first dielectric layer 151. A third wiring layer 156 is further provided in the first dielectric layer 151, a conductive layer 157 is further provided in the second dielectric layer 153, and a second solder ball 158 is further provided on the second dielectric layer 153. The third wiring layer 156 is electrically connected to the second conductive bump 145 bonded to the first dielectric layer 151, the conductive layer 157 is electrically connected to the third wiring layer 156, the second solder ball 158 is electrically connected to the conductive layer 157, and the third wiring layer 156 is electrically isolated from the first metal layer 152 so that the third wiring layer 156 is wired separately in the first dielectric layer 151.

[0124] Specifically, in this embodiment, there are two second chips 140, one of which is mounted upright on the second carrier 130, and the other is mounted inverted on the second carrier 130. The second conductive bump 145 corresponding to the upright second chip 140 is bonded to the first dielectric layer 151, and a separate electrical external connection is achieved through the third wiring layer 156, the conductive layer 157 and the second solder ball 158, which is conducive to rapid positioning when the chip fails during testing.

[0125] In this embodiment, the second chips 140 on the second carrier 130 are placed adjacently and reversely, wherein one of the second chips 140 is flipped and arranged, and its basic connection structure is the same as that of the first embodiment, and the other second chip 140 is arranged upright and electrically connected to the third wiring layer 156 arranged in the first dielectric layer 151 through the second conductive bump 145, and the third wiring layer 156 is electrically isolated from the first metal layer 152, so that the upright second chip 140 is in an electrically isolated state from the common wiring structure, and separate wiring is realized. When the subsequent chip test fails, the position of the second chip 140 in the separate wiring area can be quickly located, and at the same time, the adjacent second chip 140 is placed in reverse, which can improve the diversity of the wiring structure, that is, separate wiring is realized from the top. Specifically, during chip failure analysis, the chip position in the separate wiring area can be quickly located (such as: X-ray failure analysis-chip position reversal, chip back film analysis-reducing the back height of the chip pad surface, chip slicing analysis-position reversal, etc.), solving the problem that the traditional double-sided packaging cannot realize the reverse placement of the chip, and cannot realize the design and analysis of separate chip wiring.

[0126] Fourth embodiment

[0127] See also Fig. 20 This embodiment provides a fan-out double-sided packaging structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brief description, for parts not mentioned in this embodiment, reference may be made to the corresponding contents in the first embodiment.

[0128] In this embodiment, the packaged device includes a first heat sink 170, the first heat sink 170 is attached to the second carrier 130, the first plastic package 121 is wrapped around the first heat sink 170, and the side of the first heat sink 170 away from the second carrier 130 is exposed to the first plastic package 121. Specifically, compared with the first embodiment, the first heat sink 170 is used to replace the position of the third chip 160 in this embodiment.

[0129] In this embodiment, the first heat dissipation block 170 is arranged in the yield groove 113 and is attached to the second carrier 130, and the first heat dissipation block 170 is exposed, which can achieve direct heat dissipation of the back side of the second carrier 130 and can dissipate the heat generated by the second chip 140 on the front side from the bottom, thereby improving the heat dissipation performance.

[0130] It should be noted that the first heat dissipation block 170 here can be a metal block or a ceramic block, etc., or heat dissipation silicone can be used. The heat dissipation silicone can play a buffering role and further solve the warping problem of double-sided packaging products.

[0131] Fifth embodiment

[0132] See also Fig.21 This embodiment provides a fan-out double-sided packaging structure 100, whose basic structure and principle and the technical effects produced are the same as those of the first embodiment or the fourth embodiment. For the sake of brief description, for parts not mentioned in this embodiment, reference may be made to the corresponding contents in the first embodiment or the fourth embodiment.

[0133] In this embodiment, a second heat sink 180 is further provided on the second carrier 130, and the second heat sink 180 is attached to a side surface of the second carrier 130 away from the first carrier 110, and the second plastic package 141 is coated outside the second heat sink 180, and the second heat sink 180 and the packaged device are correspondingly provided on both side surfaces of the second carrier 130. Specifically, compared with the first embodiment, the second chip 140 at the corresponding position of the third chip 160 is replaced by the second heat sink 180 in this embodiment, and the second heat sink 180 is directly in contact with the second carrier 130, which can achieve a good heat dissipation effect.

[0134] In this embodiment, the height of the second heat sink 180 is the same as the height of the second plastic package 141, so that the second heat sink 180 can be directly bonded to the bottom of the wiring assembly layer 150, and the heat on the second carrier 130 is quickly transferred to the wiring assembly layer 150, and then transferred outwardly through the wiring assembly layer 150, thereby improving the heat dissipation between the first solder ball 155 and the assembly substrate.

[0135] It should be noted that, by providing the second heat sink 180, the welding strength of the solder ball area can be improved, which is conducive to firm welding.

[0136] In this embodiment, the second heat sink 180 may be a metal block or a ceramic block, or may be made of heat sink silicone. The heat sink silicone may play a buffering role and further solve the warping problem of the double-sided packaging product.

[0137] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A fan-out double-sided packaging structure, characterized in that: include: The first carrier board; A first chip mounted on a surface of one side of the first carrier; A first plastic package body disposed on the first carrier and covering the first chip; A second carrier board attached to the other side surface of the first carrier board; A second chip mounted on a surface of the second carrier board at a side away from the first carrier board; A second plastic package body disposed on the second carrier board and covering the second chip; A wiring assembly layer is arranged on a side of the second plastic package body away from the second carrier board; and a packaged device mounted on the other side surface of the second carrier; The first carrier board is provided with a recess extending to the second carrier board, the packaged device is arranged in the recess, the first carrier board is provided with a first wiring layer, the second carrier board is provided with a second wiring layer, the first wiring layer and the second wiring layer are electrically connected, the first chip is electrically connected to the first wiring layer, the second chip is electrically connected to the second wiring layer, and the wiring combination layer is electrically connected to the second wiring layer.

2. The fan-out double-sided packaging structure according to claim 1, characterized in that: The packaged device includes a third chip, which is flip-chip mounted on a surface of the second carrier away from the second chip, and is electrically connected to the second wiring layer.

3. The fan-out double-sided packaging structure according to claim 2, characterized in that: The fan-out double-sided packaging structure further includes a third plastic package, which is arranged on a surface of the second carrier away from the wiring assembly layer and located in the clearance groove, and the third plastic package covers the outside of the third chip.

4. The fan-out double-sided packaging structure according to claim 2 or 3, characterized in that: A conductive column is further disposed in the second plastic package, one end of which extends to the second carrier and is electrically connected to the second wiring layer, and the other end of which extends to the wiring assembly layer and is electrically connected to the wiring assembly layer.

5. The fan-out double-sided packaging structure according to claim 4, characterized in that: The first chip is flipped on the first carrier, a first conductive bump is arranged on the first chip, a first pad is arranged on a surface of the first carrier away from the second carrier, the first pad is electrically connected to the first wiring layer, and the first conductive bump is bonded to the first pad.

6. The fan-out double-sided packaging structure according to claim 5, characterized in that: The second chip is flipped on the second carrier, a second conductive bump is arranged on the second chip, a second pad is arranged on a surface of the second carrier away from the first carrier, the second pad is electrically connected to the second wiring layer, and the second conductive bump is bonded to the second pad.

7. The fan-out double-sided packaging structure according to claim 6, characterized in that: The third chip is flipped on the second carrier, a third conductive bump is arranged on the third chip, a third solder pad is arranged on a side surface of the second carrier away from the second plastic package body, the third solder pad is electrically connected to the second wiring layer, and the third conductive bump is bonded to the third solder pad.

8. The fan-out double-sided packaging structure according to claim 4, characterized in that: The wiring combination layer includes a first dielectric layer, a first metal layer, a second dielectric layer, a second metal layer and a first solder ball, the first dielectric layer covers the surface of the second plastic package body, the first metal layer is arranged in the first dielectric layer and is electrically connected to the conductive column, the second dielectric layer covers the surface of the first dielectric layer, the second metal layer is arranged in the second dielectric layer and is electrically connected to the first metal layer, and the first solder ball is arranged on a side of the second dielectric layer away from the second plastic package body and is electrically connected to the second metal layer.

9. The fan-out double-sided packaging structure according to claim 8, characterized in that: There are multiple second chips, each of which is provided with a second conductive bump. At least one second chip is mounted on the second carrier so that the corresponding second conductive bump is bonded to the first dielectric layer. A third wiring layer is also provided in the first dielectric layer, a conductive layer is also provided in the second dielectric layer, and a second solder ball is also provided on the second dielectric layer. The third wiring layer is electrically connected to the second conductive bump bonded to the first dielectric layer, the conductive layer is electrically connected to the third wiring layer, the second solder ball is electrically connected to the conductive layer, and the third wiring layer is electrically isolated from the first metal layer so that the third wiring layer is wired separately in the first dielectric layer.

10. The fan-out double-sided packaging structure according to claim 1, characterized in that: The packaged device comprises a first heat sink block, the first heat sink block is attached to the second carrier board, the first plastic package body is wrapped around the first heat sink block, and a side of the first heat sink block away from the second carrier board is exposed to the first plastic package body.

11. The fan-out double-sided packaging structure according to claim 1 or 10, characterized in that: A second heat sink is also provided on the second carrier, and the second heat sink is attached to a side surface of the second carrier away from the first carrier. The second plastic package is covered outside the second heat sink, and the second heat sink and the packaged device are correspondingly arranged on both side surfaces of the second carrier.

12. A method for preparing a fan-out double-sided packaging structure, used for preparing the fan-out double-sided packaging structure according to any one of claims 1 to 11, characterized in that: The preparation method comprises: Mounting a first chip on a surface of one side of the first carrier board; forming a first plastic package covering the first chip on the first carrier; Laying a second carrier plate on the other side surface of the first carrier plate; Cutting grooves on the first plastic package body and the first carrier board to form a clearance groove and expose the second carrier board; Mounting a packaged device in the recess; forming a third plastic package body covering the packaged device in the recess; Mounting a second chip on the second carrier board; forming a second plastic package covering the second chip on the second carrier; forming a wiring assembly layer on the second plastic package body; Among them, a first wiring layer is arranged in the first carrier board, a second wiring layer is arranged in the second carrier board, the first wiring layer and the second wiring layer are electrically connected, the first chip is electrically connected to the first wiring layer, the second chip is electrically connected to the second wiring layer, and the wiring combination layer is electrically connected to the second wiring layer.

13. A method for preparing a fan-out double-sided packaging structure, used for preparing the fan-out double-sided packaging structure according to any one of claims 1 to 11, characterized in that: The preparation method comprises: Laying a second carrier plate on one side surface of the first carrier plate; Cutting a groove on the first carrier board to form a clearance groove and expose the second carrier board; Mounting a first chip on the first carrier board; Mounting a packaged device on the second carrier board in the recess; A first plastic package is formed in the first carrier board and the clearance groove to cover the first chip and the packaging device at the same time; Mounting a second chip on a side of the second carrier away from the first chip; forming a second plastic package covering the second chip on the second carrier; forming a wiring assembly layer on a side of the second plastic package body away from the second carrier board; A first wiring layer is provided in the first carrier board, a second wiring layer is provided in the second carrier board, the first wiring layer and the second wiring layer are electrically connected, the first chip is electrically connected to the first wiring layer, the second chip is electrically connected to the second wiring layer, and the wiring combination layer is electrically connected to the second wiring layer.

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