Semiconductor structure and method of manufacturing the same

Abstract

The application relates to a semiconductor structure and a preparation method thereof. The preparation method of the semiconductor structure comprises the following steps: providing a substrate; forming a plurality of parallel and spaced grooves in the substrate; forming a word line structure in the grooves, the word line structure being composed of a conductive layer and a dielectric layer covering the bottom surface and the sidewall of the conductive layer, wherein the upper surface of the dielectric layer is lower than the upper surface of the substrate, and the upper surface of the conductive layer is lower than or flush with the upper surface of the dielectric layer; and forming a sealing layer covering the upper surfaces of the conductive layer and the dielectric layer. The preparation method of the semiconductor structure can ensure that the conductive layer will not be exposed to the dielectric layer to cause leakage by setting the upper surface of the conductive layer to be lower than or flush with the upper surface of the dielectric layer; and since the dielectric layer is lower than the substrate surface, the conductive layer and the dielectric layer can be completely sealed in the substrate after the sealing layer is formed, so that the subsequent etching process will not cause damage to the dielectric layer in the word line structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to semiconductor structures and their preparation methods. Background Technology

[0002] In traditional buried word line structures, the gate oxide layer often covers the sidewalls of the word line trench and is flush with the upper surface of the substrate. Subsequent cleaning or wet etching processes can easily damage the gate oxide layer, exposing the conductive layer in the word line structure to air and severely impacting device performance.

[0003] To address these issues, the traditional method involves reducing the height of the gate oxide layer after forming the conductive layer, making its top surface flush with the top surface of the conductive layer. Finally, an isolation layer is formed on top of the word line structure to separate it from the outside. However, this method suffers from low process margins. Reducing the gate oxide layer height makes it difficult to accurately control etching precision, easily leading to over-etching where the gate oxide layer falls below the conductive layer, and the gate oxide layer fails to completely cover the surface of the conductive layer. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor structure and its fabrication method to address the problems of low process margin and inability of the gate oxide layer to completely cover the surface of the conductive layer in traditional methods.

[0005] One embodiment of this application discloses a semiconductor structure, including: a substrate having a plurality of parallel and spaced trenches; a word line structure located in the trenches, the word line structure enclosing a conductive layer and a dielectric layer covering the bottom surface and sidewalls of the conductive layer, wherein the upper surface of the dielectric layer is lower than the upper surface of the substrate, and the upper surface of the conductive layer is lower than or flush with the upper surface of the dielectric layer; and a sealing layer covering the upper surfaces of the conductive layer and the dielectric layer.

[0006] In the above semiconductor structure, the upper surface of the conductive layer is lower than or flush with the upper surface of the dielectric layer, and the dielectric layer can completely separate the conductive layer from the active region in the substrate; the sealing layer covers the upper surfaces of the conductive layer and the dielectric layer, sealing the word line structure inside the substrate and completely isolating it from the outside, ensuring that the dielectric layer will not be damaged in subsequent wet etching or cleaning processes.

[0007] In one embodiment, the conductive layer includes a first conductive layer and a second conductive layer stacked sequentially from bottom to top, wherein the upper surface of the second conductive layer is lower than or flush with the upper surface of the dielectric layer.

[0008] In one embodiment, the first conductive layer includes a metal layer and the second conductive layer includes a polysilicon layer.

[0009] In one embodiment, the sealing layer is located above the trench, the upper surface of the sealing layer is flush with the upper surface of the substrate, and the lower surface of the sealing layer is in direct contact with the upper surfaces of the second conductive layer and the dielectric layer.

[0010] In one embodiment, the width of the sealing layer is equal to the width of the trench.

[0011] In one embodiment, the width of the sealing layer is greater than the width of the trench.

[0012] The aforementioned semiconductor structure, by setting the width of the sealing layer to be greater than the width of the trench, can improve the protective effect of the sealing layer on the word line structure, better protect the word line structure inside the substrate, and prevent the word line structure from being damaged by etching gases or etching liquids in other processes.

[0013] In one embodiment, the dielectric layer comprises a high dielectric constant material layer, and the sealing layer comprises an insulating material layer.

[0014] An embodiment of this application also discloses a method for fabricating a semiconductor structure, comprising: providing a substrate; forming a plurality of parallel and spaced trenches in the substrate; forming a word line structure in the trenches, the word line structure enclosing a conductive layer and a dielectric layer covering the bottom surface and sidewalls of the conductive layer, wherein the upper surface of the dielectric layer is lower than the upper surface of the substrate, and the upper surface of the conductive layer is lower than or flush with the upper surface of the dielectric layer; forming a sealing layer, the sealing layer covering the upper surfaces of the conductive layer and the dielectric layer.

[0015] The above-mentioned semiconductor structure fabrication method ensures that the conductive layer will not be exposed by the dielectric layer and cause leakage by setting the upper surface of the conductive layer to be lower than or flush with the upper surface of the dielectric layer. Furthermore, since the dielectric layer is lower than the substrate surface, the conductive layer and the dielectric layer can be completely sealed in the substrate after the sealing layer is formed, preventing the subsequent etching process from causing damage to the dielectric layer in the word line structure.

[0016] In one embodiment, forming a word line structure in a trench includes: forming a dielectric layer on the sidewalls and bottom of the trench; forming a first conductive layer in the trench, the upper surface of the first conductive layer being lower than the upper surface of the substrate; reducing the height of the dielectric layer and the first conductive layer such that the upper surface of the dielectric layer is lower than the upper surface of the substrate and higher than the upper surface of the first conductive layer; and forming a second conductive layer on the first conductive layer, the upper surface of the second conductive layer being lower than or flush with the upper surface of the dielectric layer.

[0017] The above-mentioned semiconductor structure fabrication method, after reducing the height of the first conductive layer and the dielectric layer, then forming the second conductive layer on the first conductive layer, can control the height of the second conductive layer to make the upper surface of the second conductive layer flush with or lower than the upper surface of the dielectric layer, thereby improving the process margin and eliminating concerns about over-etching.

[0018] In one embodiment, the dielectric layer includes a high dielectric constant material layer, the first conductive layer includes a metal layer, and the second conductive layer includes a polysilicon layer.

[0019] In one embodiment, forming a dielectric layer on the sidewalls and bottom of the trench includes: forming a dielectric material layer covering the upper surface of the substrate and the sidewalls and bottom of the trench; and removing the dielectric material layer from the upper surface of the substrate.

[0020] In one embodiment, forming a first conductive layer in a trench includes: forming a first conductive material layer, the first conductive material layer filling the trench and covering the upper surface of the substrate; removing the first conductive material layer from the upper surface of the substrate and reducing the height of the first conductive material layer in the trench until a portion of the sidewall of the dielectric layer is exposed, thereby obtaining the first conductive layer.

[0021] In one embodiment, reducing the height of the dielectric layer and the first conductive layer includes: reducing the height of the dielectric layer so that the upper surface of the dielectric layer is flush with the upper surface of the first conductive layer; and reducing the height of the first conductive layer so that the upper surface of the first conductive layer is lower than the upper surface of the dielectric layer.

[0022] In the above-mentioned semiconductor structure fabrication method, during the fabrication of the first conductive layer, the dielectric layer is etched and its height is adjusted; after the height of the dielectric layer is determined, the height of the first conductive layer is adjusted and the second conductive layer is fabricated, thereby improving the process margin and avoiding the dielectric layer being over-etched and exposing the conductive layer.

[0023] In one embodiment, forming a second conductive layer on a first conductive layer includes: forming a second conductive material layer that covers a substrate, a dielectric layer, and a first conductive layer and fills a trench; removing the second conductive material layer from the upper surface of the substrate and reducing the height of the second conductive material layer in the trench until a portion of the sidewall of the dielectric layer is exposed, thereby obtaining the second conductive layer.

[0024] In one embodiment, forming a second conductive layer on a first conductive layer includes: forming a second conductive material layer, the second conductive material layer covering a substrate, a dielectric layer and a first conductive layer, and filling a trench; removing the second conductive material layer from the upper surface of the substrate, and reducing the height of the second conductive material layer in the trench until the upper surface of the second conductive material layer is flush with the upper surface of the dielectric layer, thereby obtaining a second conductive layer.

[0025] In one embodiment, forming a sealing layer includes: forming a sealing material layer that covers the substrate, the dielectric layer, and the second conductive layer, and fills the trench; and removing the sealing material layer from the upper surface of the substrate.

[0026] In one embodiment, the sealing material layer includes an insulating material layer.

[0027] The above-mentioned semiconductor structure fabrication method can completely isolate the conductive layer and the dielectric layer from the outside by forming a sealing layer above the dielectric layer and the second conductive layer. This prevents etching liquids or gases in other processes from causing damage to the dielectric layer and exposing the conductive layer, thus affecting the device performance. Attached Figure Description

[0028] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other embodiments can be obtained from these drawings without creative effort.

[0029] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this application;

[0030] Figure 2 This is a schematic cross-sectional view of a semiconductor structure after a dielectric layer and a first conductive material layer are formed in a trench according to an embodiment of this application;

[0031] Figure 3 This is a schematic cross-sectional view of the semiconductor structure after the formation of the first conductive layer in one embodiment of this application;

[0032] Figure 4 This is a schematic cross-sectional view of the semiconductor structure after reducing the height of the dielectric layer in one embodiment of this application;

[0033] Figure 5 This is a schematic cross-sectional view of the semiconductor structure after reducing the height of the first conductive layer in one embodiment of this application;

[0034] Figure 6 This is a schematic cross-sectional view of the semiconductor structure after the formation of the second conductive layer in one embodiment of this application;

[0035] Figure 7 This is a schematic cross-sectional view of the semiconductor structure after the formation of the second conductive layer in another embodiment of this application;

[0036] Figure 8 This is a schematic cross-sectional view of the semiconductor structure after the sealing layer is formed in one embodiment of this application;

[0037] Figure 9 This is a schematic cross-sectional view of the semiconductor structure after the sealing layer is formed in another embodiment of this application;

[0038] Figure 10 This is a schematic cross-sectional view of the semiconductor structure after reducing the height of the dielectric layer in another embodiment of this application;

[0039] Figure 11 This is a schematic cross-sectional view of the semiconductor structure after the sealing layer is formed in another embodiment of this application;

[0040] Figure 12 This is a schematic cross-sectional view of the semiconductor structure after the sealing layer is formed in another embodiment of this application.

[0041] Explanation of icon numbers:

[0042] 10. Substrate; 11. Trench; 20. Word line structure; 21. Conductive layer; 211. First conductive layer; 211'. First conductive material layer; 212. Second conductive layer; 22. Dielectric layer; 30. Sealing layer. Detailed Implementation

[0043] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0045] When describing positional relationships, unless otherwise specified, when an element such as a layer, film, or substrate is referred to as being "on" another film layer, it may be directly on the other film layer or there may be intermediate film layers. Furthermore, when a layer is referred to as being "below" another layer, it may be directly below it or there may be one or more intermediate layers. It is also understood that when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intermediate layers.

[0046] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0047] In traditional buried word line structures, the gate oxide layer typically covers the sidewalls of the word line trench and is flush with the top surface of the substrate. Subsequent cleaning or wet etching processes can easily damage the gate oxide layer, exposing the conductive layer within the word line structure to air and severely impacting device performance. A traditional solution is to form a conductive layer in the word line trench, then reduce the height of the gate oxide layer so that its top surface is below the top surface of the substrate and flush with the top surface of the conductive layer. Finally, an isolation layer is formed on top of the word line structure to completely isolate it from the outside. However, this method suffers from low process margins because accurately controlling the etching precision when reducing the gate oxide layer height can easily lead to over-etching, causing the gate oxide layer to fall below the conductive layer. This results in the gate oxide layer failing to completely cover the sidewalls of the conductive layer, affecting product yield.

[0048] To solve the above problems, such as Figure 1 As shown, one embodiment of this application discloses a method for fabricating a semiconductor structure, comprising:

[0049] S10: Provides a substrate;

[0050] S20: A plurality of parallel-spaced trenches are formed in the substrate;

[0051] S30: A word line structure is formed in the trench, the word line structure includes a conductive layer and a dielectric layer covering the bottom surface and sidewalls of the conductive layer, wherein the upper surface of the dielectric layer is lower than the upper surface of the substrate, and the upper surface of the conductive layer is lower than or flush with the upper surface of the dielectric layer.

[0052] S40: Form a sealing layer that covers the upper surfaces of the conductive layer and the dielectric layer.

[0053] The above-mentioned semiconductor structure fabrication method ensures that the conductive layer will not be exposed by the dielectric layer and cause leakage by setting the upper surface of the conductive layer to be lower than or flush with the upper surface of the dielectric layer. Furthermore, since the dielectric layer is lower than the substrate surface, the conductive layer and the dielectric layer can be completely sealed in the substrate after the sealing layer is formed, preventing the subsequent etching process from causing damage to the dielectric layer in the word line structure.

[0054] Specifically, the substrate provided in step S10 may include, but is not limited to, a silicon substrate or a silicon-on-insulator substrate.

[0055] In step S20, a plurality of parallel-spaced trenches are formed in the substrate. For example, self-aligned double patterning (SADP) or self-aligned quadruple patterning (SAQP) can be used to form the trenches in the substrate as word line trenches. In some embodiments, active regions can also be formed between adjacent word line trenches. The active regions may include a first source / drain region near the substrate surface, a second source / drain region away from the substrate surface, and a channel region located between the first and second source / drain regions.

[0056] In step S30, please refer to Figures 2-7 A word line structure 20 is formed in the trench 11, wherein the word line structure 20 includes a conductive layer 21 and a dielectric layer 22 covering the bottom surface and sidewalls of the conductive layer 21. Specifically, the steps for forming the word line structure 20 include:

[0057] S31: A medium layer 22 is formed on the sidewalls and bottom of the trench 11;

[0058] S32: A first conductive layer 211 is formed in the trench 11, and the upper surface of the first conductive layer 211 is lower than the upper surface of the substrate 10;

[0059] S33: Reduce the height of the dielectric layer 22 and the first conductive layer 211 so that the upper surface of the dielectric layer 22 is lower than the upper surface of the substrate 10 and higher than the upper surface of the first conductive layer 211.

[0060] S34: A second conductive layer 212 is formed on the first conductive layer 211, and the upper surface of the second conductive layer 212 is lower than or flush with the upper surface of the dielectric layer 22.

[0061] For example, in step S31, the step of forming the dielectric layer 22 includes:

[0062] S311: Form a dielectric material layer that covers the upper surface of the substrate 10 and the sidewalls and bottom surface of the trench 11.

[0063] For example, the dielectric layer 22 can be a high dielectric constant material layer, such as a silicon oxide layer or a silicon oxynitride layer. The dielectric material layer can be formed using chemical vapor deposition, atomic layer deposition, plasma vapor deposition, in-situ steam generation (ISSG), or rapid thermal oxidation (RTO) processes, covering the upper surface of the substrate 10 and the sidewalls and bottom surface of the trench 11.

[0064] S312: Remove the dielectric layer 22 material layer from the upper surface of the substrate 10.

[0065] As an example, a chemical mechanical polishing (CMP) process or an etching process can be used to remove the dielectric material layer on the upper surface of the substrate 10, exposing the upper surface of the substrate 10 and forming a dielectric layer 22 covering the sidewalls and bottom surface of the trench 11. The upper surface of the dielectric layer 22 is flush with the upper surface of the substrate 10.

[0066] After forming the dielectric layer 22, a first conductive layer 211 is formed in the trench 11. Step S32, the step of forming the first conductive layer 211 in the trench 11, includes:

[0067] S321: A first conductive material layer 211' is formed, which fills the trench 11 and covers the upper surface of the substrate 10, such as... Figure 2 As shown.

[0068] For example, the first conductive material layer 211' can be a metal layer with low resistivity, such as Ge (germanium), W (tungsten), Cu (copper), or Au (gold). As an example, a deposition process can be used to deposit metal material in the trench 11 to form a metal layer that fills the trench 11 and covers the upper surface of the substrate 10.

[0069] S322: Remove the first conductive material layer 211' from the upper surface of the substrate 10, and lower the height of the first conductive material layer 211' in the trench 11 until part of the sidewall of the dielectric layer 22 is exposed, thus obtaining the first conductive layer 211, as shown. Figure 3 As shown.

[0070] For example, a plasma etching process can be used to etch the first conductive material layer 211' to remove the first conductive material layer 211' on the upper surface of the substrate 10, and appropriately reduce the height of the first conductive material layer 211' in the trench 11, exposing part of the sidewalls of the dielectric layer 22. By forming the first conductive layer 211 and exposing part of the sidewalls at the top of the dielectric layer 22, the purpose is to remove the exposed portion of the dielectric layer 22 in subsequent processes, so that the upper surface of the dielectric layer 22 is lower than the upper surface of the substrate 10.

[0071] S33: Reduce the height of the dielectric layer 22 and the first conductive layer 211, so that the upper surface of the dielectric layer 22 is lower than the upper surface of the substrate 10, but higher than the upper surface of the first conductive layer 211. Specific steps include:

[0072] S331: Reduce the height of the dielectric layer 22 so that the upper surface of the dielectric layer 22 is flush with the upper surface of the first conductive layer 211, such as... Figure 4 As shown.

[0073] For example, an anisotropic plasma etching process can be used to etch the exposed dielectric layer 22 in the horizontal direction, reducing the height of the dielectric layer 22 so that the upper surface of the dielectric layer 22 is flush with the upper surface of the first conductive layer 211. By using anisotropic plasma etching to etch the dielectric layer 22, the etching direction can be mainly concentrated in the horizontal direction, minimizing the etching of the dielectric layer 22 in the vertical direction, so that the dielectric layer 22 is flush with the upper surface of the first conductive layer 211 after etching.

[0074] Alternatively, in some other embodiments, a wet etching process can be used to remove the exposed dielectric layer 22 to reduce its height. In this step, the etching precision of the dielectric layer 22 does not need to be too high; it is sufficient to lower the upper surface of the dielectric layer 22 to near the upper surface of the first conductive layer 211. Even if the dielectric layer 22 is over-etched and falls below the upper surface of the first conductive layer 211, it will not affect the final device quality.

[0075] S332: Reduce the height of the first conductive layer 211 so that the upper surface of the first conductive layer 211 is lower than the upper surface of the dielectric layer 22, such as... Figure 5 As shown.

[0076] For example, plasma etching or wet etching can be used to etch the first conductive layer 211, lowering it to a target height. This target height can be a preset height value for the first conductive layer 211 in the product design. After the first conductive layer 211 is lowered to the target height, its upper surface is lower than the upper surface of the dielectric layer 22. Figure 5 As shown.

[0077] The above-described semiconductor structure fabrication method arranges the etching of the dielectric layer 22 before reducing the height of the first conductive layer 211. Even if over-etching occurs to some extent during the etching of the dielectric layer 22, it will not affect the final product quality. This is because after etching the dielectric layer 22, there is a step to reduce the height of the first dielectric layer 22, thus ensuring that the dielectric layer 22 covers the sidewalls of the first conductive layer 211. Compared to the traditional method of forming the conductive layer and then etching the dielectric layer, this method offers greater process margin.

[0078] In S34, a second conductive layer 212 is formed on the first conductive layer 211, and the upper surface of the second conductive layer 212 is lower than or flush with the upper surface of the dielectric layer 22, such as... Figure 6 or Figure 7 As shown.

[0079] For example, in some embodiments, the step of forming a second conductive layer 212 on the first conductive layer 211 includes:

[0080] S341: A second conductive material layer is formed, which covers the substrate 10, the dielectric layer 22 and the first conductive layer 211, and fills the trench 11.

[0081] For example, the second conductive material layer can be a material layer with better conductivity, such as a polycrystalline silicon layer. Specifically, the second conductive material layer can be deposited on the first conductive layer 211, wherein the second conductive material layer fills the trench 11 and covers the surfaces of the dielectric layer 22, the first conductive layer 211 and the substrate 10.

[0082] S342: Remove the second conductive material layer on the upper surface of the substrate 10 and reduce the height of the second conductive material layer in the trench 11 until part of the sidewall of the dielectric layer 22 is exposed, thus obtaining the second conductive layer 212, as shown. Figure 6 As shown.

[0083] For example, a plasma etching process or a wet etching process can be used to etch back the second conductive material layer until a portion of the sidewall of the dielectric layer 22 is exposed, resulting in the second conductive layer 212. The upper surface of the second conductive layer 212 is lower than the upper surface of the dielectric layer 22.

[0084] Optionally, in some other embodiments, the step of forming a second conductive layer 212 on the first conductive layer 211 includes:

[0085] S341': A second conductive material layer is formed, which covers the substrate 10, the dielectric layer 22 and the first conductive layer 211, and fills the trench 11;

[0086] S342': Remove the second conductive material layer from the upper surface of the substrate 10 and lower the height of the second conductive material layer in the trench 11 until the upper surface of the second conductive material layer is flush with the upper surface of the dielectric layer 22, thus obtaining the second conductive layer 212, as shown. Figure 7 As shown.

[0087] The above-described semiconductor structure fabrication method, after forming the dielectric layer 22, then forms the second conductive layer 212 on top of the first conductive layer 211, which reduces the overall process difficulty and increases the process margin. It can ensure that both the first conductive layer 211 and the second conductive layer 212 are covered by the dielectric layer 22, forming a high-quality word line structure 20.

[0088] In step S40, a sealing layer 30 is formed, which covers the upper surface of the conductive layer and the dielectric layer, such as... Figure 8 or Figure 9 As shown. Specifically, the steps for forming the sealing layer 30 include:

[0089] S41: Form a sealing material layer that covers the substrate 10, the dielectric layer 22, and the second conductive layer 212, and fills the trench 11.

[0090] For example, the sealing material layer includes an insulating material layer, such as a silicon nitride layer. The sealing material layer can be deposited on the surface of the resulting structure using atomic layer deposition or chemical vapor deposition processes to cover the substrate 10, the dielectric layer 22, and the second conductive layer 212, and to fill the trench 11.

[0091] S42: Remove the sealing material layer on the upper surface of the substrate 10 to obtain the sealing layer 30.

[0092] For example, an etching process can be used to etch back the sealing material layer to remove the sealing material layer on the upper surface of the substrate 10, so that the upper surface of the sealing layer 30 is flush with the upper surface of the substrate 10. When the upper surface of the second conductive layer 212 is lower than the upper surface of the dielectric layer 22, a schematic cross-sectional view of the semiconductor structure obtained after forming the sealing layer 30 is shown below. Figure 8 As shown. When the upper surface of the second conductive layer 212 is flush with the upper surface of the dielectric layer 22, the cross-sectional structure of the semiconductor structure obtained after forming the sealing layer 30 is shown in the figure. Figure 9 As shown.

[0093] The semiconductor structure prepared by the above method has a sealing layer 30 that encloses the word line structure 20 inside the substrate 10, so that the top of the dielectric layer 22 is not exposed on the surface of the substrate 10, avoiding damage to the dielectric layer 22 during other processes, and providing good protection for the word line structure 20.

[0094] Optionally, in some embodiments, when reducing the height of the dielectric layer 22 in step S331, the substrate 10 on both sides of the dielectric layer 22 can also be etched to a certain extent to widen the width of the upper part of the trench 11, resulting in... Figure 10 The structure shown.

[0095] For example, the process steps of reducing the height of the first conductive layer 211, forming the second conductive layer 212, and forming the sealing layer 30 can be referred to the relevant descriptions in the foregoing embodiments, and will not be repeated here. The final semiconductor structure is as follows: Figure 11 or Figure 12 As shown.

[0096] In the above-described method for fabricating the semiconductor structure, a wider sealing layer 30 can be obtained by forming a wider opening in the upper part of the trench 11. Since the width of the sealing layer 30 is greater than the width of the trench 11, it ensures that the sealing layer 30 completely covers the upper surface of the dielectric layer 22 and the upper surface of the conductive layer 21 in the trench 11, thereby improving the protective effect of the sealing layer 30 on the word line structure 20.

[0097] like Figure 8 As shown, this application also discloses a semiconductor structure, including: a substrate 10 having a plurality of parallel and spaced trenches 11 therein; a word line structure 20 located in the trenches 11, the word line structure 20 enclosing a conductive layer 21 and a dielectric layer 22 covering the bottom surface and sidewalls of the conductive layer 21, wherein the upper surface of the dielectric layer 22 is lower than the upper surface of the substrate 10, and the upper surface of the conductive layer 21 is lower than or flush with the upper surface of the dielectric layer 22; and a sealing layer 30 covering the upper surfaces of the conductive layer 21 and the dielectric layer 22.

[0098] In the aforementioned semiconductor structure, the upper surface of the conductive layer 21 is lower than or flush with the upper surface of the dielectric layer 22, which ensures that the dielectric layer 22 completely isolates the conductive layer 21 from other conductive structures and prevents leakage. Furthermore, the sealing layer 30 covers the upper surfaces of the conductive layer 21 and the dielectric layer 22, which isolates the dielectric layer 22 from the external environment. During other processes, the dielectric layer 22 will not be damaged, thus providing good protection for the word line structure 20.

[0099] In some embodiments, the conductive layer 21 includes a first conductive layer 211 and a second conductive layer 212 stacked sequentially from bottom to top, wherein the upper surface of the second conductive layer 212 is lower than or flush with the upper surface of the dielectric layer 22.

[0100] For example, the word line structure 20 can be a hybrid gate, and the conductive layer 21 contains two or more conductive materials. For example, such as Figure 8 As shown, the conductive layer 21 includes a first conductive layer 211 and a second conductive layer 212 stacked sequentially from bottom to top. The first conductive layer 211 can be a metal layer, such as Ge (germanium), W (tungsten), Cu (copper), or Au (gold). The second conductive layer 212 can be a polycrystalline silicon layer. The upper surface of the second conductive layer 212 is lower than or flush with the upper surface of the dielectric layer 22. The dielectric layer 22 can be, but is not limited to, a high-dielectric-constant material layer, such as a silicon dioxide layer.

[0101] Optionally, in some embodiments, the conductive layer 21 further includes a metal barrier layer located between the first conductive layer 211 and the second conductive layer 212, separating the first conductive layer 211 and the second conductive layer 212. The metal barrier layer may be, for example, a titanium layer or a titanium nitride layer.

[0102] Optionally, in some other embodiments, the word line structure 20 may be a metal gate. The conductive layer 21 includes a first conductive layer 211 and a metal barrier layer covering the bottom and sidewalls of the first conductive layer 211. The upper surface of the first conductive layer 211 is flush with the upper surface of the metal barrier layer. The metal barrier layer may be, for example, a titanium layer or a titanium nitride layer.

[0103] In some embodiments, please refer to Figure 8The sealing layer 30 is located above the trench 11, and the upper surface of the sealing layer 30 is flush with the upper surface of the substrate 10, while the lower surface of the sealing layer 30 is in direct contact with the upper surfaces of the second conductive layer 212 and the dielectric layer 22. For example, the sealing layer 30 may include, but is not limited to, an insulating material layer, such as a silicon nitride layer, a silicon oxynitride layer, etc.

[0104] In some embodiments, the width of the sealing layer 30 is equal to the width of the groove 11, such as... Figure 8 and Figure 9 As shown.

[0105] In some embodiments, the width of the sealing layer 30 is greater than the width of the groove 11, such as... Figure 11 and Figure 12 As shown. By setting the width of the sealing layer 30 to be greater than the width of the trench 11, the protective effect of the sealing layer 30 on the word line structure 20 can be improved, better protecting the word line structure 20 inside the substrate 10, and preventing the word line structure 20 from being damaged by etching gases or etching liquids in other processes, thus affecting device performance.

[0106] The semiconductor structure in any of the above embodiments can be applied to DRAM devices, which can improve the yield and stability of semiconductor devices.

[0107] This application also discloses a semiconductor device including the semiconductor structure in any of the above embodiments. For example, the semiconductor device further includes transistor elements, capacitor structures, and bit line structures. The semiconductor device may, for example, be a Dynamic Random Access Memory (DRAM) device.

[0108] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0109] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0110] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; Multiple parallel-spaced trenches are formed in the substrate; A word line structure is formed in the trench. The word line structure includes a conductive layer and a dielectric layer covering the bottom surface and sidewalls of the conductive layer. The upper surface of the dielectric layer is lower than the upper surface of the substrate, and the upper surface of the conductive layer is lower than or flush with the upper surface of the dielectric layer. A sealing layer is formed, which covers the upper surfaces of the conductive layer and the dielectric layer; The step of forming a character line structure in the groove includes: A dielectric layer is formed on the sidewalls and bottom of the trench; A first conductive layer is formed in the trench, wherein the upper surface of the first conductive layer is lower than the upper surface of the substrate; The heights of the dielectric layer and the first conductive layer are reduced such that the upper surface of the dielectric layer is lower than the upper surface of the substrate and higher than the upper surface of the first conductive layer. A second conductive layer is formed on the first conductive layer, wherein the upper surface of the second conductive layer is lower than or flush with the upper surface of the dielectric layer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The dielectric layer includes a high dielectric constant material layer, the first conductive layer includes a metal layer, and the second conductive layer includes a polycrystalline silicon layer.

3. The method for preparing a semiconductor structure according to claim 1, characterized in that, The formation of a dielectric layer on the sidewalls and bottom of the trench includes: A dielectric material layer is formed, which covers the upper surface of the substrate and the sidewalls and bottom surface of the trench; Remove the dielectric material layer from the upper surface of the substrate.

4. The method for preparing a semiconductor structure according to claim 1, characterized in that, The formation of the first conductive layer in the trench includes: A first conductive material layer is formed, which fills the trench and covers the upper surface of the substrate; The first conductive material layer on the upper surface of the substrate is removed, and the height of the first conductive material layer in the trench is reduced until a portion of the sidewall of the dielectric layer is exposed, thereby obtaining the first conductive layer.

5. The method for preparing a semiconductor structure according to claim 1, characterized in that, Reducing the height of the dielectric layer and the first conductive layer includes: Reduce the height of the dielectric layer so that the upper surface of the dielectric layer is flush with the upper surface of the first conductive layer; The height of the first conductive layer is reduced so that the upper surface of the first conductive layer is lower than the upper surface of the dielectric layer.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that, The formation of a second conductive layer on the first conductive layer includes: A second conductive material layer is formed, which covers the substrate, the dielectric layer and the first conductive layer, and fills the trench; The second conductive material layer on the upper surface of the substrate is removed, and the height of the second conductive material layer in the trench is reduced until a portion of the sidewall of the dielectric layer is exposed, thereby obtaining the second conductive layer.

7. The method for preparing a semiconductor structure according to claim 1, characterized in that, The formation of a second conductive layer on the first conductive layer includes: A second conductive material layer is formed, which covers the substrate, the dielectric layer and the first conductive layer, and fills the trench; Remove the second conductive material layer from the upper surface of the substrate and reduce the height of the second conductive material layer in the trench until the upper surface of the second conductive material layer is flush with the upper surface of the dielectric layer to obtain the second conductive layer.

8. The method for preparing a semiconductor structure according to claim 1, characterized in that, The formation of the sealing layer includes: A sealing material layer is formed, which covers the substrate, the dielectric layer and the second conductive layer, and fills the trench; Remove the sealing material layer from the upper surface of the substrate.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, The sealing material layer includes an insulating material layer.

10. A semiconductor structure, characterized in that, The semiconductor structure is manufactured by the preparation method according to any one of claims 1-9, and comprises: A substrate having a plurality of parallel, spaced trenches; A word line structure is located in the trench. The word line structure includes a conductive layer and a dielectric layer covering the bottom surface and sidewalls of the conductive layer. The upper surface of the dielectric layer is lower than the upper surface of the substrate, and the upper surface of the conductive layer is lower than or flush with the upper surface of the dielectric layer. A sealing layer that covers the upper surfaces of the conductive layer and the dielectric layer.

11. The semiconductor structure according to claim 10, characterized in that, The conductive layer includes a first conductive layer and a second conductive layer stacked sequentially from bottom to top, wherein the upper surface of the second conductive layer is lower than or flush with the upper surface of the dielectric layer.

12. The semiconductor structure according to claim 11, characterized in that, The first conductive layer includes a metal layer, and the second conductive layer includes a polycrystalline silicon layer.

13. The semiconductor structure according to claim 11, characterized in that, The sealing layer is located above the trench, the upper surface of the sealing layer is flush with the upper surface of the substrate, and the lower surface of the sealing layer is in direct contact with the upper surfaces of the second conductive layer and the dielectric layer.

14. The semiconductor structure according to claim 13, characterized in that, The width of the sealing layer is equal to the width of the groove.

15. The semiconductor structure according to claim 13, characterized in that, The width of the sealing layer is greater than the width of the groove.

16. The semiconductor structure according to any one of claims 10-15, characterized in that, The dielectric layer includes a high dielectric constant material layer, and the sealing layer includes an insulating material layer.

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