Semiconductor device and method of manufacturing semiconductor device

Abstract

This disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes: a gate structure including alternating layers of conductive and insulating layers; and a channel structure extending through the gate structure. Each conductive layer may include a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, and the second portion may include a first metal layer, a second metal layer within the first metal layer, and a first barrier layer interposed between the first and second metal layers.

Description

Technical Field

[0001] This disclosure generally relates to an electronic device, and more specifically, to a semiconductor device and a method of manufacturing the semiconductor device. Background Technology

[0002] The integration density of semiconductor devices is primarily determined by the area occupied by a single memory cell. Recently, as the integration density of semiconductor devices with memory cells formed on a single layer on a substrate has reached its limit, three-dimensional semiconductor devices in which memory cells are stacked on the substrate are being proposed. Furthermore, various structures and manufacturing methods are being developed to improve the operational reliability of semiconductor devices. Summary of the Invention

[0003] According to one embodiment of this disclosure, a semiconductor device may include: a gate structure including alternating layers of conductive and insulating layers; a channel structure passing through the gate structure; and contact plugs, each contact plug being connected to a respective conductive layer. Each conductive layer may include a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, and the second portion may include a first metal layer, a second metal layer within the first metal layer, and a first barrier layer interposed between the first and second metal layers.

[0004] According to one embodiment of this disclosure, a semiconductor device may include: a gate structure including alternating layers of conductive and insulating layers; a channel structure passing through the gate structure; and contact plugs, each contact plug being connected to a respective conductive layer. Each conductive layer may include a first portion having a first thickness and a second portion having a second thickness greater than the first thickness. The first portion may include a first metal layer, and the second portion includes the first metal layer and a first barrier layer in the first metal layer, wherein the first barrier layer is spaced apart from the first portion.

[0005] According to one embodiment of this disclosure, a semiconductor device may include: a gate structure comprising alternating layers of conductive and insulating layers, the conductive layers being stacked in a stepped shape; and a channel structure extending through the gate structure. Each conductive layer may include a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, and the second portion may include a first metal layer, a second metal layer within the first metal layer, and a first barrier layer interposed between the first and second metal layers.

[0006] According to one embodiment of the present disclosure, a method of manufacturing a semiconductor device may include the following steps: forming a laminate comprising alternating layers of sacrificial and insulating layers; forming a slit through the laminate; forming an opening comprising a first portion and a second portion having a thickness greater than that of the first portion by etching the sacrificial layer via the slit; forming a conductive layer in the opening, the conductive layer comprising a first metal layer, a second metal layer within the first metal layer, and a first barrier layer interposed between the first and second metal layers; and forming a contact plug electrically connected to at least one of the first metal layer, the first barrier layer, and the second metal layer in the second portion. Attached Figure Description

[0007] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E and Figure 1F This is a diagram illustrating the structure of a semiconductor device according to one embodiment of the present disclosure.

[0008] Figure 2A , Figure 2B , Figure 2C , Figure 2D and Figure 2E This is a diagram illustrating the structure of a semiconductor device according to one embodiment of the present disclosure.

[0009] Figure 3A , Figure 3B and Figure 3C This is a diagram illustrating the structure of a semiconductor device according to one embodiment of the present disclosure.

[0010] Figure 4A , Figure 4B , Figure 4C , Figure 4D and Figure 4E This is a diagram illustrating the structure of a semiconductor device according to one embodiment of the present disclosure.

[0011] Figure 5A , Figure 5B , Figure 5C , Figure 5D and Figure 5E This is a diagram illustrating the structure of a semiconductor device according to one embodiment of the present disclosure.

[0012] Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A and Figure 10BThis is a diagram illustrating a method for manufacturing a semiconductor device according to one embodiment of the present disclosure.

[0013] Figure 11A , Figure 11B , Figure 12A , Figure 12B , Figure 13A and Figure 13B This is a diagram illustrating a method for manufacturing a semiconductor device according to one embodiment of the present disclosure.

[0014] Figure 14 This is a diagram illustrating a memory system according to one embodiment of the present disclosure.

[0015] Figure 15 This is a diagram illustrating a memory system according to one embodiment of the present disclosure.

[0016] Figure 16 This is a diagram illustrating a memory system according to one embodiment of the present disclosure.

[0017] Figure 17 This is a diagram illustrating a memory system according to one embodiment of the present disclosure.

[0018] Figure 18 This is a diagram illustrating a memory system according to one embodiment of the present disclosure. Detailed Implementation

[0019] The descriptions of specific structures or functions of embodiments based on the concepts disclosed in this specification or application are for the purpose of describing embodiments based on the concepts disclosed herein. Embodiments based on the concepts disclosed herein may be implemented in various forms and should not be construed as limited to the embodiments described in this specification or application.

[0020] The embodiments of this disclosure provide a semiconductor device having a stable structure and improved properties, as well as a method for manufacturing the semiconductor device.

[0021] The integration density of semiconductor devices can be improved by using three-dimensional stacked memory cells. Furthermore, semiconductor devices with stable structures and improved reliability can be provided.

[0022] Figures 1A to 1F This is a diagram illustrating the structure of a semiconductor device according to one embodiment of the present disclosure. Figure 1A It can be a layout diagram. Figure 1B It can be along Figure 1A A cross-sectional view taken from line A-A'. Figure 1C It can be along Figure 1A The cross-sectional view taken by line B-B', and Figure 1E It can be along Figure 1A A cross-sectional view taken from line C-C'. Figure 1D and Figure 1F It could be a 3D view of the conductive layer CP.

[0023] Reference Figures 1A to 1F The semiconductor device may include a gate structure (GST), a channel structure (CH), and a contact plug (CT). Additionally, the semiconductor device may include a slit structure (SLS) or an interlayer insulating layer (21), or a combination of a slit structure (SLS) and an interlayer insulating layer (21).

[0024] The gate structure GST may include alternating layers of conductive layers CP and insulating layer 14. The conductive layers CP may be the gate electrodes of components such as memory cells and selection transistors. The conductive layers CP may include conductive materials such as polysilicon, tungsten, molybdenum, or metals. The insulating layer 14 serves to insulate the stacked conductive layers CP from each other. The insulating layer 14 may include insulating materials such as oxides, nitrides, and gaps. In one embodiment, the gap may be an air gap or a gap comprising gas.

[0025] The gate structure GST may include cell regions CR and contact regions CTR. Memory strings may be arranged in the cell regions CR. The memory strings may include stacked memory cells. Interconnect structures may be arranged in the contact regions CTR. The interconnect structures may include contact plugs and wires for applying a bias to each of the stacked conductive layers CP. The contact regions CTR of the gate structure GST may have a structure that exposes each of the conductive layers CP. As one embodiment, the conductive layers CP may be stacked in a stepped shape, and the contact regions CTR of the gate structure GST may also have a stepped shape.

[0026] Each conductive layer CP may include a first metal layer 11, a second metal layer 12, and a first barrier layer 13. The second metal layer 12 may be disposed within the first metal layer 11. The first metal layer 11 may include a first metal. The second metal layer 12 may include the same second metal as the first metal, or may include a second metal different from the first metal. The first metal layer 11 and the second metal layer 12 may be formed using the same source gas, or may be formed using different source gases. As one embodiment, the second metal layer 12 may be formed using a fluorine-based source gas. The first metal layer 11 may be formed using a source gas other than a fluorine-based source gas. The first metal layer 11 may be formed using a chlorine-based source gas. The etch rate of the second metal layer 12 may be lower than the etch rate of the first metal layer 11. As one embodiment, the first metal layer 11 may include molybdenum (Mo), and the second metal layer 12 may include tungsten (W).

[0027] The first barrier layer 13 can be interposed between the first metal layer 11 and the second metal layer 12. When the first metal layer 11 and the second metal layer 12 comprise different metals, the first barrier layer 13 can prevent or minimize the first metal layer 11 and the second metal layer 12 from reacting with each other. The first barrier layer 13 can prevent or minimize the structural bending of the insulating layer 14. In addition, the first barrier layer 13 can prevent or minimize damage to the peripheral layers during the manufacturing process. As one embodiment, the first barrier layer 13 can prevent or minimize the occurrence of defects caused by source gases or the like used when forming the second metal layer 12. In the process of depositing the second metal layer 12, the extra inflow of source gas into the peripheral layers (e.g., the first metal layer 11, the insulating layer 14, and the memory layer 17, etc.) can be prevented or minimized. As one embodiment, damage to peripheral layers such as the first metal layer 11 caused by residual gas when source gas remains in the second metal layer 12 can be prevented or minimized.

[0028] The first barrier layer 13 may be formed throughout the entire cell region CR, or it may be formed only in a portion of it. As one embodiment, the cell region CR may include a first region R1 adjacent to the slit structure SLS and a second region R2 spaced apart from the slit structure SLS. In the first region R1, the conductive layer CP may include the first barrier layer 13. In the second region R2, the conductive layer CP may or may not include the first barrier layer 13, or it may partially include the first barrier layer 13. In the second region R2, the first barrier layer 13 may not be formed between the channel structures CH, and the spaces between the channel structures CH may be filled only with the first metal layer 11 or may contain voids.

[0029] The first barrier layer 13 may be formed throughout the entire contact area CTR, or it may be formed only in a portion of the contact area (see...). Figure 1E As one implementation, the contact region CTR may include a third region R3 adjacent to the slit structure SLS and a fourth region R4 spaced apart from the slit structure SLS. In the third region R3, the conductive layer CP may include a first barrier layer 13. In the fourth region R4, the conductive layer CP may or may not include the first barrier layer 13, or may partially include the first barrier layer 13.

[0030] The first barrier layer 13 may include an insulating material such as a nitride. As one embodiment, the first barrier layer 13 may include silicon nitride. The first barrier layer 13 may include metal oxides, metal nitrides, or metal oxynitrides, or combinations thereof. Here, the metal included in the first barrier layer 13 may be the same as the first metal or the second metal, or may be a third metal different from the first metal and the second metal. As one embodiment, the first barrier layer 13 may include titanium oxide, titanium nitride, titanium oxynitride, tantalum oxide, tantalum nitride, tantalum oxynitride, molybdenum oxide, molybdenum nitride, molybdenum oxynitride, tungsten oxide, tungsten nitride, or tungsten oxynitride, or combinations thereof.

[0031] For reference, each conductive layer CP may further include a second barrier layer (not shown). Each conductive layer CP may also include voids (not shown). Voids may be arranged between channel structures CH. Voids may be arranged in the first metal layer 11 or the voids may be arranged in the first barrier layer 13.

[0032] The channel structure CH can pass through the cell region CR of the gate structure GST. Memory cells or select transistors can be arranged at the intersection of the channel structure CH and the conductive layer CP. Therefore, memory cells can be stacked. The channel structure CH can be arranged in a first direction I and a second direction II intersecting the first direction I. The channel structure CH can extend in a third direction III. The third direction III can be a direction protruding from the plane defined by the first direction I and the second direction II.

[0033] Each channel structure CH may include a channel layer 18. The channel structure CH may also include a memory layer 17 or an insulating core 19, or a combination thereof. The channel layer 18 may be a region in which a channel forming a memory cell or selection transistor is formed. The channel layer 18 may include a semiconductor material such as silicon or germanium, or a nanostructure. The memory layer 17 may be interposed between the channel layer 18 and the conductive layer CP. As one embodiment, the memory layer 17 may be formed as a sidewall surrounding the channel layer 18. The memory layer 17 may include a tunnel insulating layer, a data storage layer, or a barrier layer, or a combination thereof. The data storage layer may include a floating gate, a charge trapping material, polysilicon, a nitride, a variable resistance material, a phase change material, or a combination thereof. The insulating core 19 may be formed in the channel layer 18. The insulating core 19 may include an insulating material such as oxides, nitrides, and air gaps.

[0034] The contact plug CT can be electrically connected to the conductive layer CP. The contact plug CT can be arranged in the contact area CTR. Each contact plug CT can be connected to a second portion CP_P2 of each conductive layer CP. The contact plug CT can contact at least one of the first metal layer 11, the first barrier layer 13, or the second metal layer 12. As one embodiment, each contact plug CT can pass through the first metal layer 11 and the first barrier layer 13 and can be electrically connected to the second metal layer 12. As one embodiment, each contact plug CT can pass through the second barrier layer 23 (see...). Figure 2B The first metal layer 11 and the first barrier layer 13 are electrically connected to the second metal layer 12. A bias voltage can be applied to the gate electrode of each of the stacked memory cells via a contact plug CT.

[0035] A slit structure SLS can be arranged between gate structures GST. The slit structure SLS can be arranged between adjacent gate structures GST in a second direction II and can extend in a first direction I. As one embodiment, the slit structure SLS may include a source contact structure 16 and insulating spacers 15 surrounding the sidewalls of the source contact structure 16. As one embodiment, the slit structure SLS may consist only of insulating material. The slit structure SLS may not include the source contact structure 16 and may consist only of insulating spacers 15.

[0036] Each conductive layer CP may include a first portion CP_P1 and a second portion CP_P2 having a thickness different from that of the first portion CP_P1. In the third direction III, the thickness of the second portion CP_P2 may be greater than the thickness of the first portion CP_P1. The second portion CP_P2 may be disposed in the contact region CTR. The first portion CP_P1 may be disposed in the cell region CR, extending into the contact region CTR, and may be connected to the second portion CP_P2.

[0037] In each conductive layer CP, the configuration of the first portion CP_P1 and the configuration of the second portion CP_P2 can be different. The conductive layer CP can have a multilayer structure, and the number of layers included in the first portion CP_P1 and the number of layers included in the second portion CP_P2 can be different. The number of layers included in the second portion CP_P2 can be greater than the number of layers included in the first portion CP_P1. The materials included in the first portion CP_P1 and the materials included in the second portion CP_P2 can be different. The second portion CP_P2 can include a material with a relatively low etch rate.

[0038] Each conductive layer CP can have the same structure or different structures in the third region R3 and the fourth region R4. Figure 1C and Figure 1DThis may involve the structure of the third region R3. (See reference...) Figure 1A , Figure 1C and Figure 1D In the third region R3, each conductive layer CP may include a first portion CP_P1 and a second portion CP_P2. In the third region R3, the conductive layer CP may include a first barrier layer 13. As one embodiment, in the third region R3, the first barrier layer 13 may be included in the first portion CP_P1 and the second portion CP_P2 of the conductive layer CP. Therefore, the second portion CP_P2 may include a first metal layer 11, a second metal layer 12, and a first barrier layer 13. As one embodiment, the first portion CP_P1 may include a first metal layer 11 and a first barrier layer 13. The first metal layer 11 of the first portion CP_P1 and the first metal layer 11 of the second portion CP_P2 may be single layers connected to each other. The first barrier layer 13 of the first portion CP_P1 and the first barrier layer 13 of the second portion CP_P2 may be single layers connected to each other. The second metal layer 12 may be spaced apart from the first portion CP_P1. In other words, the first portion CP_P1 may not include the second metal layer 12.

[0039] Figure 1E and Figure 1F It could be the structure of the fourth region, R4. (See reference...) Figure 1A , Figure 1E and Figure 1F In the fourth region R4, each conductive layer CP may include a first portion CP_P1 and a second portion CP_P2. In the fourth region R4, the conductive layer CP may or may not include the first barrier layer 13, or may partially include the first barrier layer 13. As one embodiment, in the fourth region R4, the first portion CP_P1 of the conductive layer CP may not include the first barrier layer 13, and the second portion CP_P2 may include the first barrier layer 13. Therefore, the second portion CP_P2 may include a first metal layer 11, a second metal layer 12, and a first barrier layer 13. The first portion CP_P1 may include the first metal layer 11. The first metal layer 11 of the first portion CP_P1 and the first metal layer 11 of the second portion CP_P2 may be single layers connected to each other. The second metal layer 12 and the first barrier layer 13 may be spaced apart from the first portion CP_P1. In other words, the first portion CP_P1 may not include the second metal layer 12 and the first barrier layer 13.

[0040] According to the structure described above, each conductive layer CP may include a first portion CP_P1 and a second portion CP_P2 with different thicknesses. The conductive layer CP may include a second metal layer 12 only in the second portion CP_P2.

[0041] Figures 2A to 2EThis is a diagram illustrating the structure of a semiconductor device according to one embodiment. Figure 2A It can be a cross-sectional view of a unit region. Figure 2B and Figure 2D It can be a cross-sectional view of the contact area, and Figure 2C and Figure 2E This could be a three-dimensional diagram of the conductive layer CP. Content repeated above will be omitted in the following text.

[0042] Reference Figures 2A to 2E The semiconductor device may include a gate structure GST, a channel structure CH, and a contact plug CT. The gate structure GST may include alternating layers of conductive layer CP and insulating layer 14.

[0043] Each conductive layer CP may include a first metal layer 11, a second metal layer 12, a first barrier layer 13, and a second barrier layer 23. The second metal layer 12 may be disposed within the first metal layer 11. The first metal layer 11 may include a first metal. The second metal layer 12 may include a second metal that is the same as the first metal, or it may include a second metal that is different from the first metal.

[0044] The second barrier layer 23 can be formed around the first metal layer 11. The second barrier layer 23 can be interposed between the first metal layer 11 and the insulating layer 14. The second barrier layer 23 can be interposed between the first metal layer 11 and the memory layer 17. The second barrier layer 23 can be interposed between the first metal layer 11 and the interlayer insulating layer 21. The second barrier layer 23 can include the same material as the first barrier layer 13, or it can include a material different from the material of the first barrier layer 13.

[0045] The second barrier layer 23 may include an insulating material such as a nitride. As one embodiment, the second barrier layer 23 may include silicon nitride. The second barrier layer 23 may include metal oxides, metal nitrides, or metal oxynitrides, or combinations thereof. Here, the metal included in the second barrier layer 23 may be the same as the first metal or the second metal, or it may be a third metal different from the first metal and the second metal. As one embodiment, the second barrier layer 23 may include titanium oxide, titanium nitride, titanium oxynitride, tantalum oxide, tantalum nitride, tantalum oxynitride, molybdenum oxide, molybdenum nitride, molybdenum oxynitride, tungsten oxide, tungsten nitride, or tungsten oxynitride, or combinations thereof.

[0046] Each conductive layer CP may include a first portion CP_P1 and a second portion CP_P2. Each conductive layer CP may include a portion adjacent to the slit structure SLS and a portion spaced apart from the slit structure SLS, and the portion adjacent to the slit structure SLS and the portion spaced apart from the slit structure SLS may have the same structure or may have different structures.

[0047] Figure 2B and Figure 2C This can involve the structure adjacent to the slit structure SLS. (See reference...) Figure 2B and Figure 2C The second part CP_P2 may include a first metal layer 11, a second metal layer 12, a first barrier layer 13, and a second barrier layer 23. The first part CP_P1 may include a first metal layer 11, a first barrier layer 13, and a second barrier layer 23. The second barrier layer 23 of the first part CP_P1 and the second barrier layer 23 of the second part CP_P2 may be single layers connected to each other.

[0048] Figure 2D and Figure 2E This can involve structures separated from the slit structure (SLS). See reference. Figure 2D and Figure 2E The second part CP_P2 may include a first metal layer 11, a second metal layer 12, a first barrier layer 13, and a second barrier layer 23. The first part CP_P1 may include a first metal layer 11 and a second barrier layer 23. The second barrier layer 23 of the first part CP_P1 and the second barrier layer 23 of the second part CP_P2 may be single layers connected to each other.

[0049] According to the structure described above, each conductive layer CP may include a first portion CP_P1 and a second portion CP_P2 with different thicknesses. The conductive layer CP may include a second barrier layer 23 in both the first portion CP_P1 and the second portion CP_P2. The second barrier layer 23 may include the same material as the first barrier layer 13, or it may include a different material than the first barrier layer 13.

[0050] Figures 3A to 3C This is a diagram illustrating the structure of a semiconductor device according to one embodiment of the present disclosure. Figure 3A It can be a cross-sectional view of a unit region. Figure 3B It can be a cross-sectional view of the contact area, and Figure 3C This could be a three-dimensional view of the conductive layer CP. Content repeated above will be omitted in the following text.

[0051] Reference Figure 3A and Figure 3B The semiconductor device may include a gate structure GST, a channel structure CH, and a contact plug CT. The gate structure GST may include alternating layers of conductive layers CP and insulating layers 14. At least one of the conductive layers CP may include a gap V disposed between the channel structures CH.

[0052] Reference Figure 3CEach conductive layer CP may include a first portion CP_P1 and a second portion CP_P2. In one embodiment, the second portion CP_P2 may include a first metal layer 11, a second metal layer 12, and a first barrier layer 13, and the first portion CP_P1 may include the first metal layer 11. The first barrier layer 13 and the second metal layer 12 may be spaced apart from the first portion CP_P1. In other words, the first portion CP_P1 may not include the first barrier layer 13 and the second metal layer 12.

[0053] For reference, each conductive layer CP may further include a second barrier layer 23. The second barrier layer 23 may be formed around the first metal layer 11. As one embodiment, the second portion CP_P2 may include the second barrier layer 23, the first metal layer 11, the second metal layer 12, and the first barrier layer 13, and the first portion CP_P1 may include the second barrier layer 23 and the first metal layer 11.

[0054] According to the structure described above, each conductive layer CP may include a first portion CP_P1 and a second portion CP_P2 with different thicknesses. The conductive layer CP may include only the first barrier layer 13 and the second metal layer 12 in the second portion CP_P2.

[0055] Figures 4A to 4E This is a diagram illustrating the structure of a semiconductor device according to one embodiment of the present disclosure. Figure 4A It can be a cross-sectional view of a unit region. Figure 4B and Figure 4D It can be a cross-sectional view of the contact area, and Figure 4C and Figure 4E This could be a three-dimensional view of the conductive layer CP. Content repeated above will be omitted in the following text.

[0056] Reference Figures 4A to 4E The semiconductor device may include a gate structure GST, a channel structure CH, and a contact plug CT. The gate structure GST may include alternating layers of conductive layers CP and insulating layers 14. At least one of the conductive layers CP may include a gap V disposed between the channel structures CH.

[0057] Each conductive layer CP may include a first portion CP_P1 and a second portion CP_P2. Each conductive layer CP may include a portion adjacent to the slit structure SLS and a portion spaced apart from the slit structure SLS, and the portion adjacent to the slit structure SLS and the portion spaced apart from the slit structure SLS may have the same structure or different structures.

[0058] Figure 4B and Figure 4C This can involve structures separated from the slit structure (SLS). See reference. Figure 4B and Figure 4C The second part CP_P2 may include a first metal layer 11 and a first barrier layer 13, and the first part CP_P1 may include the first metal layer 11. The first barrier layer 13 may be spaced apart from the first part CP_P1. In other words, the first part CP_P1 may not include the first barrier layer 13.

[0059] Figure 4D and Figure 4E This can involve the structure adjacent to the slit structure SLS. (See reference...) Figure 4D and Figure 4E The second part CP_P2 may include a first metal layer 11 and a first barrier layer 13, and the first part CP_P1 may include a first metal layer 11 and a first barrier layer 13.

[0060] According to the structure described above, each conductive layer CP may include a first portion CP_P1 and a second portion CP_P2 with different thicknesses. In the portion of the contact region spaced apart from the slit structure SLS, the conductive layer CP may include the first barrier layer 13 only in the second portion CP_P2.

[0061] Figures 5A to 5E This is a diagram illustrating the structure of a semiconductor device according to one embodiment of the present disclosure. Figure 5A It can be a cross-sectional view of a unit region. Figure 5B and Figure 5D It can be a cross-sectional view of the contact area, and Figure 5C and Figure 5E This could be a three-dimensional view of the conductive layer CP. Content repeated above will be omitted in the following text.

[0062] Reference Figures 5A to 5E The semiconductor device may include a gate structure GST, a channel structure CH, and a contact plug CT. The gate structure GST may include alternating layers of conductive layers CP and insulating layers 14. At least one of the conductive layers CP may include a gap V disposed between the channel structures CH.

[0063] Each conductive layer CP may include a first portion CP_P1 and a second portion CP_P2. Each conductive layer CP may include a portion adjacent to the slit structure SLS and a portion spaced apart from the slit structure SLS, and the portion adjacent to the slit structure SLS and the portion spaced apart from the slit structure SLS may have the same structure or different structures.

[0064] Figure 5B and Figure 5C This can involve structures separated from the slit structure (SLS). See reference. Figure 5B and Figure 5CThe second part CP_P2 may include a first metal layer 11, a first barrier layer 13, and a gap-filling layer 22, and the first part CP_P1 may include the first metal layer 11. The first barrier layer 13 and the gap-filling layer 22 may be spaced apart from the first part CP_P1. In other words, the first part CP_P1 may not include the first barrier layer 13 and the gap-filling layer 22.

[0065] Figure 5D and Figure 5E This can involve the structure adjacent to the slit structure SLS. (See reference...) Figure 5D and Figure 5E The second part CP_P2 may include a first metal layer 11, a first barrier layer 13, and a gap-filling layer 22, and the first part CP_P1 may include the first metal layer 11 and the first barrier layer 13. The gap-filling layer 22 may be spaced apart from the first part CP_P1. In other words, the first part CP_P1 may not include the gap-filling layer 22.

[0066] The gap-filling layer 22 may include a conductor, a semiconductor material, or a dielectric material, or a combination thereof. The conductor may include a conductive material such as a metal or polysilicon. When the conductor includes a metal, it may include the same or a different metal as the metal of the first metal layer 11.

[0067] According to the structure described above, each conductive layer CP may include a first portion CP_P1 and a second portion CP_P2 with different thicknesses. In the portion of the contact region spaced apart from the slit structure SLS, the conductive layer CP may include only the first barrier layer 13 and the gap filling layer 22 in the second portion CP_P2.

[0068] Figures 6A to 10A and Figures 6B to 10B This is a diagram illustrating a method of manufacturing a semiconductor device according to one embodiment of the present disclosure. Each numbered Figure A may be a cross-sectional view of a cell region CR, and each numbered Figure B may be a cross-sectional view of a contact region CTR. Content repeated above will be omitted hereinafter.

[0069] Reference Figure 6A and Figure 6B This forms a stack ST. The stack ST may include alternating layers of sacrificial layer 31 and insulating layer 32. The sacrificial layer 31 may include a material with high etch selectivity relative to the insulating layer 32. As one embodiment, the sacrificial layer 31 may include a nitride and the insulating layer 32 may include an oxide.

[0070] Subsequently, a channel structure CH is formed through the laminate ST. Each channel structure CH may include a channel layer 34. The channel structure CH may also include a memory layer 33 or an insulating core 35, or a combination of a memory layer 33 and an insulating core 35.

[0071] Subsequently, the contact area CTR of the laminate ST is patterned into a stepped shape. In one embodiment, after forming a mask pattern on the laminate ST, an etching process using the mask pattern as an etching barrier and a mask pattern reduction process are alternately repeated. This allows each of the sacrificial layers 31 to be exposed in the contact area CTR. In each sacrificial layer 31, the portion covered by the upper insulating layer 32 can be a first portion 31_P1, and the exposed portion can be a second portion 31_P2.

[0072] Subsequently, the sacrificial layer 31 can be processed such that the thickness T2 of the second portion 31_P2 is thicker than the thickness T1 of the first portion 31_P1. As one embodiment, additional sacrificial material can be deposited on the second portion 31_P2 to selectively increase the thickness of the second portion 31_P2. The thickness T2 of the second portion 31_P2 can be selectively increased by conformally depositing the sacrificial material and then patterning it. Alternatively, the thickness T2 of the second portion 31_P2 can be selectively increased by selectively depositing the sacrificial material.

[0073] Subsequently, an interlayer insulating layer 36 is formed on the laminate ST. The interlayer insulating layer 36 may include an insulating material such as an oxide.

[0074] Reference Figure 7A and Figure 7B A slit SL is formed that passes through the interlayer insulation layer 36 and the laminate ST. The slit SL can be arranged between the channel structure CH. The sacrificial layer 31 can be exposed through the slit SL.

[0075] Subsequently, the sacrificial layer 31 is etched through a slit SL to form an opening OP. Each opening OP may include a first portion OP_P1 and a second portion OP_P2. The thickness T2 of the second portion OP_P2 may be thicker than the thickness T1 of the first portion OP_P1.

[0076] Reference Figure 8A and Figure 8BA first metal layer 37 is formed in the opening OP and the slit SL. The first metal layer 37 may be formed in a first portion OP_P1 and a second portion OP_P2 of each opening OP. Subsequently, a first barrier layer 38 is formed in the opening OP and the slit SL. The first barrier layer 38 may be formed in the first metal layer 37. The first barrier layer 38 may be formed in the first portion OP_P1 and the second portion OP_P2 of each opening OP. The first portion OP_P1 may be completely or substantially filled by the first barrier layer 38. Subsequently, a second metal layer 39 is formed in the opening OP and the slit SL. The second metal layer 39 may be formed in the first barrier layer 38. The second metal layer 39 may be formed in the second portion OP_P2 of each opening OP. The first portion OP_P1 may be filled by the first metal layer 37 and the first barrier layer 38, and the second metal layer 39 may not be formed in the first portion OP_P1.

[0077] Here, the first metal layer 37 may include a first metal. The second metal layer 39 may include the first metal or a second metal different from the first metal. The first metal layer 37 and the second metal layer 39 may be formed using the same source gas or different source gases. As one embodiment, the first metal layer 37 may be formed using a chlorine-based source gas and may include a molybdenum layer. The second metal layer 39 may be formed using a fluorine-based source gas and may include a tungsten layer. Since the second metal layer 39 is formed only in the second portion OP_P2 of the opening OP, even if the source gas remains in the second portion OP_P2, the retention of the fluorine-based source gas in the first portion OP_P1 can be prevented or mitigated. Therefore, damage to the channel structure CH due to the fluorine-based source gas remaining in the conductive layer CP can be prevented or minimized.

[0078] The deposition rate of the first metal layer 37 can be slower than that of the second metal layer 39. Since the first metal layer 37, the first barrier layer 38, and the second metal layer 39 are combined to form the conductive layer CP, the deposition time can be reduced compared to the case where the opening OP is completely or mostly filled by the first metal layer 37.

[0079] The first barrier layer 38 may be formed throughout the entire first portion OP_P1, or it may be formed only in a portion of the first portion OP_P1. As one embodiment, the first barrier layer 38 may not be formed between the channel structures CH. In this case, only the first metal layer 37 may be filled between the channel structures CH, or voids may exist. The first barrier layer 38 can minimize or prevent the inflow or residue of source gas from the second metal layer 39 into or from the first metal layer 37, and damage to peripheral layers such as the first metal layer 37. When only the first metal layer 37 is filled between the channel structures CH, the formation of the first barrier layer 38 can prevent or minimize structural bending of the insulating layer 14. When the first metal layer 37 and the second metal layer 39 comprise different metals, the first barrier layer 38 can prevent reactions between the first metal layer 37 and the second metal layer 39. As one embodiment, the first barrier layer 38 may comprise an insulating material such as a nitride. As one embodiment, the first barrier layer 38 may comprise a metal oxide, a metal nitride, or a metal oxide nitride, or a combination thereof. Here, the metal included in the first barrier layer 38 may be the same as the first metal or the second metal, or it may be a third metal that is different from the first metal and the second metal.

[0080] Reference Figure 9A and Figure 9B A conductive layer CP is formed. The conductive layer CP can be formed by etching portions of the first metal layer 37, the first barrier layer 38, and the second metal layer 39 formed in the slit SL. The etching process can be performed using a wet etching method, a dry etching method, or a combination thereof. Each conductive layer CP may include a first metal layer 37, a second metal layer 39 within the first metal layer 37, and a first barrier layer 38 interposed between the first metal layer 37 and the second metal layer 39. Thus, a gate structure GST comprising alternating layers of conductive layers CP and an insulating layer 32 is formed.

[0081] When the first metal layer 37 and the second metal layer 39 are etched using a wet etching process, the etching rate of the first metal layer 37 can be faster than that of the second metal layer 39. Therefore, abnormal etching of the first metal layer 37 can be prevented or mitigated by forming a second portion CP_P2 via combining the first metal layer 37, the first barrier layer 38, and the second metal layer 39. Abnormally rapid etching of the first metal layer 37 can be prevented or mitigated by forming the first barrier layer 38 within the first metal layer 37.

[0082] For reference, a second barrier layer 40 may be formed before the first metal layer 37 is formed. The second barrier layer 40 may include the same material as the first barrier layer 38, or it may include a different material than the first barrier layer 38. As one embodiment, the second barrier layer 40 may include a metal oxide, a metal nitride, or a metal oxynitride, or a combination thereof. Here, the metal included in the second barrier layer 40 may be the same as the first metal or the second metal, or it may be a third metal different from both the first and second metals.

[0083] Reference Figure 10A and Figure 10B A slit structure SLS is formed in the slit SL. As one embodiment, the slit structure SLS may include a source contact structure 41 and insulating spacers 42 surrounding the sidewalls of the source contact structure 41. As another embodiment, the slit structure SLS may consist only of insulating material. The slit structure SLS may not include the source contact structure 41 and may consist only of insulating spacers 42.

[0084] Subsequently, a contact plug 43 can be formed. The contact plug 43 can be electrically connected to a second portion CP_P2 of the conductive layer CP. The contact plug 43 can be electrically connected to at least one of the first metal layer 37, the first barrier layer 38, or the second metal layer 39. As one embodiment, a contact hole is formed through the interlayer insulating layer 36, the first metal layer 37, and the first barrier layer 38, exposing the second metal layer 39. The contact plug 43 is then formed by filling the contact hole with a conductive layer. Since the etch rate of the second metal layer 39 is lower than that of the first metal layer 37, the second metal layer 39 can be used as an etch stop layer when forming the contact hole.

[0085] According to the manufacturing method described above, conductive layers CP with locally different configurations can be formed. By excluding the second metal layer 39 using a fluorine-based source gas in the first portion CP_P1 adjacent to the channel structure CH, damage to the channel structure CH can be prevented or minimized. In the second portion CP_P2 to which the contact plug 43 is connected, a second metal layer 39 with a lower etch rate than the first metal layer 37 is formed, thus preventing or minimizing defects such as punches when the contact plug 43 is formed.

[0086] Figures 11A to 13A and Figures 11B to 13B This is a diagram illustrating a method of manufacturing a semiconductor device according to one embodiment of the present disclosure. Each numbered Figure A may be a cross-sectional view of a cell region CR, and each numbered Figure B may be a cross-sectional view of a contact region CTR. Content repeated above will be omitted hereinafter.

[0087] Reference Figure 11A and Figure 11B A laminate comprising alternating sacrificial layers and insulating layers 52 is formed. Subsequently, a channel structure CH is formed through the laminate. Each channel structure CH may include a channel layer 54, and may also include a memory layer 53 or an insulating core 55, or may include a combination thereof. An interlayer insulating layer 56 is then formed on the laminate.

[0088] Subsequently, a slit SL is formed through the interlayer insulating layer 56 and the laminate. Then, the sacrificial layer is etched through the slit SL to form an opening OP. Each opening OP may include a first portion OP_P1 and a second portion OP_P2.

[0089] Reference Figure 12A and Figure 12B A first metal layer 57 is formed in the opening OP and the slit SL. The first metal layer 57 may be formed in a first portion OP_P1 and a second portion OP_P2 of each opening OP. The first portion OP_P1 may be completely or substantially filled with the first metal layer 57. Subsequently, a first barrier layer 58 is formed in the opening OP and the slit SL. The first barrier layer 58 may be formed in the first metal layer 57. The first barrier layer 58 may be formed in the second portion OP_P2 of each opening OP. Subsequently, a second metal layer 59 is formed in the opening OP and the slit SL. The second metal layer 59 may be formed in the first barrier layer 58. The second metal layer 59 may be formed in the second portion OP_P2 of each opening OP. The first portion OP_P1 may be filled with the first metal layer 57, and the first barrier layer 58 and the second metal layer 59 may not be formed in the first portion OP_P1.

[0090] Reference Figure 13A and Figure 13B A conductive layer CP is formed. The conductive layer CP can be formed by etching portions of the first metal layer 57, the first barrier layer 58, and the second metal layer 59 formed in the slit SL. Each conductive layer CP may include a first metal layer 57, a second metal layer 59 within the first metal layer 57, and a first barrier layer 58 interposed between the first metal layer 57 and the second metal layer 59. Thus, a gate structure GST comprising alternating layers of conductive layers CP and an insulating layer 52 is formed.

[0091] For reference, the above process can be partially modified. In one embodiment, the second portion OP_P2 can be filled by the first barrier layer 58, and the process of forming the second metal layer 59 can be omitted. In this case, each conductive layer CP can include a first metal layer 57 and a first barrier layer 58 within the first metal layer 57. In another embodiment, the second portion OP_P2 can be partially filled by the first barrier layer 58, and a gap-filling layer instead of the second metal layer 59 can be formed in the first barrier layer 58. In this case, each conductive layer CP can include a first metal layer 57, a gap-filling layer within the first metal layer 57, and a first barrier layer 58 interposed between the first metal layer 57 and the gap-filling layer.

[0092] Subsequently, additional processes can be performed to form the slit structure and contact plugs, etc.

[0093] According to the manufacturing method described above, conductive layers CP with locally different configurations can be formed. By excluding the second metal layer 59 using a fluorine-based source gas in the first portion CP_P1 adjacent to the channel structure CH, damage to the channel structure CH can be prevented or minimized. In the second portion CP_P2 to which the contact plug is connected, a second metal layer 59 with a lower etch rate than the first metal layer 57 is formed, and therefore, when the contact plug 43 is formed, the occurrence of defects such as perforations can be prevented or minimized.

[0094] Figure 14 This is a diagram illustrating a memory system according to one embodiment of the present disclosure.

[0095] Reference Figure 14 The memory system 1000 may include a memory device 1200 storing data and a controller 1100 communicating between the memory device 1200 and the host 2000.

[0096] The host 2000 can be a device or system that stores data in or retrieves data from the memory system 1000. The host 2000 can generate requests for various operations and can output these requests to the memory system 1000. Requests may include programming requests for programming operations, read requests for read operations, and erase requests for erase operations. The host 2000 can communicate with the memory system 1000 through various interfaces such as Peripheral Component Interconnect Express PCIe, Advanced Technology Connectivity (ATA), Serial ATA (SATA), Parallel ATA (PATA), Serial Attached SCSI (SAS), Non-Volatile Memory Express (NVMe), Universal Serial Bus (USB), Multimedia Card (MMC), Enhanced Small Digital Disk Interface (ESDI), or Integrated Drive Electronics (IDE).

[0097] The host 2000 may include at least one of a computer, portable digital device, tablet computer, digital camera, digital audio player, television, wireless communication device or cellular phone, but the embodiments disclosed herein are not limited thereto.

[0098] The controller 1100 can provide overall control over the operation of the memory system 1000. The controller 1100 can control the memory device 1200 according to requests from the host 2000. The controller 1100 can control the memory device 1200 to perform programming, reading, and erasing operations, etc., according to requests from the host 2000. Alternatively, even without requests from the host 2000, the controller 1100 can perform background operations to improve the performance of the memory system 1000.

[0099] The controller 1100 can send control signals and data signals to the memory device 1200 to control the operation of the memory device 1200. The control signals and data signals can be sent to the memory device 1200 through different input / output lines. Data signals can include commands, addresses, or data. Control signals can be used to divide the input data signals into intervals.

[0100] The memory device 1200 can perform programming, reading, and erasing operations under the control of the controller 1100. The memory device 1200 can be implemented using a volatile memory device whose stored data is destroyed when power is off, or a non-volatile memory device that retains the stored data even when power is off. The memory device 1200 can be implemented using the above-mentioned references. Figures 1A to 5E The semiconductor device described herein. The memory device 1200 can be configured as described above. Figures 6A to 13B A semiconductor device manufactured using the described manufacturing method. As one embodiment, the semiconductor memory device may include a gate structure comprising alternating layers of conductive and insulating layers, a channel structure through the gate structure, and contact plugs respectively connected to the respective conductive layers. Each conductive layer may include a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, and the second portion may include a first metal layer, a second metal layer within the first metal layer, and a first barrier layer interposed between the first and second metal layers.

[0101] Figure 15 This is a diagram illustrating a memory system according to one embodiment of the present disclosure.

[0102] Reference Figure 15The memory system 30000 can be implemented as a cellular phone, smartphone, tablet computer, personal computer (PC), personal digital assistant (PDA), or wireless communication device. The memory system 30000 may include a memory device 2200 and a controller 2100 capable of controlling the operation of the memory device 2200.

[0103] The controller 2100 can control data access operations of the memory device 2200, such as programming operations, erasing operations, or reading operations, under the control of the processor 3100.

[0104] Data programmed into the memory device 2200 can be output via the display 3200 under the control of the controller 2100.

[0105] The radio transceiver 3300 can transmit and receive radio signals via the antenna ANT. For example, the radio transceiver 3300 can convert the radio signals received via the antenna ANT into signals that can be processed by the processor 3100. Therefore, the processor 3100 can process the signals output from the radio transceiver 3300 and send the processed signals to the controller 2100 or the display 3200. The controller 2100 can send the signals processed by the processor 3100 to the memory device 2200. Alternatively, the radio transceiver 3300 can convert the signals output from the processor 3100 into radio signals and output the converted radio signals to an external device via the antenna ANT. The input device 3400 can be a device capable of inputting control signals for controlling the operation of the processor 3100 or data to be processed by the processor 3100. The input device 3400 can be implemented as a pointing device such as a touchpad or computer mouse, a keypad, or a keyboard. The processor 3100 can control the operation of the display 3200, so that data output from the controller 2100, data output from the radio transceiver 3300, or data output from the input device 3400 is output through the display 3200.

[0106] According to one embodiment, the controller 2100, which is capable of controlling the operation of the memory device 2200, may be implemented as part of the processor 3100 or may be implemented as a chip separate from the processor 3100.

[0107] Figure 16 This is a diagram illustrating a memory system according to one embodiment of the present disclosure.

[0108] Reference Figure 16 The 40000 memory system can be implemented as a personal computer (PC), tablet computer, netbook, e-reader, personal digital assistant (PDA), portable multimedia player (PMP), MP3 player or MP4 player.

[0109] The memory system 40000 may include a memory device 2200 and a controller 2100 capable of controlling the data processing operations of the memory device 2200.

[0110] The processor 4100 can output data stored in the memory device 2200 via the display 4300 based on data input through the input device 4200. For example, the input device 4200 can be implemented as a pointing device such as a touchpad or computer mouse, a keypad, or a keyboard.

[0111] The processor 4100 can control the overall operation of the memory system 40000 and control the operation of the controller 2100. According to one embodiment, the controller 2100, which is capable of controlling the operation of the memory device 2200, can be implemented as part of the processor 4100 or as a chip separate from the processor 4100.

[0112] Figure 17 This is a diagram illustrating a memory system according to one embodiment of the present disclosure.

[0113] Reference Figure 17 The memory system 50000 can be implemented as an image processing device, such as a digital camera, a mobile phone equipped with a digital camera, a smartphone equipped with a digital camera, or a tablet computer equipped with a digital camera.

[0114] The memory system 50000 includes a memory device 2200 and a controller 2100 capable of controlling data processing operations (e.g., programming operations, erasing operations, or reading operations) of the memory device 2200.

[0115] The image sensor 5200 of the memory system 50000 can convert optical images into digital signals. The converted digital signals can be sent to the processor 5100 or the controller 2100. Under the control of the processor 5100, the converted digital signals can be output through the display 5300 or stored in the memory device 2200 through the controller 2100. Furthermore, data stored in the memory device 2200 can be output through the display 5300 under the control of the processor 5100 or the controller 2100.

[0116] According to one embodiment, the controller 2100, which is capable of controlling the operation of the memory device 2200, may be implemented as part of the processor 5100, or may be implemented as a chip separate from the processor 5100.

[0117] Figure 18 This is a diagram illustrating a memory system according to one embodiment of the present disclosure.

[0118] Reference Figure 18The memory system 70000 can be implemented as a memory card or a smart card. The memory system 70000 may include a memory device 2200, a controller 2100, and a card interface 7100.

[0119] The controller 2100 can control the data exchange between the memory device 2200 and the card interface 7100. According to one embodiment, the card interface 7100 may be a Secure Digital (SD) card interface or a Multimedia Card (MMC) interface, but is not limited thereto.

[0120] Card interface 7100 can interface for data exchange between host 60000 and controller 2100 according to the protocol of host 60000. According to one embodiment, card interface 7100 can support Universal Serial Bus (USB) protocol and IC-USB protocol. Here, card interface 7100 can refer to hardware capable of supporting the protocol used by host 60000, software installed in the hardware, or signal transmission method.

[0121] When the memory system 70000 is connected to the host interface 6200 of a host 60000 such as a PC, tablet computer, digital camera, digital audio player, mobile phone, console video game hardware or digital set-top box, the host interface 6200 can perform data communication with the memory device 2200 through the card interface 7100 and the controller 2100 under the control of the microprocessor 6100.

[0122] Cross-references to related applications

[0123] This application claims priority to Korean Patent Application No. 10-2021-0001543, filed with the Korean Intellectual Property Office on January 6, 2021, the entire disclosure of which is incorporated herein by reference.

Claims

1. A semiconductor device, the semiconductor device comprising: A gate structure comprising alternating layers of conductive and insulating layers; A channel structure that extends through the gate structure; as well as Contact plugs, each of which is connected to the conductive layer. Each of the conductive layers includes a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, and The second part includes a first metal layer, a second metal layer in the first metal layer, and a first barrier layer inserted between the first metal layer and the second metal layer, wherein the second metal layer is formed only in the second part.

2. The semiconductor device according to claim 1, wherein The first metal layer comprises molybdenum, and the second metal layer comprises tungsten.

3. The semiconductor device according to claim 1, wherein The first barrier layer prevents the reaction between the first metal layer and the second metal layer.

4. The semiconductor device according to claim 1, wherein The second metal layer comprises a material having an etch rate lower than that of the first metal layer.

5. The semiconductor device according to claim 1, wherein, The first metal layer and the second metal layer comprise tungsten.

6. The semiconductor device according to claim 1, wherein, Each of the contact plugs is electrically connected to at least one of the first metal layer, the first barrier layer, and the second metal layer.

7. The semiconductor device according to claim 1, wherein, The first portion includes the first metal layer, and the first barrier layer and the second metal layer are spaced apart from the first portion.

8. The semiconductor device according to claim 1, wherein, The first portion includes the first metal layer and the first barrier layer, and the second metal layer is spaced apart from the first portion.

9. The semiconductor device according to claim 1, further comprising: A second barrier layer surrounds the first metal layer.

10. The semiconductor device according to claim 9, wherein, The second barrier layer includes an oxide, nitride, or oxynitride of the first metal included in the first metal layer, the second metal included in the second metal layer, or a third metal different from the first metal and the second metal.

11. The semiconductor device according to claim 9, wherein, Each of the contact plugs is electrically connected to at least one of the second barrier layer, the first metal layer, the first barrier layer, and the second metal layer.

12. The semiconductor device according to claim 1, wherein, The conductive layers are stacked in a stepped shape.

13. A semiconductor device comprising: A gate structure comprising alternating layers of conductive and insulating layers; A channel structure that extends through the gate structure; as well as Contact plugs, each of which is connected to the conductive layer. Each of the conductive layers includes a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, and The first part includes a first metal layer, and the second part includes the first metal layer, a gap-filling layer in the first metal layer, and a first barrier layer inserted between the first metal layer and the gap-filling layer, wherein the first barrier layer is spaced apart from the first part.

14. The semiconductor device according to claim 13, wherein, The gap filling layer is spaced apart from the first portion.

15. The semiconductor device according to claim 14, wherein, The gap-filling layer comprises a conductor, a semiconductor material, or a dielectric material, or a combination of the conductor, the semiconductor material, and the dielectric material.

16. The semiconductor device according to claim 14, wherein, Each of the contact plugs is electrically connected to at least one of the first metal layer, the first barrier layer, and the gap-filling layer.

17. The semiconductor device according to claim 13, wherein, Each of the contact plugs is electrically connected to the first metal layer or the first barrier layer.

18. The semiconductor device of claim 13, further comprising: A second barrier layer surrounds the first metal layer.

19. The semiconductor device according to claim 18, wherein, The second barrier layer includes an oxide, nitride, or oxynitride of the first metal included in the first metal layer or a metal different from the first metal.

20. The semiconductor device according to claim 18, wherein, Each of the contact plugs is electrically connected to at least one of the second barrier layer, the first metal layer, and the first barrier layer.

21. The semiconductor device according to claim 13, wherein, The conductive layers are stacked in a stepped shape.

22. A semiconductor device comprising: A gate structure comprising alternating layers of conductive and insulating layers, wherein the conductive layers are stacked in a stepped shape; as well as A channel structure that extends through the gate structure. Each of the conductive layers includes a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, and The second part includes a first metal layer, a second metal layer in the first metal layer, and a first barrier layer inserted between the first metal layer and the second metal layer, wherein the second metal layer is formed only in the second part.

23. The semiconductor device according to claim 22, wherein, The first portion includes the first metal layer, and the first barrier layer and the second metal layer are spaced apart from the first portion.

24. The semiconductor device of claim 22, further comprising: A second barrier layer surrounds the first metal layer.

25. A method for manufacturing a semiconductor device, the method comprising the following steps: Forming a laminate comprising alternating layers of sacrificial and insulating layers; Forming a slit through the stacked material; An opening is formed by etching the sacrificial layer via the slit, the opening comprising a first portion and a second portion having a thickness greater than that of the first portion; A conductive layer is formed in the opening, the conductive layer comprising a first metal layer, a second metal layer in the first metal layer, and a first barrier layer interposed between the first metal layer and the second metal layer, wherein the second metal layer is formed only in the second portion; as well as A contact plug is formed that is electrically connected to at least one of the first metal layer, the first barrier layer, and the second metal layer in the second portion.

26. The method of claim 25, wherein, The step of forming the conductive layer includes the following steps: The first metal layer is formed in the first portion and the second portion of each of the openings; The first barrier layer is formed in the first portion and the second portion of each of the openings; and The second metal layer is formed in the second portion of each of the openings.

27. The method according to claim 25, wherein, The step of forming the conductive layer includes the following steps: The first metal layer is formed in the first portion and the second portion of each of the openings; The first barrier layer is formed in the second portion of each of the openings; and The second metal layer is formed in the second portion of each of the openings.

28. The method according to claim 27, wherein, When the second metal layer is formed, the first metal layer is protected by the first barrier layer.

29. The method according to claim 25, wherein, The second metal layer is spaced apart from the first portion.

30. The method according to claim 25, wherein, The second metal layer and the first barrier layer are spaced apart from the first portion.

31. The method according to claim 25, wherein, The step of forming the conductive layer includes the following steps: forming the first metal layer using a chlorine-based source gas and forming the second metal layer using a fluorine-based source gas.

32. The method according to claim 25, wherein, The first metal layer comprises molybdenum, and the second metal layer comprises tungsten.

33. The method according to claim 25, wherein, The first barrier layer prevents the reaction between the first metal layer and the second metal layer.

34. The method according to claim 25, wherein, The second metal layer comprises a material having an etch rate lower than that of the first metal layer.

35. The method according to claim 25, wherein, When the contact plug is formed, the second metal layer serves as an etch stop layer.

36. The method according to claim 25, wherein, The metal of the first metal layer is different from the metal of the second metal layer.

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