A multilayer passivated grooved gate MIS-HEMT device and its fabrication method

Abstract

This invention discloses a multilayer passivated grooved gate MIS-HEMT device and its fabrication method. The device comprises, from bottom to top, a substrate, a nucleation layer, a buffer layer, a channel layer, and a barrier layer. A source and a drain are respectively located on the left and right sides of the barrier layer. A grooved gate region is located in the middle of the barrier layer near the source, and multiple passivation layers are disposed on the grooved gate region. The multiple passivation layers include a first passivation layer, a transition layer, a mask layer, and a second passivation layer. The first passivation layer is selectively grown at the bottom of the grooved gate region of the barrier layer and contacts the upper surface of the channel layer. The transition layer is located on the upper surface of the first passivation layer. The mask layer is located on the barrier layers on both sides of the grooved gate region. The second passivation layer is located on the transition layer and extends upward to the upper surface of the mask layer. This invention combines a multilayer passivation structure with selective growth technology to achieve effective and precisely controllable deposition of the passivation layer in the gate region, improving the dielectric interface defect problem and enhancing device performance.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a multilayer passivated groove gate MIS-HEMT device and its fabrication method. Background Technology

[0002] High electron mobility transistors (HEMTs), also known as modulation-doped field-effect transistors (MODFETs), are a type of field-effect transistor that uses two materials with different band gaps to form a heterojunction, providing a channel for charge carriers. HEMTs can operate at extremely high frequencies, making them widely used in mobile phones, satellite television, and radar. In recent years, with the increasing demand for high-efficiency, high-frequency, high-voltage, and high-power devices due to energy conservation and emission reduction efforts, third-generation semiconductor materials have attracted increasing attention. Third-generation semiconductors, represented by GaN HEMT devices, have gained widespread attention due to their advantages such as large band gaps, high carrier mobility, and excellent voltage withstand performance.

[0003] Traditional AlGaN / GaN HEMT devices, with their epitaxial growth along the Ga plane, exhibit strong polarization effects, leading to a large amount of two-dimensional electron gas (2DEG) at the AlGaN / GaN heterojunction interface. Furthermore, the Schottky gate cannot deplete the high concentration of 2DEG in the channel under zero bias. When the gate voltage VGS = 0, current still flows through the HEMT channel, requiring a negative bias to deplete the 2DEG beneath the gate and put the HEMT in the off state. This undoubtedly increases the complexity of circuit design and significantly increases power consumption.

[0004] To overcome the aforementioned problems, researchers have proposed an enhancement-mode HEMT that is in the off state under zero gate bias. Currently, many schemes have been proposed to obtain enhancement-mode HEMT devices, among which the grooved gate MIS-HEMT structure is one of the alternative structures for fabricating enhancement-mode devices.

[0005] However, the presence of numerous defect states at the GaN / dielectric interface in the MIS structure reduces the stability and reliability of the device threshold voltage, affecting device performance and thus limiting the application of this device structure. Summary of the Invention

[0006] To address the aforementioned problems in the prior art, this invention provides a multilayer passivated grooved gate MIS-HEMT device and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution:

[0007] On one hand, the present invention provides a multilayer passivated grooved gate MIS-HEMT device, comprising, from bottom to top, a substrate, a nucleation layer, a buffer layer, a channel layer, and a barrier layer; a source and a drain are respectively provided on the left and right sides of the barrier layer, and both the source and drain pass through the barrier layer to form an ohmic contact with the channel layer; a left isolation region and a right isolation region of the device are respectively provided on the left side of the source and the right side of the drain; a grooved gate region is provided in the middle of the barrier layer near the source, and a multilayer passivation layer is provided on the grooved gate region; wherein,

[0008] The multilayer passivation layer includes a first passivation layer, a transition layer, a mask layer, and a second passivation layer;

[0009] The first passivation layer is selectively grown at the bottom of the recessed gate region of the barrier layer and contacts the upper surface of the channel layer;

[0010] The transition layer is located on the upper surface of the first passivation layer, and its upper surface is lower than the upper surface of the barrier layer;

[0011] The mask layer is located on the barrier layer on both sides of the recessed gate region;

[0012] The second passivation layer is located on the transition layer and extends upward to the upper surface of the mask layer to form a U-shaped cross-section structure, and the two sides of the second passivation layer are in contact with the source and drain, respectively.

[0013] The gate is located within the U-shaped groove of the second passivation layer.

[0014] In one embodiment of the present invention, the transition layer is formed by thermal oxidation of the first passivation layer, and the mask layer is made of the same material as the transition layer.

[0015] In one embodiment of the present invention, the material of the first passivation layer is Si, and the materials of the transition layer, the mask layer and the second passivation layer are all SiO2.

[0016] In one embodiment of the present invention, the thickness of the first passivation layer is 1-5 nm; the thickness of the transition layer is 0.5-2 nm; the thickness of the mask layer is 5-100 nm; and the thickness of the second passivation layer is 5-100 nm.

[0017] In one embodiment of the present invention, the barrier layer is an Al layer with a thickness of 10–30 nm. x Ga 1-x N; where x = 0.1 to 0.5.

[0018] On the other hand, the present invention also provides a method for fabricating a multilayer passivated grooved gate MIS-HEMT device, comprising the following steps:

[0019] The core layer, buffer layer, channel layer and barrier layer are sequentially fabricated on the substrate;

[0020] Ion implantation is performed on both sides of the barrier layer to form the left and right isolation regions of the device;

[0021] A mask layer is formed on the upper surface of the barrier layer;

[0022] The barrier layer is etched to form a recessed gate region;

[0023] A first passivation layer is formed within the grooved gate region;

[0024] The upper half of the first passivation layer is naturally oxidized to form a transition layer;

[0025] A second passivation layer with grooves is formed on the mask layer and the transition layer to form a multilayer passivation layer with a U-shaped cross-section together with the first passivation layer, the transition layer and the mask layer;

[0026] Electrodes are formed on the surface of the obtained sample to complete the fabrication of the multilayer passivated grooved gate MIS-HEMT device.

[0027] In one embodiment of the present invention, forming a mask layer on the upper surface of the barrier layer includes:

[0028] Using NH3, SiH4, and N2 as reactant gases, 5–100 nm SiO2 is deposited on the surface of the barrier layer using PECVD technology to form a mask layer.

[0029] In one embodiment of the present invention, forming a first passivation layer within the recessed gate region includes:

[0030] SF6 plasma was used to clean the surface of the recessed gate region to remove oxides;

[0031] A1-5 nm Si layer is grown in the recessed gate region using ALD selective technology to form a dense Si atomic layer film with the channel layer, serving as the first passivation layer.

[0032] In one embodiment of the present invention, the upper half of the first passivation layer is naturally oxidized to form a transition layer, including:

[0033] In an O2 atmosphere, the temperature of the reaction chamber is adjusted to 400℃, and the upper half of the first passivation layer in the groove gate region is naturally oxidized to form a SiO2 transition layer of 0.5-2nm.

[0034] In one embodiment of the present invention, forming a grooved second passivation layer on the mask layer and the transition layer includes:

[0035] Using NH3, SiH4, and N2 as reaction gases, 5–100 nm SiO2 is deposited on the surface of the SiO2 mask layer and the SiO2 transition layer using PECVD technology to form a groove-shaped second passivation layer.

[0036] The beneficial effects of this invention are:

[0037] 1. This invention combines a multilayer passivation structure with selective growth technology to achieve effective and precise controllable deposition of the passivation layer in the gate region, forming a low-defect heterojunction with the GaN channel layer. This avoids the GaN surface states introduced by directly depositing the dielectric on the GaN channel surface and a series of etching damage problems caused by super-region growth. It is expected to significantly improve the threshold voltage stability and reliability of the enhancement-mode recessed gate MIS-HEMT device, thereby improving the device performance.

[0038] 2. The present invention reduces the interface state problems caused by the subsequent deposition of SiO2 passivation layer by thermally oxidizing the upper half of the first passivation layer Si to form a SiO2 transition layer, thereby improving the interface quality of the passivation layer.

[0039] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the structure of a multilayer passivated grooved gate MIS-HEMT device provided in an embodiment of the present invention;

[0041] Figure 2 This is a schematic flowchart of the fabrication method of the multilayer passivated grooved gate MIS-HEMT device provided in the embodiment of the present invention;

[0042] Figure 3 a-3i is a process diagram of fabricating a multilayer passivated grooved gate MIS-HEMT device provided in an embodiment of the present invention. Detailed Implementation

[0043] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0044] Example 1

[0045] Please see Figure 1 , Figure 1This is a schematic diagram of a multilayer passivated grooved gate MIS-HEMT device provided in an embodiment of the present invention. From bottom to top, it includes a substrate 1, a nucleation layer 2, a buffer layer 3, a channel layer 4, and a barrier layer 5. A source 6 and a drain 7 are respectively located on the left and right sides of the barrier layer 5, respectively. Both the source 6 and drain 7 pass through the barrier layer 5 to form an ohmic contact with the channel layer 4. A left isolation region 8 and a right isolation region 9 are respectively located on the left side of the source 6 and the right side of the drain 7. A grooved gate region is located in the middle of the barrier layer 5 near the source 6, and a multilayer passivation layer 10 is provided on the grooved gate region.

[0046] The multilayer passivation layer 10 includes a first passivation layer 101, a transition layer 102, a mask layer 103, and a second passivation layer 104;

[0047] The first passivation layer 101 is selectively grown at the bottom of the recessed gate region of the barrier layer 5 and contacts the upper surface of the channel layer 4.

[0048] The transition layer 102 is located on the upper surface of the first passivation layer 101, and its upper surface is lower than the upper surface of the barrier layer 5;

[0049] The mask layer 103 is located on the barrier layer 5 on both sides of the recessed gate region;

[0050] The second passivation layer 104 is located on the transition layer 102 and extends upward to the upper surface of the mask layer 103 to form a U-shaped cross-section structure, and the two sides of the second passivation layer 104 are in contact with the source electrode 6 and the drain electrode 7, respectively.

[0051] Gate 11 is located within the U-shaped groove of the second passivation layer 104.

[0052] In one optional embodiment of the present invention, the substrate 1 is made of n+-GaN, SiC, sapphire, or Si; the nucleation layer 2 is AlN with a thickness of 50–400 nm; the buffer layer 3 is AlGaN with a thickness of 200–8000 nm; the channel layer 4 is GaN with a thickness of 50–500 nm; and the barrier layer 5 is AlGaN with a thickness of 10–30 nm. x Ga 1-x N; where x = 0.1 to 0.5.

[0053] Furthermore, both the left isolation region 8 and the right isolation region 9 can be formed by ion implantation, starting from the left and right ends of the barrier layer 5, with the ion implantation range extending from top to bottom from the barrier layer 5, through the channel layer 4, to the upper surface of the buffer layer 3.

[0054] In this embodiment, the transition layer 102 is formed by thermal oxidation of the first passivation layer 101, and the mask layer 103 is made of the same material as the transition layer 102.

[0055] Preferably, the material of the first passivation layer 101 is Si, and the materials of the transition layer 102, the mask layer 103 and the second passivation layer 104 are all SiO2.

[0056] As an optional embodiment of the present invention, the thickness of the first passivation layer 101 can be 1–5 nm; the thickness of the transition layer 102 is 0.5–2 nm; the thickness of the mask layer 103 is 5–100 nm; and the thickness of the second passivation layer 104 is 5–100 nm. The second passivation layer 104 has a U-shaped groove structure, with the groove embedded in the grooved gate region on the barrier layer 5, and its depth is 5–100 nm.

[0057] In this embodiment, the source 6, drain 7, and gate 11 are made of the same material, which is a metal combination containing Ti / Al.

[0058] The device provided in this embodiment combines a multilayer passivation structure with selective growth technology to realize a multilayer passivated grooved gate MIS-HEMT device structure. This avoids the GaN surface states introduced by directly depositing the dielectric on the GaN channel surface and a series of etching damage problems caused by super-region growth. It is expected to significantly improve the threshold voltage stability and reliability of the enhancement grooved gate MIS-HEMT device, thereby improving the device performance.

[0059] Example 2

[0060] Based on the above embodiment one, this embodiment provides a method for fabricating a multilayer passivated grooved gate MIS-HEMT device. The following is in conjunction with... Figure 2 and Figure 3 a-3i provides a detailed description of the method provided in this embodiment. Figure 2 This is a schematic flowchart of the fabrication method for a multilayer passivated grooved gate MIS-HEMT device provided in an embodiment of the present invention. Figure 3 a-3i is a process diagram of fabricating a multilayer passivated grooved gate MIS-HEMT device provided in an embodiment of the present invention.

[0061] Specifically, the method provided in this embodiment includes the following steps:

[0062] Step 1: Sequentially fabricate the core layer, buffer layer, channel layer, and barrier layer on the substrate.

[0063] First, Si material can be selected as the substrate and cleaned and pretreated to reduce dangling bonds on the substrate surface. Specific cleaning and surface pretreatment methods can be found in existing technologies and will not be detailed here.

[0064] Then, on the surface of the treated substrate 1, an AlN nucleation layer 2 of 50–400 nm, an AlGaN buffer layer 3 of 200–8000 nm, an intrinsic GaN channel layer 4 of 50–500 nm, and an AlGaN channel layer of 10–30 nm are epitaxially grown sequentially. x Ga 1-x N is a barrier layer 5, where x = 0.1 to 0.5, as shown in the figure. Figure 3 As shown in a.

[0065] Step 2: Ion implantation is performed on both sides of the barrier layer to form the left and right isolation regions of the device.

[0066] Specifically, nitrogen ion implantation is performed at the left and right ends of the AlxGa1-xN barrier layer surface, forming the left isolation region 8 and the right isolation region 9 of the device from the barrier layer, through the channel layer, to the upper surface of the buffer layer, as shown below. Figure 3 As shown in b.

[0067] Step 3: Form a mask layer on the upper surface of the barrier layer.

[0068] Specifically, using NH3, SiH4, and N2 as reactant gases, 5–100 nm SiO2 is deposited on the surface of the barrier layer using PECVD technology to form a mask layer 103, such as… Figure 3 As shown in c.

[0069] Step 4: Etch the barrier layer to form the recessed gate region.

[0070] Specifically, etching is performed on the side of the SiO2 mask layer 103 near the source electrode 6, and the trenching range extends from top to bottom from the SiO2 mask layer 103 through the Al x Ga 1-x From the N-barrier layer 5 to the top of the GaN channel layer 4, a recessed gate region is formed, such as... Figure 3 As shown in d.

[0071] It is important to note that using a slow etching rate can reduce etching damage.

[0072] Step 5: Form the first passivation layer in the recessed gate region.

[0073] First, SF6 plasma is used to clean the surface of the grooved gate region to remove oxides.

[0074] Then, using ALD selective growth technology, 1-5 nm of Si is grown in the recessed gate region to form a dense Si atomic layer film with the channel layer, serving as the Si passivation layer, i.e., the first passivation layer 101. Figure 3 As shown in e.

[0075] Step 6: Naturally oxidize the upper half of the first passivation layer to form a transition layer.

[0076] Specifically, under an O2 atmosphere, the temperature of the reaction chamber is adjusted to 400℃, and the upper half of the Si passivation layer in the groove gate region, i.e., the first passivation layer 101, is subjected to natural oxidation. By controlling the oxygen introduction rate, a SiO2 transition layer 102 with a thickness of 0.5–2 nm is formed. Figure 3 As shown in f.

[0077] In this embodiment, by thermally oxidizing the upper half of the first passivation layer Si to form a SiO2 transition layer, the interface state problems caused by the subsequent deposition of the SiO2 passivation layer are reduced, and the interface quality of the passivation layer is improved.

[0078] Step 7: Form a grooved second passivation layer on the mask layer and the transition layer to form a multilayer passivation layer with a U-shaped cross-section together with the first passivation layer, the transition layer and the mask layer.

[0079] Specifically, the epitaxial wafer obtained in step 6 is placed in the PECVD reaction chamber, and a 5-100 nm layer of SiO2 is deposited on the surface of the SiO2 mask layer 103 and the SiO2 transition layer 102 using the PECVD technique as a SiO2 passivation layer to form a U-shaped groove-shaped second passivation layer 104, such as... Figure 3 As shown in g.

[0080] Step 8: Form electrodes on the obtained sample surface to complete the fabrication of the multilayer passivated grooved gate MIS-HEMT device.

[0081] First, the gate electrode is fabricated.

[0082] Specifically, gate metal is deposited within and above the groove of the second passivation layer to form the gate electrode 11, such as... Figure 3 As shown in h, the gate metal is made of materials such as Ti / Al.

[0083] Then, the source and drain electrodes are fabricated.

[0084] Specifically, the obtained sample is etched using photolithography to form source and drain electrode windows; then, Ti / Al-containing ohmic metals are grown in the source and drain electrode windows using sputtering or evaporation processes, and the source electrode 6 and drain electrode 7 are formed by high-temperature rapid annealing, as shown below. Figure 3 As shown in i.

[0085] Thus, the fabrication of a multilayer passivated grooved gate MIS-HEMT device based on selective growth technology was completed.

[0086] In this embodiment, a SiO2 mask layer is first deposited above the barrier layer, and then the SiO2 mask layer and Al are etched away by trenching in the gate region. x Ga 1-xFrom the N-barrier layer down to the GaN channel layer, an in-groove Si passivation layer is formed using ALD selective growth technology. The upper half of the Si passivation layer is then naturally oxidized to form a SiO2 transition layer. Subsequently, a SiO2 passivation layer is deposited on the SiO2 mask layer and the SiO2 transition layer, forming a multi-layer passivation structure. This structure, by combining a multi-layer passivation structure with selective growth technology, achieves effective and precisely controllable deposition of the Si passivation layer within the gate region, forming a low-defect heterojunction with the GaN channel layer. This avoids the GaN surface states introduced by traditional passivation methods that directly deposit dielectric on the GaN channel surface, and is expected to significantly improve the threshold voltage stability and reliability of enhancement-mode grooved gate MIS-HEMT devices.

[0087] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0088] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0089] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0090] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A multi-layer passivated trench gate MIS-HEMT device, characterized in that, From bottom to top, it comprises a substrate (1), a nucleation layer (2), a buffer layer (3), a channel layer (4) and a barrier layer (5); the left and right sides of the barrier layer (5) are respectively provided with a source electrode (6) and a drain electrode (7), the source electrode (6) and the drain electrode (7) both pass through the barrier layer (5) and form an ohmic contact with the channel layer (4); the left side of the source electrode (6) and the right side of the drain electrode (7) are respectively provided with a left isolation area (8) and a right isolation area (9) of the device; the middle of the barrier layer (5) is provided with a recessed gate area close to the source electrode (6), and the recessed gate area is provided with a multilayer passivation layer (10); wherein, The multilayer passivation layer (10) comprises a first passivation layer (101), a transition layer (102), a mask layer (103) and a second passivation layer (104); the material of the first passivation layer (101) is Si, and the material of the transition layer (102) is SiO2; The first passivation layer (101) is selectively grown at the bottom of the recessed gate area of the barrier layer (5) and is in contact with the upper surface of the channel layer (4); The transition layer (102) is located on the upper surface of the first passivation layer (101), and the upper surface thereof is lower than the upper surface of the barrier layer (5); the transition layer (102) is formed by thermal oxidation on the upper half of the first passivation layer (101); The mask layer (103) is located on the barrier layer (5) on both sides of the recessed gate area; The second passivation layer (104) is located on the transition layer (102) and extends upward to the upper surface of the mask layer (103) to form a U-shaped cross-section structure, and the two sides of the second passivation layer (104) are respectively in contact with the source electrode (6) and the drain electrode (7); The gate electrode (11) is located in the U-shaped recess of the second passivation layer (104).

2. The multi-layer passivated trench gate MIS-HEMT device of claim 1, wherein, The materials of the mask layer (103) and the second passivation layer (104) are both SiO2.

3. The multi-layer passivated trench gate MIS-HEMT device of claim 1, wherein, The thickness of the first passivation layer (101) is 1-5 nm; the thickness of the transition layer (102) is 0.5-2 nm; the thickness of the mask layer (103) is 5-100 nm; and the thickness of the second passivation layer (104) is 5-100 nm.

4. The multi-layer passivated trench gate MIS-HEMT device of claim 1, wherein, The barrier layer (5) is Al x Ga 1-x N; wherein x = 0.1-0.

5.

5. A method for fabricating a multi-layer passivated trench gate MIS-HEMT device, characterized in that, The method comprises the following steps: sequentially forming a nucleation layer, a buffer layer, a channel layer and a barrier layer on a substrate; ion implantation is performed on the left and right sides of the barrier layer to form left and right isolation areas of the device; forming a mask layer on the upper surface of the barrier layer; etching the barrier layer to form a recessed gate area; forming a first passivation layer in the recessed gate area; thermally oxidizing the upper half of the first passivation layer to form a transition layer; forming a recessed second passivation layer on the mask layer and the transition layer to form a multilayer passivation layer with a U-shaped cross-section together with the first passivation layer, the transition layer and the mask layer; the material of the first passivation layer is Si, and the material of the transition layer is SiO2; forming an electrode on the surface of the obtained sample to complete the preparation of the multilayer passivation recess gate MIS-HEMT device.

6. The method of claim 5, wherein the method further comprises: forming a mask layer on the upper surface of the barrier layer comprises: A 5-100 nm SiO2 is deposited on the surface of the barrier layer by PECVD technology using NH3, SiH4 and N2 as reaction gas to form a mask layer.

7. The method of claim 5, wherein the method further comprises: Forming a first passivation layer in the recessed gate region includes: Cleaning the surface of the recessed gate region by SF6 plasma to remove the oxide; Growth of 1-5 nm Si on the recessed gate region by ALD selective technology to form a dense Si atomic layer film with the channel layer as the first passivation layer.

8. The method of claim 5, wherein the method further comprises: Thermal oxidation of the upper half of the first passivation layer to form a transition layer includes: Adjusting the temperature of the reaction chamber to 400 DEG C in O2 atmosphere to perform thermal oxidation of the upper half of the first passivation layer in the recessed gate region to form a 0.5-2 nm SiO2 transition layer.

9. The method of claim 5, wherein the method further comprises: Forming a recessed second passivation layer on the mask layer and the transition layer includes: Depositing 5-100 nm SiO2 on the surface of the SiO2 mask layer and the SiO2 transition layer by PECVD technology using NH3, SiH4 and N2 as reaction gas to form a recessed second passivation layer.

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