High frequency signal detector and method thereof

Abstract

A signal detector and a signal detection method, the signal detection method comprising receiving an input voltage signal; coupling the input voltage signal to a coupled voltage signal using AC coupling; establishing a DC value of the coupled voltage signal using a resistor; performing self-mixing of the coupled voltage signal by using a pair of cross-coupled MOS transistors to produce a self-mixed voltage signal; producing an output voltage by low pass filtering the self-mixed voltage signal; producing a reference voltage using a reference current terminated to a reference load; and deciding a logic signal by comparing the output voltage signal to the reference voltage.

Description

[0001] Related Applications

[0002] This application claims the benefit of priority to U.S. Patent Application No. 17 / 140,179, filed on January 4, 2021, the contents of which are incorporated by reference in its entirety for all purposes. TECHNICAL FIELD

[0003] The present disclosure relates generally to a circuit and method for high frequency signal detection. BACKGROUND

[0004] In many applications, it is necessary to detect whether the amplitude of a high frequency signal is above or below a target value. U.S. Patent No. 8,854,028 to Lin discloses a signal detector that requires a biasing circuit and results in static power consumption even when the high frequency signal is not present.

[0005] Therefore, there is a need for a high frequency signal detector that is very fast and can have zero static power consumption when the high frequency signal is not present. SUMMARY

[0006] In one embodiment, a signal detector is provided, comprising a rectifier including a pair of AC coupling capacitors configured to couple an input voltage signal to a coupled voltage signal, a pair of resistors configured to establish a DC value of the coupled voltage signal, a pair of cross-coupled MOS transistors configured to self-mix a self-mixed voltage signal from the coupled voltage signal, and a low pass filter network configured to filter the self-mixed voltage signal to an output voltage signal, a reference voltage generator including a current source configured to output a reference current and a reference load configured to establish a reference voltage from the reference current, and a comparator configured to output a logic signal from a comparison between the output voltage signal and the reference voltage.

[0007] In one embodiment, a signal detection method is provided, comprising receiving an input voltage signal, coupling the input voltage signal to a coupled voltage signal using AC coupling, establishing a DC value of the coupled voltage signal using resistors, performing self-mixing of the coupled voltage signal using a pair of cross-coupled MOS transistors to produce a self-mixed voltage signal, producing an output voltage signal by low pass filtering the self-mixed voltage signal, producing a reference voltage using a reference current that is terminated to a reference load, and determining a logic signal by comparing the output voltage signal to the reference voltage.

[0008] For a better understanding of the features and technical content of the present application, please refer to the following detailed description of the present application and the accompanying drawings. However, the provided drawings are only used for reference and illustration, and are not used to limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 A schematic diagram of a signal detector according to an embodiment of the present application is shown.

[0010] Figure 2A Analog results of output voltage versus amplitude of input voltage signal for a signal detector according to Figure 1 are shown.

[0011] Figure 2B Analog results of output voltage signal waveform for a signal detector according to Figure 1 are shown.

[0012] Figure 3 A flowchart of a signal detection method according to an embodiment of the present disclosure is shown.

[0013] SYMBOL EXPLANATION

[0014] 100: signal detector

[0015] 110: rectifier

[0016] 119: T-network

[0017] 120: reference voltage generator

[0018] 130: reference load

[0019] 140: comparator

[0020] 300: flowchart

[0021] 111, 112, 113, 114: node

[0022] 115: center node

[0023] C1: first capacitor

[0024] C2: second capacitor

[0025] C3: third capacitor

[0026] I ref : reference current

[0027] M1, M2: PMOS transistor

[0028] M3: third PMOS transistor

[0029] M4: fourth PMOS transistor

[0030] R1: first resistor

[0031] R2: second resistor

[0032] R3: third resistor

[0033] R4: fourth resistor

[0034] R5: fifth resistor

[0035] R6: sixth resistor

[0036] V B : bias voltage

[0037] V d : logic signal

[0038] V DD : power supply node

[0039] V i : voltage signal

[0040] V i+ , V c+ , V i- , V c- : voltage

[0041] V o : output voltage signal

[0042] V ref : reference voltage

[0043] V sm1 : first self-mixing voltage

[0044] V sm2 : second self-mixing voltage DETAILED DESCRIPTION

[0045] The following embodiments of the disclosed high frequency signal detector and method are described in order to explain the present application by referring to particular embodiments. Those skilled in the art will understand that the advantages of the present application are not limited to the particular embodiments described and that the scope of the present application is defined by the appended claims. The present application can be carried out or implemented by other different embodiments and the details of the present application can be modified in different ways without departing from the spirit and scope of the present application. In addition, the drawings of the present application are simple schematic illustrations and are not drawn to scale. The following embodiments will further illustrate the technical content of the present application, but the disclosed content is not intended to limit the scope of the present application. In addition, the term "or" used herein can include any one or more combinations of the associated listed items.

[0046] The present invention relates to high frequency signal detection. While the specification describes several exemplary embodiments of the invention, which are believed to be the most presentable and representative examples of the invention, it is understood that the invention can be carried out in a wide variety of ways and that the specification is not intended to limit the invention to the particular examples described or implementation of any particular features of these examples. In other instances, well-known details are not shown or described to avoid obscuring the various embodiments of the invention.

[0047] Those skilled in the art understand the terminology and basic concepts related to microelectronics used in the present invention, such as "circuit node", "power node", "ground node", "differential signal", "voltage", "current", "complementary metal oxide semiconductor (CMOS)", "p-channel metal oxide semiconductor (PMOS)", "n-channel metal oxide semiconductor", "resistor", "capacitor", "signal", "comparator", "alternating current", "AC coupling", "direct current", "DC coupling", "current source", and "load". Such terminology and basic concepts are obvious to those skilled in the art when used in a paragraph related to microelectronics, and thus will not be explained in detail here.

[0048] Those skilled in the art can read a schematic of a circuit including elements such as capacitors, resistors, NMOS transistors, PMOS transistors, and so on, and do not need a lengthy description of how one element is connected to another in the schematic. Those skilled in the art can also recognize the symbols of PMOS transistors and NMOS transistors, and recognize their "source terminal", "gate terminal", and "drain terminal". In short, in relation to MOS transistors, the "source terminal" is simply referred to as "source", the "gate terminal" is simply referred to as "gate", and the "drain terminal" is simply referred to as "drain" hereinafter. Those skilled in the art can also understand terms such as gigahertz (GHz), millivolt (mV), microampere (mA), micrometer (pm), nanometer (nm), Ohm, and femtofarad (fF).

[0049] A MOS transistor, PMOS or NMOS, has a width and a channel length. Sometimes, when it is obvious from the context that "length" refers to the "channel length" of the transistor without causing confusion, the "channel length" is simply referred to as "length". The width and length of a MOS transistor are denoted as "W / L". For example, when it is mentioned that "the W / L of an NMOS transistor is 10 pm / 30 nm", it means that the width and length of the NMOS transistor are 10 pm and 30 nm, respectively.

[0050] The present invention is presented in an engineering sense, not in a strict mathematical sense. For example, "A equals B" means "the difference between A and B is less than an engineering tolerance." "X is zero" means "the absolute value of X is less than an engineering tolerance."

[0051] In the present invention, "circuit node" is often abbreviated as "node" when the meaning of "circuit node" is clear from the context.

[0052] In the present invention, a ground node is a node that is substantially zero voltage (0V). A power node is a node that is substantially fixed voltage, and is denoted by "V DD " which is a widely used convention in the literature. In the present invention, depending on the context which is apparent to those skilled in the art, sometimes "V DD " refers to the voltage level at the power node "V DD ". For example, "V DD is 1.5V" clearly means that the voltage level on the power node V DD is 1.5V.

[0053] A DC node is a node that is substantially fixed voltage level. Both power nodes and ground nodes are DC nodes.

[0054] A circuit is a collection of transistors, capacitors, resistors, and / or other electronic devices interconnected in a specific way to achieve a specific function. A network is a single circuit or a collection of multiple circuits.

[0055] In the present invention, a signal is a variable level voltage that carries specific information, and can vary with time. The signal level at a specific point in time represents the state of the signal at that point in time.

[0056] A logic signal refers to a signal that has two states: low and high. The low state is also referred to as "0" state, and the high state is also referred to as "1" state. With respect to a logic signal Q, "Q is high" or "Q is low" means "Q is in the high state" or "Q is in the low state". Similarly, "Q is 1" or "Q is 0" means "Q is in the 1 state" or "Q is in the 0 state".

[0057] In the present invention, differential transmission scheme is widely used. When implemented in differential transmission scheme, a voltage signal includes two voltages, denoted by suffix "+" and "-", respectively, and subscripted, and the value of the voltage signal is represented by the difference between the two voltages. For example, a voltage signal V i (V c ) in a differential transmission embodiment includes voltages V i+ (Vc+ ) and voltage V i- (V c- ), and the voltage signal V i (V c ) is determined by the voltage V i+ (V c+ ) and voltage V i- (V c- ) is expressed as the difference between the voltage V i+ (V c+ ) is called the voltage signal V i (V c ) first end; voltage V i- (V c+ ) is called the voltage signal V i (V c ). The first terminal is also called the positive terminal; the second terminal is also called the negative terminal. When a voltage signal is balanced in a differential transmission scheme, the AC value of its positive terminal is opposite to the AC value of its negative terminal.

[0058] A schematic diagram of a signal detector 100 according to an embodiment of the present invention is shown in FIG. Figure 1 The signal detector 100 includes a rectifier 110 for receiving an input voltage signal V i And output an output voltage signal V o ; Reference voltage generator 120, for outputting a reference voltage V ref And a comparator 140, according to the output voltage signal V o With reference voltage V ref The comparison result between the two is used to output the logic signal V d . Input voltage signal V i The amplitude of the current is detected by the rectifier 110 and the output voltage signal V o Indicates. Reference voltage V ref Represents the input voltage signal V i If the logic signal V d Is high (low), it means the input voltage signal V i The amplitude is greater than (smaller than) the target amplitude.

[0059] In one embodiment, the signal detector 100 is integrated and fabricated on a silicon substrate using CMOS process technology. By way of example and not limitation, a 28 nm CMOS process technology is used, where the minimum channel length is 30 nm.

[0060] The rectifier 110 includes a first capacitor C1 and a second capacitor C2 for inputting a voltage signal V i And the coupled voltage signal V c Provide AC coupling between the two. In the differential transmission scheme, the input voltage signal Vi comprises a voltage V i+ and V i- , and a coupling voltage signal V c comprises a voltage V c+ and V c- at nodes 111 and 112, respectively; a first resistor R1 and a second resistor R2 are used to connect the nodes 111 and 112 to a ground node, respectively, to establish DC values of the voltages V c+ and V c- , respectively; a pair of cross-coupled PMOS transistors M1 and M2 are used to output a first self-mixing voltage V sm1 at node 113 and a second self-mixing voltage V sm2 at node 114, wherein the voltage V c+ is connected to the source of PMOS transistor M1 and the gate of PMOS transistor M2, and the voltage V c- is connected to the source of PMOS transistor M2 and the gate of PMOS transistor M1, and PMOS transistors M1 and M2 are referred to as cross-coupled because the gate of PMOS transistor M1 is connected to the source of PMOS transistor M2, and the gate of PMOS transistor M2 is connected to the source of PMOS transistor M1; a low-pass filter, implemented by a T-network 119, which comprises a third capacitor C3 to stabilize a center node 115 of the output voltage signal V o , which is coupled to the third node 113 via a third resistor R3 and to the fourth node 114 via a fourth resistor R4.

[0061] In one embodiment, the MOS transistor is implemented by a mixer; when the gate of the MOS transistor is connected to a first voltage signal and the source of the MOS transistor is connected to a second voltage signal, the drain of the MOS transistor outputs a third voltage signal comprising a mixing product of the first voltage signal and the second voltage signal due to the quadratic characteristic of the MOS transistor. Wherein the third voltage signal is approximately proportional to the square of the difference between the first voltage signal and the second voltage signal. Therefore, PMOS transistor M1 implements the mixing of the voltages V c- and V c+ , and PMOS transistor M2 implements the mixing of the voltages V c+ and V c- . Since the voltages V c+ and V c- are the same signals but with opposite signs in a differential transmission scheme, the mixing function performed by PMOS transistors M1 and M2 is referred to as self-mixing.

[0062] The T-network 119 uses the third resistor R3 and the third capacitor C3 to filter the first self-mixing voltage Vsm1 Perform the first low-pass filtering and use the fourth resistor R4 and the third capacitor C3 to filter the second self-mixing voltage V sm2 A second low-pass filter is performed, and the outputs from the first low-pass filter and the second low-pass filter are combined into an output voltage signal V at the central node 115. o .

[0063] By way of example and not limitation, in one embodiment: the voltage signal V i The frequency is 8.5GHz; C1 and C2 are 77fF; R1 and R2 are 30K ohms; the W / L of PMOS transistors M1 and M2 are 600nm / 250nm; R3 and R4 are 30K ohms; and C3 is 50fF. Output voltage signal V o The value of the input voltage signal V i The simulation results of the amplitude are as follows Figure 2A As shown. Output voltage signal V o The value of the input voltage signal V i As the amplitude increases, it increases linearly. i The target value of the amplitude will be the output voltage signal V o The value is compared with an appropriate reference voltage to infer the input voltage signal V i The amplitude of the input voltage signal V i If the target value of the amplitude is 600mV, the reference voltage will be 519mV. Figure 2A If the output voltage signal V o If the input voltage signal V i The amplitude of V is higher (lower) than the target value of 600mV. The rectifier 110 is very fast. In response to the input voltage signal V with an amplitude of 600mV i The output voltage signal V o The simulation results of the waveform are as follows Figure 2B As shown. It shows the output voltage signal V o It stabilizes within about 20ns. Since it does not consume any quiescent current, the rectifier 110 is also very power-efficient. In other words, when there is no input voltage signal, the current consumption is zero.

[0064] The reference voltage generator 120 includes a current source and a reference load 130. The current source is used to generate a reference voltage according to the bias voltage V B Output reference current I ref The reference load 130 is used to realize the reference current I ref Establish reference voltage V refThe reference load 130 includes a fifth resistor R5, a fourth PMOS transistor M4, and a sixth resistor R6 connected in series. The reference load 130 establishes a reference voltage V in a manner similar to the rectifier 110. ref . For example but not limited to: V DD is 1.5V; V B is 490mV; the W / L of the PMOS transistor M3 is 5μm / 500nm; I ref 12.5μA; V ref is 519 mV; R5 is 625 ohms; W / L of the PMOS transistor M4 is 70.4 μm / 250 nm; and R6 is 40K ohms.

[0065] Comparators are well known in the art and will not be described in detail. Comparator 140 may be implemented using any comparator circuit known in the art at the discretion of the circuit designer.

[0066] For any given network comprising a plurality of PMOS transistors and / or a plurality of NMOS transistors and a plurality of passive components (capacitors, resistors, or inductors), there exists an alternative network that is functionally equivalent to the given network, wherein the given network can be modified into the alternative network by replacing each PMOS transistor with an NMOS transistor, each NMOS transistor with a PMOS transistor, each power node with a ground node, and each ground node with a power node. The alternative network is a "flipped" version of the given network and retains the same functionality.

[0067] Although resistors R1 and R2 are shown as coupling nodes 111 and 112 to ground, this is for illustrative purposes only and is not intended to limit the present invention. Resistors R1 and R2 are used to establish the DC values ​​of nodes 111 and 112, and these values ​​do not necessarily have to be zero. The node connected to both R1 and R2 may be a DC node other than ground.

[0068] like Figure 3 As shown in the flowchart 300, the signal detection method includes: (step 310) receiving an input voltage signal; (step 320) coupling the input voltage signal to a coupled voltage signal using AC coupling; (step 330) establishing a DC value of the coupled voltage signal using a resistor; (step 340) performing self-mixing of the coupled voltage signal by using a pair of cross-coupled MOS transistors to generate a self-mixing voltage signal; (step 350) generating an output voltage signal by low-pass filtering the self-mixing voltage signal; (step 360) generating a reference voltage using a reference current terminated at a reference load; and (step 370) determining a logic signal by comparing the output voltage signal with the reference voltage.

[0069] Those skilled in the art will readily observe that numerous modifications and changes in device and method can be made without departing from the teachings of the present application. Accordingly, the above disclosure is intended to be illustrative only and not limiting of the scope of the application as set forth in the following claims.

[0070] The foregoing disclosure is not intended to limit the scope of the application to the precise embodiments described. Changes and modifications can be made to the above-described embodiments without departing from the scope of the application.

Claims

1. A signal detector comprising: A rectifier comprising: a pair of AC coupling capacitors configured to couple an input voltage signal to a coupled voltage signal; a pair of resistors configured to establish a DC value of the coupled voltage signal; a pair of cross-coupled metal oxide semiconductor transistors configured to output a self-mixing voltage signal according to a self-mixing of the coupled voltage signal; and a low-pass filter network configured to filter the self-mixing voltage signal into an output voltage signal; A reference voltage generator comprising: a current source configured to output a reference current; and a reference load configured to establish a reference voltage according to the reference current; and a comparator configured to output a logic signal according to a comparison result between the output voltage signal and the reference voltage, The pair of resistors includes: a first resistor configured to couple a first end of the coupled voltage signal to a DC node; and a second resistor configured to couple a second end of the coupled voltage signal to the DC node, wherein one end of the first resistor is directly connected to the DC node and one end of the second resistor is directly connected to the DC node.

2. The signal detector according to claim 1, wherein The pair of AC coupling capacitors includes: a first capacitor configured to couple a first end of the input voltage signal to a first end of the coupled voltage signal; and A second capacitor is configured to couple a second end of the input voltage signal to a second end of the coupled voltage signal.

3. The signal detector according to claim 1, wherein The pair of cross-coupled metal oxide semiconductor transistors includes a first metal oxide semiconductor transistor and a second metal oxide semiconductor transistor, the first end of the coupling voltage signal is coupled to the source of the first metal oxide semiconductor transistor and the gate of the second metal oxide semiconductor transistor, and the second end of the coupling voltage signal is coupled to the source of the second metal oxide semiconductor transistor and the gate of the first metal oxide semiconductor transistor.

4. The signal detector according to claim 3, wherein: The low-pass filter includes: a third capacitor configured to maintain the output voltage signal at a center node; a third resistor configured to couple the drain of the first metal oxide semiconductor transistor to the central node; and A fourth resistor is configured to couple the drain of the second metal oxide semiconductor transistor to the central node.

5. The signal detector according to claim 4, wherein The current source includes a third metal oxide semiconductor transistor configured to output the reference current according to a bias voltage.

6. The signal detector according to claim 5, wherein The reference load includes a fifth resistor, a fourth metal oxide semiconductor transistor, and a sixth resistor connected in series.

7. A signal detection method, comprising: receiving an input voltage signal; coupling the input voltage signal to a coupled voltage signal using AC coupling; Using a resistor to establish a DC value of a coupled voltage signal; performing self-mixing of the coupled voltage signal by using a pair of cross-coupled metal oxide semiconductor transistors to generate a self-mixing voltage signal; generating an output voltage signal by performing low-pass filtering on the self-mixing voltage signal; generating a reference voltage using a reference current terminated at a reference load; as well as By comparing the output voltage signal with the reference voltage to determine a logic signal, Wherein, using the resistor to establish the DC value of the coupling voltage signal includes: A first resistor is used to couple a first end of the coupled voltage signal to a DC node, and a second resistor is used to couple a second end of the coupled voltage signal to the DC node, wherein one end of the first resistor is directly connected to the DC node and one end of the second resistor is directly connected to the DC node.

8. The signal detection method according to claim 7, wherein: Coupling the input voltage signal to the coupled voltage signal using AC coupling includes: A first capacitor is used to couple a first end of the input voltage signal to a first end of the coupled voltage signal, and a second capacitor is used to couple a second end of the input voltage signal to a second end of the coupled voltage signal.

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