Voltage holding circuit, voltage monitoring circuit, and semiconductor integrated circuit

Abstract

The present invention relates to a voltage holding circuit, a voltage monitoring circuit, and a semiconductor integrated circuit. The voltage holding circuit operates in accordance with each processing cycle to hold the voltage value of an input voltage signal. The processing cycle includes a holding period and a reset period immediately following the holding period, and has: a first holding circuit (901, 903, 906, 907, 908) that operates to hold the lowest voltage value of the input voltage signal during the holding period in accordance with each of the processing cycles; and a second holding circuit (901, 902, 904, 905, 908) that operates to hold the highest voltage value of the input voltage signal during the reset period in accordance with each of the processing cycles.

Description

Technical Field

[0001] The present invention relates to a voltage holding circuit, a voltage monitoring circuit, and a semiconductor integrated circuit. Background Art

[0002] Patent Document 1 discloses a peak holding circuit having: a voltage holding element that holds an applied voltage; a charging switch element that controls a charging state of the voltage holding element; a bias circuit that applies a bias voltage to an input signal; and a comparison circuit. The comparison circuit compares the voltage of the voltage holding element with the input signal to which the bias voltage is applied, and controls the charging switch element when the voltage of the voltage holding element is lower so that the voltage holding element becomes in a charging state. The peak holding circuit outputs the holding voltage of the voltage holding element.

[0003] Patent Document 2 discloses a droop correction peak holding circuit having: a peak holding circuit including a holding capacitor that holds a peak voltage of an input signal; and a droop correction circuit that generates a voltage having a polarity opposite to that of the holding voltage of the holding capacitor of the peak holding circuit. The droop correction circuit is connected to one end of the holding capacitor of the peak holding circuit.

[0004] Patent Document 3 discloses a peak holding circuit that detects a maximum value or a minimum value, i.e., a peak, of a voltage of an input signal, i.e., an input voltage, in a predetermined period composed of a plurality of cycles, and outputs an output peak as an output signal.

[0005] Patent Document 1: Japanese Patent Laid-Open No. 11-242059

[0006] Patent Document 2: Japanese Patent Laid-Open No. 2010-244610

[0007] Patent Document 3: Japanese Patent Laid-Open No. 2003-215173

[0008] During a period in which the peak holding circuit resets the voltage holding element, a dead time occurs in which the voltage holding element cannot output an appropriate holding voltage. It is preferable that the dead time is short. Summary of the Invention

[0009] An object of the present invention is to be able to shorten a dead time in which an appropriate holding voltage cannot be output during a reset period.

[0010] The voltage holding circuit operates according to each processing cycle to hold the voltage value of the input voltage signal. This processing cycle includes a holding period and a reset period immediately following the holding period. It has: a first holding circuit that, according to each of the above processing cycles, operates to hold the lowest voltage value of the input voltage signal during the holding period; and a second holding circuit that, according to each of the above processing cycles, operates to hold the highest voltage value of the input voltage signal during the reset period.

[0011] It is possible to shorten the dead time during the reset period when an appropriate holding voltage cannot be output. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a diagram showing the change in the voltage of the power supply voltage node when dynamic voltage scaling (DVS) is not performed.

[0013] Figure 2 It is a diagram showing the change in the voltage of the power supply voltage node when dynamic voltage scaling is performed.

[0014] Figure 3 It is a block diagram showing a configuration example of the voltage monitoring circuit.

[0015] Figure 4 It is a diagram showing a voltage waveform for explaining the operation of the voltage monitoring circuit.

[0016] Figure 5 It is a circuit diagram showing a configuration example of the voltage holding circuit according to the comparative example.

[0017] Figure 6 It is for explaining Figure 5 the voltage waveform of the operation of the voltage holding circuit.

[0018] Figure 7 It is a circuit diagram showing a configuration example of the voltage holding circuit according to the first embodiment.

[0019] Figure 8 It is for explaining Figure 7 the voltage waveform of the operation of the voltage holding circuit.

[0020] Figure 9 It is a circuit diagram showing a configuration example of the voltage holding circuit according to the second embodiment.

[0021] Figure 10 It is for explaining Figure 9 the voltage waveform of the operation of the voltage holding circuit.

[0022] Figure 11 It is a circuit diagram showing a configuration example of the voltage holding circuit according to the third embodiment.

[0023] Figure 12 It is a diagram showing voltage waveforms and current waveforms for explaining Figure 11 the operation of the voltage holding circuit.

[0024] Figure 13 It is a circuit diagram showing a configuration example of the voltage holding circuit according to the fourth embodiment.

[0025] Figure 14 It is a diagram showing Figure 13 voltage waveforms for explaining the operation of the voltage holding circuit.

[0026] Figure 15 It is a diagram showing a configuration example of the voltage monitoring circuit according to the fifth embodiment.

[0027] Figure 16 It is a diagram showing a configuration example of the semiconductor integrated circuit according to the fifth embodiment.

[0028] Figure 17 It is a diagram showing a configuration example of the semiconductor integrated circuit according to the sixth embodiment.

[0029] Figure 18 It is a diagram showing a configuration example of the semiconductor integrated circuit according to the seventh embodiment.

[0030] Figure 19 It is a diagram showing a configuration example of the semiconductor integrated circuit according to the eighth embodiment.

[0031] Figure 20 It is a diagram showing a configuration example of the semiconductor integrated circuit according to the ninth embodiment.

[0032] Figure 21 It is a circuit diagram showing a configuration example of the operational amplifier.

[0033] Figure 22 It is a diagram showing the reset mode of the comparator.

[0034] Figure 23 It is a diagram showing the comparison mode of the comparator.

[0035] Figure 24 It is a circuit diagram showing a configuration example of the constant current source.

[0036] Figure 25 It is a circuit diagram showing a configuration example of the inverter.

[0037] Figure 26 It is a circuit diagram showing a configuration example of the AND circuit.

[0038] Figure 27 It is a circuit diagram showing a configuration example of the OR circuit. Detailed implementation manners

[0039] (First Embodiment)

[0040] Figure 1 This is a diagram showing the change in the voltage 104 of the power supply voltage node without performing dynamic voltage scaling (DVS). The horizontal axis represents time T, and the vertical axis represents voltage V. A constant power supply voltage Vdd is supplied to the power supply voltage node. The voltage 104 of the power supply voltage node varies due to a voltage drop according to the states 101 to 103 of the internal circuit. In the states 101 to 103, the power supply voltage Vdd is determined such that the minimum voltage value of the voltage 104 of the power supply voltage node is not lower than the minimum operating voltage Vmin. Therefore, the difference between the minimum voltage value of the voltage 104 and the minimum operating voltage Vmin becomes wasted power 105. In order to reduce the wasted power 105, dynamic voltage scaling is performed.

[0041] Figure 2 This is a diagram showing the change in the voltage 201 of the power supply voltage node when performing dynamic voltage scaling. The horizontal axis represents time T, and the vertical axis represents voltage V. The voltage 201 of the power supply voltage node varies due to a voltage drop according to the states 101 to 103 of the internal circuit. The semiconductor integrated circuit detects the minimum voltage value of the voltage 201 through dynamic voltage scaling and dynamically controls the power supply voltage Vdd so that the minimum voltage value of the voltage 201 becomes the minimum operating voltage Vmin. By dynamically controlling the power supply voltage Vdd, the semiconductor integrated circuit can reduce the power 202.

[0042] Figure 3 This is a block diagram showing a configuration example of the voltage monitoring circuit. Figure 4 This is a diagram showing voltage waveforms for explaining the operation of the voltage monitoring circuit. The voltage monitoring circuit includes a voltage holding circuit 302 and an analog / digital converter 303. The voltage holding circuit 302 inputs the voltage signal 401 of the power supply voltage node 301 and holds the minimum voltage value 402 of the voltage signal 401 at each specified period (e.g., 1 μs). The analog / digital converter 303 converts the minimum voltage value held by the voltage holding circuit 302 from analog to digital.

[0043] The decrease in the voltage signal 401 is within 1 μs, and the time axis resolution is about ns. Therefore, it is difficult for the analog / digital converter 303 to directly convert the voltage signal 401 of the power supply voltage node 301 from analog to digital with high precision. By using the voltage holding circuit 302, the voltage monitoring circuit can detect the minimum voltage value every 1 μs, for example, and achieve dynamic voltage scaling.

[0044] In addition, the voltage holding circuit 302 can also input the voltage signal 401 of the power supply voltage node 301, and hold the highest voltage value of the voltage signal 401 for each specified period (e.g., 1 μs). In this case, the analog / digital converter 303 converts the highest voltage value held by the voltage holding circuit 302 from analog to digital.

[0045] Figure 5 FIG. is a circuit diagram showing a configuration example of the voltage holding circuit 302 according to the comparative example. Figure 6 is for explaining Figure 5 FIG. is a diagram of a voltage waveform showing the operation of the voltage holding circuit 302. The voltage holding circuit 302 includes: a comparator 501, a switch 502, a capacitor 503, a switch 504, a constant current source 505, an operational amplifier 506, and a power supply voltage node 507. The switch 504 is, for example, an n-channel field effect transistor.

[0046] The input voltage signal VIN is the voltage of the input terminal IN. The output voltage VOUT is the voltage of the output terminal OUT. The reset voltage Vr is the voltage of the power supply voltage node 507. The voltage holding circuit 302 holds the lowest voltage value of the input voltage signal VIN of the input terminal IN. The input terminal IN is connected to the node to be voltage-held, for example, to the power supply voltage node.

[0047] During the holding period, the reset signal RST becomes low level. Then, the switch 502 is turned off. When the input voltage signal VIN of the input terminal IN is lower than the lowest voltage value held by the capacitor 503, the comparator 501 outputs a high level, the switch 504 is turned on, and the lowest voltage value held by the capacitor 503 decreases. In contrast, when the input voltage signal VIN of the input terminal IN is higher than the lowest voltage value held by the capacitor 503, the comparator 501 outputs a low level, the switch 504 is turned off, and the capacitor 503 maintains the lowest voltage value.

[0048] During the reset period, the reset signal RST becomes high level. Then, the switch 502 is turned on, the capacitor 503 holds the reset voltage Vr, and the output voltage VOUT becomes the reset voltage Vr. The switch 504 is turned off.

[0049] During the holding period, the voltage holding circuit 302 holds the lowest voltage value of the input voltage signal VIN of the input terminal IN and outputs the lowest voltage value as the output voltage VOUT.

[0050] The dead time 601 is the period during which the capacitor 503 is reset by the high-level reset signal RST, and it is the period during which the voltage holding circuit 302 cannot output an appropriate minimum voltage value. According to the capacitance value of the capacitor 503 and the current of the constant current source 505, the greater the difference between the input voltage signal VIN and the reset voltage Vr, the longer the dead time 601. Since the dead time 601 cannot output an appropriate minimum voltage value, it is preferably short.

[0051] In addition, the capacitor 503 is directly connected to the power supply voltage node 507. Therefore, the voltage holding circuit 302 is easily affected by the high-frequency variation of the power supply voltage of the power supply voltage node 507.

[0052] Hereinafter, a voltage holding circuit that can shorten the dead time 601 and resist the high-frequency variation of the power supply voltage will be described.

[0053] Figure 7 FIG. is a circuit diagram showing a configuration example of the voltage holding circuit 302 according to the first embodiment. The voltage holding circuit 302 includes: a comparator 701, a switch 702, a capacitor 703, a switch 704, a constant current source 705, operational amplifiers 706 and 707, a resistor 708, a capacitor 709, and a constant current source 710. The switches 702 and 704 are, for example, n-channel field effect transistors.

[0054] The - input terminal of the comparator 701 is connected to the input terminal IN, the + input terminal is connected to the + input terminal of the operational amplifier 706, and the output terminal is connected to the control terminal of the switch 704. The capacitor 703 is connected between the output terminal of the operational amplifier 707 and the + input terminal of the operational amplifier 706. The switch 702 is connected in parallel with the capacitor 703. The reset signal RST is input to the control terminal of the switch 702. The switch 704 is connected between the + input terminal of the operational amplifier 706 and the constant current source 705. The constant current source 705 is connected between the switch 704 and a reference potential node (for example, a ground potential node) having a potential lower than the power supply potential node. The - input terminal and the output terminal of the operational amplifier 706 are connected to the output terminal OUT.

[0055] The + input terminal of the operational amplifier 707 is connected to the input terminal IN, and the - input terminal is connected to the output terminal of the operational amplifier 707 via the resistor 708. The capacitor 709 is connected in parallel with the resistor 708. The constant current source 710 is connected between the - input terminal of the operational amplifier 707 and the reference potential node.

[0056] Figure 8 is for explaining Figure 7A diagram of the voltage waveform of the operation of the voltage holding circuit 302. The horizontal axis represents time T, and the vertical axis represents voltage V. The input voltage signal VIN is the voltage of the input terminal IN. The output voltage VOUT is the voltage of the output terminal OUT. The reset voltage signal VR is the voltage of the output terminal of the operational amplifier 707. The voltage holding circuit 302 operates in accordance with each processing cycle, and for each processing cycle, holds the lowest voltage value of the input voltage signal VIN at the input terminal IN. This processing cycle includes a holding period and a reset period immediately following the holding period.

[0057] The operational amplifier 707, resistor 708, capacitor 709, and constant current source 710 are generating circuits that generate a reset voltage signal VR that varies according to the input voltage signal VIN. If the resistance value of the resistor 708 is set to R and the current of the constant current source 710 is set to I, the reset voltage signal VR is represented by the following equation. The reset voltage signal VR is a signal having a voltage value that is larger than the voltage value of the input voltage signal VIN by I×R (first value).

[0058] VR = VIN + I×R

[0059] During the holding period, the reset signal RST becomes low level. Then, the switch 702 is turned off. When the input voltage signal VIN at the input terminal IN is lower than the lowest voltage value held by the capacitor 703, the comparator 701 outputs a high level, the switch 704 is turned on, and the lowest voltage value held by the capacitor 703 decreases. In contrast, when the input voltage signal VIN at the input terminal IN is higher than the lowest voltage value held by the capacitor 703, the comparator 701 outputs a low level, the switch 704 is turned off, and the capacitor 703 maintains the lowest voltage value.

[0060] The comparator 701, capacitor 703, switch 704, and constant current source 705 are holding circuits that perform the operation of holding the lowest voltage value of the input voltage signal VIN during the holding period in accordance with each processing cycle. When the voltage value of the input voltage signal VIN is less than the lowest voltage value held by the capacitor 703, the switch 704 connects the capacitor 703 to the reference potential node.

[0061] During the reset period, the reset signal RST is at a high level. Then, the switch 702 is turned on, the capacitor 703 holds the voltage value of the reset voltage signal VR, and the output voltage VOUT becomes the reset voltage signal VR. The switch 704 is turned off.

[0062] During the holding period, the voltage holding circuit 302 holds the lowest voltage value of the input voltage signal VIN at the input terminal IN and outputs this lowest voltage value as the output voltage VOUT.

[0063] The switch 702 is a reset circuit that resets the output voltage VOUT based on the reset voltage signal VR during each processing cycle and during the reset period.

[0064] The dead time 801 is the period during which the capacitor 703 is reset by the high-level reset signal RST, and it is the period during which the voltage holding circuit 302 cannot output an appropriate minimum voltage value. Since the difference between the input voltage signal VIN and the reset voltage signal VR is small, the dead time 801 can be shortened. The dead time 801 is shorter than Figure 6 the dead time 601.

[0065] In addition, since the capacitor 703 is not directly connected to the power supply voltage node, the voltage holding circuit 302 can resist high-frequency fluctuations in the power supply voltage.

[0066] Furthermore, the voltage holding circuit 302 can reverse the direction of the current by changing the circuit configuration from the Figure 7 circuit shown to form a circuit that holds the highest voltage value with respect to the input voltage signal VIN. In this case, the operational amplifier 707, resistor 708, capacitor 709, and constant current source 710 are generating circuits that generate a reset voltage signal VR that varies according to the input voltage signal VIN. The comparator 701, capacitor 703, switch 704, and constant current source 705 are holding circuits that perform the operation of holding the highest voltage value with respect to the input voltage signal VIN during the holding period. The switch 702 is a reset circuit that resets the output voltage VOUT based on the reset voltage signal VR during the reset period.

[0067] (Second Embodiment)

[0068] Figure 9 is a circuit diagram showing a configuration example of the voltage holding circuit 302 according to the second embodiment. The voltage holding circuit 302 includes: a comparator 901, AND circuits 902, 903, a constant current source 904, switches 905, 906, a constant current source 907, a capacitor 908, and an operational amplifier 909. The switches 905, 906 are, for example, n-channel field effect transistors.

[0069] The - input terminal of the comparator 901 is connected to the input terminal IN, and the + input terminal is connected to the + input terminal of the operational amplifier 909. The AND circuit 902 outputs a logical product signal of the reset signal RST and the logically inverted signal of the output signal of the comparator 901 to the control terminal of the switch 905. The AND circuit 903 outputs a logical product signal of the output signal of the comparator 901 and the logically inverted signal of the reset signal RST to the control terminal of the switch 906.

[0070] The constant current source 904 is connected between the power supply voltage node and the switch 905. The switch 905 is connected between the constant current source 904 and the + input terminal of the operational amplifier 909. The switch 906 is connected between the + input terminal of the operational amplifier 909 and the constant current source 907. The constant current source 907 is connected between the switch 906 and the reference potential node. The capacitor 908 is connected between the + input terminal of the operational amplifier 909 and the reference potential node. The - input terminal and the output terminal of the operational amplifier 909 are connected to the output terminal OUT.

[0071] Figure 10 is a diagram showing Figure 9 the voltage waveform for explaining the operation of the voltage holding circuit 302. The horizontal axis represents time T, and the vertical axis represents voltage V. The input voltage signal VIN is the voltage of the input terminal IN. The output voltage VOUT is the voltage of the output terminal OUT. The voltage holding circuit 302 operates in accordance with each processing cycle. In accordance with each processing cycle, the minimum voltage value of the input voltage signal VIN at the input terminal IN is held, and this processing cycle includes a holding period and a reset period immediately following the holding period.

[0072] The high level period of the reset signal RST is the reset period. The low level period of the reset signal RST is the holding period.

[0073] The comparator 901, the AND circuit 903, the switch 906, the constant current source 907, and the capacitor 908 are holding circuits, and in accordance with each processing cycle, they perform the operation of holding the minimum voltage value of the input voltage signal VIN during the holding period. During the holding period, since it is the period when the reset signal RST is at a low level, the output signal of the AND circuit 903 changes according to the output signal of the comparator 901. Therefore, during the holding period, the switch 906 becomes in a conductive state, and when the voltage value of the input voltage signal VIN is less than the minimum voltage value held by the capacitor 908, the capacitor 908 is connected to the constant current source 907 and the reference potential node (for example, the ground potential node). In addition, the direction of the current of the constant current source 907 is the direction (the first direction) of extracting charge from the capacitor 908. On the other hand, for the switch 906, during the reset period, since it is the period when the reset signal RST is at a high level, the output signal of the AND circuit 903 is fixed at a low level. Therefore, the switch 906 is opened during the reset period.

[0074] Comparator 901, AND circuit 902, constant current source 904, switch 905, and capacitor 908 are hold circuits that perform the operation of holding the highest voltage value of the input voltage signal VIN during the reset period immediately following the hold period in each processing cycle. During the reset period, which is the period when the reset signal RST is at a high level, the output signal of the AND circuit 902 changes according to the output signal of the comparator 901. Therefore, during the reset period, the switch 905 becomes conductive, and when the voltage value of the input voltage signal VIN is greater than the highest voltage value held by the capacitor 908, the capacitor 908 is connected to the constant current source 904 and the power supply voltage node. In addition, the direction of the current of the constant current source 904 is the direction (second direction) of injecting charge into the capacitor 908. On the other hand, for the switch 905, during the hold period, which is the period when the reset signal RST is at a low level, the output signal of the AND circuit 902 is fixed at a low level. Therefore, the switch 905 is turned off during the hold period.

[0075] During the reset period, the voltage holding circuit 302 holds the highest voltage value, so the dead time can be shortened.

[0076] In addition, the voltage holding circuit 302 can reverse the direction of the current by changing the circuit configuration from the Figure 9 shown circuit to form a circuit that holds the highest voltage value of the input voltage signal VIN during the hold period. In this case, comparator 901, AND circuit 903, switch 906, constant current source 907, and capacitor 908 are hold circuits that perform the operation of holding the highest voltage value of the input voltage signal VIN during the hold period. Comparator 901, AND circuit 902, constant current source 904, switch 905, and capacitor 908 are hold circuits that perform the operation of holding the lowest voltage value of the input voltage signal VIN during the reset period immediately following the hold period.

[0077] (Third Embodiment)

[0078] Figure 11 is a circuit diagram showing a configuration example of the voltage holding circuit 302 according to the third embodiment. Figure 11 is relative to Figure 9 by deleting the constant current sources 904, 907 and the switches 905, 906 and adding an OR circuit 1101, a switch 1102, and a bidirectional current source 1103. Figure 11 The voltage holding circuit 302 of Figure 9 performs the same operation as the voltage holding circuit 302 of

[0079] The logic sum circuit 1101 outputs the logic sum signal of the output signal of the logic product circuit 902 and the output signal of the logic product circuit 03 to the control terminal of the switch 1102. The switch 1102 is connected between the + input terminal of the operational amplifier 909 and the bidirectional current source 1103. The bidirectional current source 1103 is a current source having switches 1104, 1105, resistors 1106 to 1110, and operational amplifiers 1111, 1112, and the direction of the current is opposite during the hold period and the reset period immediately following the hold period. The switches 1104, 1105 are, for example, n-channel field effect transistors.

[0080] Figure 12 is a diagram showing Figure 11 the voltage waveform and current waveform for explaining the operation of the voltage holding circuit 302. The input voltage signal VIN is the voltage of the input terminal IN. The output voltage VOUT is the voltage of the output terminal OUT. The voltage holding circuit 302 operates in accordance with each processing cycle, and in accordance with each processing cycle, holds the lowest voltage value of the input voltage signal VIN at the input terminal IN. This processing cycle includes a hold period and a reset period immediately following the hold period.

[0081] The high level period of the reset signal RST is the reset period. The low level period of the reset signal RST is the hold period.

[0082] During the hold period, the reset signal RST is at a low level. Accordingly, the switch 1105 is turned off and the switch 1104 is turned on, and the voltage REF becomes the voltage REF1. The voltage REF1 is a positive voltage. The current I flowing through the switch 1102 is the positive current I1. The positive current I1 is a current flowing in the direction (first direction) of extracting charge from the capacitor 908. That is, the direction of the current of the bidirectional current source 1103 becomes the direction (first direction) of extracting charge from the capacitor 908 during the hold period according to the level of the reset signal RST. The comparator 901, the logic product circuit 903, the switch 1102, the bidirectional current source 1103, and the capacitor 908 are hold circuits, and perform the operation of holding the lowest voltage value of the input voltage signal VIN during the hold period in accordance with each processing cycle.

[0083] If the resistance value of the resistor 1110 is set to R, the current I flowing through the switch 1102 is represented by the following equation.

[0084] I = REF / R

[0085] During the reset period, the reset signal RST is at a high level. Then, switch 1104 is turned off and switch 1105 is turned on, and voltage REF becomes voltage REF2. Voltage REF2 is a negative voltage. The current I flowing through switch 1102 becomes a negative current I2. The negative current I2 is a current flowing in the direction of injecting charge into capacitor 908 (the second direction). That is, the direction of the current of the bidirectional current source 1103 becomes the direction of injecting charge into capacitor 908 (the second direction) during the reset period according to the level of the reset signal RST, which is opposite to the direction of the current during the holding period. Comparator 901, AND circuit 902, switch 1102, bidirectional current source 1103, and capacitor 908 are a holding circuit, and perform the operation of holding the highest voltage value of the input voltage signal VIN during the reset period immediately following the holding period for each processing cycle.

[0086] In addition, the voltage holding circuit 302 can reverse the direction of the current by changing the circuit configuration from the Figure 11 circuit shown, thereby forming a circuit that holds the highest voltage value of the input voltage signal VIN during the holding period. In this case, comparator 901, AND circuit 903, switch 1102, bidirectional current source 1103, and capacitor 908 are a holding circuit, and perform the operation of holding the highest voltage value of the input voltage signal VIN during the holding period. Comparator 901, AND circuit 902, switch 1102, bidirectional current source 1103, and capacitor 908 are a holding circuit, and perform the operation of holding the lowest voltage value of the input voltage signal VIN during the reset period immediately following the holding period.

[0087] (Fourth Embodiment)

[0088] Figure 13 is a circuit diagram showing a configuration example of the voltage holding circuit 302 according to the fourth embodiment. The voltage holding circuit 302 includes: comparator 1301, AND circuits 1302 and 1303, constant current source 1304, switches 1305 and 1306, constant current source 1307, capacitor 1308, operational amplifier 1309, and determination circuit 1310. The determination circuit 1310 includes: resistor 1311, capacitor 1312, and comparator 1313.

[0089] The - input terminal of comparator 1301 is connected to the input terminal IN, and the + input terminal is connected to the + input terminal of operational amplifier 1309. AND circuit 1302 outputs a logical product signal of the logical inversion signal of signal CONT and the output signal of comparator 1301 to the control terminal of switch 1305. AND circuit 1303 outputs a logical product signal of the output signal of comparator 1301 and the logical inversion signal of signal CONT to the control terminal of switch 1306.

[0090] The constant current source 1304 is connected between the power supply voltage node and the switch 1305. The switch 1305 is connected between the constant current source 1304 and the + input terminal of the operational amplifier 1309. The switch 1306 is connected between the + input terminal of the operational amplifier 1309 and the constant current source 1307. The constant current source 1307 is connected between the switch 1306 and the reference potential node. The capacitor 1308 is connected between the + input terminal of the operational amplifier 1309 and the reference potential node. The - input terminal and the output terminal of the operational amplifier 1309 are connected to the output terminal OUT.

[0091] The resistor 1311 is connected between the input terminal IN and the + input terminal of the comparator 1313. The capacitor 1312 is connected between the + input terminal of the comparator 1313 and the reference potential node. The output terminal of the comparator 1313 outputs the signal CONT.

[0092] Figure 14 is a diagram showing the voltage waveform for explaining Figure 13 the operation of the voltage holding circuit 302. The horizontal axis represents the time T, and the vertical axis represents the voltage V. The input voltage signal VIN is the voltage of the input terminal IN. The output voltage VOUT is the voltage of the output terminal OUT. The voltage 1401 is the voltage of the + input terminal of the comparator 1313 and is a signal that delays the input voltage signal VIN.

[0093] The determination circuit 1310 is a differentiating circuit that determines the increase or decrease of the input voltage signal VIN. When the input voltage signal VIN increases, the determination circuit 1310 outputs a signal CONT with a low level. The comparator 1301, the AND circuit 1303, the switch 1306, the constant current source 307, and the capacitor 1308 are holding circuits, and perform the operation of holding the lowest voltage value of the input voltage signal VIN for each period (the first period) in which the determination circuit 1310 determines the increase of the input voltage signal VIN. During the period in which the determination circuit 1310 determines the increase of the input voltage signal, when the input voltage signal VIN increases and the voltage value of the input voltage signal VIN is less than the lowest voltage value held by the capacitor 1308, the switch 1306 connects the capacitor 1308 to the reference potential node.

[0094] When the input voltage signal VIN decreases, the determination circuit 1310 outputs a high-level signal CONT. The comparator 1301, the AND circuit 1302, the constant current source 1304, the switch 1305, and the capacitor 1308 are holding circuits. During each period (the second period) when the determination circuit 1310 determines the decrease of the input voltage signal VIN, when the input voltage signal VIN decreases, an operation of holding the highest voltage value of the input voltage signal VIN is performed. During the period when the determination circuit 1310 determines the decrease of the input voltage signal, when the input voltage signal VIN decreases and the voltage value of the input voltage signal VIN is greater than the highest voltage value held by the capacitor 1308, the switch 1305 connects the capacitor 1308 to the power supply voltage node.

[0095] As described above, when the input voltage signal VIN increases, the voltage holding circuit 302 holds the lowest voltage value of the input voltage signal VIN, and when the input voltage signal VIN decreases, it holds the highest voltage value of the input voltage signal VIN. Thereby, the dead time can be shortened.

[0096] (Fifth Embodiment)

[0097] Figure 15 FIG. is a configuration example diagram of a voltage monitoring circuit according to the fifth embodiment. The voltage monitoring circuit includes: a plurality of voltage holding circuits 302, an analog / digital converter 303, and a switching circuit 1501 provided between the plurality of voltage holding circuits 302 and the analog / digital converter 303. The plurality of voltage holding circuits 302 are the voltage holding circuits 302 of the first to fourth embodiments, and respectively hold the lowest voltage value or the highest voltage value of the power supply voltage node 1502 to be monitored. That is, the input voltage signal VIN of each voltage holding circuit 302 is the power supply voltage of the corresponding power supply voltage node 1502 to be monitored. The switching circuit 1501 outputs the lowest voltage value or the highest voltage value held by the plurality of voltage holding circuits 302 to the analog / digital converter 303 in a time-sharing manner. The analog / digital converter 303 sequentially converts the lowest voltage value or the highest voltage value output by the switching circuit 1501 in a time-sharing manner from analog to digital. The voltage monitoring circuit can monitor the lowest voltage value or the highest voltage value of a plurality of power supply voltage nodes 1502 using a smaller number of analog / digital converters 303 than the number of power supply voltage nodes 1502.

[0098] Figure 16 FIG. is a configuration example diagram of a semiconductor integrated circuit 1600 according to the fifth embodiment. The semiconductor integrated circuit has Figure 15A voltage monitoring circuit and a power supply voltage network 1601. A power supply voltage is applied to the power supply voltage network 1601. A plurality of voltage holding circuits 302 can monitor the power supply voltages of a plurality of power supply voltage nodes in the power supply voltage network 1601 and hold the lowest voltage value or the highest voltage value thereof.

[0099] (Sixth Embodiment)

[0100] Figure 17 FIG. is a diagram showing a configuration example of a semiconductor integrated circuit 1700 according to the sixth embodiment. The semiconductor integrated circuit 1700 includes: a power input terminal 1703, a power supply voltage network 1601, an internal circuit 1701, a plurality of voltage holding circuits 302, a switching circuit 1501, an analog / digital converter 303, a control logic circuit 1702, and a control output terminal 1704.

[0101] The power supply circuit 1710 includes: a control unit 1711, an output unit 1712, a power input terminal 1713, a control input terminal 1714, and a power output terminal 1715. The power input terminal 1713 is connected to the system power supply voltage node 1716.

[0102] The output unit 1712 supplies a power supply voltage to the power supply voltage network 1601 via the power output terminal 1715 and the power input terminal 1703. A plurality of power supply voltage nodes 1502 are provided in the power supply voltage network 1601 and are nodes to be voltage-held. The internal circuit 1701 receives the supply of the power supply voltage from the plurality of power supply voltage nodes 1502 and performs processing. As a result, the power supply voltage of the power supply voltage node 1502 varies.

[0103] The plurality of voltage holding circuits 302 are the voltage holding circuits 302 of the first to fourth embodiments and hold the lowest voltage value or the highest voltage value of the plurality of power supply voltage nodes 1502, respectively. That is, the input voltage signal VIN of each voltage holding circuit 302 is the power supply voltage of the corresponding power supply voltage node 1502 to be monitored. The switching circuit 1501 outputs the lowest voltage value or the highest voltage value held by the plurality of voltage holding circuits 302 to the analog / digital converter 303 in a time-division manner. The analog / digital converter 303 converts the lowest voltage value or the highest voltage value input in a time-division manner from the switching circuit 1501 from analog to digital.

[0104] The control logic circuit 1702 receives the digital minimum voltage value or the digital maximum voltage value from the analog / digital converter 303, and outputs a control signal for controlling the power supply voltage to the control unit 1711 via the control output terminal 1704 and the control input terminal 1714. The control unit 1711 controls the output unit 1712 based on the control signal. The output unit 1712 outputs a power supply voltage corresponding to the control signal to the power supply voltage network 1601 via the power supply output terminal 1715 and the power supply input terminal 1703. Thereby, dynamic voltage scaling is performed.

[0105] (Seventh Embodiment)

[0106] Figure 18 FIG. is a diagram showing a configuration example of the semiconductor integrated circuit 1700 according to the seventh embodiment. Figure 18 of the semiconductor integrated circuit 1700 with respect to Figure 17 of the semiconductor integrated circuit 1700, the power supply circuit 1710 is deleted, and the power supply circuit 1801 is added. The power supply circuit 1801 is provided inside the semiconductor integrated circuit 1700. The system power supply voltage node 1716 is connected to the power supply circuit 1801 via the power supply input terminal 1703. The control logic circuit 1702 receives the digital minimum voltage value or the digital maximum voltage value from the analog / digital converter 303, and outputs a control signal for controlling the power supply voltage to the power supply circuit 1801. The power supply circuit 1801 controls the power supply voltage supplied to the power supply voltage network 1601 based on the control signal output by the control logic circuit 1702.

[0107] (Eighth Embodiment)

[0108] Figure 19 FIG. is a diagram showing a configuration example of the semiconductor integrated circuit 1700 according to the eighth embodiment. Figure 19 of the semiconductor integrated circuit 1700 with respect to Figure 18 of the semiconductor integrated circuit 1700, the power supply circuit 1801 is deleted, and the safety mechanism block 1901 is added. The safety mechanism block 1901 is a circuit that detects an abnormality in the minimum voltage value or the maximum voltage value of the power supply voltage supplied from the plurality of power supply voltage nodes 1502 based on the control signal output by the control logic circuit 1702, and outputs a reset signal or an alarm signal to ensure safety in the event of an abnormality. The internal circuit 1701, for example, receives the reset signal from the safety mechanism block 1901 and resets the internal operation. In addition, the internal circuit 1701, for example, receives the alarm signal from the safety mechanism block 1901 and changes the internal operation conditions and operation modes.

[0109] (Ninth Embodiment)

[0110] Figure 20This is a diagram showing a configuration example of the semiconductor integrated circuit 1700 according to the ninth embodiment. Figure 20 The semiconductor integrated circuit 1700 with respect to Figure 17 the semiconductor integrated circuit 1700, the internal circuit 1701, the power input terminal 1703, and the control output terminal 1704 are deleted, and the signal input terminal 2002 and the signal processing module 2003 are added. The multiple signal sources 2001 are, for example, sensors with a high-speed voltage displacement, and are respectively connected to the multiple voltage holding circuits 302 via the multiple signal input terminals 2002. The multiple voltage holding circuits 302 are the voltage holding circuits 302 of the first to fourth embodiments, and respectively hold the lowest voltage value or the highest voltage value of the multiple signal sources 2001. That is, the input voltage signal VIN of each voltage holding circuit 302 is the output signal of the corresponding monitored signal source 200. The control logic circuit 1702 receives the digital lowest voltage value or highest voltage value from the analog / digital converter 303, and outputs a control signal for controlling signal processing to the signal processing module 2003. The signal processing module 2003 is a circuit that performs signal processing based on the control signal output by the control logic circuit 1702.

[0111] (Other embodiments)

[0112] Figure 21 This is a circuit diagram showing a configuration example of the above operational amplifier. The source of the p-channel field effect transistor 2101 is connected to the power supply voltage node, and the gate is connected to the drain. The drain of the n-channel field effect transistor 2105 is connected to the drain of the p-channel field effect transistor 2101, the gate is connected to the - input terminal (inverting input terminal), and the source is connected to the drain of the n-channel field effect transistor 2107.

[0113] The source of the p-channel field effect transistor 2102 is connected to the power supply voltage node, the gate is connected to the gate of the p-channel field effect transistor 2101, and the drain is connected to the drain of the n-channel field effect transistor 2106. The gate of the n-channel field effect transistor 2106 is connected to the + input terminal (non-inverting input terminal), and the source is connected to the drain of the n-channel field effect transistor 2107. The gate of the n-channel field effect transistor 2107 is connected to the bias terminal, and the source is connected to the reference potential node.

[0114] The gate of the n-channel field effect transistor 2108 inputs a power-off signal. The inverter 2110 outputs a logic inverted signal of the power-off signal to the gate of the p-channel field effect transistor 2103.

[0115] The source of the p-channel field-effect transistor 2103 is connected to the power supply voltage node, and the drain is connected to the drain of the n-channel field-effect transistor 2106. The drain of the n-channel field-effect transistor 2108 is connected to the bias terminal, and the source is connected to the reference potential node.

[0116] The source of the p-channel field-effect transistor 2104 is connected to the power supply voltage node, the gate is connected to the drain of the p-channel field-effect transistor 2103, and the drain is connected to the output terminal. The drain of the n-channel field-effect transistor 2109 is connected to the output terminal, the gate is connected to the bias terminal, and the source is connected to the reference potential node.

[0117] When the power-off signal is at a low level, the p-channel field-effect transistor 2103 and the n-channel field-effect transistor 2108 are turned off, and the operational amplifier operates normally.

[0118] When the power-off signal is at a high level, the p-channel field-effect transistor 2103 and the n-channel field-effect transistor 2108 are turned on, and the p-channel field-effect transistor 2104 and the n-channel field-effect transistor 2109 are turned off. The operational amplifier is in an off state, and power saving can be achieved.

[0119] Figure 22 It is a diagram showing the reset mode of the comparator described above. Figure 23 It is a diagram showing the comparison mode of the comparator described above. The comparator alternately repeats Figure 22 the reset mode and the comparison mode.

[0120] The source of the p-channel field-effect transistor 2201 is connected to the power supply potential node, the gate is connected to the first input terminal, and the drain is connected to the source of the p-channel field-effect transistor 2203. The source of the p-channel field-effect transistor 2202 is connected to the power supply potential node, the gate is connected to the second input terminal, and the drain is connected to the source of the p-channel field-effect transistor 2204.

[0121] The gate of the p-channel field-effect transistor 2203 is connected to the second output terminal, and the drain is connected to the first output terminal. The gate of the p-channel field-effect transistor 2204 is connected to the first output terminal, and the drain is connected to the second output terminal.

[0122] The drain of the n-channel field-effect transistor 2205 is connected to the first output terminal, the gate is connected to the second output terminal, and the source is connected to the reference potential node. The drain of the n-channel field-effect transistor 2206 is connected to the second output terminal, the gate is connected to the first output terminal, and the source is connected to the reference potential node.

[0123] The switch 2207 is connected between the first output terminal and the reference potential node. In Figure 22 the reset mode, the switch 2207 and the switch 2208 are turned on. InFigure 23 In the comparison mode, switches 2207 and 2208 are turned off.

[0124] The p-channel transistor 2203 and the n-channel field effect transistor 2205 form an inverter. The p-channel transistor 2204 and the n-channel field effect transistor 2206 form an inverter.

[0125] If moving from Figure 22 the reset mode to Figure 23 the comparison mode, according to the magnitude relationship between the first input terminal and the second input terminal, either the p-channel field effect transistor 2201 or the p-channel field effect transistor 2202 conducts. The first output terminal and the second output terminal output the comparison result.

[0126] Figure 24 It is a circuit diagram showing a configuration example of the above constant current source. The + input terminal of the operational amplifier 2401 is connected to the reference voltage input node, the - input terminal is connected to the source of the n-channel field effect transistor 2404, and the output terminal is connected to the gate of the n-channel field effect transistor 2404. The reference voltage input node is connected to the bandgap circuit or an external stabilized power supply.

[0127] The source of the p-channel field effect transistor 2402 is connected to the power supply voltage node, and the gate and the drain are connected to the drain of the n-channel field effect transistor 2404. The resistor 2405 is connected between the source of the n-channel field effect transistor 2404 and the reference potential node. Through the operational amplifier 2401, the source of the n-channel field effect transistor 2404 is always maintained at the same voltage as the reference voltage input node. Thus, a constant current flows through the resistor 2405.

[0128] The source of the p-channel field effect transistor 2403 is connected to the power supply voltage node, the gate is connected to the gate of the p-channel field effect transistor 2402, and the drain is connected to the constant current output node. The p-channel field effect transistors 2402 and 2403 form a current mirror circuit. By adjusting the sizes of the p-channel field effect transistors 2402 and 2403, the mirror ratio can be changed, and the value of the constant current can be changed.

[0129] Figure 25 It is a circuit diagram showing a configuration example of the above inverter. The source of the p-channel field effect transistor 2501 is connected to the power supply voltage node, the gate is connected to the input terminal, and the drain is connected to the output terminal. The drain of the n-channel field effect transistor 2502 is connected to the output terminal, the gate is connected to the input terminal, and the source is connected to the reference potential node.

[0130] Figure 26This is a circuit diagram showing a configuration example of the above-mentioned logical product circuit. The source of the p-channel field-effect transistor 2601 is connected to the power supply voltage node, the gate is connected to the second input terminal, and the drain is connected to the drain of the n-channel field-effect transistor 2604. The source of the p-channel field-effect transistor 2602 is connected to the power supply voltage node, the gate is connected to the first input terminal, and the drain is connected to the drain of the n-channel field-effect transistor 2604.

[0131] The gate of the n-channel field-effect transistor 2604 is connected to the first input terminal, the source is connected to the drain of the n-channel field-effect transistor 2605. The gate of the n-channel field-effect transistor 2605 is connected to the second input terminal, and the source is connected to the reference potential node.

[0132] The source of the p-channel field-effect transistor 2603 is connected to the power supply voltage node, the gate is connected to the drain of the n-channel field-effect transistor 2604, and the source is connected to the output terminal. The drain of the n-channel field-effect transistor 2606 is connected to the output terminal, the gate is connected to the drain of the n-channel field-effect transistor 2604, and the source is connected to the reference potential node.

[0133] Figure 27 This is a circuit diagram showing a configuration example of the above-mentioned logical sum circuit. The source of the p-channel field-effect transistor 2701 is connected to the power supply voltage node, the gate is connected to the first input terminal, and the drain is connected to the source of the p-channel field-effect transistor 2702. The gate of the p-channel field-effect transistor 2702 is connected to the second input terminal, and the drain is connected to the drain of the n-channel field-effect transistor 2705.

[0134] The drain of the n-channel field-effect transistor 2704 is connected to the drain of the n-channel field-effect transistor 2705, the gate is connected to the first input terminal, and the source is connected to the reference potential node. The gate of the n-channel field-effect transistor 2705 is connected to the second input terminal, and the source is connected to the reference potential node.

[0135] The source of the p-channel field-effect transistor 2703 is connected to the power supply voltage node, the gate is connected to the drain of the n-channel field-effect transistor 2705, and the drain is connected to the output terminal. The drain of the n-channel field-effect transistor 2706 is connected to the output terminal, the gate is connected to the drain of the n-channel field-effect transistor 2705, and the source is connected to the reference potential node.

[0136] In addition, the above-mentioned embodiments are only examples showing the concretization of implementing the present invention, and the technical scope of the present invention cannot be limitedly interpreted by them. That is, the present invention can be implemented in various ways without departing from its technical idea or its main features.

[0137] For the above embodiments, the following remarks are also disclosed.

[0138] (Supplementary Note 1)

[0139] A voltage holding circuit that operates according to each processing cycle and holds the voltage value of an input voltage signal. The processing cycle includes a holding period and a reset period immediately following the holding period. The voltage holding circuit has:

[0140] A first holding circuit that, according to each of the above-mentioned processing cycles, performs an operation of holding the lowest voltage value of the input voltage signal during the holding period; and

[0141] A second holding circuit that, according to each of the above-mentioned processing cycles, performs an operation of holding the highest voltage value of the input voltage signal during the reset period.

[0142] (Supplementary Note 2)

[0143] The voltage holding circuit according to Supplementary Note 1, wherein

[0144] The first holding circuit has a first switch. When the voltage value of the input voltage signal is less than the voltage value held by the capacitor, the first switch connects the capacitor to a reference potential node having a potential lower than the power supply voltage node.

[0145] The second holding circuit has a second switch. When the voltage value of the input voltage signal is greater than the voltage value held by the capacitor, the second switch connects the capacitor to the power supply voltage node.

[0146] (Supplementary Note 3)

[0147] The voltage holding circuit according to Supplementary Note 2, wherein

[0148] A reset signal indicating the holding period or the reset period is input.

[0149] When the reset signal indicates the holding period, the first switch becomes in an on state. When the reset signal indicates the reset period, the first switch is turned off.

[0150] When the reset signal indicates the reset period, the second switch becomes in an on state. When the reset signal indicates the holding period, the second switch is turned off.

[0151] (Supplementary Note 4)

[0152] The voltage holding circuit according to Supplementary Note 1, wherein

[0153] The above-mentioned first holding circuit has a third switch. When the voltage value of the above-mentioned input voltage signal is less than the voltage value held by the capacitor, the above-mentioned third switch connects the above-mentioned capacitor to a first current source with the current direction being the first direction.

[0154] The above-mentioned second holding circuit has a fourth switch. When the voltage value of the above-mentioned input voltage signal is greater than the voltage value held by the capacitor, the above-mentioned fourth switch connects the above-mentioned capacitor to a second current source with the current direction being the second direction, and the second direction is opposite to the first direction.

[0155] (Appendix 5)

[0156] The voltage holding circuit according to Appendix 4, wherein,

[0157] The above-mentioned first and second current sources are constituted by a bidirectional current source with opposite current directions during the above-mentioned holding period and the above-mentioned reset period.

[0158] (Appendix 6)

[0159] The voltage holding circuit according to Appendix 5, wherein,

[0160] A reset signal indicating the above-mentioned holding period or the above-mentioned reset period is input.

[0161] The above-mentioned bidirectional current source changes the current direction according to the above-mentioned reset signal.

[0162] (Appendix 7)

[0163] A voltage holding circuit operates according to each processing cycle to hold the voltage value of an input voltage signal. This processing cycle includes a holding period and a reset period immediately following the above-mentioned holding period. The above-mentioned voltage holding circuit has:

[0164] A generating circuit that generates a reset voltage signal that varies according to the above-mentioned input voltage signal;

[0165] A holding circuit that, according to each of the above-mentioned processing cycles, performs an operation of holding the lowest voltage value of the above-mentioned input voltage signal during the above-mentioned holding period; and

[0166] A reset circuit that, according to each of the above-mentioned processing cycles, resets the output voltage based on the above-mentioned reset voltage signal during the above-mentioned reset period.

[0167] (Appendix 8)

[0168] The voltage holding circuit according to Appendix 7, wherein,

[0169] The above-mentioned holding circuit has a switch. When the voltage value of the above-mentioned input voltage signal is less than the voltage value held by the capacitor, the above-mentioned switch connects the above-mentioned capacitor to a reference potential node.

[0170] (Supplementary Note 9)

[0171] A voltage holding circuit according to Supplementary Note 7 or 8, wherein,

[0172] The generation circuit generates the reset voltage signal to have a voltage value differing from the voltage value of the input voltage signal by a first value.

[0173] (Supplementary Note 10)

[0174] A voltage holding circuit that holds a voltage value for an input voltage signal, comprising:

[0175] A determination circuit that determines an increase or decrease in the input voltage signal;

[0176] A first holding circuit that, for each first period, performs an operation of holding the lowest voltage value for the input voltage signal, wherein the first period is a period during which the determination circuit determines an increase in the input voltage signal; and

[0177] A second holding circuit that, for each second period, performs an operation of holding the highest voltage value for the input voltage signal, wherein the second period is a period during which the determination circuit determines a decrease in the input voltage signal.

[0178] (Supplementary Note 11)

[0179] A voltage holding circuit according to Supplementary Note 10, wherein,

[0180] The first holding circuit has a first switch that, during the first period, connects the capacitor to a reference potential node when the voltage value of the input voltage signal is less than the voltage value held by the capacitor,

[0181] The second holding circuit has a second switch that, during the second period, connects the capacitor to a power supply voltage node when the voltage value of the input voltage signal is greater than the voltage value held by the capacitor.

[0182] (Supplementary Note 12)

[0183] A voltage holding circuit that operates for each processing cycle and holds a voltage value for an input voltage signal, the processing cycle including a holding period and a reset period immediately following the holding period, the voltage holding circuit comprising:

[0184] A first holding circuit that, for each of the processing cycles, performs an operation of holding the highest voltage value for the input voltage signal during the holding period; and

[0185] A second holding circuit performs an operation of holding the lowest voltage value of the input voltage signal during the reset period in each of the above-mentioned processing cycles.

[0186] (Appendix 13)

[0187] A voltage holding circuit operates according to each processing cycle to hold the voltage value of an input voltage signal. The processing cycle includes a holding period and a reset period immediately following the holding period. The voltage holding circuit includes:

[0188] A generation circuit that generates a reset voltage signal that varies according to the input voltage signal;

[0189] A holding circuit that performs an operation of holding the highest voltage value of the input voltage signal during the holding period in each of the above-mentioned processing cycles; and

[0190] A reset circuit that resets the output voltage based on the reset voltage signal during the reset period in each of the above-mentioned processing cycles.

[0191] (Appendix 14)

[0192] A voltage monitoring circuit includes:

[0193] A voltage holding circuit that operates according to each processing cycle to hold the voltage value of an input voltage signal, where the processing cycle includes a holding period and a reset period immediately following the holding period; and

[0194] An analog / digital converter that converts the voltage value held by the voltage holding circuit from analog to digital.

[0195] The voltage holding circuit includes:

[0196] A first holding circuit that performs an operation of holding the lowest voltage value of the input voltage signal during the holding period in each of the above-mentioned processing cycles; and

[0197] A second holding circuit that performs an operation of holding the highest voltage value of the input voltage signal during the reset period in each of the above-mentioned processing cycles.

[0198] (Appendix 15)

[0199] A voltage monitoring circuit includes:

[0200] A voltage holding circuit that operates according to each processing cycle to hold the voltage value of an input voltage signal. The processing cycle includes a holding period and a reset period immediately following the holding period; and

[0201] An analog / digital converter that converts the voltage value held by the voltage holding circuit from analog to digital.

[0202] The above voltage holding circuit has:

[0203] A generating circuit that generates a reset voltage signal that varies according to the above input voltage signal;

[0204] A holding circuit that, for each of the above processing cycles, performs an operation of holding the lowest voltage value of the above input voltage signal during the above holding period; and

[0205] A reset circuit that, for each of the above processing cycles, resets the output voltage based on the above reset voltage signal during the above reset period.

[0206] (Supplementary Note 16)

[0207] A voltage monitoring circuit having:

[0208] A voltage holding circuit that holds a voltage value of an input voltage signal; and

[0209] An analog / digital converter that converts the voltage value held by the above voltage holding circuit from analog to digital,

[0210] The above voltage holding circuit has:

[0211] A determination circuit that determines an increase or decrease in the above input voltage signal;

[0212] A first holding circuit that, for each first period, performs an operation of holding the lowest voltage value of the above input voltage signal, where the above first period is a period in which the above determination circuit determines an increase in the above input voltage signal; and

[0213] A second holding circuit that, for each second period, performs an operation of holding the highest voltage value of the above input voltage signal, where the above second period is a period in which the above determination circuit determines a decrease in the above input voltage signal.

[0214] (Supplementary Note 17)

[0215] A voltage monitoring circuit having:

[0216] A voltage holding circuit that operates for each processing cycle and holds a voltage value of an input voltage signal, where the above processing cycle includes a holding period and a reset period immediately following the above holding period; and

[0217] An analog / digital converter that converts the voltage value held by the above voltage holding circuit from analog to digital,

[0218] The above voltage holding circuit has:

[0219] A first holding circuit that, for each of the above-described processing cycles, performs an operation of holding the highest voltage value of the input voltage signal during the above-described holding period; and

[0220] A second holding circuit that, for each of the above-described processing cycles, performs an operation of holding the lowest voltage value of the input voltage signal during the above-described reset period.

[0221] (Supplementary Note 18)

[0222] A voltage monitoring circuit having:

[0223] A voltage holding circuit that operates for each processing cycle to hold a voltage value of an input voltage signal, where the above-described processing cycle includes a holding period and a reset period immediately following the above-described holding period; and

[0224] An analog / digital converter that converts the voltage value held by the above-described voltage holding circuit from analog to digital,

[0225] The above-described voltage holding circuit has:

[0226] A generation circuit that generates a reset voltage signal that varies according to the above-described input voltage signal;

[0227] A holding circuit that, for each of the above-described processing cycles, performs an operation of holding the highest voltage value of the above-described input voltage signal during the above-described holding period; and

[0228] A reset circuit that, for each of the above-described processing cycles, resets the output voltage based on the above-described reset voltage signal during the above-described reset period.

[0229] (Supplementary Note 19)

[0230] The voltage monitoring circuit according to any one of Supplementary Notes 14 to 18, wherein

[0231] There are a plurality of the above-described voltage holding circuits, wherein

[0232] A switching circuit is further provided between the plurality of the above-described voltage holding circuits and the above-described analog / digital converter,

[0233] The above-described switching circuit outputs the voltage values held by the plurality of the above-described voltage holding circuits to the above-described analog / digital converter in a time-division manner.

[0234] (Supplementary Note 20)

[0235] A semiconductor integrated circuit having:

[0236] An internal circuit that processes based on an input voltage signal;

[0237] A voltage holding circuit that holds the voltage value of the above input voltage signal according to each processing cycle, where the above processing cycle includes a holding period and a reset period immediately following the above holding period; and

[0238] An analog / digital converter that converts the voltage value held by the above voltage holding circuit from analog to digital,

[0239] The above voltage holding circuit has:

[0240] A first holding circuit that performs an operation of holding the lowest voltage value of the above input voltage signal during the above holding period according to each of the above processing cycles; and

[0241] A second holding circuit that performs an operation of holding the highest voltage value of the above input voltage signal during the above reset period according to each of the above processing cycles.

[0242] (Supplementary Note 21)

[0243] A semiconductor integrated circuit having:

[0244] An internal circuit that processes based on an input voltage signal;

[0245] A voltage holding circuit that holds the voltage value of the above input voltage signal according to each processing cycle, where the above processing cycle includes a holding period and a reset period immediately following the above holding period; and

[0246] An analog / digital converter that converts the voltage value held by the above voltage holding circuit from analog to digital,

[0247] The above voltage holding circuit has:

[0248] A generation circuit that generates a reset voltage signal that varies according to the above input voltage signal;

[0249] A holding circuit that performs an operation of holding the lowest voltage value of the above input voltage signal during the above holding period according to each of the above processing cycles; and

[0250] A reset circuit that resets the output voltage based on the above reset voltage signal during the above reset period according to each of the above processing cycles.

[0251] (Supplementary Note 22)

[0252] A semiconductor integrated circuit having:

[0253] An internal circuit that processes based on an input voltage signal;

[0254] A voltage holding circuit that holds the voltage value of the above input voltage signal; and

[0255] An analog / digital converter that converts the voltage value held by the above voltage holding circuit from analog to digital.

[0256] The above voltage holding circuit has:

[0257] A determination circuit that determines an increase or decrease in the above input voltage signal;

[0258] A first holding circuit that performs an operation of holding the lowest voltage value of the above input voltage signal for each first period, where the above first period is a period in which the above determination circuit determines an increase in the above input voltage signal; and

[0259] A second holding circuit that performs an operation of holding the highest voltage value of the above input voltage signal for each second period, where the above second period is a period in which the above determination circuit determines a decrease in the above input voltage signal.

[0260] (Supplementary Note 23)

[0261] A semiconductor integrated circuit having:

[0262] An internal circuit that processes based on an input voltage signal;

[0263] A voltage holding circuit that holds a voltage value based on the above input voltage signal for each processing cycle, where the above processing cycle includes a holding period and a reset period immediately following the above holding period; and

[0264] An analog / digital converter that converts the voltage value held by the above voltage holding circuit from analog to digital,

[0265] The above voltage holding circuit has:

[0266] A first holding circuit that performs an operation of holding the highest voltage value of the above input voltage signal during the above holding period for each of the above processing cycles; and

[0267] A second holding circuit that performs an operation of holding the lowest voltage value of the above input voltage signal during the above reset period for each of the above processing cycles.

[0268] (Supplementary Note 24)

[0269] A semiconductor integrated circuit having:

[0270] An internal circuit that processes based on an input voltage signal;

[0271] A voltage holding circuit that holds a voltage value based on the above input voltage signal for each processing cycle, where the above processing cycle includes a holding period and a reset period immediately following the above holding period; and

[0272] An analog / digital converter that converts the voltage value held by the above voltage holding circuit from analog to digital.

[0273] The above voltage holding circuit has:

[0274] A generation circuit that generates a reset voltage signal that varies according to the above input voltage signal;

[0275] A holding circuit that, for each of the above processing cycles, performs an operation of holding the highest voltage value of the above input voltage signal during the above holding period; and

[0276] A reset circuit that, for each of the above processing cycles, resets the output voltage based on the above reset voltage signal during the above reset period.

[0277] (Supplementary Note 25)

[0278] The semiconductor integrated circuit according to any one of Supplementary Notes 20 to 24, wherein

[0279] The above input voltage signal is the power supply voltage of the power supply voltage node of the above internal circuit,

[0280] The above semiconductor integrated circuit has a logic circuit that receives the digital voltage value output by the above analog / digital converter and outputs a control signal for controlling the above power supply voltage.

[0281] (Supplementary Note 26)

[0282] The semiconductor integrated circuit according to Supplementary Note 25, wherein

[0283] It has a power supply circuit that controls the power supply voltage supplied to the power supply voltage node of the above internal circuit based on the above control signal.

[0284] (Supplementary Note 27)

[0285] The semiconductor integrated circuit according to Supplementary Note 25, wherein

[0286] It has a safety mechanism block that detects an abnormality in the power supply voltage supplied to the power supply voltage node of the above internal circuit based on the above control signal and outputs a reset signal or an alarm signal.

[0287] (Supplementary Note 28)

[0288] The semiconductor integrated circuit according to any one of Supplementary Notes 20 to 24, wherein

[0289] The above input voltage signal is the output signal of a signal source,

[0290] The above semiconductor integrated circuit has:

[0291] A logic circuit that receives the digital voltage value output by the above analog / digital converter and outputs a control signal for controlling signal processing; and

[0292] A signal processing module that performs signal processing based on the above control signal.

[0293] It is possible to shorten the dead time during which an appropriate holding voltage cannot be output during reset.

Claims

1. A voltage holding circuit that operates according to each processing cycle to hold the voltage value of an input voltage signal. The processing cycle includes a holding period and a reset period immediately following the holding period. The voltage holding circuit has: A first holding circuit that, according to each of the above processing cycles, operates to hold the lowest voltage value of the input voltage signal during the holding period; and A second holding circuit that, according to each of the above processing cycles, operates to hold the highest voltage value of the input voltage signal during the reset period.

2. The voltage holding circuit according to claim 1, wherein, The first holding circuit has a first switch. When the voltage value of the input voltage signal is less than the voltage value held by the capacitor, the first switch connects the capacitor to a reference potential node having a potential lower than the power supply voltage node. The second holding circuit has a second switch. When the voltage value of the input voltage signal is greater than the voltage value held by the capacitor, the second switch connects the capacitor to the power supply voltage node.

3. The voltage holding circuit according to claim 2, wherein, A reset signal indicating the holding period or the reset period is input. When the reset signal indicates the holding period, the first switch becomes in a conductive state. When the reset signal indicates the reset period, the first switch is turned off. When the reset signal indicates the reset period, the second switch becomes in a conductive state. When the reset signal indicates the holding period, the second switch is turned off.

4. The voltage holding circuit according to claim 1, wherein, The first holding circuit has a third switch. When the voltage value of the input voltage signal is less than the voltage value held by the capacitor, the third switch connects the capacitor to a first current source in which the direction of the current is the first direction. The second holding circuit has a fourth switch. When the voltage value of the input voltage signal is greater than the voltage value held by the capacitor, the fourth switch connects the capacitor to a second current source in which the direction of the current is the second direction, and the second direction is opposite to the first direction.

5. The voltage holding circuit according to claim 4, wherein, The first current source and the second current source are constituted by a bidirectional current source in which the direction of the current is opposite during the holding period and the reset period.

6. A voltage holding circuit that operates according to each processing cycle to hold the voltage value of an input voltage signal. The processing cycle includes a holding period and a reset period immediately following the holding period. The voltage holding circuit has: A generating circuit that generates a reset voltage signal that varies according to the input voltage signal; A holding circuit that, according to each of the above processing cycles, operates to hold the lowest voltage value of the input voltage signal during the holding period; and A reset circuit that, according to each of the above processing cycles, resets the output voltage based on the reset voltage signal during the reset period. The above-mentioned holding circuit has a switch. When the voltage value of the above-mentioned input voltage signal is less than the voltage value held by the capacitor, the above-mentioned switch connects the above-mentioned capacitor to the reference potential node.

7. A voltage holding circuit that holds the voltage value of an input voltage signal, comprising: A determination circuit that determines an increase or decrease in the above-mentioned input voltage signal; A first holding circuit that, for each first period, performs an operation of holding the lowest voltage value of the above-mentioned input voltage signal, wherein, The above-mentioned first period is a period in which the above-mentioned determination circuit determines an increase in the above-mentioned input voltage signal; and A second holding circuit that, for each second period, performs an operation of holding the highest voltage value of the above-mentioned input voltage signal, wherein the above-mentioned second period is a period in which the above-mentioned determination circuit determines a decrease in the above-mentioned input voltage signal.

8. The voltage holding circuit according to claim 7, wherein, The above-mentioned first holding circuit has a first switch. During the above-mentioned first period, when the voltage value of the above-mentioned input voltage signal is less than the voltage value held by the capacitor, the above-mentioned first switch connects the above-mentioned capacitor to the reference potential node, The above-mentioned second holding circuit has a second switch. During the above-mentioned second period, when the voltage value of the above-mentioned input voltage signal is greater than the voltage value held by the capacitor, the above-mentioned second switch connects the above-mentioned capacitor to the power supply voltage node.

9. A voltage monitoring circuit, comprising: A voltage holding circuit that operates for each processing cycle and holds the voltage value of an input voltage signal, wherein, The above-mentioned processing cycle includes a holding period and a reset period immediately following the above-mentioned holding period; and An analog / digital converter that converts the voltage value held by the above-mentioned voltage holding circuit from analog to digital, The above-mentioned voltage holding circuit has: A first holding circuit that, for each of the above-mentioned processing cycles, performs an operation of holding the lowest voltage value of the input voltage signal during the above-mentioned holding period; and A second holding circuit that, for each of the above-mentioned processing cycles, performs an operation of holding the highest voltage value of the above-mentioned input voltage signal during the above-mentioned reset period.

10. A voltage monitoring circuit, comprising: A voltage holding circuit that operates for each processing cycle and holds the voltage value of an input voltage signal, the above-mentioned processing cycle including a holding period and a reset period immediately following the above-mentioned holding period; and An analog / digital converter that converts the voltage value held by the above-mentioned voltage holding circuit from analog to digital, The above-mentioned voltage holding circuit has: A generation circuit that generates a reset voltage signal that varies according to the above-mentioned input voltage signal; A holding circuit that, for each of the above-mentioned processing cycles, performs an operation of holding the lowest voltage value of the above-mentioned input voltage signal during the above-mentioned holding period; and A reset circuit that, for each of the above-mentioned processing cycles, resets the output voltage based on the above-mentioned reset voltage signal during the above-mentioned reset period, The above-mentioned holding circuit has a switch. When the voltage value of the above-mentioned input voltage signal is less than the voltage value held by the capacitor, the above-mentioned switch connects the above-mentioned capacitor to the reference potential node.

11. A voltage monitoring circuit, comprising: A voltage holding circuit that holds the voltage value of an input voltage signal; and An analog / digital converter that converts the voltage value held by the above voltage holding circuit from analog to digital. The above voltage holding circuit has: A determination circuit that determines an increase or decrease in the above input voltage signal; A first holding circuit that performs an operation of holding the lowest voltage value of the above input voltage signal for each first period, wherein, The above first period is a period in which the above determination circuit determines an increase in the above input voltage signal; and A second holding circuit that performs an operation of holding the highest voltage value of the above input voltage signal for each second period, wherein the above second period is a period in which the above determination circuit determines a decrease in the above input voltage signal.

12. A semiconductor integrated circuit having: An internal circuit that processes based on an input voltage signal; A voltage holding circuit that holds a voltage value of the above input voltage signal for each processing cycle, wherein, The above processing cycle includes a holding period and a reset period immediately following the above holding period; and An analog / digital converter that converts the voltage value held by the above voltage holding circuit from analog to digital, The above voltage holding circuit has: A first holding circuit that performs an operation of holding the lowest voltage value of the above input voltage signal during the above holding period for each of the above processing cycles; and A second holding circuit that performs an operation of holding the highest voltage value of the above input voltage signal during the above reset period for each of the above processing cycles.

13. A semiconductor integrated circuit having: An internal circuit that processes based on an input voltage signal; A voltage holding circuit that holds a voltage value of the above input voltage signal for each processing cycle, wherein, The above processing cycle includes a holding period and a reset period immediately following the above holding period; and An analog / digital converter that converts the voltage value held by the above voltage holding circuit from analog to digital, The above voltage holding circuit has: A generation circuit that generates a reset voltage signal that varies according to the above input voltage signal; A holding circuit that performs an operation of holding the lowest voltage value of the above input voltage signal during the above holding period for each of the above processing cycles; and A reset circuit that resets the output voltage based on the above reset voltage signal during the above reset period for each of the above processing cycles, The above holding circuit has a switch that connects the above capacitor to a reference potential node when the voltage value of the above input voltage signal is less than the voltage value held by the capacitor.

14. A semiconductor integrated circuit having: An internal circuit that processes based on an input voltage signal; A voltage holding circuit that holds a voltage value of the above input voltage signal; and An analog / digital converter that converts the voltage value held by the above voltage holding circuit from analog to digital, The above voltage holding circuit has: A determination circuit that determines an increase or decrease in the above input voltage signal; A first holding circuit that performs an operation of holding the lowest voltage value of the above input voltage signal for each first period, wherein, The above first period is a period in which the above determination circuit determines an increase in the above input voltage signal; and A second holding circuit performs an operation of holding the highest voltage value of the input voltage signal in each second period, where the second period is a period in which the determination circuit determines a decrease in the input voltage signal.

15. The semiconductor integrated circuit according to any one of claims 12 to 14, wherein, the input voltage signal is the power supply voltage of the power supply voltage node of the internal circuit, the semiconductor integrated circuit has a logic circuit that receives the digital voltage value output from the analog / digital converter and outputs a control signal for controlling the power supply voltage.

16. The semiconductor integrated circuit according to claim 15, wherein, it has a power supply circuit that controls the power supply voltage supplied to the power supply voltage node of the internal circuit based on the control signal.

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