Memory control method and system

Abstract

The present application provides a memory control method and system. The memory architecture includes: one or more accelerators, a controller, and a transaction interface. Each accelerator in the one or more accelerators includes a corresponding storage area configured to store data and a corresponding computing unit configured to perform calculations. The corresponding storage area and the corresponding computing unit are configured to interact with each other. The controller is arranged in cooperation with the one or more accelerators. The controller is configured to control the one or more accelerators, receive commands from a host, and perform operations in response to receiving the commands. The transaction interface is arranged in cooperation between the controller and the host, and the transaction interface includes a command and address signal channel, and the command and address signal channel is configured to transmit command and address signals from the host to the controller.

Description

Background Art

[0001] In the field of memory technology, designers and producers are concerned about improving memory architecture in terms of speed, capacity, cost, power efficiency, control efficiency, etc. Therefore, the interface of the memory is developed and upgraded to promote the improvement of the memory architecture. Generally, a dual in-line memory module (DIMM) includes a series of dynamic random access memory (DRAM) chips. The host can control the DRAM chips in the memory module through a memory interface including multiple channels. However, when the memory module works as a slave device, the memory module does not send a feedback signal to the host. Therefore, when the host performs different operations on the memory module, the host does not have any information about whether the operation is successful and when the operation is completed. Therefore, it is necessary to improve the memory control of the memory interface so that the communication between the host and the memory can be carried out accurately and flexibly. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The detailed description is set forth with reference to the accompanying drawings. In the drawings, the left-most digit(s) of a reference number identifies the drawing in which the reference number first appears. The use of the same reference numbers in different drawings indicates similar or identical items or features.

[0003] Figure 1A An example communication diagram of a memory system and a host is shown;

[0004] Figure 1B An example communication diagram of a memory system and a host is shown;

[0005] Figure 2 An example communication diagram of a memory system and a host is shown;

[0006] Figure 3 An example communication diagram of a memory system and a host is shown;

[0007] Figure 4 An example communication diagram of a memory system and a host is shown;

[0008] Figure 5 An example diagram illustrating communications between a host and a memory system;

[0009] Fig. 6A An example diagram illustrating communications between a host and a memory system;

[0010] Figure 6B An example diagram illustrating communications between a host and a memory system;

[0011] Figure 7 An example diagram showing communication between a host and a memory system in an out-of-order (OoO) manner is shown;

[0012] Fig. 8A and Figure 8B An example process of memory control is shown;

[0013] Fig. 9 An example process of memory control is shown;

[0014] Fig.10 An example table comparing characteristics of a memory architecture based on a conventional DDR interface and a memory architecture based on a transactional interface is shown. DETAILED DESCRIPTION

[0015] The systems and methods discussed in this application relate to improving memory control, and more particularly, to improving memory control methods and systems.

[0016] Typically, the speed of memory does not keep pace with the speed of the central processing unit (CPU). Data movement from memory is more expensive than computation in terms of bandwidth, energy, and latency. The growing gap between CPU and memory is called the "memory wall."

[0017] Some accelerator architectures are designed to provide powerful computing power and large memory capacity / bandwidth to solve the memory wall crisis. Examples of accelerator architectures may include, but are not limited to, intelligent random access memory (IRAM), DRAM-based reconfigurable in-situ accelerator (DRISA), in-memory computing (PIM) architecture, etc. The PIM architecture is a memory architecture that can perform computing and processing in the memory of a computing device.

[0018] As an attractive solution to the memory wall problem, the development of PIM architecture has risen rapidly. With PIM architecture, certain kinds of algorithms can be processed by data processing units (DPUs) inside the memory. Although researchers have studied the PIM concept for decades, attempts to implement PIM architecture have encountered difficulties due to practical considerations. For example, designers of PIM architecture cannot achieve the same high memory capacity on a single chip as on multiple chips. For traditional memory arrays, memory chip to memory chip communication can become a major bottleneck. Moreover, PIM has a poor position in the memory market. For example, 128MB of memory from different manufacturers may not be interchangeable, which may hurt interoperability and drive up prices.

[0019] In recent years, with the advancement of emerging memory technology, the practicality problem has been alleviated. For example, one approach is to integrate the DPU inside the DRAM. The distance between the DPU and the memory cells in the DRAM is short, and the energy to move data back and forth is small, and the latency is very low, which means that calculations can be performed quickly within the memory, which also frees up the CPU to do other kinds of complex work. In other words, the PIM architecture can speed up calculations and reduce the overhead of data movement.

[0020] Emerging data-intensive workloads / applications can no longer be processed by conventional computers, which often suffer from the von Neumann bottleneck. The idea behind the von Neumann bottleneck is that the throughput of a computer system is limited by the relative power of the processor compared to the maximum data transfer rate. The processor is idle for a certain amount of time when accessing memory. However, new generations of data-intensive workloads / applications such as machine learning tasks can benefit from PIM technology. PIM acceleration schemes enable processing cores to be localized next to the data, solving the bottleneck of big data computing. PIM solutions can reportedly accelerate data-intensive workloads / applications by 20 times at almost zero additional energy cost. Developing PIM schemes opens up new horizons for the big data era in terms of performance and cost efficiency.

[0021] However, because the PIM architecture requires unconventional control techniques, it remains challenging to integrate the PIM architecture with traditional computing systems in a seamless manner.Many current approaches do not address how to adequately implement the various controls of the PIM.

[0022] Figure 1A An example communication diagram 100 of a memory system 102 and a host 104 is shown. In an implementation, the memory system 102 may be any suitable type of memory architecture, such as a DDR-based architecture, etc. In an implementation, the memory system 102 may include volatile memory (such as SRAM, DRAM, etc.) and non-volatile memory (such as flash memory, phase change memory, spin-transfer torque magnetic random access memory (STT-RAM), resistive random access memory (ReRAM), etc.) or any combination thereof. In an implementation, the host 104 may include, but is not limited to, a CPU, an application-specific integrated circuit (ASIC), a graphics processing unit (GPU), a field programmable gate array (FPGA), a digital signal processor (DSP), or any combination thereof.

[0023] Reference Figure 1A, the memory system 102 may include a controller 106 and n memory cells, including memory cell_1 108, memory cell_2 110, memory cell_3 112, ..., and memory cell_n 114. By way of example and not limitation, the total number n of memory cells in the memory system 102 is a power of 2.

[0024] The controller 106 is configured to receive command and address signals from the host 104 via command and address signal channels / lines 116. The controller 106 is further configured to control each of the memory units of memory unit_1 108, memory unit_2 110, memory unit_3 112, ..., and memory unit_n 114.

[0025] Each memory unit of memory unit_1 108, memory unit_2 110, memory unit_3 112, ..., and memory unit_n 114 is configured to transmit data / signals to / from the host 104 via a data bus 118. In an implementation, each memory unit of memory unit_1 108, memory unit_2 110, memory unit_3 112, ..., and memory unit_n 114 can be a memory chip of "x4" ("by four"), "x8" ("by eight"), "x16" ("by sixteen"), etc., where "c4", "x8" and "x16" refer to the data width of the chip in bits. In an implementation, memory unit_1 108, memory unit_2 110, memory unit_3 112, ..., and memory unit_n 114 are configured to transmit data / signals with any suitable data width (e.g., 16 bits). In an implementation, each memory unit of memory unit_1 108, memory unit_2 110, memory unit_3 112, ..., and memory unit_n 114 may be configured with an accelerator architecture.

[0026] The host 104 includes a memory controller 120. The host 104 is configured to exchange data / signals with the memory system 102 via a data bus 118 using the memory controller 120. In an embodiment, the data width of the data bus can be any suitable width, for example, 64 bits. The host 104 is also configured to send command and address signals to the controller 106 of the memory system 102 via a command and address signal channel / line 116 using the memory controller 120.

[0027] The command and address signal channel / line 116 and the data bus 118 may be collectively referred to as an interface 122. In other words, the interface 122 may include the command and address signal channel / line 116 and the data bus 118. The interface 122 is provided in cooperation between the host 104 and the memory system 102. In an implementation, the interface 122 may be any suitable memory interface, such as a DDR interface. In an embodiment, the interface 122 may further include other lines / channels, such as a clock line, a control signal line, etc.

[0028] Figure 1B An example communication diagram 100' of a memory system 102' and a host 104' is shown. In an implementation, the memory system 102' can be any suitable type of memory architecture, such as a DDR-based architecture, etc. In an implementation, the memory system 102' can include volatile memory (such as SRAM, DRAM, etc.) and non-volatile memory (such as flash memory, phase change memory, STT-RAM, ReRAM, etc.) or any combination thereof. In an implementation, the host 104' can include, but is not limited to, a CPU, an ASIC, a GPU, an FPGA, a DSP, or any combination thereof.

[0029] See also Figure 1B , the memory system 102' may include a controller 106' and n memory cells, including memory cell_1' 108', memory cell_2' 110', memory cell_3' 112', ..., and memory cell_n 114'. As an example and not limitation, the total number n of memory cells in the memory system 102' is a power of 2.

[0030] Controller 106' is configured to receive command and address signals from host 104' via command and address signal channels / lines 116'. Controller 106' is also configured to control each memory unit of memory unit_1' 108', memory unit_2' 110', memory unit_3' 112', ..., and memory unit_n 114'.

[0031] Each memory unit of memory unit_1'108', memory unit_2'110', memory unit_3'112', ..., and memory unit_n 114' is configured to transmit data / signals to / from the host 104' via a data bus 118'. In an implementation, each memory unit of memory unit_1'108', memory unit_2'110', memory unit_3'112', ..., and memory unit_n 114' may be a "x4" ("by four"), "x8" ("by eight"), "x16" ("by sixteen"), etc. memory chip, where "x4", "x8" and "x16" refer to the data width of the chip in bits. In an implementation, memory cell_1 ' 108 ', memory cell_2 ' 110 ', memory cell_3 ' 112 ', ..., and memory cell_n 114 ' are configured to transmit data / signals with any suitable data width (eg, 16 bits).

[0032] The host 104' includes a memory controller 120'. The host 104' is configured to utilize the memory controller 120' to exchange data / signals with the memory system 102' via a data bus 118'. In an implementation, the data width of the data bus may be any suitable width, for example, 64 bits. The host 104' is also configured to utilize the memory controller 120' to send command and address signals to the controller 106' of the memory system 102' via a command and address signal channel / line 116'.

[0033] The command and address signal channel / line 116' and the data bus 118' may be collectively referred to as an interface 122'. In other words, the interface 122' may include the command and address signal channel / line 116' and the data bus 118'. The interface 122' is provided between the host 104' and the memory system 102'. In an embodiment, the interface 122' may also include other lines / channels, such as clock lines, control signal lines, etc.

[0034] In an implementation, each memory unit of memory unit_1'108', memory unit_2'110', memory unit_3'112', ..., and memory unit_n 114' may be configured with an accelerator architecture, such as a PIM architecture. In an implementation, memory unit_1'108' may include a data area 124' configured to store data, a computing block (abbreviated as COMPT) 126' configured to store data, and a computing block 128' configured to perform calculations. The data area 124' is further configured to communicate / interact with the computing block 126' and the computing block 128'. The memory unit_2'110' may include a data area 130' configured to store data, a computing block 132' configured to store data, and a computing block 134' configured to perform calculations. The data area 130' is further configured to communicate / interact with the computing block 132' and the computing block 134'. Memory unit_3'112' may include a data area 136' configured to store data, a computing block 138' configured to store data, and a computing block 140' configured to perform calculations. The data area 136' is further configured to communicate / interact with the computing block 138' and the computing block 140'. Memory unit_n 114' may include a data area 142' configured to store data, a computing block 144' configured to store data, and a computing block 146' configured to perform calculations. The data area 142' is further configured to communicate / interact with the computing block 144' and the computing block 146'. Although Figure 1B It is shown that each memory unit includes one data area and two computing blocks, but the present disclosure is not limited thereto, and each memory unit may include other numbers of data areas and computing blocks. Using the PIM architecture, the computing blocks within the memory unit will process certain types of algorithms, thereby eliminating some expensive data movement between the memory system 102' and the host 104' and greatly improving the overall efficiency of the calculation. In other words, the PIM architecture can speed up calculations and reduce the overhead of data movement.

[0035] However, when the memory system 102 / 102' operates as a slave device, no feedback signal is sent from the memory system 102 / 102' to the host 104 / 104'. Therefore, when the host 104 / 104' performs different operations on the memory, the host 104 / 104' does not have any information about whether the operation is successful and when the operation is completed. Therefore, there is a need for improved memory control so that communication between the host and the memory can be carried out accurately and flexibly. In other words, improved memory control.

[0036] The Joint Electron Device Engineering Council (JEDEC) has released the Non-Volatile Dual In-Line Memory Module-P (NVDIMM-P) protocol. According to this protocol, the double data rate (DDR) DRAM interface is modified to an emerging transactional memory interface for communicating with the host. The emerging transactional memory interface can be extended to support different storage media, such as non-volatile memory (NVM), flash memory, managed DRAM, etc.

[0037] Figure 2 An example communication diagram 200 of a memory system 202 and a host 204 is shown. In an implementation, the memory system 202 may be any suitable type of memory architecture, such as a DDR-based architecture, an NVDIMM-based architecture, etc. In an implementation, the memory system 202 may include volatile memory (such as SRAM, DRAM, etc.) and non-volatile memory (such as flash memory, phase change memory, STT-RAM, ReRAM, etc.) or any combination thereof. In an embodiment, the host 204 may include (but is not limited to) a CPU, an ASIC, a GPU, an FPGA, a DSP, or any combination thereof.

[0038] Reference Figure 2 , memory system 202 may include medium 206, controller 208, and n data buffers (DBs) including DB_1 210, DB_2 212, DB_3 214, DB_4 216, DB_5 218, DB_6 220, DB_7 222, DB_8 224, ..., and DB_n 226. By way of example and not limitation, the total number n of data buffers in memory system 202 is a power of 2.

[0039] The medium 206 is configured to communicate with the controller 208. In implementations, the medium 206 may include, but is not limited to, volatile memory (such as SRAM, DRAM, etc.) and non-volatile memory (such as flash memory, phase change memory, STT-RAM, ReRAM, etc.) or any combination thereof.

[0040] The controller 208 is configured to communicate with and control the data buffers including DB_1 210, DB_2 212, DB_3 214, DB_4 216, DB_5 218, DB_6 220, DB_7 222, DB_8 224, ..., and DB_n 226 to transfer data / signals to or from the data buffers. The controller 208 is further configured to send a response / acknowledgement signal to the host 204 via a first response signal channel / line RESPONSE_A 228 and a second response signal channel / line RESPONSE_B 230.

[0041] The controller 208 is further configured to receive command and address signals from the host 204 via a command and address signal channel / line 232 .

[0042] Each data buffer of DB_1 210, DB_2 212, DB_3 214, DB_4 216, DB_6 220, DB_5 218, DB_7 222, DB_8 224, ..., and DB_n 226 is configured to maintain signal integrity and deliver high performance input / output (I / O) as data / signals move between the host 204 and the memory system 202 via the data bus. Each data buffer of DB_1 210, DB_2 212, DB_3 214, DB_4 216, DB_6 220, DB_5 218, DB_7 222, DB_8 224, ..., and DB_n 226 is also configured to communicate with the controller 208 to transfer data / signals. As an example, data buffer DB_5 218 is further configured to communicate with the host via a check bit channel / line CB7:0 234. Additionally or alternatively, other data buffers may be configured to communicate with the host via the check bit channel / line CB7:0234.

[0043] In an embodiment, the data width of the data bus may be any suitable width, for example, 64 bits, etc. The data bus may include 64 data lines DQ0, DQ1, DQ2, ..., DQ63. As an example, the data line DQ63:32 236 may be configured to transmit data / signals from the host 204 to the data buffers DB_1 210, DB_2 212, DB_3 214, and DB_4 216 or to transmit data / signals from the data buffers DB_1 210, DB_2 212, DB_3 214, and DB_4 216 to the host 204. Data lines DQ31:0 may be configured to transmit data / signals from data buffers DB_6 220 , DB_7 222 , DB_8 224 , . . . , and DB_n 226 to host 204 or to transmit data / signals from host 204 to data buffers DB_6 220 , DB_7 222 , DB_8 224 , . . . , and DB_n 226 .

[0044] The check bit channel / line CB7:0 234 may be configured to transfer data / signals from the host 204 to the data buffer DB_5 218, or from the data buffer DB_5 218 to the host 204. In an implementation, the memory system 202 may operate in an error correction code (ECC) mode, in which the memory system 202 may detect and / or correct common kinds of internal data corruption. The check bit channel / line CB7:0 234 may be configured to transfer ECC signals from the host 204 to the data buffer DB_5 218, or from the data buffer DB_5 218 to the host 204. Additionally or alternatively, the memory system 202 may operate in a non-ECC mode or a partial ECC (custom, non-JEDEC standard compliant ECC algorithm requiring fewer ECC bits) mode.

[0045] The check bit channel / row CB7:0 234 may also be configured to transmit metadata from the host 204 to the data buffer DB_5 218, or to transmit metadata from the data buffer DB_5 218 to the host 204. The metadata may include, but is not limited to, information about the type of data, the protection level of the data, the priority level of the data, the persistence requirement of the data, the customized ECC data, etc. The protection level of the data, the priority level of the data, the persistence requirement of the data, and the customized ECC data may be dynamically configured and / or adjusted. The metadata may be used by the controller 208 to direct the data to different media. For example, the persistence requirement of the data in the metadata indicates that the data needs to be permanently saved, so the controller 208 saves the data in a persistent memory (such as a phase change memory, STT-RAM, ReRAM, etc.) according to the metadata. For example, the persistence requirement of the data in the metadata indicates that the data does not need to be permanently saved, so the controller 208 saves the data in a volatile memory (such as SRAM, DRAM, etc.) according to the metadata. For example, the protection level of the data in the metadata is relatively high, so the controller 208 saves the data with multiple copies. For example, the customized ECC data may include ECC data customized by a user.

[0046] The command and address signal channel / line 232 is configured to transmit command and address signals from the host 204 to the controller 208 .

[0047] The first and second response signal channels / lines RESPONSE_A 228 and RESPONSE_B 230 are configured to transmit a response / acknowledgement signal from the controller 208 to the host 204. In an embodiment, the first response signal channel / line RESPONSE_A 228 may be configured to transmit an error signal from the controller 208 to the host 204. Additionally or alternatively, the two response signal channels / lines RESPONSE_A 228 and RESPONSE_B 230 may be integrated into one channel / line.

[0048] The data bus (including data lines DQ 0:63), the check bit channel / line CB7:0 234, the command and address signal channel / line 232, the first and second response signal channels / lines RESPONSE_A 228 and RESPONSE_B 230 may be collectively referred to as a transaction interface 240. In other words, the transaction interface 240 may include the data bus (including data lines DQ 0:63), the check bit channel / line CB7:0 234, the command and address signal channel / line 232, the first and second response signal channels / lines RESPONSE_A 228 and RESPONSE_B 230. The transaction interface 240 is provided between the host 204 and the memory system 202. In an embodiment, the transaction interface 240 may further include other lines / channels, such as a clock line, a control signal line, etc.

[0049] Using the above example communication diagram 200, a response / confirmation signal can be sent from the memory system 202 to the host 204. Therefore, when the host 204 performs different operations on the memory system 202, the host 204 can have information about whether the operation is successful and when the operation is completed, which will be described in detail below. Therefore, the communication between the host 204 and the memory system 202 can be carried out accurately and flexibly. In other words, memory control is improved.

[0050] Figure 3 An exemplary communication diagram 300 of a memory system 302 and a host 304 is shown. In an implementation, the memory system 302 may be any suitable type of memory architecture, such as a DDR-based architecture, an NVDIMM-based architecture, etc. In an implementation, the memory system 302 may include volatile memory (such as SRAM, DRAM, etc.) and non-volatile memory (such as flash memory, phase change memory, STT-RAM, ReRAM, etc.) or any combination thereof. In an embodiment, the host 304 may include (but is not limited to) a CPU, an ASIC, a GPU, an FPGA, a DSP, or any combination thereof.

[0051] refer to Figure 3, the memory system 302 may include a controller 306, a first computing unit 308, a first memory unit 310, a second computing unit 312, a second memory unit 314, and n data buffers, including DB_1 316, DB_2 318, DB_3 320, DB_4 322, DB_5 324, DB_6 326, DB_7 328, DB_8 330, ..., and DB_n 332. As an example and not a limitation, the total number of data buffers n is a power of 2. The dashed box 334 indicates that the first computing unit 308 and the first memory unit 310 can be referred to as a first accelerator 334. The dashed box 336 indicates that the second computing unit 312 and the second memory unit 314 can be referred to as a second accelerator 336. With the accelerator architecture, some calculations can be processed by the computing unit within the memory system 302, thereby eliminating some expensive data movement between the host 304 and the memory system 302, and greatly improving the overall efficiency of the calculation block.

[0052] although Figure 3 Two computing units and two memory units are shown, but the present disclosure is not limited thereto, and the memory system 302 may include other numbers of computing units and memory units. In an implementation, the first memory unit 310 and the second memory unit 314 may also be referred to as storage areas. In an implementation, the number of computing units may be the same as the number of memory units. In an implementation, the number of data buffers may not necessarily be the same as the number of computing units or the number of memory units. Although Figure 3 The memory system 302 is shown to include two accelerators 334 and 336, but the disclosure is not limited thereto. Other numbers of accelerators may be included in the memory system 302.

[0053] The controller 306 is configured to communicate with and control the first computing unit 308, the first memory unit 310, the second computing unit 312, and the second memory unit 314. The controller 306 is further configured to communicate with and control the data buffers of DB_1 316, DB_2 318, DB_3 320, DB_4 322, DB_5 324, DB_6 326, DB_7 328, DB_8 330, ..., and DB_n 332 for transferring data / signals to / from the data buffers.

[0054] The controller 306 is also configured to send a response / acknowledgement signal to the host 304 via a response signal channel / line 338. The controller 306 is also configured to receive command and address signals from the host 304 via a command and address signal channel / line 340.

[0055] In an implementation, "deterministic timing" may refer to a scenario where an operation (such as a read / write / compute operation) has a predictable completion time (for a write or compute operation) or return time (for a read or compute operation), regardless of how long the operation takes. Operations such as read / write / compute operations must end at a predetermined time (for a write or compute operation) or return the result of the operation (for a read or compute operation) at a predetermined time. In an implementation, "non-deterministic timing" may refer to a scenario where the completion or return time of an operation (such as a read / write / compute operation) has not yet been determined, but depends on the runtime required for the operation.

[0056] The controller 306 is also configured to work with deterministic / fixed timing. In an implementation, the host 304 is configured to send a read command to the controller 306. The controller 306 is also configured to receive a read command from the host 304 and prepare data according to the read command. The controller 306 is also configured to send data to the host 304 with a deterministic / fixed timing (e.g., 10ns, 20ns, etc.) after receiving the read command. In an implementation, the host 304 is further configured to send a write command to the controller 306, and the data to be written to the data buffer. The controller 306 is configured to receive a write command from the host 304, and perform a write operation according to the write command without sending a response / confirmation signal back to the host 304.

[0057] The controller 306 is also configured to operate in a non-deterministic / non-fixed timing and / or runtime-dependent mode. The runtime-dependent mode may refer to a dependency of a series of operations, where subsequent operations depend on the results of previous operations.

[0058] In an implementation, the host 304 is further configured to send a read command to the controller 306. The controller 306 is further configured to receive a read command from the host 304 and prepare data according to a read command with non-deterministic / non-fixed timing. The controller 306 is also configured to send a response / confirmation signal to the host 304 via a response signal channel / line 338 after the data is ready. The response / confirmation signal includes information indicating that the data is ready. Because the time point at which the data is ready is non-deterministic / non-fixed, the host 304 needs to wait for a response / confirmation signal from the controller 306. The host 304 is further configured to receive a response / confirmation signal from the controller 306 via a response signal channel / line 338.

[0059] In an implementation, the host 304 is further configured to send a calculation command to the controller 306. The controller 306 is also used to receive the calculation command, instructing the computing unit to perform calculations in a non-deterministic / non-fixed timing according to the calculation command. Because the time point at which the calculation is completed is non-deterministic and / or depends on the running time of the calculation, the host 304 needs to wait for a response / confirmation signal from the controller 306. The host 304 is also used to send a get command to the controller 306 after receiving the response / confirmation signal. The controller 306 is also configured to receive the get command from the host 304 and send data to the host 304 via the data buffer according to the get command.

[0060] In an implementation, the host 304 is further configured to send a write command and data to be written into the data buffer to the controller 306. The controller 306 is also configured to receive a write operation from the host 304 and perform the write operation with a non-deterministic / non-fixed timing according to the write operation. The controller 306 is also configured to send a response / confirmation signal to the host 304 via a response signal channel / line 338 after the write operation is completed / successful. The response / confirmation signal includes information indicating that the write operation is completed / successful.

[0061] In an implementation, the controller 306 and the host 304 may communicate in an out-of-order manner. The term out-of-order means that the order in which one or more commands are sent / received is different from the order in which one or more response / acknowledgement signals are received / sent. Figure 7 Describe in more detail.

[0062] The controller 306 is also configured to request permission from the host 304, which allows the controller 306 of the memory system 302 not to receive commands and / or data from the host 304 for a period of time. In other words, the controller 306 is allowed to fully control the memory system 302 during the period of time. In an implementation, the term "full control" may refer to a situation where the controller 306 becomes the sole controller of the memory system 302, which is not controlled by any external host and does not receive commands and / or data from any external host during the period of time. For example, the memory system 302 may take time to perform internal operations, such as moving data between volatile memory units and non-volatile memory units, performing garbage collection operations in memory units, performing calculations using computing units, and the like. In such a case, the controller 306 may send a request for permission to the host 304 so that during the requested period of time, the host 304 will not send commands and / or data to the memory system 302. In an implementation, the request may be sent from the controller 306 to the host 304 via a response / confirmation signal channel / line 338. The host 304 is further configured to return permission to the controller 306 via the command and address signal channel / line 340. The host 304 is further configured to not send commands and / or data to the memory system 302 during the period requested by the controller 306. The period may be dynamically set and / or adjusted based on actual needs.

[0063] The controller 306 is also configured to receive metadata from the host 304 through the data buffer 320 via the check bit channel / row CB7:0 342. In an implementation, the memory system 302 can operate in an ECC mode, wherein the memory system 302 can detect and / or correct common types of internal data corruption. Additionally or alternatively, the memory system 302 can operate in a non-ECC or partial ECC (customized, requiring fewer ECC bits, non-JEDEC standard compatible ECC algorithm) mode. The metadata may include, but is not limited to, information about the type of data, the protection level of the data, the priority level of the data, the persistence requirements of the data, the customized ECC data, etc. The protection level of the data, the priority of the data, the persistence requirements of the data, and the customized ECC data can be dynamically configured and / or adjusted. The metadata can be used by the controller 306 to direct the data to different memory units. For example, the persistence requirements of the data in the metadata indicate that the data needs to be permanently saved, and therefore the controller 306 saves the data in a persistent memory unit such as a phase change memory, STT-RAM, ReRAM, etc. according to the metadata. For example, the persistence requirement of the data in the metadata indicates that the data does not need to be permanently saved, and thus the controller 306 saves the data in a volatile memory unit such as DRAM according to the metadata. For example, the protection level of the data in the metadata is relatively high, and thus the controller 306 may save the data with multiple copies. For example, the customized ECC data may include ECC data customized by a user.

[0064] The first computing unit 308 is used to perform calculations. The first computing unit 308 is further configured to communicate / interact with the first memory unit 310. The first computing unit 308 is further configured to communicate with the controller 306 and is controlled by the controller 306. Certain types of algorithms can be processed by the first computing unit 308 within the memory system 302, thereby eliminating some expensive data movement between the memory system 302 and the host 304, and greatly improving the overall efficiency of the calculation. Thus, the first accelerator 334 can speed up the calculation and reduce the overhead of data movement.

[0065] The first memory unit 310 is used to store data. The first memory unit 310 is further configured to communicate / interact with the first computing unit 308. The first memory unit 310 is further configured to communicate with the controller 306 and be controlled by the controller 306. In an implementation, the first memory unit 310 may include a volatile memory (such as SRAM, DRAM, etc.) and a non-volatile memory (such as flash memory, phase change memory, STT-RAM, ReRAM, etc.) or any combination thereof.

[0066] The second computing unit 312 is used to perform calculations. The second computing unit 312 is also configured to communicate / interact with the second memory unit 314. The second computing unit 312 is also configured to communicate with the controller 306 and be controlled by the controller 306. Certain types of algorithms can be processed by the second memory unit 314 inside the memory system 302, thereby eliminating some expensive data movement between the memory system 302 and the host 304, and greatly improving the overall efficiency of the calculation. Thus, the second accelerator 336 can speed up the calculation and reduce the overhead of data movement.

[0067] The second storage unit 314 is used to store data. The second storage unit 314 is also configured to communicate with the second computing unit 312. The second storage unit 314 is further configured to communicate with the controller 306 and is controlled by the controller 306. In an implementation, the second storage unit 314 may include a volatile memory (such as SRAM, DRAM, etc.) and a non-volatile memory (such as flash memory, phase change memory, STT-RAM, ReRAM, etc.) or any combination thereof.

[0068] Each data buffer of DB_1 316, DB_2 318, DB_3 320, DB_4 322, DB_5 324, DB_6 326, DB_7 328, DB_8 330, ..., and DB_n 332 is configured to maintain signal integrity and deliver high performance I / O as data / signals move between the host 304 and the memory system 302 via the data bus. Each data buffer of DB_1 316, DB_2 318, DB_3 320, DB_4 322, DB_5 324, DB_6 326, DB_7 328, DB_8 330, ..., and DB_n 332 is further configured to communicate with the controller 306 to transfer data / signals. As an example, data buffer DB_5 324 is also configured to communicate with the host 304 via the check bit channel / line CB7:0 342. Additionally or alternatively, other data buffers may be configured to communicate with the host 304 via the check bit channel / line CB7:0 342.

[0069] By way of example and not limitation, the data width of the data bus may be any suitable width, for example, 64 bits, etc. The data bus may include 64 data lines DQ0, DQ1, DQ2, ..., DQ63. As an example, data line DQ63:32 344 is configured to transfer data / signals from the host 304 to the data buffers DB_1 316, DB_2 318, DB_3 320, and DB_4 or from the data buffers DB_1 316, DB_2 318, DB_3 320, and DB_4 to the host 304. Data line DQ31:0346 is configured to transmit data / signals from data buffers DB_6 326, DB_7 328, DB_8 330, ..., and DB_n 332 to host 304, or to transmit data / signals from host 304 to data buffers DB_6 326, DB_7 328, DB_8 330, ..., and DB_n 332.

[0070] The check bit channel / line CB7:0 342 may be configured to transfer data / signals from the host 304 to the data buffer DB_5 324 or from the data buffer DB_5 324 to the host 304. In an implementation, the check bit line CB7:0 342 may be configured to transfer ECC signals from the host 304 to the data buffer DB_5 324 or from the data buffer DB_5 324 to the host 304. In an embodiment, the check bit channel / line CB7:0 342 may be further configured to transfer metadata from the host 304 to the data buffer DB_5 324 or from the data buffer DB_5 324 to the host 304.

[0071] The command and address signal channel / line 340 is configured to transmit command and address signals from the host 304 to the controller 306 .

[0072] The response signal channel / line 338 is configured to transmit a response / confirmation signal from the controller 306 to the host 304 .

[0073] In an implementation, a memory unit may be mapped as a host-managed memory or considered as a software-managed memory in the memory system 302. For example, if a memory unit is mapped as a host-managed memory, the host 304 may instruct the memory unit to perform a read / write operation via the controller 306. If a memory unit is considered as a software-managed memory, the memory unit is not visible from the perspective of the host 304, and the software is responsible for instructing the memory unit to perform a read / write operation via the controller 306.

[0074] The data bus (including data lines DQ 0:63), the check bit channel / line CB7:0 342, the command and address signal channel / line 340, and the response signal channel / line 338 may be collectively referred to as a transaction interface 348. In other words, the transaction interface 348 may include the data bus (including data lines DQ 0:63), the check bit channel / line CB7:0 342, the command and address signal channel / line 340, and the response signal channel / line 338. The transaction interface 348 is provided between the host 304 and the memory system 302. In an embodiment, the transaction interface 348 may further include other lines / channels, such as clock lines, control signal lines, etc.

[0075] Using the above example communication diagram 300, a response / confirmation signal can be sent from the memory system 302 to the host 304. Therefore, when the host 304 performs different operations on the memory system 302, the host 304 can have information about whether the operation is successful and when the operation is completed. Therefore, the communication between the host 304 and the memory system 302 can be carried out accurately and flexibly. In other words, memory control is improved.

[0076] Figure 4 An example communication diagram 400 of a memory system 402 and a host 404 is shown. In an implementation, the memory system 402 may be any suitable type of memory architecture, such as a DDR-based architecture, an NVDIMM-based architecture, etc. In an implementation, the memory system 402 may include volatile memory (such as SRAM, DRAM, etc.) and non-volatile memory (such as flash memory, phase change memory, STT-RAM, ReRAM, etc.) or any combination thereof. In an embodiment, the host 404 may include (but is not limited to) a CPU, an ASIC, a GPU, an FPGA, a DSP, or any combination thereof.

[0077] Reference Figure 4 , the storage system 402 may include a controller 406, a first memory unit / first accelerator 408, a second memory unit / second accelerator 410, and n data buffers including DB_1 412, DB_2 414, DB_3 416, DB_4 418, DB_5 420, DB_6 422, DB_7 424, DB_8 426, ..., and DB_n 428. By way of example and not limitation, the total number of data buffers n is a power of 2. Although Figure 4 Two storage units / accelerators in the storage system 402 are shown, but the disclosure is not limited thereto and the storage system 402 may include other numbers of storage units / accelerators. In implementations, the number of data buffers need not be the same as the number of memory units.

[0078] The controller 406 is configured to communicate with and control the first storage unit / first accelerator 408 and the second storage unit / second accelerator 410. The controller 406 is configured to communicate with and control each data buffer of DB_1 412, DB_2 414, DB_3 416, DB_4 418, DB_5 420, DB_6 422, DB_7 424, DB_8 426, ..., and DB_n 428 for transmitting data / signals to / from the data buffers.

[0079] The controller 406 is also configured to send a response / acknowledgement signal to the host 404 via a response signal channel / line 430. The controller 406 is also configured to receive command and address signals from the host 404 via a command and address signal channel / line 432.

[0080] The controller 406 is also configured to operate with deterministic / fixed timing. In an embodiment, the host 404 is configured to send a read command to the controller 406. The controller 406 is also configured to receive a read command from the host 404 and prepare data according to the read command. The controller 406 is also configured to send data to the host 404 with deterministic / fixed timing (e.g., 10ns, 20ns, etc.) after receiving the read command. In an implementation, the host 404 is further configured to send a write command and data to be written to the data buffer to the controller 406. The controller 406 is configured to receive a write command from the host 404 and perform a write operation according to the write command without returning a response / confirmation signal to the host 404.

[0081] The controller 406 is also configured to operate in a non-deterministic / non-fixed timing and / or in a runtime-dependent mode. The runtime-dependent mode may refer to a dependency of a series of operations, where subsequent operations depend on the results of previous operations.

[0082] In an embodiment, the host 404 is further configured to send a read command to the controller 406. The controller 406 is further configured to receive the read command from the host 404 and prepare data according to the read command in a non-deterministic / non-fixed timing. The controller 406 is also configured to send a response / confirmation signal to the host 404 via a response signal channel / line 430 after the data is ready. The response / confirmation signal includes information indicating that the data is ready. Because the time point at which the data is ready is non-deterministic / non-fixed, the host 404 needs to wait for the response / confirmation signal from the controller 406. The host 404 is further configured to receive a response / confirmation signal from the controller 406 via a response signal channel / line 430.

[0083] In an embodiment, the host 404 is further configured to send a calculation command to the controller 406. The controller 406 is further configured to receive the calculation command and instruct the memory unit to perform the calculation at a non-deterministic / non-fixed timing according to the calculation command. Because the time point at which the calculation is completed is non-deterministic and / or depends on the running time of the calculation, the host 404 needs to wait for a response / confirmation signal from the controller 406. The host 404 is also used to send a get command to the controller 406 after receiving the response / confirmation signal. The controller 406 is also configured to receive a get command from the host 404 and send data to the host 404 via a data buffer according to the get command.

[0084] In an implementation, the host 404 is further configured to send a write command and data to be written into the data buffer to the controller 406. The controller 406 is further configured to receive a write operation from the host 404 and perform the write operation with a non-determined / non-fixed timing according to the write operation. The controller 406 is also used to send a response / confirmation signal to the host 404 through a response signal channel / line 430 after the write operation is completed / successful. The response / confirmation signal includes information indicating that the write operation is completed / successful.

[0085] In an implementation, the controller 406 may communicate with the host 404 in an out-of-order manner. Figure 7 Describe in more detail.

[0086] The controller 406 is also configured to request permission from the host 404, which allows the controller 406 of the memory system 402 not to receive commands and / or data from the host 404 for a period of time. In other words, the controller 406 is allowed to fully control the memory system 402 during the period of time. The term "full control" may refer to a situation where the controller 406 becomes the sole controller of the memory system 402, which is not controlled by any external host and does not receive commands and / or data from any external host during the period of time. For example, the memory system 402 may spend time performing internal operations, such as moving data between volatile memory units and non-volatile memory units, performing garbage collection operations in memory units, performing calculations using computing units, etc. In such a case, the controller 406 may send a request for permission to the host 404 so that during the requested period of time, the host 404 will not send commands and / or data to the memory system 302. In an embodiment, the request may be sent from the controller 406 to the host 404 via a response / confirmation signal channel / line 430. The host 404 is also configured to return permission to the controller 406 via the command and address signal channel / line 432. The host 404 is further configured to not send commands and / or data to the memory system 402 during the period requested by the controller 406. The period can be dynamically set and / or adjusted based on actual needs.

[0087] The controller 406 is also configured to receive metadata from the host 404 through the data buffer_5 420, for example, via the check bit channel / line CB7:0 434. In an implementation, the memory system 402 can operate in an ECC mode, wherein the memory system 402 can detect and / or correct common types of internal data corruption. Additionally or alternatively, the memory system 402 can operate in a non-ECC mode or a partial ECC (a customized, non-JEDEC standard compliant ECC algorithm requiring fewer ECC bits). The metadata may include, but is not limited to, information about the type of data, the protection level of the data, the priority level of the data, the persistence requirements of the data, the customized ECC data, etc. The protection level of the data, the priority level of the data, the persistence requirements of the data, and the customized ECC data can be dynamically configured and / or adjusted. The metadata can be used by the controller 406 to direct the data to different memory units. For example, the persistence requirements of the data in the metadata indicate that the data needs to be permanently saved, and therefore the controller 406 saves the data in a persistent memory unit, such as a phase change memory, STT-RAM, ReRAM, etc., according to the metadata. For example, the persistence requirement of the data in the metadata indicates that the data does not need to be permanently saved, and thus the controller 406 saves the data in a volatile memory unit such as DRAM according to the metadata. For example, the protection level of the data in the metadata is relatively high, and thus the controller 406 may save the data with multiple copies. For example, the customized ECC data may include ECC data customized by a user.

[0088] The first memory unit / first accelerator 408 is configured to communicate with the controller 406 and be controlled by the controller 406. In an implementation, the first memory unit / first accelerator 408 may include a volatile memory (such as SRAM, DRAM, etc.) and a non-volatile memory (such as flash memory, phase change memory, STT-RAM, ReRAM, etc.) or any combination thereof.

[0089] In an embodiment, the first memory unit / first accelerator 408 may be configured with an accelerator architecture, for example, a PIM architecture. In an implementation, the first memory unit / first accelerator 408 may include a first data area 436 and a first computing unit 438. In an implementation, the first data area 436 may also be referred to as a storage area. The first data area 436 is used to store data. The first computing unit 438 is configured to perform calculations. The first data area 436 and the first computing unit 438 are configured to communicate / interact with each other. The first memory unit / first accelerator 408 is further configured to perform calculations using the first computing unit 406 under the control of the controller 406. Although Figure 4The first memory unit / first accelerator 408 is shown to include one data area and one computing unit, but the present disclosure is not limited thereto, and the first memory unit / first accelerator 408 may include other numbers of data areas and computing units. Using the PIM architecture, the computing unit within the memory unit / accelerator 408 will process certain types of algorithms, thereby eliminating some expensive data movement between the memory system 402 and the host 404, and greatly improving the overall efficiency of the calculation. In other words, the PIM architecture can speed up calculations and reduce the overhead of data movement.

[0090] The second memory unit / second accelerator 410 is configured to communicate with the controller 406 and be controlled by the controller 406. In an implementation, the second memory unit / second accelerator 410 may include a volatile memory (such as SRAM, DRAM, etc.) and a non-volatile memory (such as flash memory, phase change memory, STT-RAM, ReRAM, etc.) or any combination thereof.

[0091] In an embodiment, the second memory unit / second accelerator 410 may be configured with an accelerator architecture, for example, a PIM architecture. In an implementation, the second memory unit / second accelerator 410 may include a second data area 440 and a second computing unit 442. In an implementation, the second data area 440 may also be referred to as a storage area. The second data area 440 is used to store data. The second computing unit 442 is used to perform calculations. The second data area 440 and the second computing unit 442 are configured to communicate / interact with each other. The second memory unit / second accelerator 410 is further configured to perform calculations using the first computing unit 406 under the control of the controller 406. Although Figure 4 The second memory unit / second accelerator 410 is shown to include one data area and one computing unit, but the present disclosure is not limited thereto, and the second memory unit / second accelerator 410 may include other numbers of data areas and computing units. Using the PIM architecture, certain types of algorithms will be processed by the computing unit within the first memory unit / first accelerator 408, thereby eliminating some expensive data movement between the memory system 402 and the host 404, and greatly improving the overall efficiency of the calculation. In other words, the PIM architecture can speed up calculations and reduce the overhead of data movement.

[0092] Each data buffer of DB_1 412, DB_2 414, DB_3 416, DB_4 418, DB_5 420, DB_6 422, DB_7 424, DB_8 426, ..., and DB_n 428 is configured to maintain signal integrity and deliver high performance I / O as data / signals move between the host 404 404 and the memory system 402 via the data bus. Each data buffer of DB_1 412, DB_2 414, DB_3 416, DB_4 418, DB_5 420, DB_6 422, DB_7 424, DB_8 426, ..., and DB_n 428 is further configured to communicate with the controller 406 to deliver the data / signals. As an example, data buffer DB_5 420 is also configured to communicate with the host 404 via the check bit channel / line CB7:0 434. Additionally or alternatively, other data buffers may be configured to communicate with the host 404 via the check bit channel / line CB7:0 434.

[0093] By way of example and not limitation, the data width of the data bus may be any suitable width, for example, 64 bits. The data bus may include 64 data lines DQ0, DQ1, DQ2, ..., DQ63. By way of example, data line DQ63:32 444 is configured to transmit data / signals from the host 404 to data buffers DB_1 412, DB_2 414, DB_3 416, and DB_4, or to transmit data / signals from data buffers DB_1 412, DB_2 414, DB_3 416, and DB_4 to the host 404. Data line DQ31:0 446 is configured to transmit data / signals from host 404 to data buffers DB_6 422 , DB_7 424 , DB_8 426 , . . . , and DB_n 428 or to transmit data / signals from data buffers DB_6 422 , DB_7 424 , DB_8 426 , . . . , and DB_n 428 to host 404 .

[0094] The parity bit lane / line CB7:0 434 may be configured to transfer data / signals from the host 404 to the data buffer DB_5 420 or from the data buffer DB_5 420 to the host 404. In an embodiment, the parity bit lane / line CB7:0 434 may be configured to transfer ECC signals from the host 404 to the data buffer DB_5 420 or from the data buffer DB_5 420 to the host 404. In an implementation, the parity bit lane / line CB7:0 434 may be further configured to transfer metadata from the host 404 to the data buffer DB_5 420 or from the data buffer DB_5 420 to the host 404.

[0095] The response signal channel / line 430 is configured to transmit a response / confirmation signal from the controller 406 to the host 404 .

[0096] The command and address signal channel / line 432 is configured to transmit command and address signals from the host 404 to the controller 406 .

[0097] In an implementation, a memory unit may be mapped as a host-managed memory or considered as a software-managed memory in the memory system 402. For example, if a memory unit is mapped as a host-managed memory, the host 404 may instruct the memory unit to perform a read / write operation via the controller 406. If a memory unit is considered as a software-managed memory, the memory unit is not visible from the perspective of the host 404, and the software is responsible for instructing the memory unit to perform a read / write operation via the controller 406.

[0098] The data bus (including data lines DQ 0:64), the check bit channel / line CB7:0 434, the command and address signal channel / line 432, and the response signal channel / line 430 may be collectively referred to as a transaction interface 448. In other words, the transaction interface 448 may include a data bus (including data lines DQ 0:64), a check bit channel / line CB7:0 434, a command and address signal channel / line 432, and a response signal channel / line 430. The transaction interface 448 is provided between the host 404 and the memory system 402. In an embodiment, the transaction interface 448 may further include other lines / channels, such as a clock line, a control signal line, etc.

[0099] Using the above example communication diagram 400, a response / confirmation signal can be sent from the memory system 402 to the host 404. Therefore, when the host 404 performs different operations on the memory system 402, the host 404 can have information about whether the operation is successful and when the operation is completed. Therefore, the communication between the host 404 and the memory system 402 can be carried out accurately and flexibly. In other words, memory control is improved.

[0100] Figure 5 An example diagram 500 illustrating communications between a host 502 and a memory system 504 is shown.

[0101] refer to Figure 5 , at 506 , the host 502 sends a read command to the memory system 504 .

[0102] At 508, the memory system 504 prepares the data with a deterministic / fixed timing (eg, 10 ns, 20 ns, etc.) after receiving the read command.

[0103] At 510 , the memory system 504 sends data to the host 502 .

[0104] At 512 , the host 502 sends a write command to the memory system 504 .

[0105] At 514, the host 502 sends data to be written to the memory system 504 with deterministic / fixed timing. In an implementation, the host 502 sends the data to be written to the memory system 504 at a deterministic / timed time point (eg, 5ns, 10ns, etc.) after sending the write command.

[0106] At 516 , the memory system 504 performs a write operation according to the write command.

[0107] The example diagram 500 of communication with deterministic timing / fixed timing between a host 502 and a memory system 504 is for illustration purposes and the present disclosure is not limited thereto. Figure 5 Although steps / operations are shown in a certain order, they may be performed in a different order. Figure 5 Any step / operation in can be performed once, twice or multiple times. In addition, additional steps / operations can be added to the example diagram 500.

[0108] In the above example diagram 500, a response / confirmation signal can be sent from the memory system 504 to the host 502. Therefore, when the host 504 performs different operations on the memory system 504, the host 502 can have information about whether the operation is successful and when the operation is completed. Therefore, the communication between the host 502 and the memory system 504 can be carried out accurately and flexibly. In other words, memory control is improved.

[0109] Fig. 6A An example diagram 600 of communications between a host 602 and a memory system 604 is shown.

[0110] refer to Fig. 6A At 606 , the host 602 sends a read and / or compute command to the memory system 604 .

[0111] At 608, the memory system 604 prepares data and / or performs calculations in a non-deterministic / non-fixed timing according to the read and / or calculation commands. In an implementation, at which point in time the data is ready and / or the calculation is completed is non-deterministic and / or depends on the runtime of the calculation.

[0112] At 610, after the data is ready and / or the calculation is completed, the memory system 604 sends a first response / confirmation signal to the host 602. The first response / confirmation signal includes information indicating that the data is ready and / or the calculation is completed.

[0113] At 612, the host 602 sends a get command to the memory system 604 at a deterministic / fixed timing. In an implementation, the host 602 sends a get command at a deterministic / timed time point (e.g., 5n, 10ns, etc.) after receiving a response / confirmation signal from the memory system 604.

[0114] Dashed lane / elliptical area 614 indicates that the operations performed at 610 and 612 may be referred to as a handshaking process between the host 602 and the memory system 604 .

[0115] At 616, the memory system 604 sends the data and / or calculation results to the host 602 in a deterministic / fixed timing. In an implementation, after receiving the get command from the host 602, the memory system 604 sends the data and / or calculation results to the host 602 at a deterministic / timed time point (e.g., 10ns, 20ns, etc.).

[0116] At 618 , the host 602 sends a write command to the memory system 604 .

[0117] At 620, the host 602 sends the data to be written to the memory system 604 at a deterministic / fixed timing. In an implementation, the host 602 sends the data to be written to the memory system 604 at a deterministic / timed time point (eg, 5ns, 10ns, etc.) after sending the write command.

[0118] At 622, the memory system 604 performs a write operation according to the write command having the non-deterministic timing.

[0119] At 624, after completing the write operation, the memory system 604 sends a second response / acknowledgement signal to the host 602. The second response / acknowledgement signal includes information indicating that the write operation is complete / successful.

[0120] The example diagram 600 of communication between a host 602 and a memory system 604 with deterministic / fixed timing and non-deterministic / non-fixed timing is for illustration purposes, and the present disclosure is not limited thereto. Fig. 6A Although steps / operations are shown in a certain order, they may be performed in a different order. Fig. 6A Any step / operation in can be performed once, twice or multiple times. In addition, additional steps / operations can be added to the example diagram 600.

[0121] In the above example diagram 600, a response / confirmation signal can be sent from the memory system 604 to the host 602. Therefore, when the host 604 performs different operations on the memory system 604, the host 602 can have information about whether the operation is successful and when the operation is completed. Therefore, the communication between the host 602 and the memory system 604 can be carried out accurately and flexibly. In other words, memory control is improved.

[0122] Figure 6B An example diagram 600' is shown of communications between a host 602' and a memory system 604'.

[0123] refer to Figure 6B At 606', the host 602' sends a computing command to the memory system 604'.

[0124] At 608', the memory system 604' performs the computation according to the computation command with non-deterministic / non-fixed timing. In an implementation, at which point in time the computation is completed is non-deterministic and / or depends on the runtime of the computation.

[0125] At 610', after the computation is complete, the memory system 604' sends a first response / acknowledgement signal to the host 602'. The first response / acknowledgement signal includes information indicating that the computation is complete.

[0126] At 612', the host 602' sends a get command to the memory system 604' at a deterministic / fixed timing. In an implementation, the host 602' sends the get command at a deterministic / timed time point (e.g., 5n, 10ns, etc.) after receiving a response / confirmation signal from the memory system 604'. In an implementation, the operation at 612' may be optional.

[0127] Dashed lane / elliptical area 614' indicates that the operations performed at 610' and 612' may be referred to as a handshaking process between the host 602' and the memory system 604'.

[0128] At 616', the memory system 604' sends the calculation result to the host 602' at a deterministic / fixed timing. In an implementation, after receiving the get command from the host 602', the memory system 604' sends the calculation result to the host 602' at a deterministic / timed time point (e.g., 10ns, 20ns, etc.). In an implementation, the operation at 612' may be optional.

[0129] In an implementation, after the memory system 604' completes the calculation, the host 602' may not always need to obtain the calculation result. For example, the calculation result may be an intermediate result. Therefore, the operations at 612' and 616' may be optional.

[0130] The example diagram 600' of communication between a host 602' and a memory system 604' with deterministic / fixed timing and non-deterministic / non-fixed timing is for illustration purposes and the present disclosure is not limited thereto. Figure 6B Although steps / operations are shown in a certain order, these steps / operations may be performed in a different order. Figure 6B Any step / operation in can be performed once, twice or multiple times. In addition, additional steps / operations can be added to the example diagram 600 '.

[0131] In the above example diagram 600', a response / confirmation signal can be sent from the memory system 604' to the host 602'. Therefore, when the host 604' performs different operations on the memory system 604', the host 602' can have information about whether the operation is successful and when the operation is completed. Therefore, the communication between the host 602' and the memory system 604' can be carried out accurately and flexibly. In other words, memory control is improved.

[0132] Figure 7 An example diagram of communication between a host 702 and a memory system 704 in an out-of-order manner is shown.

[0133] refer to Figure 7 At 706, the host 702 sends a first command to the memory system 704. In an implementation, the first command may include, but is not limited to, a read command, a calculation command, a write command and data to be written, or any combination thereof.

[0134] At 708, the memory system 704 performs a first operation according to the first command. In an implementation, the first operation may include, but is not limited to, preparing data, performing a calculation, performing a write operation, or any combination thereof.

[0135] At 710, the host 702 sends a second command to the memory system 704. In an implementation, the second command may include, but is not limited to, a read command, a calculation command, a write command and data to be written, or any combination thereof.

[0136] At 712, the memory system 704 performs a second operation according to the second command. In an implementation, the second operation may include, but is not limited to, preparing data, performing a calculation, performing a write operation, or any combination thereof.

[0137] At 714, the memory system 704 sends a second response / confirmation signal to the host 702. The second response / confirmation signal includes information indicating that the second operation is complete.

[0138] At 716, the memory system 704 sends a first response / acknowledgement signal to the host 702. The first response / acknowledgement signal includes information indicating that the first operation is complete.

[0139] Dashed box 718 illustrates operations to be performed when the second command includes a read command and / or a compute command.

[0140] At 720 , the host 702 sends a second get command to the memory system 704 .

[0141] At 722, the memory system 704 sends the second data to the host.

[0142] Dashed box 724 illustrates operations to be performed when the first command includes a read command and / or a compute command.

[0143] At 726 , the host 702 sends a first get command to the memory system 704 .

[0144] At 728, the memory system 704 sends the first data to the host.

[0145] like Figure 7 As shown, the first command is sent from the host 702 to the memory system 704 before the second command. However, the first response / confirmation signal is sent from the memory system 704 to the host 702 after the second response / confirmation signal. Thus, the order in which the more than one command is sent / received is different from the order in which the more than one response / confirmation signal is received / sent. Therefore, the host 702 and the memory system 704 communicate in an out-of-order manner.

[0146] The example diagram 700 of communication between the host 702 and the memory system 704 in an out-of-order manner is for illustration purposes and the present disclosure is not limited thereto. Figure 7 Although steps / operations are shown in a certain order, these steps / operations may be performed in a different order. Figure 7 Any step / operation in can be performed once, twice or multiple times. In addition, additional steps / operations can be added to the example diagram 700.

[0147] In the above example diagram 700, a response / confirmation signal can be sent from the memory system 704 to the host 702. Therefore, when the host 704 performs different operations on the memory system 704, the host 702 can have information about whether the operation is successful and when the operation is completed. Therefore, the communication between the host 702 and the memory system 704 can be carried out accurately and flexibly. In other words, memory control is improved.

[0148] Fig. 8A and Figure 8B An example process 800 of memory control is shown.

[0149] refer to Fig. 8A At block 802, a host sends a first command to a memory system. In an implementation, the first command includes a read command. Additionally or alternatively, the first command includes a compute command. Additionally or alternatively, the first command includes a write command and data to be written.

[0150] At block 804, the memory system receives a first command from a host.

[0151] At block 806, in response to receiving the first command, the memory system performs a first operation according to the first command. In an implementation, the first operation is performed with non-deterministic / non-fixed timing. The details of the non-deterministic timing are as described above and are not repeated here. In an embodiment, performing the first operation includes preparing data according to a read command. Additionally or alternatively, performing the first operation includes performing a calculation according to a calculation command. Additionally or alternatively, performing the first operation includes performing a write operation according to a write command.

[0152] At block 808, after completing the first operation, the memory system sends a first response signal to the host. In an embodiment, the first response signal includes information indicating that the first operation is complete.

[0153] At block 810, the host receives a first response signal from the memory system. In an implementation, the first response signal is received via a non-deterministic / non-fixed timing. The details of the non-deterministic timing are described above and will not be repeated here.

[0154] Dashed box 812 illustrates operations to be performed when the first command includes a read command and / or a compute command.

[0155] At block 814, in response to receiving the first response signal, the host sends a get command to the memory system.

[0156] At block 816, the memory system receives a get command from the host.

[0157] At block 818, in response to receiving the get command from the host, the memory system sends the first data to the host.

[0158] At block 820, the host sends a second command to the memory system. In an implementation, the second command includes a read command. Additionally or alternatively, the second command includes a compute command. Additionally or alternatively, the second command includes a write command and data to be written.

[0159] At block 822, the memory system receives a second command from the host.

[0160] At block 824, in response to receiving the second command, the memory system performs a second operation according to the second command. In an implementation, the second operation is performed with non-deterministic / non-fixed timing. The details of the non-deterministic / non-fixed timing are as described above and are not repeated here. In an embodiment, performing the second operation includes preparing data according to a read command. Additionally or alternatively, performing the second operation includes performing a calculation according to a calculation command. Additionally or alternatively, performing the second operation includes performing a write operation according to a write command.

[0161] At block 826, after completing the second operation, the memory system sends a second response signal to the host. In an embodiment, the second response signal includes information indicating that the second operation is complete.

[0162] At block 828, the host receives a second response signal from the memory system. In an implementation, the second response signal is received via a non-deterministic timing sequence. The details of the non-deterministic timing sequence are described above and will not be repeated here.

[0163] In an implementation, the host and the memory system may communicate in an out-of-order manner. For example, on the host side, the host may send a first command to the memory system before a second command. The host may receive a second response signal from the memory system before a first response signal. On the memory system side, the memory system may receive a first command from the host before a second command. The memory system may send a second response signal to the host before the first response signal. As such, the order in which one or more commands are sent / received is different from the order in which one or more response / confirmation signals are received / sent, and thus the host and the memory system communicate in an out-of-order manner. Reference Figure 7 Describe in more detail.

[0164] refer to Figure 8B At block 830, the host sends metadata to the memory system. The details of the metadata are as described above and will not be repeated here.

[0165] At block 832, the memory system receives metadata from the host.

[0166] At block 834, the memory system sends a request for permission to the host. The details of the permission are as described above and will not be repeated here.

[0167] At block 836, the host receives a request for permissions from the memory system.

[0168] At block 838, in response to receiving the request for permission, the host sends permission to the memory system, thereby allowing the memory system to not receive commands and / or data from the host for a period of time. In other words, the controller is allowed to fully control the memory system during the period. The details of full control are as described above and will not be repeated here.

[0169] At block 840, the memory system receives permissions from the host.

[0170] The example process 800 is for illustration purposes only and the present disclosure is not limited thereto. Fig. 8A and Figure 8B Although the blocks / boxes are shown in a certain order in the drawings, they may be performed in a different order. Fig. 8A and Figure 8B Any block / frame in the example process 800 may be performed once, twice, or multiple times. In addition, additional blocks / frames may be added to the example process 800. In addition, any block / frame may be combined / split.

[0171] Using the above example process 800, a response signal can be sent from the memory system to the host. Therefore, when the host performs various operations on the memory system, the host can have information about whether the operation is successful and when the operation is completed. Therefore, the communication between the host and the memory system can be carried out accurately and flexibly.

[0172] In other words, memory control is improved.

[0173] Fig. 9 An example process 900 of memory control is shown.

[0174] At block 902, the memory architecture receives a command from a host via a transaction interface provided between the memory architecture and the host. In an implementation, the memory architecture may receive a read command. In an implementation, the memory architecture may receive a compute command. In an implementation, the memory architecture may receive a write command and data to be written.

[0175] At block 904, the memory architecture performs an operation in response to receiving the command. In an implementation, the operation may be performed using non-deterministic timing. In an implementation, the memory architecture prepares data according to a read command. In an implementation, the memory architecture performs a computation according to a compute command. In an implementation, the memory architecture performs a write operation according to a write command.

[0176] At block 906, the memory architecture sends a response signal to the host via a response signal channel of the transaction interface indicating completion of the operation.

[0177] In an implementation, the memory architecture may receive metadata from the host via a transaction interface. In an implementation, the memory architecture may send a request for permission to the host via a transaction interface, and receive permission from the host via the transaction interface, thereby allowing the memory architecture to not receive commands and / or data from the host for a period of time. In other words, the controller is allowed to fully control the memory architecture during the period. The details of full control are as described above and will not be repeated here.

[0178] Using the above example process 900, a response signal can be sent from the memory system to the host. Therefore, when the host performs various operations on the memory system, the host can have information about whether the operation is successful and when the operation is completed. Therefore, the communication between the host and the memory system can be carried out accurately and flexibly.

[0179] In other words, memory control is improved.

[0180] Fig.10 An example table 1000 comparing the characteristics of a memory architecture based on a conventional DDR interface and a memory architecture based on a transactional interface is shown. In an implementation, a memory architecture based on a transactional interface may utilize the memory architecture described above with reference to Figures 4 to 9 The described memory system is implemented.

[0181] Reference Fig.10 , table 1000 may include the following:

[0182] Row 1002 shows the number of accelerators per module for a conventional memory architecture based on a DDR interface and a memory architecture based on a transaction interface. Row 1004 shows the maximum capacity of a conventional memory architecture based on a DDR interface and a memory architecture based on a transaction interface. Row 1006 shows whether the memory-to-host response is supported by a conventional memory architecture based on a DDR interface and a memory architecture based on a transaction interface. Row 1008 shows whether ECC support is difficult for a conventional memory architecture based on a DDR interface and a memory architecture based on a transaction interface. Row 1010 shows whether a conventional memory architecture based on a DDR interface and a memory architecture based on a transaction interface support non-deterministic communication. Row 1012 shows whether a conventional memory architecture based on a DDR interface and a memory architecture based on a transaction interface support out-of-order communication. Row 1014 shows host requirements for a conventional memory architecture based on a DDR interface and a memory architecture based on a transaction interface.

[0183] Column 1016 shows the characteristics of the following conventional DDR interface-based modules. For example, the number of accelerators per module N is less than or equal to 16, because conventional DDR interface-based modules can include up to 16 chips. The maximum capacity of conventional DDR interface-based modules is in the order of GB. Memory to host response is not applicable to (N / A) conventional DDR interface-based modules, because conventional DDR interface-based modules cannot send response / confirmation signals. Compared with the memory architecture based on the transaction interface, ECC support is relatively difficult for modules based on the conventional DDR interface. Because conventional DDR interface-based modules cannot send response / confirmation signals, conventional DDR interface-based modules do not support non-deterministic communication. Conventional DDR interface-based modules do not support out-of-order communication, because conventional DDR interface-based modules cannot send response / confirmation signals. Regarding host requirements, conventional DDR interface-based modules require the host to have structure / logic to support conventional DDR operations.

[0184] Column 1018 shows the following characteristics of a memory architecture based on a transactional interface. For example, there is no limit on the number of accelerators for each module of a memory architecture based on a transactional interface. The maximum capacity of a memory architecture based on a transactional interface is in the order of TB. Memory-to-host communication is supported by a memory architecture based on a transactional interface. Compared to traditional DDR interface-based modules, ECC support is relatively easy for a memory architecture based on a transactional interface. Non-deterministic communication is supported by a memory architecture based on a transactional interface. A memory architecture based on a transactional interface supports out-of-order communication. Regarding host requirements, a memory architecture based on a transactional interface requires the host to have a structure / logic to support transactional interface operations.

[0185] In summary, compared with the traditional module based on the DDR interface, the characteristics of the module based on the transaction interface are improved.

[0186] The process, mechanism and system described herein are only examples, and are not intended to impose any limitation on the scope of the present disclosure. The numerals and values ​​used herein are for the purpose of description, rather than limiting the scope of the present disclosure. The process, mechanism and system described herein can be implemented in any computing device, system, environment and / or configuration, including but not limited to personal computers, server computers, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set-top boxes, game consoles, programmable consumer electronics, network PCs, minicomputers, mainframe computers, distributed computing environments.

[0187] Some or all of the operations of the above methods may be performed by executing computer-readable instructions stored on a computer-readable storage medium, as defined below. The term "computer-readable instructions" as used in the specification and claims includes routines, applications, application modules, program modules, programs, components, data structures, algorithms, etc. Computer-readable instructions can be implemented on different system configurations, including single-processor or multi-processor systems, minicomputers, mainframe computers, personal computers, handheld computing devices, microprocessor-based programmable consumer electronics, combinations thereof, and the like.

[0188] Computer-readable storage media may include volatile memory (such as random access memory (RAM)) and / or non-volatile memory (such as read-only memory (ROM), flash memory, etc.). Computer-readable storage media may also include additional removable storage and / or non-removable storage, including but not limited to flash memory, magnetic storage, optical storage, and / or tape storage that can provide non-volatile storage of computer-readable instructions, data structures, program modules, etc.

[0189] Non-transient computer-readable storage media are examples of computer-readable media. Computer-readable media include at least two types of computer-readable media, namely computer-readable storage media and communication media. Computer-readable storage media include volatile and non-volatile, removable and non-removable media implemented with any process or technology for storing information such as computer-readable instructions, data structures, program modules or other data. Computer-readable storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), DRAM, other types of RAM, ROM, electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, cassettes, tapes, disk storage or other magnetic storage devices, or any other non-transmission media that can be used to store information for access by a computing device. In contrast, communication media can implement computer-readable instructions, data structures, program modules or other data in modulated data signals (such as carrier waves) or other transmission mechanisms. As defined herein, computer-readable storage media do not include communication media.

[0190] Computer readable instructions stored on one or more non-transitory computer readable storage media, when executed by one or more processors, may perform the operations described above with reference to Figures 1-9. In general, computer readable instructions include routines, programs, objects, components, data structures, etc. that perform specific functions or implement specific abstract data types. The order in which the operations are described is not intended to be construed as a limitation, and any number of the described operations may be combined in any order and / or in parallel to implement a process.

[0191] Sample Clauses

[0192] Item 1. A memory architecture comprising: one or more accelerators, each of the one or more accelerators comprising a corresponding storage area configured to store data and a corresponding computing unit configured to perform calculations, the corresponding storage area and the corresponding computing unit being configured to interact with each other; a controller, arranged in cooperation with the one or more accelerators, the controller being configured to control the one or more accelerators; receiving commands from a host; and performing operations in response to receiving the commands; and a transaction interface, arranged in cooperation between the controller and the host, the transaction interface comprising command and address signal channels, the command and address signal channels being configured to transmit command and address signals from the host to the controller.

[0193] Item 2. A memory architecture according to Item 1, wherein the controller is further configured to execute the operation with deterministic timing to complete the operation at a predetermined time if the operation includes at least one of a read operation, a compute operation, and a write operation; and to return the result of the operation to the host at a predetermined time if the operation includes at least one of a read operation and a compute operation.

[0194] Item 3. A memory architecture according to Item 1, wherein the transaction interface further includes a response signal channel, and wherein the controller is further configured to perform an operation with non-deterministic timing; and when the operation is completed, a response signal indicating the completion of the operation is sent to the host via the response signal channel.

[0195] Item 4. A memory architecture according to Item 1, wherein the controller is further configured to send a request for permission to the host; and receive the permission from the host, wherein the permission allows the memory architecture to not receive commands and / or data from the host within a cycle.

[0196] Item 5. A memory architecture according to Item 1, wherein the transaction interface further includes a data bus configured to transfer data from a host to the memory architecture / from the memory architecture to the host; and a check bit channel for transferring metadata and / or error correction code (ECC) from the host to the memory architecture, or from the memory architecture to the host.

[0197] Item 6. A system comprising: a memory architecture comprising one or more accelerators, each of the one or more accelerators comprising a corresponding storage area configured to store data and a corresponding computing unit configured to perform calculations, the corresponding storage area and the corresponding computing unit being configured to interact with each other; a controller, arranged in cooperation with the one or more accelerators, the controller being configured to control the one or more accelerators; receiving commands from a host; and performing operations in response to receiving the commands; and a transaction interface, arranged in cooperation between the controller and the host, the transaction interface comprising a command and address signal channel, the command and address signal channel being configured to transmit command and address signals from the host to the controller; the host, arranged in cooperation with the transaction interface, the host being configured to send the command and address signals.

[0198] Clause 7. A system according to Clause 6, wherein the controller is further configured to execute the operation with deterministic timing to complete the operation at a predetermined time if the operation includes at least one of a read operation, a compute operation, and a write operation; and to return the result of the operation to the host at a predetermined time if the operation includes at least one of a read operation and a compute operation.

[0199] Clause 8. A system according to clause 6, wherein the transaction interface further includes a response signal channel; and wherein the controller is further configured to perform an operation with non-deterministic timing; and when the operation is completed, a response signal indicating the completion of the operation is sent to the host via the response signal channel.

[0200] Clause 9. The system of clause 6, wherein the controller is further configured to send a request for permission to the host; and receive the permission from the host, the permission allowing the memory architecture to not receive commands and / or data from the host for a period of time.

[0201] Item 10. A method comprising: receiving, by a memory architecture, a command from a host via a transaction interface cooperatively arranged between the memory architecture and the host; performing, by the memory architecture, an operation in response to receiving the command; and sending, by the memory architecture, a response signal indicating completion of the operation to the host via a response signal channel of the transaction interface.

[0202] Clause 11. The method of clause 10, wherein performing, by the memory architecture in response to receiving the command, the operation comprises performing, by the memory architecture, the operation with non-deterministic timing.

[0203] Clause 12. A method according to clause 10, wherein receiving the command from the host through the memory architecture via the transaction interface cooperatively arranged between the memory architecture and the host includes receiving a read command from the host through the memory architecture via the transaction interface cooperatively arranged between the memory architecture and the host.

[0204] Clause 13. The method of clause 12, wherein performing, by the memory architecture, the operation in response to receiving the command comprises preparing, by the memory architecture, data in response to receiving a read command.

[0205] Clause 14. The method of clause 13, further comprising: receiving, by the memory architecture, a get command from the host; and sending, by the memory architecture, the data to the host in response to receiving the get command from the host.

[0206] Clause 15. A method according to clause 10, wherein receiving the command from the host through the memory architecture via the transaction interface cooperatively set between the memory architecture and the host includes receiving a computing command from the host through the memory architecture via the transaction interface cooperatively set between the memory architecture and the host.

[0207] Clause 16. The method of Clause 15, wherein performing, by the memory architecture, the operation in response to receiving the command comprises performing, by the memory architecture, a computing operation in response to receiving the computing command.

[0208] Clause 17. A method according to clause 10, wherein receiving the command from the host through the memory architecture via the transaction interface cooperatively set between the memory architecture and the host includes receiving a write command and data to be written from the host through the memory architecture via the transaction interface cooperatively set between the memory architecture and the host.

[0209] Clause 18. The method of Clause 17, wherein performing, by the memory architecture in response to receiving the command, the operation comprises performing, by the memory architecture in response to receiving the write command and data to be written, a write operation.

[0210] Clause 19. The method of clause 10, further comprising: receiving, by the memory architecture, metadata and / or error correction code (ECC) from the host via a transaction interface cooperatively provided between the memory architecture and the host.

[0211] Clause 20. The method of clause 10, further comprising: sending, by the memory architecture, a permission request to the host; and receiving the permission from the host, the permission allowing the memory architecture to not receive commands and / or data from the host for a period of time.

[0212] Item 21. A computer-readable storage medium storing computer-readable instructions executable by one or more processors, wherein the computer-readable instructions, when executed by the one or more processors, cause the one or more processors to perform actions, the actions comprising: sending a command by a host to the memory architecture via a transaction interface cooperatively arranged between the memory architecture and the host; and receiving a response signal indicating completion of an operation from the memory architecture via a response signal channel of the transaction interface cooperatively arranged between the memory architecture and the host.

[0213] Clause 22. The computer-readable storage medium of Clause 21, wherein the response signal is received by the host from the memory architecture with non-deterministic timing.

[0214] Clause 23. A computer-readable storage medium according to Clause 21, wherein sending the command to the memory architecture by the host via the transaction interface cooperatively set up between the memory architecture and the host includes sending a read command to the memory architecture by the host via the transaction interface cooperatively set up between the memory architecture and the host.

[0215] Clause 24. The computer-readable storage medium of clause 23, the actions further comprising: sending, by the host, a get command to the memory architecture; and receiving, by the host, data from the memory architecture.

[0216] Clause 25. A computer-readable storage medium according to Clause 21, wherein sending the command to the memory architecture by the host via the transaction interface cooperatively set up between the memory architecture and the host includes sending a computing command to the memory architecture by the host via the transaction interface cooperatively set up between the memory architecture and the host.

[0217] Clause 26. A computer-readable storage medium according to Clause 21, wherein sending the command to the memory architecture by the host via the transaction interface cooperatively arranged between the memory architecture and the host includes sending a write command and data to be written to the memory architecture by the host via the transaction interface cooperatively arranged between the memory architecture and the host.

[0218] Clause 27. According to the computer-readable storage medium of Clause 21, the action also includes: sending metadata and / or error correction code (ECC) by the host to the memory architecture via the transaction interface set up between the memory architecture and the host.

[0219] Clause 28. According to the computer-readable storage medium described in Clause 21, the action also includes: receiving, by the host, a request for permissions from the memory architecture; and in response to receiving the request, sending, by the host, the permissions to the memory architecture, wherein the permissions allow the memory architecture to not receive the request for commands and / or data from the host for a period of time.

[0220] in conclusion

[0221] Although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that

[0222] The subject matter defined in the appended claims is not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as example forms of implementing the claims.

Claims

1. A memory architecture comprising: One or more accelerators, each accelerator of the one or more accelerators comprising: a corresponding storage area configured to store data and a corresponding computing unit configured to perform calculations, the corresponding storage area and the corresponding computing unit being configured to interact with each other; A controller is provided in cooperation with the one or more accelerators, the controller being configured to: control the one or more accelerators; receive a command from a host; and perform an operation in response to receiving the command; and A transaction interface is provided between the controller and the host, the transaction interface includes a command and address signal channel, the command and address signal channel is configured to transmit command and address signals from the host to the controller; the transaction interface also includes: a check bit channel, configured to transmit metadata from the host to a data buffer in the memory architecture, or, to transmit metadata from a data buffer in the memory architecture to the host; the metadata is used to instruct the controller to direct data to different media.

2. The memory architecture of claim 1, wherein: The controller is further configured to: If the operation includes at least one of a read operation, a compute operation, and a write operation, performing the operation in a deterministic timing to complete the operation at a predetermined time; as well as If the operation includes at least one of a read operation and a calculation operation, a result of the operation is returned to the host at a predetermined time.

3. The memory architecture of claim 1 , wherein: The transaction interface further includes a response signal channel; and Wherein, the controller is further configured to perform the operations in a non-deterministic timing; and When the operation is completed, a response signal indicating the completion of the operation is transmitted to the host via the response signal channel.

4. The memory architecture of claim 1, wherein: The controller is further configured to: sending a request for permission to the host; and The permission is received from the host, the permission allowing the memory architecture to not receive commands and / or data from the host for a period of time.

5. The memory architecture of claim 1, wherein: The transaction interface further comprises: a data bus configured to transfer data from the host to the memory architecture or from the memory architecture to the host; and The check bit channel is further configured to transmit an error correction code (ECC) from the host to the memory architecture or from the memory architecture to the host.

6. A memory control system, comprising: Memory architecture, including: One or more accelerators, each accelerator of the one or more accelerators includes a corresponding storage area configured to store data and a corresponding computing unit configured to perform calculations, the corresponding storage area and the corresponding computing unit are configured to interact with each other; a controller, arranged in cooperation with the one or more accelerators, the controller being configured to control the one or more accelerators; receive a command from a host; and perform an operation in response to receiving the command; and a transaction interface, arranged between the controller and the host, the transaction interface comprising a command and address signal channel, the command and address signal channel being configured to transmit command and address signals from the host to the controller; the transaction interface further comprising: a check bit channel, being configured to transmit metadata from the host to a data buffer in the memory architecture, or to transmit metadata from a data buffer in the memory architecture to the host; the metadata being used to instruct the controller to direct data to different media; The host is arranged in cooperation with the transaction interface, and is configured to send the command and address signals, and the data.

7. The system according to claim 6, wherein: The controller is further configured to: If the operation includes at least one of a read operation, a calculation operation, and a write operation, performing the operation in a deterministic timing to complete the operation at a predetermined time; and If the operation includes at least one of a read operation and a calculation operation, a result of the operation is returned to the host at a predetermined time.

8. The system according to claim 6, wherein: The transaction interface further includes a response signal channel; and Wherein, the controller is further configured as follows: performing the operations in a non-deterministic timing; and When the operation is completed, a response signal indicating the completion of the operation is transmitted to the host via the response signal channel.

9. The system according to claim 6, wherein: The controller is further configured to: sending a request for permission to the host; and The permission is received from the host, the permission allowing the memory architecture to not receive commands and / or data from the host for a period of time.

10. A memory control method, comprising: Receiving, by the memory architecture, commands and metadata from the host via a transaction interface cooperatively arranged between the memory architecture and the host; performing, by the memory architecture, an operation in response to receiving the command and metadata, wherein the metadata is used to instruct a controller to direct data to a different medium; and The memory architecture sends a response signal indicating completion of the operation to the host via a response signal channel of the transaction interface; The transaction interface further includes: a check bit channel configured to transmit metadata from the host to a data buffer in the memory architecture, or to transmit metadata from the data buffer in the memory architecture to the host.

11. The method according to claim 10, wherein: The memory architecture performing an operation in response to receiving the command includes: The operations are performed by the memory architecture with non-deterministic timing.

12. The method according to claim 10, wherein: The receiving, by the memory architecture, a command from the host via the transaction interface cooperatively arranged between the memory architecture and the host comprises: The memory architecture receives a read command from the host via the transaction interface cooperatively arranged between the memory architecture and the host.

13. The method according to claim 12, wherein: The memory architecture performing the operation in response to receiving the command comprises: Data is prepared by the memory architecture in response to receiving the read command.

14. The method according to claim 13, further comprising: receiving, by the memory architecture, a get command from the host; as well as In response to receiving the get command from the host, the data is sent by the memory architecture to the host.

15. The method according to claim 10, wherein: The receiving, by the memory architecture, the command from the host via the transaction interface cooperatively arranged between the memory architecture and the host comprises: A computing command is received by the memory architecture from the host via the transaction interface cooperatively arranged between the memory architecture and the host.

16. The method according to claim 15, wherein: The memory architecture performing the operation in response to receiving the command comprises: A computing operation is performed by the memory architecture in response to receiving the computing command.

17. The method according to claim 10, wherein: The receiving, by the memory architecture, a command from the host via the transaction interface cooperatively arranged between the memory architecture and the host comprises: The memory architecture receives a write command and data to be written from the host via the transaction interface cooperatively arranged between the memory architecture and the host.

18. The method according to claim 17, wherein: The memory architecture performing the operation in response to receiving the command comprises: A write operation is performed by the memory architecture in response to receiving the write command and the data to be written.

19. The method according to claim 10, further comprising: The memory architecture receives an error correction code (ECC) from the host via the transaction interface cooperatively arranged between the memory architecture and the host.

20. The method according to claim 10, further comprising: sending, by the memory architecture, a request for permission to the host; as well as The permission is received from the host, the permission allowing the memory architecture to not receive commands and / or data from the host for a period of time.

21. A computer-readable storage medium storing computer-readable instructions executable by one or more processors, wherein when executed by the one or more processors, the computer-readable instructions cause the one or more processors to perform actions, the actions comprising: The host sends a command and metadata to the memory architecture via a transaction interface cooperatively provided between the memory architecture and the host, wherein the metadata is used to instruct the controller to direct data to different media; and The host receives a response signal indicating that the operation is completed from the memory architecture via a response signal channel of the transaction interface provided between the memory architecture and the host; The transaction interface further includes: a check bit channel configured to transmit metadata from the host to a data buffer in the memory architecture, or to transmit metadata from the data buffer in the memory architecture to the host.

22. The computer-readable storage medium of claim 21, wherein: The response signal is received by the host from the memory architecture with non-deterministic timing.

23. The computer-readable storage medium of claim 21, wherein: The sending of the command and metadata by the host to the memory architecture via the transaction interface cooperatively arranged between the memory architecture and the host comprises: The host sends a read command and metadata to the memory architecture via the transaction interface cooperatively arranged between the memory architecture and the host.

24. The computer-readable storage medium of claim 23, the actions further comprising: Sending, by the host, a get command to the memory architecture; as well as Data is received by the host from the memory architecture.

25. The computer-readable storage medium of claim 21, wherein: The sending of the command and metadata by the host to the memory architecture via a transaction interface cooperatively arranged between the memory architecture and the host comprises: The host sends computing commands and metadata to the memory architecture via a transaction interface cooperatively arranged between the memory architecture and the host.

26. The computer-readable storage medium of claim 21, wherein: The sending of the command and metadata by the host to the memory architecture via a transaction interface cooperatively arranged between the memory architecture and the host comprises: The host sends a write command, data to be written, and metadata to the memory architecture via a transaction interface cooperatively arranged between the memory architecture and the host.

27. The computer-readable storage medium of claim 21, the actions further comprising: The host sends an error correction code ECC to the memory architecture via the transaction interface cooperatively arranged between the memory architecture and the host.

28. The computer-readable storage medium of claim 21, the actions further comprising: Receiving, by the host, a request for permission from the memory architecture; as well as In response to receiving the request, the host sends the permission to the memory architecture, the permission allowing the memory architecture to not receive the request for commands and / or data from the host for a period of time.

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