Signal processing device, imaging device, reading device, image forming device, and signal processing method

Abstract

A signal processing device includes a data writing unit, a channel number conversion unit, and a plurality of serial data transmission units. The data writing unit is configured to write data of m channels into a memory. The channel number conversion unit is configured to output data read from the memory as data of n channels, where m is greater than n. The plurality of serial data transmission units are configured to transmit the data of the n channels to a processing device in a subsequent stage.

Description

Technical Field

[0001] The present invention relates to a signal processing device, an imaging device, a reading device, an image forming device, and a signal processing method. Background Art

[0002] A conventionally known imaging device including a solid-state imaging element has a three-line sensor structure including RGB pixels or a four-line sensor structure capable of reading invisible light such as infrared light in addition to visible light such as RGB.

[0003] On the other hand, a technology for reducing the data transmission speed is disclosed in Patent Document 1. In this technology, an image readout signal is converted into digital data, speed conversion is performed using a RAM (Random Access Memory), and then the data is transmitted using LVDS (Low Voltage Differential Signaling). Summary of the invention

[0004] [Technical issues]

[0005] However, in a conventional four-line sensor, considering that image data of four colors is transmitted as image signals to a signal processing IC in a subsequent stage through a dedicated transmission line, and when there are many IF signals between the sensor IC and the signal processing IC, limitations occur when installing the IC, which is a problem.

[0006] Furthermore, in order to process image data having four colors, simply, the number of systems only needs to be increased. In Patent Document 1, six systems are used. However, in order to process image data of RGB*10 bits, a system providing at least five LVDS data channels is sufficient; therefore, even in the case of processing three or more colors, it is expected that all data can be transmitted in five systems. Furthermore, increasing the number of channels leads to limitations when mounting ICs, which is a problem.

[0007] The present invention has been accomplished in view of the above circumstances, and an object of the present invention is to transmit data at a low cost without increasing the number of channels.

[0008] [Solution to the problem]

[0009] A signal processing device according to one aspect of the present invention includes a data writing unit, a channel number conversion unit, and a plurality of serial data transmission units. The data writing unit is configured to write data of m channels into a memory. The channel number conversion unit is configured to output data read from the memory as data of n channels, where m is greater than n. The plurality of serial data transmission units are configured to transmit the data of the n channels to a processing device in a subsequent stage.

[0010] [Beneficial Effects of the Invention]

[0011] According to one aspect of the present invention, it is possible to suppress the occurrence of restrictions when mounting an IC at low cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a diagram showing the structure of one example of the image forming apparatus according to the first embodiment.

[0013] Figure 2 is a cross-sectional view illustrating an example of the structure of the image reading apparatus.

[0014] Figure 3 is a block diagram showing the electrical connection of each unit in the image reading apparatus.

[0015] Figure 4 is a diagram showing a circuit configuration example of a signal processing unit and an image processing unit in the image reading apparatus.

[0016] Figure 5 is a diagram showing one example of the structure of a channel number conversion circuit included in the signal processing unit.

[0017] Figure 6 is a timing chart showing one example of data processing in the signal processing unit.

[0018] Figure 7 is a timing chart showing one example of data processing in the image processing unit.

[0019] Figure 8 is a diagram showing a circuit configuration example of a signal processing unit and an image processing unit in an image reading apparatus according to the second embodiment.

[0020] Fig. 9 is a diagram showing a circuit configuration example of a signal processing unit and an image processing unit in an image reading apparatus according to a third embodiment.

[0021] Fig.10 is a timing chart showing one example of data processing in the signal processing unit according to the fourth embodiment.

[0022] Fig.11 is a timing chart showing one example of data processing in the signal processing unit according to the fifth embodiment.

[0023] Fig.12 is a diagram showing a circuit configuration example of a signal processing unit and an image processing unit in an image reading apparatus according to a sixth embodiment. DETAILED DESCRIPTION

[0024] Embodiments of a signal processing apparatus, an imaging apparatus, a reading apparatus, an image forming apparatus, and a signal processing method are described in detail below with reference to the accompanying drawings.

[0025] First embodiment

[0026] Figure 1 1 is a diagram showing a structure of an example of an image forming apparatus 100 according to the first embodiment. Figure 1 In the present invention, the image forming apparatus 100 is generally referred to as a multifunction peripheral, which has at least two functions among a copy function, a printer function, a scanner function, and a fax function.

[0027] The image forming apparatus 100 includes an image reading apparatus 101 as a reading apparatus and an ADF (Automatic Document Feeder) 102, and also includes an image forming unit 103 located therebelow. As for the image forming unit 103, in order to describe the internal structure, the internal structure of the outer cover removed therefrom is illustrated.

[0028] ADF 102 is a document support unit that positions a document containing an image to be read at a reading position. ADF 102 automatically transports the document on the mounting table to the reading position. Image reading device 101 reads the document transported by ADF 102 at a predetermined reading position. In addition, image reading device 101 includes a contact glass located on its upper surface, and reads a document on the contact glass corresponding to the reading position, the contact glass being a document support unit having a document thereon. Specifically, image reading device 101 is a scanner that internally includes a light source, an optical system, and a solid-state imaging element such as a CMOS image sensor. Image reading device 101 reads reflected light from a document irradiated with a light source using a solid-state imaging element through an optical system.

[0029] The image forming unit 103 includes a manual paper feed roller 104 to which recording paper is fed by hand, and a recording paper supply unit 107 to supply recording paper. The recording paper supply unit 107 has a mechanism to feed recording paper from a multi-stage recording paper feed cassette 107a. The supplied recording paper is sent to the secondary transfer belt 112 through a registration roller 108.

[0030] The toner image on the intermediate transfer belt 113 is transferred at the transfer unit 114 onto the recording paper transported on the secondary transfer belt 112 .

[0031] In addition, the image forming unit 103 includes an optical writing device 109, a tandem system image forming unit (Y, M, C, K) 105, an intermediate transfer belt 113, the above-mentioned secondary transfer belt 112, etc. Through the image forming process of the image forming unit 105, the image written by the optical writing device 109 can be formed on the intermediate transfer belt 113 as a toner image.

[0032] Specifically, the image forming unit (Y, M, C, K) 105 includes four photosensitive drums (Y, M, C, K) so that the photosensitive drums can rotate. Around each photosensitive drum, an image forming element 106 is provided. The image forming element 106 includes a charging roller, a developing device, a primary transfer roller, a cleaner unit, and a static eliminator. In each photosensitive drum, the image forming element 106 works, and the image on the photosensitive drum is transferred to the intermediate transfer belt 113 by each primary transfer roller.

[0033] The intermediate transfer belt 113 is set at the roller gap between each photosensitive drum and each primary transfer roller, where tension is applied by a driving roller and a driven roller. When the intermediate transfer belt 113 is running, the toner image transferred to the intermediate transfer belt 113 by the primary transfer is transferred to the recording paper on the secondary transfer belt 112 by the secondary transfer device through secondary transfer. When the secondary transfer belt 112 is running, the recording paper is conveyed to the fixing device 110, and the toner image is fixed on the recording paper as a color image. After that, the recording paper is discharged to the paper output tray outside the machine. In the case of double-sided printing, the recording paper is turned over by the turning mechanism 111, and the turned over recording paper is sent to the secondary transfer belt 112.

[0034] Note that the image forming unit 103 is not limited to forming an image by the electrophotographic method as described above, and may form an image by an inkjet method.

[0035] Next, the image reading apparatus 101 is described.

[0036] Figure 2 1 is a cross-sectional view showing an example of the structure of the image reading device 101. Figure 2 As shown, the image reading device 101 includes a sensor board 10 in a main body 11, and the sensor board 10 includes an imaging device 9, a lens unit 8, a first bracket 6 and a second bracket 7. The first bracket 6 includes a light source 2 and a mirror 3, and the light source 2 is an LED (light emitting diode). The second bracket 7 includes mirrors 4 and 5. The image reading device 101 also has a contact glass 1 and a reference white plate 13 located on its upper surface.

[0037] In the reading operation, the image reading device 101 causes the light source 2 to emit light upward while moving the first carriage 6 and the second carriage 7 from the standby position (home position) in the sub-scanning direction (direction A). Then, the first carriage 6 and the second carriage 7 form an image on the imaging device 9 through the lens unit 8 using the reflected light from the document 12.

[0038] For example, when the power is turned on, the image reading device 101 sets a reference by reading the reflected light from the reference white plate 13. That is, the image reading device 101 moves the first bracket 6 to just below the reference white plate 13, turns on the light source 2, and causes the reflected light from the reference white plate 13 to form an image on the imaging device 9; thus, gain control is performed.

[0039] In the imaging device 9 (see Figure 4 ) is arranged in which pixels for converting the incident light amount into an electrical signal are arranged. The pixels are arranged in a matrix, and the electrical signals obtained from the pixels are transmitted to the signal processing unit 21 of the subsequent stage in a predetermined order at regular intervals (see Figure 4 ) (Pixel readout signal). On each pixel, a filter that transmits light of a specific wavelength is provided. In the imaging device 9 according to the present embodiment, each signal obtained from a pixel group provided with the same filter is referred to as a channel.

[0040] Figure 3 1 is a block diagram showing the electrical connection of each unit in the image reading device 101. Figure 3 As shown, in addition to the above-mentioned imaging device 9 and light source 2, the image reading device 101 further includes an image processing unit 20, a control unit 23, and a light source driving unit 24. The light source driving unit 24 drives the light source 2.

[0041] The imaging device 9 includes a solid-state imaging element 22 and a signal processing unit 21 corresponding to a signal processing device. The solid-state imaging element 22 is a sensor of a reduction optical system, such as a CMOS image sensor, etc. The solid-state imaging element 22 includes a pixel array 220. The pixel array 220 includes a plurality of photodiodes (PDs) arranged in a matrix to form pixels, and transmits the photoelectric conversion results to the signal processing unit 21 of the subsequent stage in a predetermined order.

[0042] The signal processing unit 21 includes a gain control unit (amplifier), an offset control unit, an A / D conversion unit (ADC circuit), etc. The signal processing unit 21 performs gain control, offset control, A / D conversion, etc. on the image signal (R / G / B / NIR) output from the solid-state imaging element 22.

[0043] The control unit 23 controls the setting of each unit of the light source driving unit 24 , the solid-state imaging element 22 , the signal processing unit 21 , and the image processing unit 20 .

[0044] The image processing unit 20 performs various image processing.

[0045] Next, the circuit structure of each of the signal processing unit 21 and the image processing unit 20 is described in detail.

[0046] here, Figure 4is a diagram illustrating a circuit configuration example of the signal processing unit 21 and the image processing unit 20 in the image reading apparatus 101 .

[0047] In the present embodiment, each of m and n is an integer of 1 or greater satisfying m>n. In the description of the present embodiment, image data acquired by the solid-state imaging element 22 is processed; however, the signal processing device having a structure according to the present invention is not limited to the case of processing only image data.

[0048] like Figure 4 As shown, the signal processing unit 21 includes an ADC circuit 211, a speed conversion circuit 212 corresponding to the data writing unit and the speed conversion unit, a channel number conversion circuit 213 corresponding to the channel number conversion unit, a data transmission clock generation circuit 214, a mapping circuit 215, a parallel-serial circuit 216, a data transmission circuit 217, a data storage clock generation circuit 218, a control register 219, etc. The control register 219 stores various settings therein by the control unit 23.

[0049] like Figure 4 As shown, in the signal processing unit 21, the ADC circuit 211 converts the pixel readout signal (A1 to Am) of each channel obtained from the solid-state imaging element 22 into digital data (DI1 to DIm) having 10 bits. Synchronously with the speed conversion circuit write clock (WCLK) having the same frequency as the pixel readout frequency, the converted DI1 to DIm signals are written into the speed conversion circuit 212. Note that WCLK is generated by the data storage clock generation circuit 218.

[0050] The data written in the memory of the speed conversion circuit 212 is read out in synchronization with the speed conversion circuit read clock (RCLK). Note that RCLK is generated by the data transfer clock generation circuit 214 which generates the data transfer clock (SERCLK).

[0051] The m channels and 10-bit data (DO1 to DOm) read from the memory in the speed conversion circuit 212 are converted into 10-bit data of n channels (D1 to Dn) synchronized with MCLK by the channel number conversion circuit 213. Note that MCLK is generated by the data transmission clock generation circuit 214 that generates the data transmission clock (SERCLK).

[0052] Here, the channel number conversion circuit 213 included in the signal processing unit 21 is described in detail. Figure 5 2 is a diagram showing an example of the structure of the channel number conversion circuit 213 included in the signal processing unit 21. Here, m is four, and n is three. Figure 5As shown, the channel number conversion circuit 213 includes a data reordering unit 2131, a processing selection register 2132, and a selector 2133. In the channel number conversion circuit 213, the data reordering unit 2131 reorders the four-channel image data (DO1 to DO4) read out from the speed conversion circuit 212 to generate three-channel image data (D1 to D3).

[0053] The selector 2133 selectively outputs three-channel image data ( D1 to D3 ) to be output to the subsequent stage through control via the processing selection register 2132 .

[0054] Note that the channel number conversion circuit 213 may have a function of selecting a portion of the input multi-channel image data and outputting the selected image data without reordering the data. For example, in the case where only predetermined three-channel image data (DO1 to DO3) are required in the image processing unit 20, as shown in FIG. Figure 5 As shown, predetermined three-channel image data can be output by bypassing the data reordering unit 2131. Therefore, only by processing the setting of the selection register 2132, three-channel or four-channel image data transmission switching becomes possible in one device without changing the circuit or switching the transmission line.

[0055] The data (D1 to Dn) converted by the channel number conversion circuit 213 is transmitted to the image processing unit 20 through the mapping circuit 215, the parallel-serial circuit 216 and the data transmission circuit 217 of the subsequent stage. The mapping circuit 215 performs mapping processing on the data (D1 to Dn) converted by the channel number conversion circuit 213, and obtains five systems of MA to ME signals with 7 bits, for example. The parallel-serial circuit 216 performs parallel-serial conversion on the MA to ME signal, and obtains the SA to SE signal synchronized with the SERCLK signal. In addition, the image processing unit 20 generates a transmission data synchronization clock SCK for performing serial-parallel conversion. Therefore, the channel number conversion circuit 213, the mapping circuit 215, the parallel-serial circuit 216 and the data transmission circuit 217 realize a data transmission unit.

[0056] On the other hand, Figure 4 As shown, the image processing unit 20 includes a data transmission circuit 201, a serial-to-parallel circuit 202, a mapping circuit 203, a channel number conversion circuit 204, a memory 205, various image processing circuits 206, an image processing clock generation circuit 207, and the like.

[0057] like Figure 4As shown, in the image processing unit 20, the channel number conversion circuit 204 converts the data of n channels and 10 bits, which have been transmitted through the serial-to-parallel circuit 202 and the mapping circuit 203 of the subsequent stage, into data of m channels and 10 bits (PI1 to PIm), and writes the data into the memory 205 provided for the m channels using the clock (PCLK) synchronized with the clock transmitted together with the data through the data transmission circuit 201. After the memory is read out in the image processing unit 20, the processing in the various image processing circuits 206 is performed in synchronization with the clock (SCLK) generated by the image processing clock generation circuit 207.

[0058] Note that in the following description, as an example, the number of channels m of input data from the solid-state imaging element 22 is four, and the number of channels n of data transmission is three. Note that m is not limited to four, and n is not limited to three.

[0059] Next, the data processing in the signal processing unit 21 is described in detail. Here, Figure 6 is a timing chart showing an example of data processing in the signal processing unit 21. Figure 6 In the example shown, four channels of image data are processed in the signal processing unit 21 .

[0060] Note that Figure 6 In the present invention, details of the process from the output of the solid-state imaging element 22 to the generation of digital data by the ADC circuit 211 are omitted.

[0061] like Figure 6 As shown, the output (DI1 to DI4) from the ADC circuit 211 is written to the speed conversion circuit 212 in synchronization with WCLK. The image data read out from the speed conversion circuit 212 is executed in synchronization with the clock RCLK different from WCLK. When the frequency of writing to the speed conversion circuit 212 and reading from the speed conversion circuit 212 is the same, the reading in the speed conversion circuit 212 exceeds the writing in the speed conversion circuit 212. Therefore, it is necessary to write the speed conversion circuit 212 in advance and install a large-scale speed conversion circuit. The clock generation circuit (data storage clock generation circuit 218) for writing to the speed conversion circuit 212 and the clock generation circuit (data transmission clock generation circuit 214) for reading from the speed conversion circuit 212 are separately provided so that the frequencies of WCLK and RCLK and MCLK can be appropriately independently controlled by the control unit 23, which will be described below. Therefore, the circuit scale of the speed conversion circuit 212 required in the present invention can be minimized.

[0062] like Figure 6As shown, the frequencies of WCLK as well as RCLK and MCLK are independently controlled by the control unit 23, so that the data transmission speed can be appropriately set regardless of the number of image data channels to be processed.

[0063] That is, a clock generating circuit (data storage clock generating circuit 218) for writing to the speed conversion circuit 212 and a clock generating circuit (data transmission clock generating circuit 214) for reading from the speed conversion circuit 212 are separately provided, so that the speed of reading from the speed conversion circuit 212 can be higher than the speed of writing in the speed conversion circuit 212, and thus the number of channels can be reduced. In the case where the write and read clocks are generated in one clock generating circuit, the readout is late, and thus many memory circuits are required.

[0064] In the Figure 6 In the example of converting the four-channel image data into three-channel data shown in FIG. 1 , the three-channel data transmitted per clock MCLK is data of three pixels obtained from one desired channel of the four-channel image data input to the channel number conversion circuit 213. Therefore, in all data transmission periods, the data to be transmitted is selected, and the invalid image data is not transmitted; therefore, the invalid pixel data is not multiplied in the entire clock, and all necessary data can be transmitted with the least clock. Note that, for example, in the case where data is transmitted every two pixels in one clock MCLK, a pixel loss occurs in each clock.

[0065] Note that Figure 6 In the timing diagram of , the signal processing unit 21 controls the RCLK for reading from the speed conversion circuit 212 so that the frequency of the RCLK is equal to the frequency of the MCLK, but only three pulses are generated among four pulses. It is only necessary that the RCLK can be read out at a speed at which the speed difference between writing and reading can be absorbed, and for example, a clock having a frequency equal to the frequency of the WCLK synchronized with the MCLK can be used.

[0066] In the case where the number of channels m of input data from the solid-state imaging element 22 is four and the number of channels n of data transmission is three, MCLK is generated in a clock generation circuit (data transmission clock generation circuit 214) different from the clock generation circuit (data storage clock generation circuit 218) that generates WCLK. The frequency of MCLK is 4 / 3 times (m / n times) the frequency of WCLK. When the frequency of MCLK is 4 / 3 times the frequency of WCLK, the write bit rate and the read bit rate become equal, and the number of stages in the memory (circuit scale) of the speed conversion circuit can be reduced. Therefore, writing in the speed conversion circuit 212, reading in the speed conversion circuit 212, and data transmission can be efficiently performed, and the size of the speed conversion circuit 212 can be minimized.

[0067] In the signal processing unit 21 in which the large-scale speed conversion circuit 212 can be installed, the frequency ratio between MCLK and WCLK can be freely set. For example, the frequency of MCLK can be equal to or greater than 4 / 3 times the frequency of WCLK. By making the data transmission frequency higher in this way, data transmission can be performed in a short time. For example, when the frequency of MCLK is equal to or greater than 4 / 3 times (m / n times) the frequency of WCLK, power consumption can be reduced by turning off the data transmission circuit 217 when data transmission is not performed (except for the effective data transmission period). Even when processing different numbers of channels m, the data transmission frequency can be unified, and the transmission path design or noise countermeasure components can be made universal.

[0068] In addition, the frequency of MCLK can be equal to or less than 4 / 3 times (m / n times) the frequency of WCLK. In this case, the data transmission frequency can be reduced. High transmission frequency causes electromagnetic noise (EMI noise) in the transmission path, deterioration of transmission signal quality, or increase in power consumption; therefore, making the frequency of MCLK equal to or less than 4 / 3 times the frequency of WCLK is effective in suppressing these problems. Even when processing different numbers of channels m, the data transmission frequency can be unified, and the transmission path design or noise countermeasure components can be made universal.

[0069] In the case of transmitting four-channel or three-channel image data in the signal processing unit 21 having a structure capable of processing four-channel image data, the control unit 23 can control so that the transmission frequency becomes equal regardless of the number of channels included in the data to be transmitted. That is, the data transmission frequency is made the same in the four-color data transmission and the three-color data transmission.

[0070] In other words, when digital data with different channel numbers m1 and m2 are converted into data of n channels as digital data of m channels, the speed conversion circuit readout frequency is controlled to be the same. Therefore, since the data transmission frequency can be set to a constant frequency regardless of the number of image channels m to be processed, it is possible to consider only a limited frequency to deal with the reflection or dim shape of the waveform to be considered in the design of the transmission line. Only EMI countermeasure components, etc. are required only for specific frequencies, and the number of steps in the design and the installation cost can be reduced.

[0071] Next, data processing in the image processing unit 20 is described in detail.

[0072] here, Figure 7 is a timing chart illustrating one example of data processing in the image processing unit 20. Figure 7 In the example shown, four channels of image data are processed in the image processing unit 20 .

[0073] like Figure 7As shown, in the image processing unit 20, the serial-to-parallel circuit 202 performs serial-to-parallel conversion on the signal transmitted through the data transmission circuit 201, and then the mapping circuit 203 performs processing opposite to the mapping performed in the signal processing unit 21; therefore, signals of three channels of P1 to P3 having 10 bits are obtained. The image data formed of P1 to P3 is converted into a signal having four channels by the channel number conversion circuit 204. The data is reordered to become the opposite order to that obtained in the channel number conversion in the signal processing unit 21.

[0074] like Figure 7 As shown, the image data of four channels include one unnecessary image data among the four data, and the unnecessary image data is not written to the memory 205. The image data read from the memory 205 does not include the unnecessary image data, and the image data of four channels obtained in the signal processing unit 21 is directly demodulated.

[0075] In the present embodiment, the number of channels m of input data is 4, and the number of channels n of data transmission is 3. Specifically, in another possible structure of each channel, the input channel may be image data of three colors of visible light R / G / B and image data obtained from invisible light such as near infrared light (NIR). In this case, if an invisible light image is required, the number of input channels is four, and if not, the number of input channels is three. According to the structure in the present embodiment, for data transmission from the signal processing unit 21 to the image processing unit 20, a three-channel data transmission channel can be provided, regardless of whether an invisible light image needs to be acquired.

[0076] According to the present embodiment, the solid-state imaging element 22 transmits the image data of m channels to the image processing unit 20 through the data transmission circuit 217 of n channels, so that the data transmission can be performed using the same circuit structure as the circuit structure for transmitting the data of n channels. Therefore, there is no need to provide another transmission path for transmitting the data of m channels, and the additional increase of the mounting area or components can be prevented. Therefore, the number of channels does not increase, and data can be transmitted at a low cost.

[0077] Since the onboard structure required for data transmission is the same regardless of the readout channel, it is possible to realize an imaging device that can transmit image data by performing readout of visible light (three colors of RGB) and image readout by simultaneously illuminating visible light and invisible light (RGB+NIR) in one circuit structure.

[0078] In addition, for example, even if the imaging device reads visible light and invisible light (m-color reading device), when the imaging device does not need invisible image information, the data transmission speed can be changed to that of the n-color reading device only by setting; therefore, consumption can be reduced.

[0079] In the present embodiment, the data transmission circuits 217 and 201 between the signal processing unit 21 and the image processing unit 20 are not limited to a specific circuit; however, a low-amplitude differential signal output unit such as LVDS (low voltage differential signal) or VbyOne (registered trademark) can be used to perform data transmission. By adopting the differential signal output as described above, noise resistance is improved, so when the data transmission frequency is high and long-distance transmission is performed, this is effective.

[0080] Second embodiment

[0081] Next, a second embodiment is described.

[0082] The signal processing unit 21 in the image reading device 101 according to the second embodiment is different from the signal processing unit 21 in the first embodiment in that the number of channels for writing in the speed conversion circuit 212 is limited. In the second embodiment, the description of the same parts as in the first embodiment is omitted, and points different from the first embodiment are described.

[0083] Figure 8 is a diagram showing a circuit configuration example of the signal processing unit 21 and the image processing unit 20 in the image reading apparatus 101 according to the second embodiment.

[0084] like Figure 8 As shown, in a case where the signal processing unit 21 capable of processing m channels (e.g., four channels) of image data only requires n channels (e.g., three channels) of image data, writing in the speed conversion circuit 212 is limited to the image data of n channels, rather than the entire m channels.

[0085] Specifically, the signal processing unit 21 in the image reading device 101 stores in the speed conversion circuit 212 only digital data on n channels which are less than or equal to m channels selected from the digital data of m channels input to the speed conversion circuit 212 .

[0086] By acquiring image data while reducing the number of channels in this way, it is possible to reduce access (write) to the speed conversion circuit 212. Therefore, the number of write accesses to the speed conversion circuit 212 can be reduced, and power consumption can be reduced.

[0087] Third embodiment

[0088] Next, a third embodiment is described.

[0089] The signal processing unit 21 in the image reading device 101 according to the third embodiment is different from the signal processing unit 21 in the first embodiment in that the number of channels for reading from the speed conversion circuit 212 is limited. In the third embodiment, the description of the same parts as in the first embodiment is omitted, and the points different from the first embodiment are described.

[0090] Fig. 9 is a diagram showing a circuit configuration example of the signal processing unit 21 and the image processing unit 20 in the image reading apparatus 101 according to the third embodiment.

[0091] like Fig. 9 As shown, in a case where the signal processing unit 21 capable of processing image data of m channels (e.g., four channels) only needs image data of n channels (e.g., three channels), the reading of the speed conversion circuit 212 is limited only to the image data of n channels, rather than the entire m channels.

[0092] Specifically, the signal processing unit 21 in the image reading device 101 reads out only the digital data on n channels that are less than or equal to the m channels selected from the digital data of m channels stored in the speed conversion circuit 212 .

[0093] By acquiring image data while reducing the number of channels in this way, it is possible to reduce access (readout) to the speed conversion circuit 212. Therefore, the number of read accesses to the speed conversion circuit 212 can be reduced, and power consumption can be reduced.

[0094] Fourth embodiment

[0095] Next, a fourth embodiment is described.

[0096] The signal processing unit 21 in the image reading device 101 according to the fourth embodiment is different from the signal processing unit 21 in the first to third embodiments in that, for each pixel in each channel, data is sequentially selected and output in each channel as data of n channels (for example, three channels) transmitted per MCLK clock. In the description of the fourth embodiment, the description of the same parts as those of the first to third embodiments is omitted, and points different from those of the first to third embodiments are described.

[0097] Fig.10 is a timing chart showing one example of data processing in the signal processing unit 21 according to the fourth embodiment. Fig.10In the example shown, in which the image data of four channels is converted into three channels, for each pixel in each of the m channels, the data is sequentially selected and output as the data of the three channels transmitted for each MCLK clock. More specifically, for example, in one MCLK clock cycle, the data is transmitted in the order of (channel 1, channel 2, channel 3), (channel 4, channel 1, channel 2), (channel 3, channel 4, channel 1) and (channel 2, channel 3, channel 4, channel 4). In all data transmission periods, the data to be transmitted is selected, and invalid image data is not transmitted. Therefore, in the entire clock, invalid pixel data will not be multiplied, so all data can be transmitted with the least clock. Note that in the case of transmitting data of two pixels in one MCLK clock, the loss of one pixel occurs in each clock.

[0098] Fifth embodiment

[0099] Next, a fifth embodiment is described.

[0100] The signal processing unit 21 in the image reading device 101 according to the fifth embodiment is different from the signal processing unit 21 in the first to fourth embodiments in that the number of channels written in the speed conversion circuit 212 is smaller than the number of channels read from the speed conversion circuit 212. In the description of the fifth embodiment, the description of the same parts as those of the first to fourth embodiments is omitted, and points different from those of the first to fourth embodiments are described.

[0101] Fig.11 1 is a timing chart showing an example of data processing in the signal processing unit 21 according to the fifth embodiment. In the first embodiment, the writing in the speed conversion circuit 212 and the reading in the speed conversion circuit 212 are performed by the same number of channels. In this embodiment, Fig.11 As shown, the number of channels for reading from the speed conversion circuit 212 (eg, three channels) is less than the number of channels for writing in the speed conversion circuit 212 (eg, four channels).

[0102] In the structure of this embodiment, the RCLK used for the read speed conversion circuit and the MCLK used for transmitting data are also the same clock.

[0103] In this structure, by controlling the readout of the speed conversion circuit 212, for example, image data of four channels are written at a time, and when reading out, the data storage address of the written data is specified, so that image data of three channels can be read out. Therefore, the readout of the speed conversion circuit and the channel number conversion can be performed at the same time. In this case, the channel number conversion after the readout of the speed conversion circuit is unnecessary.

[0104] Sixth embodiment

[0105] Next, a sixth embodiment is described.

[0106] The image processing unit 20 according to the sixth embodiment is different from the image processing unit 20 in the first to fifth embodiments in that the pixel array 220 and the signal processing unit 21 are provided as one element of the solid-state imaging element 22. In the description of the sixth embodiment, the description of the same parts as those of the first to fifth embodiments is omitted, and points different from those of the first to fifth embodiments are described.

[0107] Fig.12 1 is a diagram illustrating an example of a circuit structure of an image reading device 101 according to a sixth embodiment. Fig.12 As shown, in the image reading device 101 , the imaging device 9 includes a pixel array 220 as one element of a solid-state imaging element 22 and a signal processing unit 21 .

[0108] In this way, the pixel array 220 that converts input light into an electrical signal and the signal processing unit 21 that converts the output signal of the pixel array 220 into digital data are made into one chip as the solid-state imaging element 22. Therefore, wiring on the board connecting the pixel array 220 and the signal processing unit 21 or a circuit for exchanging signals becomes unnecessary. In particular, in the image reading device 101 that acquires image data at high speed, the signals controlling the pixel array 220 and the signal processing unit 21 also need to operate at high speed, and the board needs to have a layout that takes into account crosstalk of control signals on the board, etc. By forming one chip as described in the present embodiment, restrictions on the layout on the board are reduced.

[0109] The embodiments of the present invention have been described, and the specific structures of the components, the contents of processing, and the data formats in these embodiments are not limited to those described in the embodiments.

[0110] The structures of the above-described embodiments can be performed in appropriate combination with each other unless they contradict each other.

[0111] [Reference Symbol List]

[0112] 2 Light Source

[0113] 9 Imaging equipment

[0114] 21 Signal processing equipment

[0115] 22 Solid-state imaging element

[0116] 212 Speed ​​conversion unit, data writing unit

[0117] 213 Channel number conversion unit

[0118] 215, 216, 217 Serial data transmission unit

[0119] 100 Image forming equipment

[0120] 101 Read Device

[0121] 103 Image forming unit

[0122] [Citation List]

[0123] [Patent Document]

[0124] [PTL 1]

[0125] Japanese Patent Publication No. 2017-063299

Claims

1. A signal processing device, comprising: a data writing unit configured to write data of m channels into a memory, each of the m channels corresponding to one of the m colors; a channel number conversion unit configured to output the data read from the memory as data of n channels, wherein m is a variable and is greater than n, and n is a constant; a plurality of serial data transmission units configured to transmit the data of the n channels to a processing device in a subsequent stage; as well as The plurality of serial data transmission units are configured to perform data transmission using signal lines, the number of which is the minimum number required to transmit data of n channels; The signal processing device further comprises a speed conversion unit, wherein the speed conversion unit is configured to make the speed of reading data from the memory greater than the speed of writing data to the memory, wherein The channel number conversion unit is configured to convert the data of the m channels into the data of the n channels, and the data reading speed of the data of the m channels is made higher through the speed conversion unit; The speed conversion unit is configured to make a frequency of reading data from the memory equal to or greater than m / n times a frequency of writing data to the memory.

2. The signal processing device according to claim 1, wherein: The speed conversion unit includes a circuit configured to generate a clock for writing data to the memory, and a circuit configured to generate a clock for reading data from the memory.

3. The signal processing device according to claim 1, wherein: The speed conversion unit is configured to control a frequency of reading data from the memory to be the same even when converting data of different numbers of channels m1 and m2 as data of the m channels into data of the n channels.

4. The signal processing device according to any one of claims 1 to 3, wherein: The data writing unit is configured to write only the data of the n channels among the data of the m channels into the memory when only the data of the n channels are needed.

5. The signal processing device according to any one of claims 1 to 3, wherein: The speed conversion unit is configured to read only the data of the n channels preselected from the data of the m channels written in the memory when only the data of the n channels is needed.

6. The signal processing device according to claim 1, wherein: The channel number conversion unit is configured so that the data of the n channels transmitted per reference clock are n data obtained from a desired channel among the data of the m channels.

7. The signal processing device according to claim 1, wherein: The channel number conversion unit is configured to sequentially select data of the n channels transmitted per reference clock one by one from each of the m channels.

8. An imaging device, comprising a solid-state imaging element, the solid-state imaging element comprising: Pixel array; as well as According to the signal processing device according to any one of claims 1 to 7, data read by the pixel array is input into the signal processing device.

9. A reading device comprising: a light source configured to emit light; as well as The imaging device according to claim 8, the imaging device is configured to receive reflected light of the light emitted from the light source.

10. An image forming device comprising: The reading device according to claim 9; as well as Image forming unit.

11. A signal processing method performed in a signal processing device, the signal processing method comprising: Write the data of m channels into the memory, each of the m channels corresponds to one of the m colors; as well as transmitting the data of the m channels read from the memory to a processing device in a subsequent stage as a plurality of serial signals of n channels, wherein m is a variable and is greater than n, and n is a constant; wherein data transmission is performed using signal lines, the number of which is the minimum number required to transmit data of n channels; The method further comprises: making the speed of reading data from the memory greater than the speed of writing data to the memory, wherein The step of transmitting the data of the m channels read from the memory as multiple serial signals of n channels to a processing device in a subsequent stage includes: converting the data of the m channels into the data of the n channels, making the data reading speed of the data of the m channels greater; and making the frequency of reading data from the memory equal to or greater than m / n times the frequency of writing data to the memory.

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