Pre-charging of NAND strings by injecting holes through the substrate during programming

Abstract

Apparatus and techniques are described for pre-charging NAND string channels in the pre-charge phase of a program operation. In one aspect, a hole-type pre-charge process is used at the source end of a NAND string, where the bottom of the NAND string is connected to a p-well of a substrate. Holes from the p-well are injected into the channel by applying a positive voltage to the p-well, and a lower voltage such as 0V or a negative voltage to the source side select gate transistor and memory cells. In another approach, a hole-type pre-charge process and an electron-type pre-charge process are used sequentially in separate time periods. In another approach, a hole-type pre-charge process is used at the source end of a NAND string, while an electron-type pre-charge process is used at the drain end of the NAND string.

Description

Background Technology

[0001] This technology relates to the operation of memory devices.

[0002] Semiconductor memory devices have become increasingly common in a variety of electronic devices. For example, non-volatile semiconductor memories are used in cellular phones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices.

[0003] Charge storage materials (such as floating gates) or charge trapping materials can be used in such memory devices to store charges representing data states. Charge trapping materials can be arranged vertically in a three-dimensional (3D) stacked memory structure or horizontally in a two-dimensional (2D) memory structure. An example of a 3D memory structure is the Bit Cost Scalable (BiCS) architecture, which comprises a stack of alternating conductive and dielectric layers.

[0004] Memory devices include memory cells that can be arranged in series to form NAND strings (e.g., NAND chains), where select-gate transistors are positioned at the ends of the NAND string to selectively connect the channels of the NAND string to source lines or bit lines. However, various challenges exist in operating such memory devices. Attached Figure Description

[0005] Figure 1A This is a block diagram of an exemplary memory device.

[0006] Figure 1B It shows Figure 1A Example of temperature sensing circuit 116.

[0007] Figure 2 It is shown Figure 1A A block diagram of one embodiment of the sensing block 51.

[0008] Figure 3 It shows Figure 1A An exemplary specific implementation of a power control circuit 115 for supplying voltage to a block of memory cells in a plane.

[0009] Figure 4 This is a perspective view of a memory device 500, which includes... Figure 1A A set of blocks in an exemplary 3D configuration of memory structure 126.

[0010] Figure 5 It shows Figure 1A An exemplary transistor 520 in the memory structure 126.

[0011] Figure 6 It shows Figure 4An exemplary cross-sectional view of block BLK0, including a portion of NAND strings 700n and 710n.

[0012] Figure 7A It shows the relationship with Figure 4 and Figure 6 An exemplary view of the NAND string in a consistent block BLKO.

[0013] Figure 7B It shows the connection to Figure 7A An exemplary view of the memory cell WL3 in subblock SB0, which has a corresponding NAND string, bit line and sensing circuitry.

[0014] Figure 8A The bandgap diagram of the source end of the NAND string is shown when electrons are extracted from the channel during the source line pre-charge process.

[0015] Figure 8B It shows when in Figure 8A The bandgap diagram of the source terminals of a NAND string when electrons are no longer extracted from the channel during the source line pre-charge process.

[0016] Figure 8C The bandgap plot of the source end of the NAND string is shown when electrons are extracted from the channel during the p-well pre-charge process.

[0017] Figure 8D The bandgap diagram of the source end of the NAND string is shown when holes are injected into the channel during p-well pre-charge.

[0018] Figure 9 The channel voltage and Figures 8A-8D A consistent graph showing the time required for pre-charging using holes and electrons.

[0019] Figure 10 A table showing different pre-charge processes is provided.

[0020] Figure 11 It shows the relationship with Figure 10 The flowchart illustrates an exemplary programming operation consistent with the pre-charge mode.

[0021] Figure 12 An exemplary Vth distribution of a set of memory cells with three bits and eight data states per cell is shown.

[0022] Figure 13A It shows the relationship with Figure 11 An example voltage signal used in consistent programming operations.

[0023] Figure 13B It shows in Figure 13A Examples of verification voltages used in different programming loops.

[0024] Figure 14 It shows the method for performing with Figure 11 and Figure 13A An example voltage signal for consistent programming operations.

[0025] Figure 15 It shows that with Figure 14 The graph shows the Vth curve, which is a measure of programming interference, for the erase state memory cell that varies during the electronic precharge time period t0-tl and the hole precharge time period tl-t2.

[0026] Figure 16 It shows the connection to Figure 7A A diagram of a subset of word lines of memory cells in a NAND string 700n. Detailed Implementation

[0027] This invention describes an apparatus and technique for pre-charging a NAND string channel during a pre-charge phase of a programming operation. The technique includes injecting holes into the source terminals of the NAND string.

[0028] In some memory devices, memory cells are joined together, such as in NAND strings within a block or sub-block. Each NAND string includes: a plurality of memory cells connected in series between one or more drain-side select-gate transistors (called SGD transistors) at the drain end of the NAND string's connection bit line; and one or more source-side select-gate transistors (called SGS transistors) at the source end of the NAND string or other memory strings or connected groups of memory cells at the source end of the connection source line. The select-gate transistor is also called the select gate. Furthermore, the memory cells may be arranged with a common control gate line (e.g., a word line) serving as the control gate. A set of word lines extends from the source side of the block to the drain side of the block. Memory cells can be connected in other types of strings and in other ways.

[0029] In a 3D memory structure, memory cells can be arranged in stacked vertical NAND strings on a substrate, where the stack includes alternating conductive and dielectric layers. The conductive layers serve as word lines connecting to the memory cells. Each NAND string may have a pillar shape that intersects the word lines to form the memory cells. In a 2D memory structure, memory cells can be arranged in horizontal NAND strings on a substrate.

[0030] In 3D memory structures, each NAND string includes channels that extend vertically within the stack. See, for example... Figure 6 The NAND string 700n has a channel 660. The source end 700s of the NAND string is connected to the substrate 611, and the drain end 700d of the NAND string is connected to the bit line BL0.

[0031] In programming operations for memory cells in a selected NAND string, the goal is to precharge the channel of the unselected NAND string before applying a programming pulse to the selected word line. By boosting the channel voltage, the possibility of programming interference is reduced during the application of the programming pulse. One method of precharging the channel is electronic precharging, in which electrons are extracted from the channel to increase the channel voltage. This involves applying a positive voltage to the drain and / or source terminals of the NAND string simultaneously with applying a positive voltage to the memory cell and the select gate transistor via the corresponding word line and control line. By applying a positive voltage to the memory cell and the select gate transistor, the associated channel region becomes conductive, facilitating the movement of electrons toward the ends of the NAND string.

[0032] However, electronic pre-charge requires a long recovery time, which degrades performance. Furthermore, in some cases, such as during multi-pass programming, the channel boost may be insufficient. For example, in the second pass of a two-pass programming operation, the memory cell will have a raised threshold voltage, making it difficult to conduct the associated channel region to facilitate electron movement towards the ends of the NAND string.

[0033] The technology presented herein addresses the aforementioned and other issues. In one aspect, a hole-type precharge process is used to inject holes into the source terminals of a NAND string, wherein the bottom of the NAND string is connected to a p-well of the substrate. This p-well is the region beneath the memory cell block. Holes from the p-well are injected into the channel by applying a positive voltage to the p-well and applying a lower voltage, such as 0V or a negative voltage, to the SGS transistor and memory cell. The lower voltage can be applied at least to a subset 1620 of the source terminals of the NAND string adjacent to the word line. Figure 16 ).

[0034] In another approach, hole-type precharge and electron-type precharge processes are used sequentially at the source end of the NAND string within separate time periods. This method offers advantages compared to using either the hole-type or electron-type precharge process separately at the source end of the NAND string. Furthermore, the duration of the two processes can be optimized based on factors such as the location of selected word lines within the block.

[0035] In another approach, a hole-type precharge process is used at the source end of the NAND string, while an electronic precharge process is used at the drain end. This hybrid approach facilitates simultaneous charging of the NAND string from both ends.

[0036] Generally speaking, the precharge process can also be optimized based on the risk of programming interference, which is a function of, for example, the position of the selected word line in the block or the position of the sub-block.

[0037] These and other features will be discussed further below.

[0038] Figure 1A This is a block diagram of an exemplary storage device. Memory device 100, such as a non-volatile memory system, may include one or more memory dies 108. Memory die 108 or a chip includes a memory structure 126 of memory cells, such as an array of memory cells, control circuitry 110, and read / write circuitry 128. Memory structure 126 is addressable via word lines through row decoder 124 and via bit lines through column decoder 132. Read / write circuitry 128 includes a plurality of sensing blocks 51, 52, ..., 53 (sensing circuitry) and allows for parallel reading or programming of pages of memory cells. Typically, a controller 122 is included in the same memory device 100 (e.g., a removable memory card) as one or more memory dies 108. The controller may be separate from the memory dies. Commands and data are transmitted between host 140 and controller 122 via data bus 120 and between controller and one or more memory dies 108 via line 118.

[0039] The memory structure can be a 2D memory structure or a 3D memory structure. The memory structure may include one or more memory cell arrays, including 3D arrays. The memory structure may include a monolithic 3D memory structure in which multiple memory stages are formed on (but not in) a single substrate (such as a wafer), without intermediate substrates. The memory structure may include any type of non-volatile memory, which is monolithically formed in one or more physical stages of memory cell arrays having active regions disposed on a silicon substrate. The memory structure may be in a non-volatile memory device having circuitry associated with the operation of the memory cells, whether the associated circuitry is on or within the substrate.

[0040] Control circuitry 110 cooperates with read / write circuitry 128 to perform memory operations on memory structure 126, and includes a state machine, on-chip address decoder 114, power control module 115 (power control circuitry), temperature sensing circuitry 116, and precharge configuration circuitry 117. Storage area 113 may be provided, for example, for operating parameters and software / code. In one embodiment, the state machine is software-programmed. In other embodiments, the state machine does not use software and is implemented entirely in hardware (e.g., electrical circuitry).

[0041] On-chip address decoder 114 provides an address interface between the hardware addresses used by the host or memory controller and the hardware addresses used by decoders 124 and 132. Power control module 115 controls the power and voltage supplied to word lines, select gate lines, bit lines, and source lines during memory operation. This power control module may include drivers for word lines, SGS and SGD transistors, and source lines. See also... Figure 3 In one approach, the sensing block may include a bit line driver. Temperature sensing circuitry 116 can detect the temperature of the memory device over its lifetime, for example, every minute. An exemplary embodiment of the temperature sensing circuitry is shown in Figure 1B. Precharge configuration circuitry 117 can provide settings for precharge operation, as discussed further below.

[0042] Circuits 116 and 117 may include hardware, software, and / or firmware for performing the processes described herein.

[0043] In some specific implementations, some components of the components may be combined. In various designs, one or more components (alone or in combination) other than memory structure 126 may be considered as at least one control circuit configured to perform the techniques described herein, including the steps of the processes described herein. For example, the control circuit may include any one or a combination of the following: control circuit 110, state machine 112, decoders 114 and 132, power control module 115, temperature sensing circuit 116, precharge configuration circuit 117, sensing blocks 51, 52…53, read / write circuit 128, controller 122, etc.

[0044] An off-chip controller 122 (in one embodiment, circuitry) may include a processor 122e, memories such as ROM 122a and RAM 122b, and an error correction code (ECC) engine 245. The ECC engine can correct numerous read errors. RAM 122b may be DRAM, which includes a storage location 122c for uncommitted data. During programming, a copy of the data to be programmed is stored in storage location 122c until programming is successfully completed. In response to successful completion, the data is erased from this storage location and committed or released to a block of memory cells. Storage location 122c may store one or more word lines of data.

[0045] A memory interface 122d may also be provided. The memory interface, which communicates with the ROM, RAM, and processor, is a circuit that provides an electrical interface between the controller and the memory die. For example, the memory interface can change the format or timing of signals, provide buffers, isolate surges, latch I / O, etc. The processor can issue commands to the control circuitry 110 (or any other component of the memory die) via the memory interface 122d.

[0046] The memories in controller 122, such as ROM 122a and RAM 122b, include code such as a set of instructions, and the processor is operable to execute that set of instructions to provide the functionality described herein. Alternatively or otherwise, the processor may access the code from a subset 126a of the memory structure, such as reserved areas of memory cells in one or more word lines.

[0047] For example, the controller can use code to access memory structures, such as for programming, reading, and erasing operations. The code may include boot code and control code (e.g., a set of instructions). Boot code is the software that initializes the controller during boot or startup and enables it to access memory structures. The controller can use the code to control one or more memory structures. Upon power-up, processor 122e fetches boot code from ROM 122a or subset 126a for execution, and the boot code initializes system components and loads control code into RAM 122b. Once the control code is loaded into RAM, it is executed by the processor. The control code includes drivers that perform basic tasks such as controlling and allocating memory, prioritizing instruction processing, and controlling input and output ports.

[0048] The controller, such as RAM 122b and / or control circuitry 110, may store parameters indicating the expected number of failed bits in the block. These parameters may include, for example, the number of bits per cell stored in the memory cell, a portion of the word line programmed in the block or sub-block, a portion of the sub-block programmed in the block, the strength of the ECC processing used to store and read data in the block, the duration of the pre-read voltage pulse (if used), and read accuracy, such as bit line or word line voltage settling time and the number of sense passes.

[0049] Generally, control code may include instructions to perform the functions described herein, including the steps of the flowcharts discussed further below, and provide voltage waveforms, including those discussed further below. Control circuitry may be configured to execute instructions for performing the functions described herein.

[0050] In one embodiment, the host is a computing device (e.g., a laptop computer, desktop computer, smartphone, tablet computer, digital camera) that includes one or more processors and one or more processor-readable storage devices (RAM, ROM, flash memory, hard disk drive, solid-state memory) storing processor-readable code (e.g., software) for programming the one or more processors to perform the methods described herein. The host may also include additional system memory, one or more input / output interfaces, and / or one or more input / output devices that communicate with the one or more processors.

[0051] In addition to NAND flash memory, other types of non-volatile memory can also be used.

[0052] Semiconductor memory devices include volatile memory devices such as dynamic random access memory (DRAM) or static random access memory (SRAM), non-volatile memory devices such as resistive random access memory (ReRAM), electrically erasable programmable read-only memory (EEPROM), flash memory (which can also be considered a subgroup of EEPROM), ferroelectric random access memory (FRAM), and magnetoresistive random access memory (MRAM), as well as other semiconductor elements capable of storing information. Each type of memory device can have different configurations. For example, flash memory devices can be configured with NAND or NOR.

[0053] The memory device can be formed from passive and / or active components in any combination. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include resistivity-switching storage elements, such as antifuse or phase-change materials, and optional steering elements, such as diodes or transistors. Furthermore, by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements comprising charge storage regions, such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0054] Multiple memory elements can be configured such that they are connected in series or that each element can be accessed individually. By way of non-limiting example, a flash memory device (NAND memory) in a NAND configuration typically contains memory elements connected in series. A NAND string is an example of a group of transistors connected in series, comprising memory cells and SG transistors.

[0055] NAND memory arrays can be configured such that the array consists of multiple strings of memory, where a string consists of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, memory elements can be configured such that each element can be accessed individually, such as in a NOR memory array. NAND memory configurations and NOR memory configurations are examples, and memory elements can be configured in other ways.

[0056] Semiconductor memory elements located within and / or on a substrate can be arranged in two or three dimensions, such as 2D memory structures or 3D memory structures.

[0057] In a 2D memory structure, semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a 2D memory structure, the memory elements are arranged in a plane (e.g., in an xy-direction plane) that extends substantially parallel to the main surface of the substrate supporting the memory elements. The substrate may be a wafer on which layers of the memory elements are formed, or it may be a carrier substrate attached to the memory elements after they have been formed. As a non-limiting example, the substrate may include a semiconductor, such as silicon.

[0058] Memory elements can be arranged in a single memory device level in an ordered array (such as in multiple rows and / or columns). However, memory elements can be arranged in unconventional or non-orthogonal configurations. Each memory element may have two or more electrodes or contact lines, such as bit lines and word lines.

[0059] Arrange a 3D memory array such that the memory elements occupy multiple planes or multiple memory device levels to form a three-dimensional structure (i.e., in the x, y and z directions, where the z direction is substantially perpendicular to the main surface of the substrate and the x and y directions are substantially parallel to the main surface of the substrate).

[0060] As a non-limiting example, a 3D memory structure can be vertically arranged as a stack of multiple 2D memory device levels. As another non-limiting example, a 3D memory array can be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main surface of the substrate, i.e., in the y-direction), with each column having multiple memory elements. These columns can be arranged in a 2D configuration, for example, in the xy-plane, resulting in a 3D arrangement of the memory elements, where the elements are located on multiple vertically stacked memory planes. Other configurations of the three-dimensional memory elements can also constitute a 3D memory array.

[0061] By way of non-limiting example, in a 3D NAND memory array, memory elements may be coupled together to form NAND strings within a single horizontal (e.g., xy) memory device level. Alternatively, memory elements may be coupled together to form vertical NAND strings spanning multiple horizontal memory device levels. Other 3D configurations are conceivable, where some NAND strings contain memory elements within a single memory level, while others contain memory elements spanning multiple memory levels. The 3D memory array can also be designed in both NOR and ReRAM configurations.

[0062] Typically, in a monolithic 3D memory array, one or more memory device levels are formed above a single substrate. Optionally, the monolithic 3D memory array may also have one or more memory layers located at least partially within a single substrate. As a non-limiting example, the substrate may include a semiconductor, such as silicon. In a monolithic 3D array, the layer constituting each memory device level of the array is typically formed on the layer of the lower memory device level of the array. However, the layers of adjacent memory device levels in a monolithic 3D memory array may be shared between memory device levels or there may be intermediate layers between memory device levels.

[0063] 2D arrays can be formed individually and then packaged together to form a non-monolithic memory device with multi-layered memory. For example, a non-monolithic stacked memory can be constructed by forming memory stages on separate substrates and then stacking the memory stages on top of each other. The substrates can be thinned or removed from the memory device stages before stacking, but since the memory device stages are initially formed on separate substrates, the resulting memory array is not a monolithic 3D memory array. Furthermore, multiple 2D or 3D memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packaged together to form a stacked chip memory device.

[0064] Typically, associated circuitry is required to operate and communicate with the memory element. As a non-limiting example, a memory device may have circuitry for controlling and driving the memory element to perform functions such as programming and reading. This associated circuitry may be located on the same substrate as the memory element and / or on a separate substrate. For example, a controller for memory read-write operations may be located on a separate controller chip and / or on the same substrate as the memory element.

[0065] Those skilled in the art will recognize that this technology is not limited to the described 2D and 3D exemplary structures, but encompasses all relevant memory structures as described herein and as understood by those skilled in the art in terms of their nature and scope.

[0066] Figure 1B It shows Figure 1A An example of a temperature sensing circuit 116. The circuit includes pMOSFETs 131a, 131b, and 134, bipolar transistors 133a and 133b, and resistors R1, R2, and R3. I1, I2, and I3 represent currents. Voutput is the temperature-based output voltage supplied to the analog-to-digital converter (ADC) 129. Vbg is a temperature-independent voltage. A voltage level generation circuit 135 uses Vbg to set multiple voltage levels. For example, a reference voltage can be divided into several levels using a resistor divider circuit.

[0067] The ADC compares Voutput with the voltage level and selects the closest match, outputting the corresponding digital value (VTemp) to the processor 122e. This is data indicating the temperature of the memory device. In one approach, ROM fuse 123 stores data that correlates the matched voltage level with temperature. The processor then uses the temperature to set temperature-based parameters in the memory device, such as by utilizing comparator circuitry.

[0068] Vbg is obtained by applying a base-emitter voltage (Vbe) and the voltage drop across resistor R2 across transistor 131b. Bipolar transistor 133a has a larger area (factor N) than transistor 133b. PMOS transistors 131a and 131b are of equal size and arranged in a current mirror configuration, such that currents I1 and I2 are approximately equal. Therefore, Vbg = Vbe + R2 × I2 and I1 = Ve / R1, therefore I2 = Ve / R1. Thus, Vbg = Vbe + R2 × kT ln(N) / R1 × q, where T is temperature, k is the Boltzmann constant, and q is the unit of charge.

[0069] The source of transistor 134 is connected to the supply voltage Vdd, and the node between the drain of the transistor and resistor R3 is the output voltage Voutput. The gate of transistor 134 is connected to the same terminal as the gates of transistors 131a and 131b, and the current through transistor 134 mirrors the current through transistors 131a and 131b.

[0070] Figure 2 It is shown Figure 1A A block diagram of one embodiment of the sensing block 51.

[0071] Individual sensing blocks 51 are divided into one or more core portions referred to as sensing circuits 60-63 or sensing amplifiers, and a common portion referred to as management circuitry 190. In one embodiment, each sensing circuit is connected to a corresponding bit line and NAND string, and the common management circuitry 190 is connected to a group of multiple (e.g., four or eight) sensing circuits. Each sensing circuit in the group communicates with its associated management circuitry via a data bus 176. Thus, there are one or more management circuits communicating with the sensing circuitry of a group of memory elements (memory cells).

[0072] As an example, sensing circuit 60 operates during a programming cycle to provide a pre-charge / programming-suppression voltage to unselected positioning lines or a programming-enable voltage to selected positioning lines. See also Figure 14In the Vbl, the unselected bit line connects to the unselected NAND string and the unselected memory cell within it. The unselected memory cell can be a memory cell within the unselected NAND string, where the memory cell is connected to either the selected or unselected word line. Alternatively, the unselected memory cell can be a memory cell within the selected NAND string, where the memory cell is connected to the unselected word line. The selected bit line connects to the selected NAND string and the selected memory cell within it.

[0073] The sensing circuit 60 also operates during the verification test in the programming cycle to sense the memory cell, thereby determining whether it has been programmed by reaching the assigned data state (e.g., as indicated by Vth, the verification voltage of the assigned data state). The sensing circuit 60 also operates during read operations to determine the data state to which the memory cell has been programmed. The sensing circuit performs this sensing by determining whether the conduction current in the connected bit lines is above or below a predetermined threshold level. This indicates whether Vth of the memory cell is below or above the word line voltage, respectively.

[0074] The sensing circuit may include a selector 56 or a switch connected to transistor 55 (e.g., nMOS). Based on the voltage at the control gate 58 and drain 57 of transistor 55, the transistor may operate as a transmission gate or a bit line clamp. When the voltage at the control gate is sufficiently higher than the voltage at the drain, the transistor operates as a transmission gate to pass the voltage at the drain to the bit line (BL) at the source 59 of the transistor. For example, a programming-suppression voltage such as 1V to 2V may be passed when pre-charging and suppressing an unselected NAND string. Alternatively, a programming-enable voltage such as 0V may be passed to allow programming in a selected NAND string. Selector 56 may pass a supply voltage Vdd (e.g., 3V to 4V) to the control gate of transistor 55 to make it operate as a transmission gate.

[0075] When the voltage at the control gate is lower than the voltage at the drain, transistor 55 operates as a source follower to set or clamp the bit line voltage at Vcg-Vth, where Vcg is the voltage at the control gate 58 and Vth (e.g., 1V) is the threshold voltage of transistor 55. This assumes the source line is at 0V. This mode can be used during sensing operations such as read and verification operations. Therefore, the bit line voltage is set by transistor 55 based on the voltage output by selector 56. For example, selector 56 can pass Vbl_sense + Vth (e.g., 1.5V) to transistor 55 to provide Vbl_sense (e.g., 0.5V) on the bit line. Vbl selector 173 can pass a relatively high voltage, such as Vdd, to the drain 57, which is higher than the control gate voltage on transistor 55, to provide source follower mode during sensing operations.

[0076] Vbl selector 173 can transmit one of a plurality of voltage signals. For example, the Vbl selector can transmit a program-suppress voltage signal that increases from an initial voltage (e.g., 0V) to a program-suppress voltage (e.g., the voltage Vbl_inh for the corresponding bit line of an unselected NAND string during a programming cycle). Vbl selector 173 can also transmit a programming-enable voltage signal, such as 0V, for the corresponding bit line of a selected NAND string during a programming cycle. For example, the Vbl selector can select from a program-enable voltage signal based on a command from processor 192. Figure 3 The voltage signal of the BL voltage driver 340 in the middle.

[0077] In one approach, the selector 56 of each sensing circuit can be controlled separately from the selectors of other sensing circuits. The Vbl selector 173 of each sensing circuit can also be controlled separately from the Vbl selectors of other sensing circuits.

[0078] During sensing, sensing node 171 is charged until an initial voltage Vsense_init, such as 3V, is reached. The sensing node is then passed to bit lines via transistor 55, and the amount of decay of the sensing node is used to determine whether the memory cell is in a conductive or non-conductive state. Specifically, comparator circuit 175 determines the amount of decay by comparing the sensing node voltage with a trip voltage during sensing. If the sensing node voltage decays below the trip voltage Vtrip, the memory cell is in a conductive state and its Vth is equal to or lower than the verification voltage. If the sensing node voltage does not decay below Vtrip, the memory cell is in a non-conductive state and its Vth is higher than the verification voltage. For example, the comparator circuit 175 sets the sensing node latch 172 to 0 or 1 based on whether the memory cell is in a conductive or non-conductive state. The data in the sensing node latch can be read by processor 192 and used to update bits of trip latch 174. Subsequently, for the next programming cycle, the processor can use the bits in the trip latch and the allocated data state in latches 194-197 to determine whether the memory cell and NAND string are selected for or not for programming in the programming cycle, thereby passing the appropriate enable or suppress bit line voltage to the bit line respectively. Latches 194-197 can be considered as data latches or user data latches because they store the data to be programmed into the memory cell.

[0079] The management circuitry 190 includes a processor 192, four sets of exemplary data latches 194-197 for the sensing circuits 60-63, and an I / O interface 196 coupled between the data latch sets and the data bus 120. Each sensing circuit may be provided with a set of three data latches, for example, including individual latches LDL, MDL, and UDL. In some cases, different numbers of data latches may be used. In a three-bit implementation per unit, the LDL stores bits for the next page of data, the MDL stores bits for intermediate page data, and the UDL stores bits for the previous page of data.

[0080] Processor 192 performs calculations to determine the data stored in the sensed memory cells and stores the determined data in the set of data latches. Each set of data latches 194-197 stores data bits determined by processor 192 during a read operation and data bits imported from data bus 120 during a programming operation; these data bits represent write data to be programmed into memory. I / O interface 196 provides an interface between data latches 194-197 and data bus 120.

[0081] During a read operation, the system operates under the control of state machine 112, which controls the supply of different control gate voltages to the addressed memory cell. As it progresses through various predefined control gate voltages corresponding to different memory states supported by the memory, a sensing circuit can trip at one of these voltages, and the corresponding output is provided from the sensing circuit to the processor 192 via data bus 176. The processor 192 then determines the resulting memory state by considering the tripping event of the sensing circuit and information about the control gate voltages applied via input line 193 from the state machine. It then calculates the binary code of the memory state and stores the resulting data bits in data latches 194-197.

[0082] Some implementations may include multiple processors 192. In one implementation, each processor 192 will include output lines (not shown) such that each output line is wire-ORed together. In some implementations, the output lines are inverted before being connected to the wires or lines. This configuration allows for rapid determination of when the programming process is complete during programming verification testing, as the state machine receiving the wires or lines can determine when all programmed bits have reached the desired level. For example, when each bit reaches its desired level, a logic zero for that bit is sent to the wire or line (or data one is inverted). When all bits output data 0 (or data one is inverted), the state machine knows to terminate the programming process. Because each processor communicates with eight sensing circuits, the state machine needs to read the wires or lines eight times, or logic can be added to the processor 192 to accumulate the results of the relevant bit lines, so that the state machine only needs to read the wires or lines once. Similarly, by correctly selecting the logic levels, the global state machine can detect when the first bit changes its state and adjust the algorithm accordingly.

[0083] During the programming or verification operation of a memory cell, the data to be programmed (written data) is stored in data latch groups 194-197 from the data bus 120. During reprogramming, the corresponding set of data latches for the memory cell can store data indicating when the memory cell can be reprogrammed based on the programming pulse magnitude value.

[0084] Under the control of the state machine, the programming operation applies a series of programming voltage pulses to the control gate of the addressed memory cell. The amplitude of each voltage pulse can be incrementally increased by one step from the previous programming pulse during the process, a process known as incremental step pulse programming. Each programming voltage is followed by a verification operation to determine whether the memory cell has been programmed to the desired memory state. In some cases, the processor 192 monitors the read-back memory state relative to the desired memory state. When both are consistent, the processor 192 sets the bit line to a programming-inhibited mode, such as by updating its latch. This prevents further programming of the memory cell coupled to the bit line, even if additional programming pulses are applied to its control gate.

[0085] Each set of data latches 194-197 can be implemented as a stack of data latches for each sensing circuit. In one embodiment, each sensing circuit 60 has three data latches. In some specific implementations, the data latches are implemented as shift registers so that parallel data stored therein is converted into serial data for the data bus 120 and vice versa. All data latches corresponding to read / write blocks of memory cells can be connected together to form a block shift register, thereby enabling the serial transfer of input or output data blocks. Specifically, the read / write circuit module group is adjusted such that its data latch group shifts data sequentially into or out of the data bus as if they were part of a shift register for the entire read / write block.

[0086] Data latches indicate when an associated memory cell has reached certain milestones in a programming operation. For example, a latch might identify when the Vth of a memory cell is below a specific verification voltage. Data latches also indicate whether a memory cell is currently storing one or more bits from a page of data. For example, an LDL latch can be used to store the next page of data. An LDL latch is toggled (e.g., from 0 to 1) when the next page bit is stored in the associated memory cell. An MDL or UDL latch is toggled for each three-bit cell when the middle or previous page bit is stored in the associated memory cell, respectively. This occurs when the associated memory cell has completed programming.

[0087] Figure 3 It shows Figure 1A An exemplary specific implementation of power control circuitry 115 for supplying voltage to memory cell blocks in a plane is provided. In one approach, the circuitry shown may be repeated for each plane of the die. In this example, memory structure 126 includes a set of four associated blocks BLK0 to BLK3, and another set of four associated blocks BLK4 to BLK7. The blocks may be in one or more planes. Figure 1A The line decoder 124 provides voltage to the word lines and the select gate control lines for each block via a transfer transistor 322. The line decoder provides a control signal to the transfer transistor, which connects the block to the line decoder. In one method, the transfer transistors for each group of blocks are controlled by a common control gate voltage. Therefore, all transfer transistors in a group of blocks are either on or off at a given time. If a transfer transistor is on, voltage from the line decoder is provided to the corresponding control gate line or word line. If a transfer transistor is off, the line decoder is disconnected from the corresponding control gate line or word line, causing the voltage to float on the corresponding control gate line or word line.

[0088] For example, control gate line 312 is connected to transmission transistor groups 313-316, which in turn are connected to the control gate lines of BLK4-BLK7, respectively. Control gate line 317 is connected to transmission transistor groups 318-321, which in turn are connected to the control gate lines of BLK0-BLK3, respectively.

[0089] Typically, programming or reading operations are performed on a selected block at a time within a block. Erasing operations can be performed on a selected block or a sub-block. The line decoder connects global control line 302 to local control line 303. Control lines represent conductive paths. Voltage is supplied on the global control lines of many voltage drivers. Some voltage drivers can supply voltage to switch 350 connected to the global control line. Control transfer transistor 324 is used to transfer voltage from the voltage driver to switch 350.

[0090] The voltage driver may include a selected data word line (WL) driver 347 that provides voltage on the selected data word line during programming or read operations. Driver 347 may provide a pre-charge voltage and a programming voltage on WLn during a programming cycle of a programming operation. Driver 348 may be used for unselected data word lines, and dummy word line drivers 349 and 349a may be used respectively for... Figure 6 Voltages are provided on the dummy word lines WLDD and WLDS. For example, driver 348 can be used to apply a precharge voltage and a pass voltage on unselected word lines during a programming cycle of a programming operation. See also Figure 14 VWL_unsel in.

[0091] The voltage driver may also include a separate SGD driver for each sub-block. For example, such as in Figure 7A In this block, SGD drivers 346, 346a, 346b, and 346c may be provided for SB0, SB1, SB2, and SB3, respectively. The SGD drivers provide voltage to control lines connected to the control gate of the SGD transistor (drain-side selected gate transistor). In one option, the SGS driver 345 is common to different sub-blocks within the block and provides voltage to control lines connected to the control gate of the SGS transistor (source-side selected gate transistor).

[0092] Various components, including the line decoder, can receive commands from a controller, such as state machine 112 or controller 122, to perform the functions described herein.

[0093] The p-well voltage driver 330 provides a voltage Vp-well to the p+ contact 612b in the p-well region 611b, for example, via conductive path 682. See also Figure 6In one approach, the p-well region 611b is common to the block. The block also shares a set of bit lines 342. A source line (SL) voltage driver 331 provides a voltage Vsl to the n+ contact 612c in the p-well region 611b, for example, via a local interconnect 651.

[0094] Bit line voltage driver 340 includes voltage sources that supply voltage to bit line 342, such as a programming-inhibition voltage signal Vbl_inh, a programming-enabling voltage signal Vbl_en, and a precharge voltage signal Vbl_pc. Figure 14 The system includes a programming-suppression voltage signal (Vbl_sense) and a sensing voltage. The programming-enable voltage signal has a value of 1V to 2V, for example, to suppress programming in the NAND string. The programming-enable voltage signal has a value of 0V, for example, to allow programming of selected memory cells in the NAND string. The precharge voltage signal has a value of 1V to 2V, for example, to precharge the channels of the NAND string. The sensing voltage can have a value of 0.5V, for example, to facilitate sensing of selected memory cells in the NAND string during read operations or verification tests.

[0095] In such Figures 4 to 7B In the stacked memory device shown, multiple sets of interconnected memory cells can be arranged in NAND strings that extend vertically upward from a substrate. In one approach, the bottom (or source end) of each NAND string contacts the substrate, for example, a well region, and the top (or drain end) of each NAND string is connected to a corresponding bit line.

[0096] Figure 4 This is a perspective view of a memory device 500, which includes... Figure 1AA set of blocks in an exemplary 3D configuration of a memory structure 126. On the substrate are exemplary blocks BLK0-BLK3 of memory cells (memory elements), and peripheral regions having circuitry used by the blocks. Peripheral regions 504 extend along the edges of each block, while peripheral regions 505 are located at the ends of the block set. The circuitry may include voltage drivers that can be connected to the block's control gate layer, bit lines, and source lines. In one approach, control gate layers at a common height in the blocks are commonly driven. The substrate 501 may also carry circuitry beneath the blocks, and one or more lower metal layers patterned in conductive paths to carry signals from the circuitry. These blocks are formed in a middle region 502 of the memory device. In an upper region 503 of the memory device, one or more upper metal layers are patterned in conductive paths to carry signals from the circuitry. Each block includes a stacked region of memory cells, where alternating stacked layers represent word lines. In one possible approach, each block has opposing layered sides from which vertical contacts extend upward to the upper metal layers to form connections with conductive paths. Although four blocks are depicted as an example, two or more blocks extending in the x and / or y directions can be used.

[0097] In one possible approach, these blocks are arranged in a plane, with the length of the plane in the x-direction representing the direction in which the signal path to the word line extends through one or more upper metal layers (word line or SGD line direction), and the width of the plane in the y-direction representing the direction in which the signal path to the bit line extends through one or more upper metal layers (bit line direction). The z-direction represents the height of the memory device. These blocks can also be arranged in multiple planes.

[0098] Figure 5 It shows Figure 1A An exemplary transistor 520 in the memory structure 126. The transistor includes a control gate CG, a drain D, a source S, and a channel CH, and may, for example, represent a memory cell or a select gate transistor. The drain terminal of the transistor is optionally connected to the bit line BL via one or more other transistors in the NAND string, and the source terminal of the transistor is optionally connected to the source line SL via one or more other transistors in the NAND string.

[0099] Figure 6 It shows Figure 4 An exemplary cross-sectional view of a block BLKO including a portion of NAND strings 700n and 710n. In this example, NAND strings 700n and 710n are in different sub-blocks SB0 and SB1, respectively. The block includes a stack 610 of alternating conductive layers (word line layers) and dielectric layers. These layers may be rectangular plates having a height in the z-direction, a width in the y-direction, and a length in the x-direction.

[0100] The stack is described as comprising one, but optionally one or more, alternating conductive and dielectric layers. The stack includes a set of alternating conductive and dielectric layers, wherein memory vias are formed during the manufacturing process.

[0101] The conductive layers include SGS, WLDS, WL0-WL95, WLDD, and SGD(0). The conductive layer connected to the control gate of the memory cell is called a word line, and the conductive layers connected to the control gates of the source-side select-gate transistor and the drain-side select-gate transistor are called source-side control lines and drain-side control lines, respectively. WLDS and WLDD are dummy word lines or conductive layers connected to dummy memory cells that are not qualified to store user data. A dummy memory cell may have the same structure as a data memory cell, but the controller considers that the memory cell unqualified to store any type of data, including user data. One or more dummy memory cells may be provided at the drain and / or source ends of the NAND string of the memory cell to provide a gradual transition of the channel voltage gradient. WL0-WL95 are data word lines connected to the data memory cell that are qualified to store user data. By way of example only, the stack includes ninety-six data word lines. DL is an exemplary dielectric layer.

[0102] The top 610t and bottom 610b of the stack are shown. WL95 is the topmost data word line or conductive layer, and WL0 is the bottommost data word line or conductive layer.

[0103] NAND strings are formed by etching memory vias in a stack and then depositing multiple thin layers of material along the sidewalls of the memory vias. Memory cells are formed in regions where word lines intersect with the multiple thin layers, and select-gate transistors are formed in regions where SGS and SGD control lines intersect with the multiple thin layers. For example, a drain-side select-gate transistor 716 is formed where the SGD control line intersects with the multiple thin layers, a source-side select-gate transistor 701 is formed where the SGS control line intersects with the multiple thin layers, the topmost data memory cell 714 is formed where the WL95 word line intersects with the multiple thin layers, and the bottommost data memory cell 703 is formed where the WLO word line intersects with the multiple thin layers.

[0104] Multiple thin layers may form a ring layer and may be deposited, for example, using atomic layer deposition. These layers may include, for example, a barrier oxide layer 663, a charge trapping layer 664 or film (such as silicon nitride (Si3N4) or other nitrides), a tunnel layer 665 (e.g., gate oxide), and a channel 660 (e.g., comprising polysilicon). A dielectric core 666 (e.g., comprising silicon dioxide) may also be provided. Word lines or control lines may comprise a metal, such as tungsten. In this example, all layers are disposed within memory vias. In other methods, some of the layers may be disposed within word line or control line layers. Multiple thin layers form columnar active regions (AA) of a NAND string.

[0105] Stacked on substrate 611. In one method, the substrate includes a p-well region 611a connected to the source end of the NAND string (see also...). Figure 3 The p-well region may include an epitaxial region 612 extending upward adjacent to the source-side selected gate transistor. The p-well region may include an n+ contact 612c connected to a local interconnect 651 to receive a source line voltage and a p+ contact 612b connected to a conductive path 682 to receive a p-well voltage. The local interconnect 651 may include a conductive material 651b, such as a metal surrounded by an insulating material 651a, to prevent metal conduction with adjacent word lines. In one possible embodiment, the p-well region is formed in an n-well 613, which in turn is formed in a p-type semiconductor region 614 of the substrate.

[0106] The NAND string 700n has a source end 700s connected to the p-well at the bottom 610b of the stack 610. The NAND string 700n also has a drain end 700d connected to the bit line BL0 via a bit line contact 680 containing n-type material at the top 610t of the stack.

[0107] NAND strings can be considered to have floating channels because the length of the channels is not formed on the substrate.

[0108] When a memory cell is programmed, electrons are stored in a portion of the charge-trapping layer associated with the memory cell. These electrons are attracted from the channel into the charge-trapping layer and then pass through the tunneling layer. The Vth of the memory cell increases proportionally to the amount of charge stored. See also Figure 12 During the erasure operation, electrons return to the channel.

[0109] Figure 7A It shows the relationship with Figure 4 and Figure 6An exemplary view of NAND strings within a consistent block BLKO. The NAND strings are arranged in a 3D configuration within sub-blocks of the block. Each sub-block includes multiple NAND strings, with one example NAND string depicted. For example, SB0, SB1, SB2, and SB3 include example NAND strings 700n, 710n, 720n, and 730n, respectively. The NAND strings have... Figure 6 Consistent data word lines, dummy word lines, and select gate lines. Each sub-block comprises a set of NAND strings extending in the x-direction and having a common SGD line or control gate layer. NAND strings 700n, 710n, 720n, and 730n are located in sub-blocks SB0, SB1, SB2, and SB3, respectively. Block programming can be based on word line programming order. One option is to program memory cells in different word line portions within different sub-blocks one at a time, before programming memory cells in the next word line. For example, this could involve programming WL0 in SB0, SB1, SB2, and SB2, then programming WL1 in SB0, SB1, SB2, and SB2, and so on. For example, the word line programming order could start with WL0 (source end word line) and end with WL95 (drain end word line).

[0110] NAND strings 700n, 710n, 720n, and 730n each have channels 700a, 710a, 720a, and 730a, respectively. Additionally, NAND string 700n includes an SGS transistor 701, dummy memory cells 702, data memory cells 703-714, dummy memory cells 715, and an SGD transistor 716. NAND string 710n includes an SGS transistor 721, dummy memory cells 722, data memory cells 723-734, dummy memory cells 735, and an SGD transistor 736. NAND string 720n includes an SGS transistor 741, dummy memory cells 742, data memory cells 743-754, dummy memory cells 755, and an SGD transistor 756. The NAND string 730n includes an SGS transistor 761, a dummy memory cell 762, data memory cells 763-774, a dummy memory cell 775, and an SGD transistor 776.

[0111] This example illustrates one SGD transistor at the drain terminal of each NAND string and one SGS transistor at the source terminal of each NAND string. In one approach, the SGD transistors in SB0, SB1, SB2, and SB3 can be driven by separate control lines SGD(0), SGD(1), SGD(2), and SGD(3), respectively. In another approach, multiple SGD and / or SGS transistors can be provided in the NAND string.

[0112] After erasing a block of memory cells in an erase operation, programming can occur, where memory cells are programmed according to word line programming order. For example, programming can begin with the word line on the source side of the block and proceed to the word line on the drain side, one word line at a time. Word lines can also be programmed in a sub-block programming order, for example, extending from SBO to SB3 when four sub-blocks exist. For example, a portion of the memory cells in WLn of SBO is programmed first, then a portion of the memory cells in WLn of SB1, a portion of the memory cells in WLn of SB2, and then a portion of the memory cells in WLn of SB3. WLn refers to the word line selected for programming. The programming operation may include one or more sets of increasing programming voltages or pulses applied to the word lines in a corresponding programming cycle, also known as a program-verify iteration, such as... Figure 13A As described in the text. Verification tests can be performed after each programming voltage to determine whether the memory cell has been programmed. This is done when the memory cell is in the allocated data state represented by the threshold voltage (Vth) distribution, such as... Figure 12 As shown, the programming is complete.

[0113] Figure 7B It shows the connection to Figure 7A An exemplary view of a memory cell in WL3 within a sub-block SBO, the memory cell having a corresponding NAND string, bit lines, and sensing circuitry. (The image shows...) Figure 7A The SBO includes memory cells 706 and channels 700a in NAND strings 700n, as well as corresponding bit lines BL0. The SBO also includes memory cells 706a, 706b, and 706c in NAND strings 701n, 702n, and 703n, respectively, which have channels 700b, 700c, and 700d, and are connected to bit lines BL1, BL2, and BL3, respectively. Bit lines BL0-BL3 are respectively connected to... Figure 2 The sensing circuits 60-63.

[0114] In the programming loop, memory cells 706 and 706a can be examples of selected and unselected memory cells, respectively. In this case, NAND strings 700n and 701n are examples of selected and unselected NAND strings, respectively, and bit lines BL0 and BL1 are examples of selected and unselected bit lines, respectively.

[0115] Figure 8A This shows a bandgap diagram of the source terminals of a NAND string when electrons are extracted from the channel during source line pre-charging. Figures 8A-8DIn this diagram, the vertical direction represents the energy used for the conduction band (CB) and valence band (VB), and the horizontal direction represents the distance at the source end of the NAND string, from the source end of the channel to the substrate. Furthermore, electrons are represented by "e-", holes by "h-", and recombination of electrons and holes is represented by "h+e-".

[0116] exist Figure 8A In this process, a high bias is applied to the SGS transistor and to the source line, causing electrons to be extracted from the channel to the substrate. Specifically, when a high bias is applied to the source line including the n+ contact 612c in the p-well, an n-type inverting layer is formed in the substrate between the n+ contact and the channel, which allows for electron extraction. With fewer electrons in the channel, the channel voltage increases. This example of pre-charging involves the movement of charge carriers in one direction.

[0117] Figure 8B It shows when in Figure 8A The bandgap diagram of the source terminals of a NAND string when electrons are no longer extracted from the channel during the source line pre-charge process.

[0118] When a low bias is applied to an SGS transistor and a high bias is maintained on the source line, an energy barrier is created, which stops the extraction of electrons from the channel.

[0119] Figure 8C This diagram shows the bandgap of the source end of a NAND string when electrons are extracted from the channel during p-well precharge. P-well precharge can include two precharge mechanisms, such as electron extraction and hole injection. In this example, when a high bias is applied to the p-well and then to the SGS transistor, for example via the p+ contact 612b, electrons are extracted from the channel into the p-well to recombine with holes in the p-well, as indicated by "h+e-". Alternatively, hole injection from the p-well into the channel is prevented.

[0120] Figure 8D This diagram shows the bandgap at the source end of a NAND string when holes are injected into the channel during p-well pre-charge. In this example, holes are injected into the channel when a low bias is applied to the SGS transistor and a high bias is maintained on the p-well. In this channel, these holes recombine with electrons, as indicated by "h+e-", thereby increasing the channel voltage. Alternatively, electrons are prevented from being extracted from the channel into the p-well.

[0121] Figure 9 The channel voltage and Figures 8A-8DGraph of consistent pre-charge times using holes and electrons. The solid curve represents the rate of pre-charge occurring with electron-type pre-charge, and the dashed curve represents the rate of pre-charge occurring with faster hole-type pre-charge. In the case of electron-type pre-charge, for electrons to conduct in the channel, the following condition must be met: Vpch - Vch > Vt_e, or Vpch - Vt_e > Vch, where Vpch represents the word line and control line voltages for the memory cell and select gate transistor respectively, Vch represents the channel voltage, and Vt_e represents the electron voltage. During the pre-charge operation, as the channel voltage increases, the channel becomes less conductive, making it more difficult to charge. The maximum Vch is the smaller of Vddsa or Vpch - Vt_e, where Vddsa is the voltage of the power supply of the memory chip.

[0122] In the case of hole-type pre-charge, for holes to conduct in the channel, the following condition must be met: Vpch - Vch < Vt_h, or Vpch - Vt_h < Vch, where Vt_h represents the hole voltage. During the pre-charge operation, as the channel voltage increases, the channel becomes more conductive, making it easier to charge. Thus, the pre-charge process is faster and more efficient. The maximum Vch is Vddsa, as long as Vpch - Vt_h < Vddsa. When high Vt_h occurs in the channel region of a memory cell with a high programming state or when Vpch < 0V, it is easier to conduct holes. If negative Vpch is available on the chip, hole-type pre-charge at the source end of the NAND string ( Figure 10 process C in) may be sufficient to pre-charge the entire NAND string channel.

[0123] If negative Vpch is not available on the chip and the minimum value of Vpch is 0V, both methods are possible. In the first method, a reverse (or top-to-bottom) word line programming order is used. This involves programming the word lines starting from the top of the stack and going one word line at a time to the bottom of the stack or to an intermediate level in the stack between the top and the bottom. Electron-type pre-charge can be performed first, followed by hole-type pre-charge, consistent with Figure 10 process D in.

[0124] In the second method, a normal (or bottom-to-top) word line programming order is used. This involves programming the word lines starting from the bottom of the stack and going one word line at a time to the top of the stack or to an intermediate level in the stack. Electron-type pre-charge can be performed at the drain end of the NAND string, while hole-type pre-charge is performed at the source end of the NAND string, consistent with Figure 10 process E in.

[0125] Figure 10A table showing the different precharge processes marked A through E is provided. Process A includes an electronic precharge from the drain side, where the voltages of the bit line, SGS line, and drain-side word line are greater than 0V. Process B includes an electronic precharge from the source side, where the voltages of the source line, p-well, SGS line, and source-side word line are greater than 0V. Process C includes a hole-type precharge from the source side, where the voltages of the source line and p-well are greater than 0V, and the voltages of the SGS line and source-side word line are 0V or less. Process D includes processes B and C, which are performed independently in time, with process C following process B being more efficient. Process D is particularly suitable when using a top-to-bottom word line programming order. Process E includes processes A and C, which are performed simultaneously. Process E is particularly suitable when using a bottom-to-top word line programming order.

[0126] Figure 11 It shows the relationship with Figure 10 A flowchart of an exemplary programming operation consistent with the precharge mode. Step 1100 begins a programming operation for a set of NAND strings. This programming operation includes memory cells in the NAND strings connected to selected word lines among a plurality of word lines. Step 1101 begins a programming cycle. Step 1102 includes a precharge phase 1407 for performing the programming operation. Figure 14 This pre-charge phase includes injecting holes into the source side of the NAND string. Note that this injection can occur for all NAND strings in the block (including selected and unselected NAND strings). For selected NAND strings, the bit line is grounded during a subsequent programming pulse to remove the channel boost.

[0127] In an exemplary embodiment of step 1102, in order to inject holes into the channel at the source end of the NAND string, the control circuit is configured to bias a subset 1620 of the source side of a plurality of word lines at the source end 700s of the NAND string 700n with a corresponding voltage not exceeding 0V (e.g., 0V or <0V), while biasing the source side of the gate control line SGS with a corresponding voltage not exceeding 0V, biasing the n-type contact 612c with a corresponding positive voltage, and biasing the p+ contact 612b with a corresponding positive voltage.

[0128] Step 1103 indicates an option for a pre-charge phase that includes individually extracting electrons from the source side of the NAND string, and... Figure 10 The process is consistent with D. Hole injection in step 1102 can occur within a first time period, and electron extraction in step 1103 can occur within a separate second time period. The second time period can be... Figure 14 tl-t2 in the context is after the first time interval t0-t1.

[0129] In an exemplary embodiment of step 1103, before holes are injected into the channel at the source end of the NAND string, the control circuit is configured to extract electrons from the channel at the source end of the NAND string. Extracting electrons from the channel at the source end of the NAND string includes simultaneously biasing a subset of the source side of multiple word lines at the source end of the NAND string with a corresponding positive voltage, biasing the source side of the gate control line with a corresponding positive voltage, biasing the n-type contact with a corresponding positive voltage, and biasing the p+ contact with a corresponding positive voltage.

[0130] Step 1104 represents an alternative option for the pre-charge phase, which includes simultaneously extracting electrons from the drain side of the NAND string, and... Figure 10 The process is the same as E. Alternatively, you can use either of the two options in steps 1102 and 1103.

[0131] In an exemplary implementation of step 1104, in order to precharge the channel, during the injection of holes into the channel at the source terminal of the NAND string, the control circuit is configured to extract electrons from the channel at the drain terminal of the NAND string. Extracting electrons from the channel at the drain terminal of the NAND string includes:

[0132] Simultaneously, a subset 1600 of the drain side of multiple word lines at the drain terminal 700d of the NAND string is biased with a corresponding positive voltage, the gate control line SGD is selected by biasing the drain side with a corresponding positive voltage, and the drain terminal is biased with a corresponding positive voltage.

[0133] Step 1105 includes the programming phase 1408, which performs programming operations. Figure 14 The programming phase involves applying a programming pulse to a selected word line. The programming pulse may have an initial pass voltage Vpass, followed by a peak level Vpgm.

[0134] Step 1106 includes the verification phase 1409 of performing programming operations. Figure 14 The verification phase includes applying a verification signal 1406 to a selected word line and sensing a selected memory cell during different verification voltages of the verification signal. For example, the verification signal can be... Figure 12 , Figure 13A and Figure 13B Consistent.

[0135] Step 1107 determines whether a next programming loop exists in the programming operation. If the decision is true, the next programming loop begins at step 1101. If the decision is false, the programming operation is completed at step 1108.

[0136] Figure 12An exemplary Vth distribution for a set of memory cells with three bits and eight data states per cell is shown. The vertical axis depicts the number of memory cells on a logarithmic scale, and the horizontal axis depicts the Vth of memory cells on a linear scale. The techniques presented herein can be used with both single-level and multi-level cells.

[0137] Each memory cell can be associated with a data state based on the data written in the program command. Based on the data state of the memory cell, the memory cell will remain in an erase (Er) state or be programmed into a programmed data state. For example, in a one-bit memory device per cell, there are two data states: erase and programmed. In a two-bit memory device per cell, there are four data states: erase and three programmed data states, referred to as A, B, and C data states. In a three-bit memory device per cell, there are eight data states: erase and seven programmed data states, referred to as A, B, C, D, E, F, and G data states. In a four-bit memory device per cell, there are sixteen data states: erase state S0 and fifteen programmed data states S1-S15. Each data state can be represented by a series of threshold voltages (Vth) in the memory cell.

[0138] After a memory cell is programmed, data can be read back during a read operation. A read operation may involve applying a series of read voltages to a word line while sensing circuitry determines whether a cell connected to the word line is in a conductive (on) or non-conductive (off) state. If the cell is in a non-conductive state, the Vth of the memory cell exceeds the read voltage. This read voltage is set to a level between threshold voltage levels expected in adjacent data states. Furthermore, during a read operation, the voltage of an unselected word line ramps up to a read-through or on level that is high enough to place the unselected memory cell in a strongly conductive state to avoid interfering with the sensing of the selected memory cell. The word line being programmed or read is referred to as the selected word line WLn.

[0139] In one approach, at the start of a programming operation, memory cells are initially in an erase (Er) state, as shown in Vth distribution 1200. After a successful programming operation, memory cells assigned to the AG state are represented by Vth distributions 1201-1207, each with an associated verification voltage VvA-VvG. Read voltages VrA-VrG can be used to read the state of the memory cells during a read operation.

[0140] In an erase operation, the data memory cell transitions from a Vth distribution of programmed data states (e.g., state AG) to an erase state. The erase operation includes an erase phase where the memory cell is biased for erasure, followed by an erase-verification test. The erase-verification test can be performed using an erase verification voltage VvEr applied to the word line.

[0141] In this eight-state example, the Er-G state is an example of the assigned data state, and the AG state is an example of the programmed data state.

[0142] Figure 13A It shows the relationship with Figure 11 An exemplary voltage signal used in a consistent programming operation. Voltage signal 1300 includes a set of programming pulses applied to a word line selected for programming, including an initial programming pulse 1301. This initial programming pulse has a voltage Vpgm_init, and dVpgm represents the step size between successive programming pulses. As an example, a single programming pass with fifteen programming cycles is used. As the programming operation progresses, a verification signal (including exemplary verification signal 1302) in each programming cycle may include a lower allocation data state, then an intermediate allocation data state, and then a higher allocation data state, such as... Figure 13B As shown. See also Figure 14 Signals, such as details of programming loops.

[0143] The example verification signal depicts three verification voltages for simplicity. The verification signal is applied to the selected word line during the programming cycle after the programming pulse is applied. During the verification test, the memory cell is sensed to determine its programming progress while the verification signal is applied. The verification signal includes one or more voltages used to determine whether the memory cell has completed programming to the allocated data state. The result of sensing Vth relative to the verification voltage can be used to suppress further programming of the memory cell.

[0144] Data that is programmed or read can be arranged into pages. For example, with two bits per unit, two pages of data can be stored in memory cells connected to the word line. The next and previous pages of data can be determined by reading the memory cells using read voltages VrA and VrC; and VrB, respectively.

[0145] With three bits per cell, three pages of data can be stored in memory cells connected to the word lines. The data for the next, middle, and previous pages can be determined by reading the memory cells using the read voltages of VrA and VrE; VrB; and VrC and VrG, respectively.

[0146] Figure 13B It shows in Figure 13A Examples of verification voltages used in different programming loops. Horizontal bars and... Figure 13AThe programming cycle axis is time-aligned. The bars overlap in some programming cycles, thus indicating that verification operations can be performed on multiple data states in the programming cycle. In the case of eight data states, the bars indicate that verification voltages for states A, B, C, D, E, F, and G will be applied to programming cycles 1-4, 3-6, 5-8, 7-10, 9-12, 11-14, and 12-15, respectively.

[0147] In one approach, the programming cycle for performing verification tests is predetermined before programming operations. In another approach, the programming cycle for performing verification tests is adaptively determined as programming progresses. For example, after a specified portion of a memory cell in state A has passed its verification test, the verification test for state B can begin in the next programming cycle.

[0148] Figure 14 It shows the method for performing with Figure 11 and Figure 13A Exemplary voltage signals for consistent programming operations. The vertical dimension represents voltage, and the horizontal dimension represents time in time points t0-tl2. The depicted time period corresponds to a programming cycle and includes a pre-charge phase 1407 (t0-t2), a programming phase 1408 (t2-t8), and a verification phase 1409 (t9-tl2). Voltage signals 1400, 1410, 1420, 1430, 1440, and 1450 represent VWLn, VWL_unsel, Vsgd, Vsgs, Vbl, and Vsl / Vp-well, respectively. VWL_unsel may include data word lines and dummy word lines.

[0149] As mentioned, the pre-charge phase is used for applications such as... Figure 10 The various processes depicted charge the channels of the NAND string. VWLn is the voltage applied to a selected word line. During the pre-charge phase, three voltages are shown for VWLn. Curve 1401 shows positive voltages such as 1V to 2V, curve 1402 shows 0V, and curve 1403 shows negative voltages such as -1V to -2V. Curve 1403a shows the voltages used for… Figure 10 Option D in the pre-charging process.

[0150] During the programming phase, VWLn increases from 0V (curve 1402a) to the pass voltage Vpass (curve 1404) at t3, and then increases to the peak level Vpgm (curve 1405) at t5. VWLn then drops back to 0V at t6 before the verification phase 1409. During the verification phase, a verification signal 1406 is applied to the selected word line, and the selected memory cell is sensed during different verification voltages of the verification signal. In this example, the verification voltage is... Figure 13B The programming loop 12 is consistent with VvE, VvF, and VvG.

[0151] VWL_unsel represents the voltage applied to an unselected word line. In some cases, different voltages can be applied to different groups of unselected word lines. Curve 1411 shows positive voltages such as 1V to 2V, curve 1412 shows 0V, and curve 1413 shows negative voltages such as -1V to -2V. During the programming phase, VWL_unsel increases from 0V (curve 1412a) to Vpass (curve 1414), and then drops back to 0V at tl2 at the end of the verification phase 1409. Curve 1413a shows the voltage applied to unselected word lines. Figure 10 Option D in the pre-charging process.

[0152] Vsgd represents the voltage applied to the SGD transistor (also known as the drain-side selected gate transistor) via the SGD control line. Curve 1421 shows a positive voltage, such as 4V to 6V, for all SGD transistors in the block. This allows Vbl to be passed to the channel. For the SGD transistors of the selected NAND string, curve 1422 shows Vsgd_sel during the programming phase, for example, 2.5V. Vsgd_sel is high enough to provide the associated SGD transistor of the selected NAND string with a conductive state, which receives the programming-enable voltage Vbl_en = 0V. For the SGD transistors of the unselected NAND string, curve 1423 shows Vsgd_unsel during the programming phase, for example, 0V. This provides the associated SGD transistor of the unselected NAND string with a non-conductive state. This allows the associated channel to be boosted via capacitive coupling as VWLn and VWL_unsel ramp up from 0V to Vpass. This is a complement to the boost from the precharge phase. Curve 1424 shows Vsgd_sel at elevated levels, such as 4V to 6V, during the verification phase to allow sensing to occur in the associated NAND string. Curve 1425 shows Vsgd_unsel at 0V during the verification phase, because no sensing occurs in the associated NAND string.

[0153] Vsgs represents the voltage applied to the SGS transistor (also known as a source-side selected gate transistor) via the SGS control line. In one approach, all SGS transistors in a block are connected and receive the same voltage. During the precharge phase, curve 1431 shows positive voltages, such as 4V to 6V, for all SGS transistors in the block. This allows Vsl or Vp-well to pass to the channel, such as for source-side electronic precharge. Curve 1432 shows 0V, and curve 1433 shows negative voltages, such as -1V to -2V. These values ​​are suitable for source-side hole-type precharge. Curve 1433a shows the voltages used for... Figure 10 Option D in the pre-charging process.

[0154] Curve 1434 shows Vsgs = 0V during the programming phase. Curve 1435 shows Vsgd at elevated levels, such as 4V to 6V, during the verification phase to allow sensing to occur in the selected NAND string.

[0155] Vbl represents the bit line voltage, which can be set individually for selected and unselected NAND strings. During the precharge phase, curve 1441 shows the positive precharge voltage Vbl_pc for the selected NAND string, such as 2V, when using drain-side electronic precharge. Curve 1443 shows 0V for the bit line connected to an unselected NAND string. During the programming phase, curve 1442 shows, for example, a programming-suppression voltage Vbl_inh = 1.5V for an unselected NAND string, and curve 1443 shows, for example, a programming-enable voltage Vbl_en = 0V for a selected NAND string. Curve 1444 shows, for example, Vbl = 0.5V during the verification phase.

[0156] Vsl represents the source line voltage, and Vp-well represents the p-well voltage. Generally, the value of Vsl will be similar to Vp-well to prevent leakage in the substrate. During the pre-charge phase in the first time period from t0 to t1, curve 1451 shows a positive pre-charge voltage such as 2V. In one option, as shown by curve 1452, Vsl / Vp-well decreases back to 0V at tl at the end of the first time period (curve 1456). In another option, with... Figure 10 The pre-charge process D is consistent with that shown by curve 1453, where Vsl / Vp-well remains at a positive voltage during the second time period from tl to t2, and then drops back to 0V at t2 at the end of the second time period. During the programming phase, curve 1454 shows Vsl / Vp-well at a positive voltage to help maintain the SGS transistor in a non-conductive state. Curve 1455 shows Vsl / Vp-well also at a positive level during the verification phase.

[0157] For electronic pre-charge from the drain side ( Figure 10 In process A), at least 1600 drain-side subsets of the word line are required. Figure 16 Vbl, Vsgd, and VWL_unsel are positive, consistent with curves 1401, 1421, and 1411, respectively.

[0158] For electronic pre-charge from the source side ( Figure 10 In process B), at least the source-side subset 1620 of the word line ( Figure 16The Vsl / Vp-well, Vsgs, and VWL_unsel values ​​are positive, consistent with curves 1451 / 1452, 1431, and 1411, respectively.

[0159] For hole-type pre-charge from the source side ( Figure 10 In process C), Vsl / Vp-well is positive (e.g., consistent with curve 1451), and for at least the source-side subset 1620 of the word line ( Figure 16 The Vsgs and VWL_unsel of the memory cell are 0V (e.g., consistent with curves 1432 and 1412, respectively) or <0V (e.g., consistent with curves 1433 and 1413, respectively). Generally, Vwl / Vp-well is larger than Vsgs and VWL_unsel for at least a subset 1620 of the word line, for example, approximately 1V to 4V, such that the source-control gate voltages of the associated SGS transistor and memory cell are positive. Hole-type precharge is greater when Vsgs and VWL_unsel are as low as possible. In some memory devices, 0V is the lowest voltage that can be applied to Vsgs and VWL_unsel. In other memory devices, negative voltages such as -1V to -2V should be used if available for Vsgs and VWL_unsel to maximize the efficiency of hole-type precharge.

[0160] for Figure 10 Processes D and B are executed between t0 and t1, consistent with curves 1451 / 1452, 1431, and 1411, followed by process C between t1 and t2. For process C, curve 1453 indicates how Vsl / Vp-well remains at a positive voltage. Curves 1402a and 1403a indicate how VWL_sel can remain at 0V or <0V, respectively. Curves 1412a and 1413a indicate how VWL_unsel can remain at 0V or <0V, respectively. Curves 1434 and 1433a indicate how Vsgs can remain at 0V or <0V, respectively.

[0161] for Figure 10 Process E, as described above, includes the drain-side subset 1600 of the bias word line, and process A can be used together with process C, as described above, includes the source-side subset 1620 of the bias word line.

[0162] The voltage shown is an example.

[0163] Figure 15 It shows that with Figure 14The graph shows the Vth curve, a measure of programming interference, for erase state memory cells that vary during the electronic precharge period t0-tl and the hole precharge period tl-t2. Vth represents the upper tail of the Vth distribution, and lower values ​​indicate lower programming interference due to better channel boost.

[0164] As discussed, in the pre-charge process D, electron-type pre-charge from the source side is followed by hole-type pre-charge from the source side. Curves 1500a and 1500b represent Vth when the electron-type pre-charge time period t0-tl is relatively short or long, respectively. As expected, Vth decreases as the time period t0-tl increases. Curves 1510a and 1510b represent Vth when the hole-type pre-charge time period tl-t2 is relatively short or long, respectively. As expected, Vth decreases as the time period tl-t2 increases.

[0165] The curve illustrates that hole-based precharging is more efficient than electronic precharging when the selected word line WLn is closer to the last programmed word line in the block. Therefore, the ratio of the second time period (tl-t2) utilizing hole-based precharging to the first time period (t0-tl) utilizing electronic precharging can be adjusted to optimize channel boost. For example, this ratio can be a function of the position of the selected word line WLn among multiple word lines. In one approach, the ratio is larger when WLn is closer to the last programmed word line in the block. When a bottom-to-top word line programming order exists, the last programmed word line in the block can be the topmost word line, or when a top-to-bottom word line programming order exists, the last programmed word line in the block can be the bottommost word line.

[0166] The ratio can be adjusted based on the risk of programming interference (PD). The ratio can be larger when the risk of PD is greater. In one approach, control circuitry is configured to determine the risk of programming interference during programming operations and increase the ratio when the risk of PD is relatively high. For example, as mentioned, the location of WLn indicates the risk of programming interference. Other risk factors for increasing PD may include higher temperatures and a higher number of program-erase cycles for the block. Control circuitry can be configured to determine the risk of programming interference during programming operations and, when the risk of PD is relatively high, adjust the time period during which holes are injected into the channel at the source end of the NAND string for a relatively long period.

[0167] Figure 16 It shows the connection to Figure 7AA diagram illustrating subsets of word lines in a memory cell within a NAND string 700n. Word lines are defined as WL0-WL19 in the source-side subset 1620, WL20-WL75 in the intermediate subset 1610, and WL76-WL95 in the drain-side subset 1600. The source-side and drain-side subsets of word lines may each comprise, for example, approximately 5%-20% or up to 50% of the total number of data word lines in a block. As described above, when the source end of the NAND string is precharged using a precharge process, this process may be sufficient to bias the source-side subset of the word lines, but not sufficient to bias the intermediate or drain-side subsets. Similarly, when the drain end of the NAND string is precharged using a precharge process, this process may be sufficient to bias the drain-side subset of the word lines, but not sufficient to bias the intermediate or source-side subsets. For example, with... Figure 10 Different pre-charge processes consistent with process E can be used simultaneously at the source and drain terminals by different biasing of the word line source-side subset and drain-side subset.

[0168] The source-side subset of the multiple word lines includes consecutive word lines (WLO-WLn-1) ranging from the source-side word line (WL0) of the multiple word lines to the source-side adjacent word line (WLn-1) of the selected word line (WLn) among the multiple word lines, and the drain-side subset of the multiple word lines includes consecutive word lines (WL95-WLn) ranging from the drain-side word line (WL95) to the selected word line (WLn).

[0169] Therefore, it can be seen that in one specific embodiment, an apparatus includes: a NAND string extending vertically in a stack of spaced conductive layers, the NAND string including a source end and a drain end, the NAND string including a channel, a plurality of memory cells and a source-side select gate transistor at the source end, and the spaced conductive layers including a plurality of word lines connected to the plurality of memory cells and a source-side select gate control line connected to the source-side select gate transistor; a substrate including a p-well in contact with the source end of the NAND string, an n-type contact in the p-well and a p+ contact in the p-well; and control circuitry. The control circuitry is configured to precharge the channel during a programming operation, wherein, in order to precharge the channel, the control circuitry is configured to inject holes into the channel at the source end of the NAND string, the hole injection into the channel at the source end of the NAND string including simultaneously biasing the source-side select gate control line with a corresponding voltage not exceeding 0V, biasing the n-type contact with a corresponding positive voltage and biasing the p+ contact with a corresponding positive voltage.

[0170] In another specific embodiment, a method includes: precharging a channel of a NAND string in a block during a precharge phase of a programming cycle of a programming operation, the channel of each NAND string extending between a source-side selected gate transistor at the source end of the NAND string and a drain-side selected gate transistor at the drain end of the NAND string, the source end of the NAND string being connected to a substrate, the NAND string being connected to a plurality of word lines, and the precharging of the channel including injecting holes from the substrate into the channel at the source end of the NAND string; and after the precharging of the channel, applying a programming pulse to a selected word line among the plurality of word lines.

[0171] In another embodiment, an apparatus includes: a substrate; memory cell blocks arranged on the substrate in NAND strings, each NAND string including a source-side select-gate transistor at the source end of the NAND string, a drain-side select-gate transistor at the drain end of the NAND string, memory cells between the source and drain ends, and a channel extending from the source end to the drain end, wherein the source end of the NAND string is connected to the substrate, the NAND string extends upward from the substrate, and the memory cells are connected to a plurality of word lines; and control circuitry. The control circuitry is configured to precharge the channel during a programming operation before applying a programming voltage to a selected word line among the plurality of word lines, wherein, in order to precharge the channel, the control circuitry is configured to apply a corresponding voltage signal to the substrate, the source-side select-gate transistor, and the plurality of word lines for a first time period (t0-t1), the corresponding voltage signal initially having a corresponding positive voltage, and after the first time period, during a second time period (t1-t2), the corresponding voltage signal for the source-side select-gate transistor and the plurality of word lines decreases while the corresponding voltage signal on the substrate remains at its corresponding positive level.

[0172] The specific embodiments of the invention described above have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible in light of the foregoing teachings. The described embodiments were chosen to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to best utilize the invention in various embodiments and various modifications suitable for the intended particular use. The scope of the invention is intended to be defined by the appended claims.

Claims

1. A pre-charging device, comprising: NAND strings (700n, 710, 720n, 730n) extend vertically in a stack (610) of spaced conductive layers (SGS, WLDS, WL0-WL95, WLDD, SGD), each NAND string including a source end (700s) and a drain end (700d), each NAND string including a channel (660), a plurality of memory cells (703-714, 723-734, 743-754, 763-774) and source-side select gate transistors (701, 721, 741, 761) at the source end, and the spaced conductive layers including a plurality of word lines (WL0-WL95) connected to the plurality of memory cells and a source-side select gate control line (SGS) connected to the source-side select gate transistors; A substrate (611) comprising a p-well (612) in contact with the source end of the NAND string, an n-type contact (612c) in the p-well, and a p+ contact (612b) in the p-well; and Control circuitry (110, 122), configured to precharge the channel during a programming operation, wherein, in order to precharge the channel, the control circuitry is configured to inject holes into the channel at the source terminals of the NAND string, wherein injecting the holes into the channel at the source terminals of the NAND string includes simultaneously biasing the source-side select gate control line with a corresponding voltage not exceeding 0V, biasing the n-type contact with a corresponding positive voltage, and biasing the p+ contact with a corresponding positive voltage; and in: The NAND string includes drain-side selected gate transistors (716, 736, 756, 776) located at the drain terminal; The spaced-apart conductive layer includes drain-side select gate control lines (SGD(0), SGD(1), SGD(2), SGD(3)) connected to the drain-side select gate transistor; and To precharge the channel, during the injection of holes into the channel at the source end of the NAND string, the control circuit is configured to extract electrons from the channel at the drain end of the NAND string. Extracting electrons from the channel at the drain end of the NAND string includes simultaneously biasing a subset of the drain side of the plurality of word lines at the drain end of the NAND string with a corresponding positive voltage, biasing the drain side to select the gate control line with a corresponding positive voltage, and biasing the drain end with a corresponding positive voltage.

2. The apparatus according to claim 1, wherein: The corresponding voltage on the source-side gate control line is a negative voltage.

3. The apparatus according to claim 1 or 2, wherein: In order to inject the holes into the channel at the source end of the NAND string, the control circuit is configured to bias a subset of the source-side word lines at the source end of the NAND string with a corresponding voltage not exceeding 0V, while biasing the source-side gate control line with the corresponding voltage not exceeding 0V, biasing the n-type contact with the corresponding positive voltage, and biasing the p+ contact with the corresponding positive voltage.

4. The apparatus according to claim 3, wherein: The corresponding voltage of the source-side subset of the plurality of word lines is a negative voltage.

5. The apparatus according to claim 1 or 2, wherein: To precharge the channel, before injecting the holes into the channel at the source end of the NAND string, the control circuit is configured to extract electrons from the channel at the source end of the NAND string. Extracting the electrons from the channel at the source end of the NAND string includes simultaneously biasing a subset of the source-side word lines at the source end of the NAND string with a corresponding positive voltage, biasing the source-side selected gate control line with a corresponding positive voltage, biasing the n-type contact with a corresponding positive voltage, and biasing the p+ contact with a corresponding positive voltage.

6. The apparatus according to claim 5, wherein: The programming operation includes the word line programming order from top to bottom in the stack.

7. The apparatus according to claim 1, wherein: The process of injecting holes into the channel at the source end of the NAND string includes biasing a subset of the source-side word lines at the source end of the NAND string with a corresponding voltage not exceeding 0V (1620), while simultaneously biasing a subset of the drain-side word lines at the drain end of the NAND string with the corresponding positive voltage.

8. The apparatus according to claim 7, wherein: The source-side subset of the plurality of word lines includes consecutive word lines within the range from the source-side word line (WL0) of the plurality of word lines to the source-side adjacent word line (WLn-1) of a selected word line (WLn) among the plurality of word lines; and The drain-side subset of the plurality of word lines includes a range of consecutive word lines from the drain-side word line (WL95) to the selected word line.

9. The apparatus according to claim 7, wherein: The corresponding voltage of the source-side subset of the plurality of word lines is a negative voltage.

10. A pre-charging method, comprising: During the pre-charge phase of the programming cycle of the programming operation, the channels (660) of the NAND strings (700n, 710, 720n, 730n) in the blocks (BLK0-BLK3) are pre-charged. The channel of each NAND string extends between the source-side gate select transistors (701, 721, 741, 761) at the source end (700s) of the NAND string and the drain-side gate select transistors (716, 736, 756, 776) at the drain end (700d) of the NAND string. The source end of the NAND string is connected to the substrate (611). The NAND string is connected to a plurality of word lines (WL0-WL95). The pre-charging of the channel includes injecting holes from the substrate into the channel at the source end of the NAND string. as well as After the pre-charging of the channel, a programming pulse (1301) is applied to a selected word line (WLn) among the plurality of word lines; and in: The drain terminal of the NAND string is connected to the corresponding bit lines (BL0-BL3); and The pre-charging of the channel includes extracting electrons from the channel into the bit line at the drain end of the NAND string, while simultaneously injecting holes from the substrate into the channel at the source end of the NAND string.

11. The method of claim 10, wherein: Multiple word lines are connected to the memory cells (703-714, 723-734, 743-754, 763-774) of the NAND string; The control line (SGS) is connected to the source-side select gate transistor; and the injection of the hole from the substrate into the channel at the source end of the NAND string includes applying a positive voltage to the substrate, and applying a voltage not exceeding 0V to the control line and to a subset of the adjacent source-side select gate transistors of the plurality of word lines.

12. The method according to claim 10 or 11, wherein: The pre-charging of the channel includes extracting electrons from the channel into the substrate at the source end of the NAND string, and injecting holes from the substrate into the channel at the source end of the NAND string in time, independent of the process.

13. A pre-charging device, comprising: substrate; Memory cell blocks are arranged on the substrate in NAND strings. Each NAND string includes a source-side select-gate transistor at the source end of the NAND string, a drain-side select-gate transistor at the drain end of the NAND string, a memory cell between the source end and the drain end, and a channel extending from the source end to the drain end. The source end of the NAND string is connected to the substrate, the NAND string extends upward from the substrate, and the memory cell is connected to a plurality of word lines. A control circuit configured to precharge the channel during a programming operation before applying a programming voltage to a selected word line among the plurality of word lines. To precharge the channel, the control circuit is configured to apply a corresponding voltage signal to the substrate, the source-side select-gate transistor, and the plurality of word lines for a first time period. This corresponding voltage signal initially has a corresponding positive voltage. After the first time period, during a second time period, the corresponding voltage signal for the source-side select-gate transistor and the plurality of word lines decreases while the corresponding voltage signal on the substrate remains at its corresponding positive level. in: The drain terminal of the NAND string is connected to the corresponding bit lines (BL0-BL3); and The pre-charging of the channel includes extracting electrons from the channel into the bit line at the drain end of the NAND string, while simultaneously injecting holes from the substrate into the channel at the source end of the NAND string.

14. The apparatus according to claim 13, wherein: The corresponding voltage signals for the source-side gate select transistor and the plurality of word lines are reduced to a level not exceeding 0V.

15. The apparatus according to claim 13 or 14, wherein: The voltage signal for the source-side gate selector transistor and the plurality of word lines is reduced to a negative voltage level.

16. The apparatus according to claim 13 or 14, wherein: The second time period is a function of the position of the selected character line among the plurality of character lines.

17. The apparatus according to claim 13 or 14, wherein: The ratio of the second time period to the first time period is a function of the position of the selected character line among the plurality of character lines.

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