High voltage pulse generating circuit

Abstract

Some embodiments include a high voltage pulse generation circuit comprising: a high voltage pulse generation power supply; a transformer electrically coupled with the high voltage pulse generation power supply; an output electrically coupled with the transformer and configured to output high voltage pulses having an amplitude greater than 1 kV, a pulse repetition frequency greater than 1 kHz; a bias compensation circuit arranged in parallel with the output, the bias compensation circuit comprising: a first inductance comprising an inductive element and any stray inductance between the bias compensation circuit and the high voltage pulse generation power supply; and a second inductance comprising an inductive element and any stray inductance between the bias compensation circuit and the output.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 62 / 936,288, filed November 15, 2019, entitled “NANOSECOND PULSER BIASCOMPENSATION WITH CORRECTION”, the entire contents of which are incorporated herein by reference.

[0003] This application claims priority to U.S. Provisional Patent Application No. 62 / 937,214, filed November 18, 2019, entitled “NANOSECOND PULSER BIASCOMPENSATION WITH CORRECTION”, the entire contents of which are incorporated herein by reference. Background Technology

[0004] In a plasma deposition system, wafers are typically held electrostatically in a processing chamber by chucks. Plasma is created within the chamber, and high-voltage pulses are introduced to accelerate ions within the plasma onto the wafer. If the potential between the chuck and the wafer exceeds a specific voltage threshold (e.g., approximately ±2 kV), the forces on the wafer can become large enough to damage or destroy it. Summary of the Invention

[0005] Some embodiments include a high-voltage pulse generating circuit comprising: a high-voltage pulse generating power supply; a transformer electrically coupled to the high-voltage pulse generating power supply; an output electrically coupled to the transformer and configured to output a high-voltage pulse having an amplitude greater than 1 kV and a pulse repetition frequency greater than 1 kHz; and a bias compensation circuit electrically coupled to the transformer, the output at one end, and ground at the other end, wherein the stray inductance of the bias compensation circuit is less than approximately 1 μH.

[0006] In some embodiments, the bias compensation circuit includes a bias compensation diode, a DC power supply, and a bias compensation capacitor.

[0007] In some embodiments, the bias compensation circuit includes: a first inductor, which includes an inductor element and a stray inductance between the bias compensation circuit and the high-voltage pulse generating power supply; and a second inductor, which includes an inductor element and a stray inductance between the bias compensation circuit and the output.

[0008] In some embodiments, the second inductance is less than approximately 1 μH.

[0009] In some embodiments, the first inductance is greater than the second inductance. In some embodiments, the second inductance is less than 20% of the first inductance.

[0010] In some embodiments, the bias compensation circuit further includes: a bias compensation diode; a DC power supply; and a plurality of switches arranged in parallel with the bias compensation diode. In some embodiments, the high-voltage pulse generating power supply generates a plurality of high-voltage bursts, wherein each burst includes a plurality of high-voltage pulses; and wherein the plurality of switches are open during each of the plurality of high-voltage bursts and closed between each of the plurality of high-voltage bursts.

[0011] Some embodiments include a high-voltage pulse generating circuit comprising: a high-voltage pulse generating power supply; a transformer electrically coupled to the high-voltage pulse generating power supply; an output electrically coupled to the transformer and configured to output a high-voltage pulse having an amplitude greater than 1 kV and a pulse repetition frequency greater than 1 kHz; and a bias compensation circuit electrically coupled to the transformer, the output at one end, and ground at the other end, the bias compensation circuit comprising: a first inductor including an inductive element and a stray inductance between the bias compensation circuit and the high-voltage pulse generating power supply; and a second inductor including an inductive element and a stray inductance between the bias compensation circuit and the output.

[0012] In some embodiments, the second inductance is less than approximately 1 μH. In some embodiments, the first inductance is greater than the second inductance. In some embodiments, the second inductance is less than 20% of the first inductance.

[0013] In some embodiments, the bias compensation circuit further includes: a bias compensation diode; a DC power supply; and a plurality of switches arranged in parallel with the bias compensation diode. In some embodiments, the high-voltage pulse generating power supply generates a plurality of high-voltage bursts, wherein each burst includes a plurality of high-voltage pulses; and wherein the plurality of switches are turned on during each burst.

[0014] Some embodiments include a high-voltage pulse generating circuit comprising: a high-voltage pulse generating power supply; a transformer electrically coupled to the high-voltage pulse generating power supply; an output electrically coupled to the transformer and configured to output a high-voltage pulse having an amplitude greater than 1 kV and a pulse repetition frequency greater than 1 kHz; and a bias compensation circuit electrically coupled to the transformer, the output at one end, and ground at the other end. In some embodiments, the bias compensation circuit includes: a stray inductor less than approximately 1 μH; a bias compensation diode; a DC power supply arranged in series with the bias compensation diode; and an inductor arranged in series with the bias compensation diode and the DC power supply.

[0015] In some embodiments, the high-voltage pulse generating circuit may include a bias compensation resistor arranged across the bias compensation diode.

[0016] In some embodiments, the bias compensation has a resistance of less than approximately 100 kΩ.

[0017] In some embodiments, the high-voltage pulse generating circuit may include a first stray inductance of less than approximately 1 μH between the bias compensation diode and the point between the output and the transformer.

[0018] In some embodiments, the high-voltage pulse generating circuit may include a second stray inductance between the bias compensation diode and the capacitor of less than approximately 1 μH.

[0019] In some embodiments, the high-voltage pulse generating circuit may include a first stray inductance between the capacitor and ground of less than approximately 1 μH.

[0020] In some embodiments, the capacitor has a capacitance of less than approximately 1 mF.

[0021] In some embodiments, the bias compensation circuit further includes: a bias compensation diode; a DC power supply; and a plurality of switches arranged in parallel with the bias compensation diode. In some embodiments, the high-voltage pulse generating power supply generates a plurality of high-voltage bursts, wherein each burst includes a plurality of high-voltage pulses; and wherein the plurality of switches are turned on during each burst.

[0022] These illustrative embodiments are mentioned not to limit or define this disclosure, but to provide examples to aid in understanding it. Additional embodiments are discussed in the detailed description and are further described herein. The advantages provided by one or more of the various embodiments can be further understood by examining this specification or by practicing one or more of the embodiments presented. Attached Figure Description

[0023] These and other features, aspects and advantages of this disclosure will be better understood when reading the following detailed description with reference to the accompanying drawings.

[0024] Figure 1 This is a circuit diagram of a high-voltage pulse generating circuit according to some embodiments.

[0025] Figure 2 Example waveforms generated by a high-voltage pulse generating circuit according to some embodiments are shown.

[0026] Figure 3 This is a circuit diagram of a high-voltage pulse generating circuit according to some embodiments.

[0027] Figure 4 Example waveforms generated by a high-voltage pulse generating circuit according to some embodiments are shown.

[0028] Figure 5 This is a circuit diagram of a high-voltage pulse generating circuit according to some embodiments.

[0029] Figure 6 Example waveforms generated by a high-voltage pulse generating circuit according to some embodiments are shown.

[0030] Figure 7 This is a circuit diagram of a high-voltage pulse generating circuit according to some embodiments.

[0031] Figure 8 Example waveforms generated by a high-voltage pulse generating circuit according to some embodiments are shown.

[0032] Figure 9 This is a circuit diagram of a high-voltage pulse generating circuit according to some embodiments.

[0033] Figure 10 Example waveforms from a high-voltage pulse generation circuit according to some embodiments are shown.

[0034] Figure 11A Example waveforms from a high-voltage pulse generating circuit according to some embodiments are shown.

[0035] Figure 11B Example waveforms from a high-voltage pulse generation circuit according to some embodiments are shown.

[0036] Figure 12 This is a circuit diagram of a high-voltage pulse generating circuit according to some embodiments.

[0037] Figure 13 This is a circuit diagram of a high-voltage pulse generator circuit according to some embodiments. It includes a buffer and voltage divider resistors.

[0038] Figure 14 This is a circuit diagram of a high-voltage pulse generating circuit according to some embodiments.

[0039] Figure 15 This is a block diagram of a high-voltage switch with an isolated power supply according to some embodiments.

[0040] Figure 16 Example waveforms from a high-voltage pulse generating circuit according to some embodiments are shown.

[0041] Figure 17 Example waveforms from a high-voltage pulse generating circuit according to some embodiments are shown.

[0042] Figure 18Example waveforms from a high-voltage pulse generating circuit according to some embodiments are shown.

[0043] Figure 19 This is a circuit diagram of a high-voltage pulse generating circuit according to some embodiments.

[0044] Figure 20 This is a circuit diagram of a high-voltage pulse generating circuit according to some embodiments.

[0045] Figure 21 This is a circuit diagram of a high-voltage pulse generating circuit according to some embodiments.

[0046] Figure 22 This is a circuit diagram of a high-voltage pulse generating circuit according to some embodiments. Detailed Implementation

[0047] In plasma deposition systems, wafers are typically held electrostatically in a processing chamber by chucks. Plasma is created within the processing chamber, and high-voltage pulses are introduced to accelerate ions within the plasma onto the wafer. If the potential between the chuck and the wafer exceeds a specific voltage threshold (e.g., approximately ±2 kV), the forces on the wafer can be large enough to damage or destroy it. Furthermore, it can be advantageous to introduce higher voltage pulses into the processing chamber to increase channel depth, improve quality, or accelerate the etching process. Introducing high and relatively high voltage pulses into the plasma within the deposition processing chamber can affect the potential between the chuck and the wafer and may damage or destroy the wafer.

[0048] Systems and methods are disclosed for ensuring that the voltage between the wafer and the clip is close to or below a threshold (e.g., approximately ±2 kV) during periods when a high-voltage pulse occurs and during periods when no high-voltage pulse occurs. For example, these systems can also limit the self-biasing of the wafer when using a high-voltage RF power supply. For example, these systems and methods can compensate for voltage changes to ensure that the voltage between the clip and the wafer does not exceed a voltage threshold.

[0049] In some embodiments, the high-voltage pulse generating circuit can generate pulse voltages introduced into the plasma having amplitudes of approximately 1 kV, 2 kV, 5 kV, 10 kV, 15 kV, 20 kV, 30 kV, 40 kV, etc. In some embodiments, the high-voltage pulse generating circuit can be switched at frequencies up to approximately 500 kHz. In some embodiments, the high-voltage pulse generating circuit can provide a single pulse with a pulse width varying from approximately 50 nanoseconds to approximately 1 nanosecond. In some embodiments, the high-voltage pulse generating circuit can be switched at frequencies greater than approximately 10 kHz. In some embodiments, the high-voltage pulse generating circuit can operate with a rise time of less than approximately 20 ns.

[0050] As used throughout this document, the term "high voltage" can include voltages greater than approximately 1 kV, 10 kV, 20 kV, 50 kV, 100 kV, 1,000 kV, etc.; the term "high frequency" can include frequencies greater than approximately 1 kHz, 10 kHz, 100 kHz, 200 kHz, 500 kHz, 1 MHz, etc.; the term "high repetition rate" can include rates greater than approximately 1 kHz, 10 kHz, 100 kHz, 200 kHz, 500 kHz, 1 MHz, etc.; and the term "rapid rise time" can include times less than approximately 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, 1,000 kV, etc. Rise time of 0 ns, etc.; the term "fast fall time" can include fall times of less than approximately 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, 1,000 ns, etc.; the term "low capacitance" can include capacitance of less than approximately 1.0 pF, 10 pF, 100 pF, 1,000 pF, etc.; the term "low inductance" can include inductance of less than approximately 10 nH, 100 nH, 1,000 nH, 10,000 nH, etc.; and the term "short pulse width" can include pulse widths of less than approximately 10,000 ns, 1,000 ns, 500 ns, 250 ns, 100 ns, 20 ns, etc.

[0051] Figure 1 This is a circuit diagram of a high-voltage pulse generation circuit 100 according to some embodiments. The high-voltage pulse generation circuit 100 can be summarized into six stages (these stages may be broken down into other stages or summarized into fewer stages, and may include or exclude the components shown in the figure). The high-voltage pulse generation circuit 100 includes a pulse generator stage 101, a resistive output stage 102, a lead stage 103, a DC bias circuit 104, a second lead stage 105, and a plasma load 106. The pulse generator stage 101, the resistive output stage 102, and / or the DC bias circuit 104 may include the high-voltage pulse generation circuit. The lead stage 103 or the second lead stage 105 may also be included in the high-voltage pulse generation circuit. The plasma load 106 may include a plasma load within a processing chamber.

[0052] In some embodiments, a processing chamber that may be included in the plasma load 106 may include: a processing chamber body including a processing chamber cover; one or more sidewalls; and a processing chamber base defining a processing volume. A gas inlet is deployed through the processing chamber cover to supply one or more processing gases to the processing volume from a processing gas source in fluid communication therewith. In some embodiments, a plasma generator may be configured to ignite and sustain a processing plasma from the processing gas, including one or more inductors or antennas deployed near the processing chamber cover outside the processing volume. For example, one or more inductors may be electrically coupled to an RF power source, for example, via an RF matching circuit. The plasma generator is used to ignite and sustain the processing plasma using the processing gas and an electromagnetic field generated by the inductors and the RF power source. The processing volume may be fluidly coupled to one or more dedicated vacuum pumps via a vacuum outlet, which may maintain the processing volume under sub-atmospheric pressure conditions and evacuate it from processing and / or other gases. For example, a substrate support assembly deployed in the processing volume may be deployed on a support shaft, for example, extending through the processing chamber base.

[0053] In some embodiments, the substrate can be loaded into and removed from the processing volume through an opening in one or more sidewalls sealed with a door or valve during plasma treatment of the substrate. In some embodiments, a lift pin system can be used to transfer the substrate to and from the receiving surface of the ESC substrate support.

[0054] In some embodiments, the substrate support assembly may include a support base and / or an ESC substrate support member, which may be thermally coupled to and deployed on the support base. In some embodiments, the support base may be used to regulate the temperature of the ESC substrate support member and the substrate deployed on the ESC substrate support member during substrate processing. In some embodiments, the support base includes one or more cooling channels deployed therein, which are fluidly coupled to and in fluid communication with a coolant source (e.g., a refrigerant source with relatively high resistance or a water source). In some embodiments, the ESC substrate support member includes a heater (e.g., a resistive element embedded in its dielectric material). In some embodiments, the support base may be formed of a corrosion-resistant thermally conductive material (e.g., a corrosion-resistant metal (e.g., aluminum, aluminum alloy, or stainless steel)) and coupled to the substrate support member by adhesive or mechanical means. In some embodiments, the ESC substrate support is formed of a dielectric material (e.g., a bulk sintered ceramic material (e.g., a corrosion-resistant metal oxide or metal nitride material (e.g., alumina (Al2O3), aluminum nitride (AlN), titanium oxide (TiO), titanium nitride (TiN), yttrium oxide (Y2O3), mixtures thereof, or combinations thereof))). In some embodiments, the ESC substrate support also includes a bias electrode embedded in its dielectric material. In some embodiments, the bias electrode may include a clip electrode that can be used to secure (or clip) the substrate to a support surface of the ESC substrate support and / or bias the substrate relative to the processed plasma using the pulsed voltage biasing scheme described herein. For example, the bias electrode may be formed of one or more conductive portions (e.g., one or more metal meshes, foils, plates, or combinations thereof). In some embodiments, the bias electrode may be electrically coupled to the HVM, which provides it with a clip voltage (e.g., a static DC voltage between approximately -5000V and approximately 5000V) using an electrical conductor (e.g., a coaxial transmission line (e.g., a coaxial cable)).

[0055] In some embodiments, the bias electrode may be spaced apart from the substrate receiving surface of the ESC substrate support by a dielectric material layer of the ESC substrate support, and thus spaced apart from the substrate. In this configuration, the parallel plate-like structure is formed by the bias electrode and a dielectric material layer that may have an effective capacitance between about 5 nF and about 50 nF. Typically, the dielectric material layer has a thickness between about 0.1 mm and about 1 mm (e.g., between about 0.1 mm and about 0.5 mm (e.g., about 0.3 mm)). In some embodiments, the bias electrode may be electrically coupled to the pulse generator stage 101 using an external conductor, such as a transmission line. In some embodiments, for example, the dielectric material and layer thickness may be selected such that the capacitance Ce of the dielectric material layer is between about 5 nF and about 50 nF (e.g., between about 7 and about 10 nF).

[0056] In some embodiments, a high-voltage pulse generating circuit can establish a pulsed voltage waveform across a load that may include a bias electrode. The high-voltage pulse generating circuit may include a nanosecond pulse generator, a bias compensation circuit, a resistive output stage, and / or an energy recovery circuit. By repeatedly closing and opening its internal switches at a predetermined rate, the nanosecond pulse generator can maintain a predetermined, substantially constant positive voltage across its output (i.e., ground) during periodic repetition time intervals of predetermined length.

[0057] The transmission line can electrically connect the output of the high-voltage pulse generating circuit to the clamp electrode (e.g., the bias electrode). The output of the high-voltage pulse generating circuit can be the location where the plasma load 106 begins. The electrical conductors of the transmission line that can be connected to the bias electrode and / or the bias electrode of the coupling assembly can include: (a) a coaxial transmission line, which may include a flexible coaxial cable with inductance Lflex connected in series with a rigid coaxial transmission line with inductance Lrigid; (b) insulated high-voltage corona-resistant connecting leads; (c) bare wire; (d) a metal rod; (e) an electrical connector; or (f) any combination of the electrical elements in (a)-(e). Note that the internal electrical conductors may include the same bias element as the external electrical conductors.

[0058] In some embodiments, the bias electrode may be a metal plate embedded in an electrostatic clip and separated from the plasma by a thin dielectric material layer. In some embodiments, the clip electrode may be a bias electrode embedded within an electrostatic clip portion (e.g., an ESC substrate support). The external conductor (e.g., a transmission line) and the bias electrode have some combined stray capacitance to ground Cs.

[0059] In some embodiments, the high-voltage pulse generation circuit 100 (or pulse generator stage 101) can introduce pulses into the load stage, wherein the voltage is greater than 1kV, 10kV, 20kV, 50kV, 100kV, 1,000kV, etc., wherein the rise time is less than approximately 1ns, 10ns, 50ns, 100ns, 250ns, 500ns, 1,000ns, etc., wherein the fall time is less than approximately 1ns, 10ns, 50ns, 100ns, 250ns, 500ns, 1,000ns, etc., and the frequency is greater than approximately 1kHz, 10kHz, 100kHz, 200kHz, 500kHz, 1MHz, etc.

[0060] In some embodiments, for example, pulse generator stage 101 may include any device capable of generating pulses greater than 500V, peak currents greater than 10 amperes, or pulse widths less than approximately 10,000 ns, 1,000 ns, 100 ns, 10 ns, etc. As another example, pulse generator stage 101 may generate pulses with amplitudes greater than 1 kV, 5 kV, 10 kV, 50 kV, 200 kV, etc. As another example, pulse generator stage 101 may generate pulses with rise or fall times less than approximately 5 ns, 50 ns, or 300 ns, etc.

[0061] In some embodiments, the pulse generator stage 101 may generate multiple high-voltage bursts. For example, each burst may include multiple high-voltage pulses having fast rise and fast fall times. For example, the multiple high-voltage pulses may have a pulse repetition frequency of approximately 10 Hz to 10 kHz. More specifically, for example, the multiple high-voltage bursts may have burst repetition frequencies of approximately 10 Hz, 100 Hz, 250 Hz, 500 Hz, 1 kHz, 2.5 kHz, 5.0 kHz, 10 kHz, etc.

[0062] Within each of the multiple high-voltage bursts, the high-voltage pulse can have a pulse repetition frequency of approximately 1 kHz, 10 kHz, 100 kHz, 200 kHz, 500 kHz, 1 MHz, etc.

[0063] In some embodiments, the burst repetition frequency time is from one burst until the next burst. This is the frequency at which the bias compensation switch operates.

[0064] In some embodiments, the pulse generator stage 101 may include one or more solid-state switches S1 coupled to the voltage source V2 (e.g., solid-state switches such as IGBTs, MOSFETs, SiC MOSFETs, SiC junction transistors, FETs, SiC switches, GaN switches, photoconductive switches, etc.). In some embodiments, the pulse generator stage 101 may include one or more source buffer resistors R3, one or more source buffer diodes D4, one or more source buffer capacitors C5, or one or more source freewheeling diodes D2. One or more switches and / or circuits may be arranged in parallel or in series.

[0065] In some embodiments, pulse generator stage 101 may generate multiple high-voltage pulses having high frequency, fast rise time, fast fall time, and being at a high frequency. Pulse generator stage 101 may include one or more nanosecond pulse generators.

[0066] In some embodiments, the pulse generator stage 101 may include a high-voltage pulse generating power supply.

[0067] For example, pulse generator stage 101 may include any pulse generator described in U.S. Patent Application Serial No. 14 / 542,487 entitled “High Voltage Nanosecond Pulser,” which is incorporated herein in its entirety for all purposes. For example, pulse generator stage 101 may include any pulse generator described in U.S. Patent No. 9,601,283 entitled “Efficient IGBT Switching,” which is incorporated herein in its entirety for all purposes. For example, pulse generator stage 101 may include any pulse generator described in U.S. Patent Application Serial No. 15 / 365,094 entitled “High Voltage Transformer,” which is incorporated herein in its entirety for all purposes.

[0068] For example, pulse generator stage 101 may include a high-voltage switch (e.g., see [link]). Figure 3 For example, pulse generator stage 101 may include... Figure 15 The high-voltage switch 1500 described herein. As another example, for instance, the pulse generator stage 101 may include any switch described in U.S. Patent Application Serial No. 16 / 178,565, filed November 1, 2018, entitled “High Voltage Switch with Isolated Power,” which is incorporated herein in its entirety for all purposes.

[0069] In some embodiments, pulse generator stage 101 may include transformer T2. Transformer T2 may include a transformer core (e.g., a toroidal or non-toroidal core); at least one primary winding wound around the transformer core once or less; and a secondary winding wound around the transformer core multiple times.

[0070] In some embodiments, transformer T2 may include a single-turn primary winding and a multi-turn secondary winding surrounding the transformer core. For example, a single-turn primary winding may include one or more wires wound around the transformer core one or fewer times. For example, a single-turn primary winding may include more than 2, 10, 20, 50, 100, 250, 1200, etc., individual single-turn primary windings. In some embodiments, the primary winding may include conductive sheets.

[0071] For example, a multi-turn secondary winding may include a single conductor wound multiple times around the transformer core. For example, a multi-turn secondary winding may be wound around the transformer core more than 2 times, 10 times, 25 times, 50 times, 100 times, 250 times, 500 times, etc. In some embodiments, multiple multi-turn secondary windings may be wound around the transformer core. In some embodiments, the secondary winding may include conductive sheets.

[0072] In some embodiments, a high-voltage transformer can be used to output a voltage greater than 1,000 volts with a fast rise time of less than 150 nanoseconds, less than 50 nanoseconds, or less than 5 ns.

[0073] In some embodiments, the high-voltage transformer may have low impedance and / or low capacitance. For example, the high-voltage transformer has stray inductances of less than 100nH, 50nH, 30nH, 20nH, 10nH, 2nH, or 100pH measured on the primary side, and / or the transformer has stray capacitances of less than 100pF, 30pF, 10pF, or 1pF measured on the secondary side.

[0074] Transformer T2 may include the transformer disclosed in U.S. Patent Application No. 15 / 365,094 entitled “High Voltage Transformer,” which is incorporated herein for all purposes.

[0075] In some embodiments, multiple pulse generators may be combined in parallel or in series, or both. In some embodiments, pulse generator stage 101 may be coupled to resistive output stage 102 across inductor L1 and / or resistor R1. In some embodiments, inductor L1 may include an inductance of approximately 5 μH to approximately 25 μH. In some embodiments, resistor R1 may include a resistance of approximately 50 ohms to approximately 250 ohms. Each of the multiple pulse generator stages 101 may also include one or both of choke diode D4 or diode D6. In some embodiments, capacitor C4 may represent the stray capacitance of diode D6.

[0076] In some embodiments, the resistive output stage 102 can discharge a capacitive load (e.g., a wafer and / or plasma).

[0077] In some embodiments, the resistor output stage 102 may include one or more inductive elements represented by inductor L1 and / or inductor L5. For example, inductor L5 may represent the stray inductance of the leads in the resistor output stage 102 and may have an inductance less than approximately 500nH, 250nH, 100nH, 50nH, 25nH, 10nH, etc. For example, inductor L1 may be configured to minimize the power flowing from the pulse generator stage 101 into resistor R1.

[0078] In some embodiments, the resistive output stage 102 may include at least one resistor R1, which may include, for example, multiple resistors connected in series or in parallel, which can discharge a load (e.g., a plasma sheath capacitor).

[0079] In some embodiments, resistor R1 can dissipate the charge from plasma load 106 on a fast time scale (e.g., 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, 1,000 ns, etc.). The resistance of resistor R1 can be low to ensure that pulses across plasma load 106 have a fast fall time tf.

[0080] In some embodiments, the resistive output stage 102 may be configured to discharge an average power of more than about 1 kilowatt during each pulse cycle, and / or discharge one joule or less of energy during each pulse cycle. In some embodiments, the resistance of resistor R1 in the resistive output stage may be less than 200 ohms.

[0081] Capacitor C11 can represent the stray capacitance of resistor R1 (or multiple resistors arranged in series or parallel by resistor R1), including the capacitance of the arrangement of resistors in series and / or parallel. For example, the capacitance of stray capacitance C11 can be less than 500pF, 250pF, 100pF, 50pF, 10pF, 1pF, etc. For example, the capacitance of stray capacitance C11 can be less than the load capacitance (e.g., less than the total capacitance of C2, C3 and / or C9 or the individual capacitance of C2, C3 or C9).

[0082] In some embodiments, the resistor output stage 102 may include a collection of circuit elements that can be used to control the shape of a voltage waveform across a load. In some embodiments, the resistor output stage 102 may include only passive elements (e.g., resistors, capacitors, inductors, etc.). In some embodiments, the resistor output stage 102 may include active circuit elements (e.g., switches) as well as passive circuit elements. In some embodiments, for example, the resistor output stage 102 may be used to control the voltage rise time and / or voltage fall time of a waveform.

[0083] In some embodiments, the resistor output stage 102 can be used in a circuit with pulses having one or both of a high pulse voltage (e.g., a voltage greater than 1kV, 10kV, 20kV, 50kV, 100kV, etc.) or a high frequency (e.g., a frequency greater than 1kHz, 10kHz, 100kHz, 200kHz, 500kHz, 1MHz, etc.).

[0084] In some embodiments, the resistive output stage 102 can be selected to handle high average power, high peak power, fast rise time, and fast fall time. For example, the average rated power can be greater than about 0.5kW, 1.0kW, 10kW, 25kW, etc., or the peak rated power can be greater than about 1kW, 10kW, 100kW, 1MW, etc.

[0085] In some embodiments, the resistor output stage 102 may include a series or parallel network of passive components. For example, the resistor output stage 102 may include a series connection of a resistor, a capacitor, and an inductor. As another example, the resistor output stage 102 may include a capacitor connected in parallel with an inductor and a capacitor-inductor combination connected in series with a resistor.

[0086] In some embodiments, for example, the choke diode D1 can ensure that current flows through the resistor R1. For example, the capacitor C8 can represent the stray capacitance of the choke diode D1.

[0087] In some embodiments, the resistive output stage 102 may be replaced by an energy recovery circuit or any other sink stage or any other circuit that can rapidly sink charge from the plasma on a fast time scale.

[0088] In an embodiment, lead stage 103 may represent one or both of the leads or traces between resistive output stage 102 and DC bias circuit 104. Inductor L2 or inductor L6 may represent inductance for one or both of the leads or traces.

[0089] In this example, the DC bias circuit 104 does not include any bias compensation. The DC bias circuit 104 includes an offset supply voltage V1, which can bias the output voltage, for example, in a positive or negative manner. In some embodiments, the offset supply voltage V1 can be adjusted to change the offset between the wafer voltage and the clip voltage. In some embodiments, the offset supply voltage V1 can have a voltage of approximately ±5kV, ±4kV, ±3kV, ±2kV, ±1kV, etc.

[0090] In some embodiments, bias capacitor C12 can isolate (or separate) the DC bias voltage from one or both of the resistive output stage or other circuit elements. For example, bias capacitor C12 can allow potential transfer from one part of the circuit to another. In some embodiments, this potential transfer can ensure that the electrostatic force holding the wafer in place on the clip remains below a voltage threshold. Resistor R2 can isolate the DC bias power supply from the high-voltage pulsed output from pulse generator stage 101.

[0091] For example, the bias capacitor C12 is 100pF, 10pF, 1pF, 100μF, 10μF, 1μF, etc. For example, the resistor R2 can have a high resistance (e.g., such as about 1k ohm, 10k ohm, 100k ohm, 1M ohm, 10M ohm, 100M ohm, etc.).

[0092] The second lead stage 105 represents the circuit elements between the high-voltage pulse generating circuit and the plasma load 106. For example, resistor R13 can represent the resistance of the lead or transmission line connecting the output of the high-voltage pulse generating circuit to the electrode (e.g., plasma load 106). For example, capacitor C1 can represent the stray capacitance in the lead or transmission line.

[0093] In some embodiments, plasma load 106 may represent an idealized or effective circuit for a semiconductor processing chamber (e.g., a plasma deposition system, a semiconductor manufacturing system, a plasma sputtering system, etc.). For example, capacitor C2 may represent the capacitance of a clip on which the wafer can be mounted. For example, the clip may include a dielectric material. For example, capacitor C1 may have a small capacitance (e.g., approximately 10 pF, 100 pF, 500 pF, 1 nF, 10 nF, 100 nF, etc.).

[0094] For example, capacitor C3 can represent the sheath capacitance between the plasma and the wafer. For example, resistor R6 can represent the sheath resistance between the plasma and the wafer. For example, capacitor L7 can represent the sheath capacitance between the plasma and the wafer. For example, current source I2 can represent the ion current passing through the sheath. For example, capacitor C1 or capacitor C3 can have small capacitances (e.g., approximately 10pF, 100pF, 500pF, 1nF, 10nF, 100nF, etc.).

[0095] For example, capacitor C9 can represent the capacitance within the plasma between the processing chamber wall and the top surface of the wafer. For example, resistor R7 can represent the resistance within the plasma between the processing chamber wall and the top surface of the wafer. For example, current source I1 can represent the ion current in the plasma. For example, capacitor C1 or capacitor C9 can have small capacitances (e.g., approximately 10pF, 100pF, 500pF, 1nF, 10nF, 100nF, etc.).

[0096] As used herein, plasma voltage is the voltage measured from ground to circuit point 123; wafer voltage is the voltage measured from ground to circuit point 122 and may represent the voltage at the surface of the wafer; clip voltage is the voltage measured from ground to circuit point 121; electrode voltage is the voltage measured from ground to circuit point 124; and input voltage is the voltage measured from ground to circuit point 125.

[0097] Figure 2Example waveforms generated by the high-voltage pulse generation circuit 100 are shown. In these example waveforms, pulse waveform 205 may represent the voltage supplied to plasma load 106. As shown, pulse waveform 205, representing the voltage at circuit point 124, generates a pulse with the following qualities: a high voltage (e.g., greater than approximately 4 kV as shown in the waveform), a fast rise time (e.g., less than approximately 200 ns as shown in the waveform), a fast fall time (e.g., less than approximately 200 ns as shown in the waveform), and a short pulse width (e.g., less than approximately 300 ns as shown in the waveform). Waveform 210 may represent the voltage at circuit point 122 (e.g., at the surface of the wafer). Waveform 215 represents the current flowing through the plasma (e.g., the current flowing through inductor L7).

[0098] During the transition state (e.g., during the initial number of pulses not shown in the figure), high-voltage pulses from pulse generator stage 101 charge capacitor C2. Because the capacitance of capacitor C2 is larger than that of one or both of capacitors C3 and C1, or because of the short pulse width, capacitor C2 can receive multiple pulses from the high-voltage pulse generator to be fully charged. Once capacitor C2 is fully charged, the circuit reaches a steady state, as... Figure 2 The waveform is shown in the image.

[0099] In a steady state, and when switch S1 is open, capacitor C2 is charged and slowly dissipates through resistor output stage 102, as shown by the slightly rising slope of waveform 210. Once capacitor C2 is charged, and simultaneously with switch S1 being open, the voltage at the wafer surface (the point between capacitors C2 and C3) is negative. This negative voltage can be the negative value of the voltage of the pulse provided by pulse generator stage 101. Figure 2 The example waveform shown has a voltage of approximately 4 kV per pulse; and the steady-state voltage at the wafer is approximately -4 kV. This results in a negative potential across the plasma (e.g., across capacitor C3), which accelerates positive ions from the plasma to the wafer surface. Simultaneously with switch S1 being turned on, the charge on capacitor C2 is slowly dissipated through the resistive output stage.

[0100] When switch S1 changes from open to closed, as capacitor C2 is charged, the voltage across capacitor C2 can flip (the pulse from the pulse generator is high, as shown in waveform 205). Furthermore, as capacitor C2 charges, the voltage at circuit point 123 (e.g., at the surface of the wafer) changes to approximately zero, as shown in waveform 210. Therefore, the pulse from the high-voltage pulse generator can generate a plasma potential (e.g., the potential in the plasma) that rises from a negative high voltage to zero and returns to a negative high voltage at a high frequency, having any or all of a fast rise time, a fast fall time, or a short pulse width.

[0101] In some embodiments, the operation of the resistive output stage, represented by resistive output stage 102, can rapidly discharge stray capacitance C1 and allow the voltage at the point between capacitors C2 and C3 to quickly return to its stable negative value of approximately -4kV, as shown in waveform 210. The resistive output stage can allow the voltage at the point between capacitors C2 and C3 to exist for approximately % of the time, and thus maximize the time for ions to accelerate into the wafer. In some embodiments, the components included within the resistive output stage can be specifically selected to optimize the duration of ion acceleration into the wafer and to keep the voltage approximately constant during that time. Thus, for example, short pulses with fast rise and fast fall times can be useful, allowing for a long period of fairly uniform negative potential.

[0102] In some embodiments, a bias compensation subsystem may be used to adjust the clip voltage in the semiconductor processing chamber. For example, the clip voltage may be applied to the clip to track the trajectory of bursts of on / off modes to ensure a constant voltage on the clip.

[0103] In some embodiments, any various high-voltage pulse generating circuits may include the resistive output stage disclosed in this document, and may include any or all components, arrangements, functions, etc. shown or described in U.S. Patent Application Serial No. 15 / 941,731 entitled “High Voltage Resistive Output Stage Circuit” filed March 30, 2018, which is incorporated herein in its entirety for all purposes.

[0104] Figure 3 This is a circuit diagram of a high-voltage pulse generating circuit 300 according to some embodiments. The high-voltage pulse generating circuit 300 is similar to the high-voltage pulse generating circuit 100. In this example, the pulse generator stage 110 includes a high-voltage switch S1. In some embodiments, the high-voltage switch S1 may include a plurality of switches arranged in series to jointly open and close a high voltage. For example, the high-voltage switch S1 may include... Figure 15 The high-voltage switch 1500 described herein. As another example, for instance, the high-voltage switch S4 may include any switch described in U.S. Patent Application Serial No. 16 / 178,565, filed November 1, 2018, entitled “High Voltage Switch with Isolated Power,” which is fully incorporated herein for all purposes.

[0105] In any embodiment, pulse generator stage 101 or pulse generator stage 110 can be used to generate high-voltage pulses. Furthermore, pulse generator stage 101 and pulse generator stage 110 can be interchanged.

[0106] In this example, the DC bias circuit 104 does not include any bias compensation.

[0107] In some embodiments, the pulse generator stage 101 can generate pulses having the following properties: voltages greater than 1kV, 10kV, 20kV, 50kV, 100kV, 1,000kV, etc.; rise times less than approximately 1ns, 10ns, 50ns, 100ns, 250ns, 500ns, 1,000ns, etc.; fall times less than approximately 1ns, 10ns, 50ns, 100ns, 250ns, 500ns, 1,000ns, etc.; and frequencies greater than approximately 1kHz, 10kHz, 100kHz, 200kHz, 500kHz, 1MHz, etc.

[0108] In some embodiments, the pulse generator stage 101 includes an radio frequency power supply (e.g., an RF generator).

[0109] Figure 4 Example waveforms generated by a high-voltage pulse generating circuit (e.g., high-voltage pulse generating circuit 100 or high-voltage pulse generating circuit 300) are shown. Wafer waveform 405 represents the voltage on the wafer, and clip waveform 410 is the voltage on the clip. Figure 3 The wafer waveform 405 was measured at the location marked 122 on the circuit diagram. Figure 3 The clamp waveform 410 is measured at location 121 on the circuit diagram. As shown, during pulse generation, the difference between the clamp waveform 410 and the wafer waveform 405 is approximately 4 kV. At peak voltages exceeding 2 kV, this could potentially damage the wafer on the clamp within the processing chamber.

[0110] Figure 4 The waveform in the image shows six bursts of approximately 10 seconds, each containing multiple pulses.

[0111] Figure 5 This is a circuit diagram of a high-voltage pulse generating circuit 500 according to some embodiments. The high-voltage pulse generating circuit 500 is similar to the high-voltage pulse generating circuit 300. The pulse generator stage 110, the resistor output stage 102, and / or the DC bias circuit 104 may include the high-voltage pulse generating circuit. A lead stage 103 or a second lead stage 105 may also be included in the high-voltage pulse generating circuit. The plasma load 106 may include a plasma load within the processing chamber.

[0112] In this example, the bias compensation circuit 114 is a passive bias compensation circuit and may include a bias compensation diode 505 and a bias compensation capacitor 510. The bias compensation diode 505 may be arranged in series with the offset supply voltage V1. The bias compensation capacitor 510 may be arranged across one or both of the offset supply voltage V1 and the resistor R2. The bias compensation capacitor 510 may have a capacitance of less than 100nF to 100μF (e.g., approximately 100μF, 50μF, 25μF, 10μF, 2μF, 500nF, 200nF, etc.).

[0113] In some embodiments, the bias compensation diode 505 can conduct a current between 10A and 1kA at a frequency between 10Hz and 10kHz.

[0114] In some embodiments, the bias capacitor C12 may allow a voltage offset between the output of the pulse generator stage 101 (e.g., at the location marked 125) and the voltage on the electrode (e.g., at the location marked 124). In operation, for example, the electrode may be at a DC voltage of -2kV during a burst, while the output of the nanosecond pulse generator alternates between +6kV during the pulse and 0kV between pulses.

[0115] For example, the bias capacitor C12 can have a capacitance of less than approximately 100nF, 10nF, 1nF, 100μF, 10μF, 1μF, etc. For example, the resistor R2 can have a high resistance (e.g., such as approximately 1k ohm, 10k ohm, 100k ohm, 1M ohm, 10M ohm, 100M ohm, etc.).

[0116] In some embodiments, the bias compensation capacitor 510 and the bias compensation diode 505 can allow a voltage offset between the output of the pulse generator stage 101 and the voltage on the electrode (e.g., at the location marked 125) established at the beginning of each burst, achieving the desired equilibrium state. For example, during a series of high-voltage pulses (e.g., approximately 5-100), at the beginning of each burst, charge is transferred from capacitor C12 to the bias compensation capacitor 510, establishing the correct voltage in the circuit.

[0117] In some embodiments, the output may result in voltage overshoot or voltage drop unless corrected. For example, a voltage overshoot may occur at the beginning of a burst when the voltage at position 121 and the voltage at position 124 rise above the desired value (e.g., 2 kV). A voltage drop may occur throughout the burst (e.g., approximately 5 ms) as the voltage at position 124 shifts downwards through the burst (e.g., the peak-to-peak voltage remains unchanged). A voltage drop can reduce the voltage at position 121 from the desired value by up to 1.5 kV. Ideally, the voltage at position 124 should be flat (i.e., voltage overshoot or voltage drop should be minimized or eliminated).

[0118] In some embodiments, the voltage at position 124 should not exceed the voltage at position 121, as it is substantially clamped at the diode by the bias compensation capacitor 510. At the start of each burst, the pulse generator stage 110 can drive almost all of its output current through diode 505 and bias compensation capacitor 510 to change the voltage on bias capacitor C12. However, if there is significant stray inductance in this path (e.g., the sum of L22, L23, and L24), this inductance may reduce the voltage and prevent current flow. This could allow the voltage at position 124 to rise (voltage overshoot at position 124) or cause current to flow instead to position 121 and the plasma load to charge the clip (voltage overshoot at position 121).

[0119] In some embodiments, voltage drop or overshoot can be addressed by limiting the sum of stray inductances (e.g., inductors L22, L23, and L24 as described below). In some embodiments, the sum of stray inductances L22, L23, and L24 can be as low as 50 nH. For example, this inductance can help keep overshoot below 400 V.

[0120] In some embodiments, diode 505 and bias compensation capacitor 510 may be arranged in a stripline such that current flows in a U-shaped path. For example, the stripline may be a transmission line trace surrounded by dielectric material between two ground planes suspended on an inner layer of the PCB. In some embodiments, the separation between diode 505 and bias compensation capacitor 510 may be maximized. In some embodiments, the stripline of diode 505 and bias compensation capacitor 510 may be as wide as possible (e.g., 10, 8, 6, 4, 3, 2, 1, 1 / 2 inches).

[0121] In some embodiments, the lead inductance L22 can be minimized or eliminated by connecting point 124 to the input of diode 505 (e.g., at stray inductance L22).

[0122] In some embodiments, the lead inductance L24 can be minimized or eliminated by directly connecting the low side of the bias compensation capacitor 510 to ground (e.g., at stray inductance L24).

[0123] In this example, the bias compensation circuit 114 includes a stray inductance L22 between diode 505 and the location marked 124, a stray inductance L23 between diode 505 and bias compensation capacitor 510, or a stray inductance L24 between bias compensation capacitor 510 and ground. Circuit 500 includes a plasma-side inductance L... p and switch-side inductor L s For example, the plasma-side stray inductance L p This can include all inductors, regardless of stray, parasitic, or originating from any element between the bias compensation circuit 114 and the plasma load 106 (e.g., such as L7) and any other stray inductors on that side of the circuit. For example, the switch-side inductor Ls can include all inductors, regardless of stray, parasitic, or originating from any element between the bias compensation circuit 114 and the switch S1 (e.g., such as, individually or in combination, inductors 1915, L1, 1940, L2, and / or L6) and any other stray inductors on that side of the circuit.

[0124] In some embodiments, the switch-side inductance Ls should be greater than the plasma-side stray inductance Lp. In some embodiments, the plasma-side stray inductance Lp is 20% of the switch-side inductance Ls. In some embodiments, the plasma-side stray inductance Lp is less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc.

[0125] In some embodiments, stray inductance L22 has an inductance less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc. In some embodiments, stray inductance L23 has an inductance less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc. In some embodiments, stray inductance L24 has an inductance less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc. In some embodiments, the sum of stray inductances L22, L23, and L24 is less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc.

[0126] In some embodiments, stray inductances L22, L23, or L24 can be minimized in various ways. For example, the conductors along stray inductances L22, L23, or L24 can be wider than industry standards (e.g., greater than 1 / 8, 1 / 4, 3 / 8, 1 / 2, 1, 2.5, 5 inches, etc.). As another example, various circuit elements (e.g., diode 505 or bias compensation capacitor 510) can include multiple diodes or capacitors connected in parallel or series.

[0127] In some embodiments, the distance between components can be minimized to reduce stray inductance. For example, the top and bottom conductors of individual bias component circuit elements can be separated by less than approximately 1, 2, 5, 15, 20, 25, 30, 35, or 40 centimeters. As another example, a discrete component including diode 505 can be deployed within 10, 8, 6, 4, 3, 2, 1, or 1 / 2 inches from the location marked 124 or ground. As another example, a discrete component including bias compensation capacitor 510 can be deployed within 10, 8, 6, 4, 3, 2, 1, or 1 / 2 inches from the location marked 124 or ground.

[0128] In embodiments, the volume of a discrete element including one or both of a diode 505 and / or a bias compensation capacitor 510 may be less than 1200, 1000, 750, or 500 cubic centimeters.

[0129] In some embodiments, a resistor 515 may be included across diode 505. In some embodiments, resistor 515 may have a resistance value of less than about 1 kΩ to 1 MΩ (e.g., less than about 100 kΩ).

[0130] In some embodiments, the bias compensation capacitor 510 may have a capacitance of less than about 1 μF or less than about 1 mF. The bias compensation capacitor 510 may have a stray inductance of less than about 1 nH, 10 nH, 100 nH, 1 μH, etc.

[0131] Figure 6 An example waveform generated by the high-voltage pulse generation circuit 500 is shown. As shown, the voltage bias between the wafer waveform 605 and the clip waveform 610 remains constant during the pulse burst but remains charged after the burst. In this example, the difference between the wafer waveform 605 and the clip waveform 610 during pulse generation is less than approximately 2 kV, which is within acceptable tolerance. However, in this example, the difference between the wafer waveform 605 and the clip waveform 610 between pulses is greater than approximately 7 kV, which may not be within acceptable tolerance.

[0132] Figure 6 The waveform in the image shows six bursts of approximately 10 seconds, each containing multiple pulses.

[0133] Figure 7 This is a circuit diagram of a high-voltage pulse generating circuit 700 according to some embodiments. The high-voltage pulse generating circuit 700 is similar to the high-voltage pulse generating circuit 500 and includes a second pulse generator circuit 705. The pulse generator stage 110, the resistor output stage 102, the second pulse generator 701, the second pulse generator circuit 705, or the DC bias circuit 104 may include the high-voltage pulse generating circuit.

[0134] The second pulse generator circuit 705 may include a bias compensation circuit 114 or components similar to the bias compensation circuit 114.

[0135] The second pulse generator circuit 705 may include a second pulse generator 701. For example, the second pulse generator 701 may include... Figure 1 or Figure 3 The pulse generator stage 110 shown may include one or more or all of its components. For example, the pulse generator stage 110 may include components as described in this document (e.g., Figure 15 The nanosecond pulse generator or high-voltage switch disclosed in the relevant paragraphs. In some embodiments, the second pulse generator 701 may be configured to turn off when the pulse generator stage 101 is generating a pulse (e.g., during a burst), and the second pulse generator 701 may be configured to turn on when the pulse generator stage 101 is not generating a pulse (e.g., between bursts).

[0136] The second pulse generator circuit 705 may also include an inductor L9 on the secondary side of the transformer T2, and the switch 710 may be coupled to a voltage source V6. The inductor L9 may represent the stray inductance of the second pulse generator circuit 705 and may have a low inductance (e.g., less than approximately 500nH, 250nH, 100nH, 50nH, 25nH, etc.). In some embodiments, the voltage source V6 may represent a trigger for the switch 710.

[0137] In some embodiments, the second pulse generator circuit 705 may include a choke diode D7. For example, the choke diode D7 may ensure that current flows from the switch 710 to the plasma load 106. For example, a capacitor C14 may represent the stray capacitance of the choke diode D7. For example, the capacitance of the capacitor C14 may have a low capacitance (e.g., less than about 1 nF, 500 pF, 200 pF, 100 pF, 50 pF, 25 pF, etc.).

[0138] In some embodiments, switch 710 can be opened while pulse generator stage 110 is generating a pulse, and closed when pulse generator stage 110 is not generating a pulse, to offset (or bias) the voltage provided by pulse generator stage.

[0139] In some embodiments, switch 710 may include a plurality of switches arranged in series to jointly open and close a high voltage. In some embodiments, switch 710 may include Figure 15The high-voltage switch 1500 described herein. As another example, the high-voltage switch 905 may, for example, include any switch described in U.S. Patent Application Serial No. 16 / 178,565, filed November 1, 2018, entitled “High Voltage Switch with Isolated Power,” which is incorporated herein in its entirety for all purposes.

[0140] In this example, the bias compensation circuit 114 includes a stray inductance L22 between diode 505 and the location marked 124, a stray inductance L23 between diode 505 and bias compensation capacitor 510, or a stray inductance L24 between bias compensation capacitor 510 and ground. The high-voltage pulse generation circuit 700 includes a plasma-side inductance Lp and a switching-side inductance Ls. For example, the plasma-side stray inductance Lp can include all inductors, whether stray, parasitic, or originating from any element between bias compensation circuit 114 and plasma load 106 (e.g., L7) and any other stray inductance on that side of the circuit. For example, the switching-side inductance L... s This may include all inductors, whether stray, parasitic, or from any element between the bias compensation circuit 114 and the switch S1 (e.g., individually or in combination, inductors 1915, L1, 1940, L2, and / or L6) and any other stray inductors on that side of the circuit.

[0141] In some embodiments, the switch-side inductance Ls should be greater than the plasma-side stray inductance Lp. In some embodiments, the plasma-side stray inductance Lp is 20% of the switch-side inductance Ls. In some embodiments, the plasma-side stray inductance Lp is less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc.

[0142] In some embodiments, stray inductance L22 has an inductance less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc. In some embodiments, stray inductance L23 has an inductance less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc. In some embodiments, stray inductance L24 has an inductance less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc. In some embodiments, the sum of stray inductances L22, L23, and L24 is less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc.

[0143] In some embodiments, stray inductances L22, L23, or L24 can be minimized in various ways. For example, the conductors along stray inductances L22, L23, or L24 can be wider than industry standards (e.g., greater than 1 / 8, 1 / 4, 3 / 8, 1 / 2, 1, 2.5, 5 inches, etc.). As another example, various circuit elements (e.g., diode 505 or bias compensation capacitor 510) can include multiple diodes or capacitors connected in parallel or series.

[0144] In some embodiments, the distance between components can be minimized to reduce stray inductance. For example, the top and bottom conductors of various bias compensation circuit elements may be separated by less than approximately 1, 2, 5, 15, 20, 25, 30, 35, or 40 cm. As another example, a discrete component including diode 505 may be deployed within 10, 8, 6, 4, 3, 2, 1, or 1 / 2 inches from the location marked 124 or ground. As another example, a discrete component including bias compensation capacitor 510 may be deployed within 10, 8, 6, 4, 3, 2, 1, or 1 / 2 inches from the location marked 124 or ground.

[0145] In embodiments, the volume of a discrete element including one or both of a diode 505 and / or a bias compensation capacitor 510 may be less than 1200, 1000, 750, or 500 cubic centimeters.

[0146] In some embodiments, the bias compensation capacitor 510 may have a capacitance of less than about 1 μF or less than about 1 mF. The bias compensation capacitor 510 may have a stray inductance of less than about 1 nH, 10 nH, 100 nH, 1 μH, etc.

[0147] Figure 8 Example waveforms generated by the high-voltage pulse generation circuit 700 are shown. Wafer waveform 805 represents the voltage on the card holder, and waveform 810 is the voltage on the card holder. Figure 7 The wafer waveform 805 is measured at the location marked 122 on the circuit diagram. Figure 7 The circuit diagram shows the location 121 on the card holder, where the card holder waveform 810 is measured. Figure 7 The bias waveform 815 is measured at the location marked 124 on the circuit diagram. In this example, the bias compensation capacitor 510 is discharging, and the second pulse generator circuit 705 may require a power supply higher than V2, for example, to repeatedly charge the bias capacitor, which may require several kilowatts of power.

[0148] Figure 8 The waveform in the image shows six bursts of approximately 10 seconds, each containing multiple pulses.

[0149] Figure 9 This is a circuit diagram of a high-voltage pulse generating circuit 900 according to some embodiments. The high-voltage pulse generating circuit 900 is similar to the high-voltage pulse generating circuit 100. The pulse generator stage 110, the resistor output stage 102, and / or the bias compensation circuit 914 may include the high-voltage pulse generating circuit.

[0150] In this embodiment, the bias compensation circuit 914 may include a high-voltage switch 905 coupled across the bias compensation diode 505 and coupled to the power supply V1. In some embodiments, the high-voltage switch 905 may include a plurality of high-voltage switches 905 arranged in series to jointly open and close a high voltage. For example, the high-voltage switch 905 may include Figure 15 The high-voltage switch 1500 is described in the figure. In some embodiments, the high-voltage switch 905 may be coupled to a switch trigger V4.

[0151] The high-voltage switch 905 may be coupled in series with one or both of the bias compensation inductor L4 and the resistor R11. The bias compensation inductor L4 may limit the peak current through the high-voltage switch 905. For example, the bias compensation inductor L4 may have an inductance of less than about 100nH (e.g., about 250nH, 100nH, 50nH, 25nH, 10nH, 5nH, 1nH, etc.). For example, the resistor R11 may dissipate power to the resistive output stage 102. For example, the resistor R11 may have a resistance of less than about 1000 ohms, 500 ohms, 250 ohms, 100 ohms, 50 ohms, 10 ohms, etc. In some embodiments, the bias compensation inductor L4 is deployed in series with the diode D10 and the resistor R11.

[0152] In some embodiments, the high-voltage switch 905 may include a snubber circuit. The snubber circuit may include a resistor R9, a snubber diode D8, a snubber capacitor C15, and a snubber resistor R10.

[0153] In some embodiments, resistor R8 may represent a stray resistance offset from the supply voltage V1. For example, resistor R8 may have a high resistance (e.g., a resistor of approximately 10k ohms, 100k ohms, 1M ohms, 10M ohms, 100M ohms, 1G ohms, etc.).

[0154] In some embodiments, the high-voltage switch 905 may include a plurality of switches arranged in series to jointly open and close a high voltage. For example, the high-voltage switch 905 may include Figure 15The high-voltage switch 1500 described herein. As another example, the high-voltage switch 905 may, for example, include any switch described in U.S. Patent Application Serial No. 16 / 178,565, filed November 1, 2018, entitled “High Voltage Switch with Isolated Power,” which is incorporated herein in its entirety for all purposes.

[0155] In some embodiments, the high-voltage switch 905 can be turned on while the pulse generator stage 110 is generating a pulse, and closed when the pulse generator stage 110 is not generating a pulse. For example, when the high-voltage switch 905 is closed, current can be short-circuited across the bias compensation diode 505. Short-circuiting this current allows the bias between the wafer and the clip to be less than 2kV, which can be within acceptable tolerances.

[0156] In some embodiments, the high-voltage switch 905 can allow the electrode voltage (marked at position 124) and wafer voltage (marked at position 122) to recover rapidly (e.g., less than approximately 100 ns, 200 ns, 500 ns, 1 μs) to the clip potential (marked at position 121). For example, in Figure 10 , Figure 11A and Figure 11B This situation is illustrated in the image.

[0157] In this example, the bias compensation circuit 914 includes a stray inductance L22 between diode 505 and the location marked 124, a stray inductance L23 between diode 505 and bias compensation capacitor 510, or a stray inductance L24 between bias compensation capacitor 510 and ground. The high-voltage pulse generation circuit 900 includes a plasma-side inductance Lp and a switching-side inductance Ls. For example, the plasma-side stray inductance Lp can include all inductors, whether stray, parasitic, or originating from any element between bias compensation circuit 914 and plasma load 106 (e.g., L7) and any other stray inductance on that side of the circuit. For example, the switching-side inductance L... s This may include all inductors, whether stray, parasitic, or from any element between the bias compensation circuit 914 and the switch S1 (e.g., individually or in combination, inductors 1915, L1, 1940, L2, and / or L6) and any other stray inductors on that side of the circuit.

[0158] In some embodiments, the switch-side inductance Ls should be greater than the plasma-side stray inductance Lp. In some embodiments, the plasma-side stray inductance Lp is 20% of the switch-side inductance Ls. In some embodiments, the plasma-side stray inductance Lp is less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc.

[0159] In some embodiments, stray inductance L22 has an inductance less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc. In some embodiments, stray inductance L23 has an inductance less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc. In some embodiments, stray inductance L24 has an inductance less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc. In some embodiments, the sum of stray inductances L22, L23, and L24 is less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc.

[0160] In some embodiments, stray inductances L22, L23, or L24 can be minimized in various ways. For example, the conductors along stray inductances L22, L23, or L24 can be wider than industry standards (e.g., greater than 1 / 8, 1 / 4, 3 / 8, 1 / 2, 1, 2.5, 5 inches, etc.). As another example, various circuit elements (e.g., diode 505 or bias compensation capacitor 510) can include multiple diodes or capacitors connected in parallel or series. In some embodiments, the top and bottom conductors between various bias compensation circuit elements can be separated by less than approximately 1, 2, 5, 15, 20, 25, 30, 35, or 40 cm.

[0161] In some embodiments, the bias compensation capacitor 510 may have a capacitance of less than about 1 μF or less than about 1 mF. The bias compensation capacitor 510 may have a stray inductance of less than about 1 nH, 10 nH, 100 nH, 1 μH, etc.

[0162] For example, the bias compensation inductor L4 may have an inductance of less than approximately 100 nH (e.g., approximately 250 nH, 100 nH, 50 nH, 25 nH, 10 nH, 5 nH, 1 nH, etc.). In embodiments, the volume of the discrete components including one or both of the diode 505 and / or the bias compensation capacitor 510 may be less than 1200, 1000, 750, or 500 cubic centimeters.

[0163] In some embodiments, a resistor 515 may be included across diode 505. In some embodiments, resistor 515 may have a resistance value of less than about 1 kΩ to 1 MΩ (e.g., less than about 100 kΩ).

[0164] In some embodiments, the high-voltage switch 905 and / or diode D8 may have some parasitic (or stray) capacitance. For example, this parasitic capacitance may combine with the bias compensation inductor L4 to produce some ringing. For example, this ringing may produce some voltage drop across the bias compensation capacitor 510. In some embodiments, the voltage drop across the bias compensation capacitor 510 can be minimized or eliminated by keeping the inductance of the bias compensation inductor L4 low. In some embodiments, diode D10 may be used with or in place of the bias compensation inductor L4 to further reduce or minimize any voltage drop across the bias compensation capacitor 510.

[0165] For example, certain values ​​and / or arrangements of the inductance can compensate for or correct for overshoot in capacitor C2 from inductor L5 ringing to capacitor C2, resonant ringing of capacitor C2 or capacitor C1 with inductor L5, or decrease in parasitic capacitance caused by the interaction of L4 with high-voltage switch 905 and / or diode D8.

[0166] Figure 10 Example waveforms generated by a high-voltage pulse generating circuit 900 according to some embodiments are shown. Wafer waveform 1005 represents the voltage on the wafer, clip waveform 1010 represents the voltage on the clip, and bias waveform 1015 represents the voltage from bias compensation circuit 914. Figure 9 The wafer waveform 1005 was measured at the location marked 122 on the circuit diagram. Figure 9 The clamp waveform 1010 is measured at the location marked 121 on the circuit diagram. Figure 9 The bias waveform 1015 is measured at the location marked 124 on the circuit diagram.

[0167] Figure 10 The waveform in the image shows six bursts of approximately 10 seconds, each containing multiple pulses.

[0168] Figure 11A and Figure 11B Example waveforms from a high-voltage pulse generation circuit 900 according to some embodiments are shown. Figure 11A This shows a single burst with 340 pulses, and Figure 11B This shows a few pulses within the burst. Waveform 1105 shows the voltage at the electrode ( Figure 9 The position marked in 124), and waveform 1110 shows the voltage at the wafer ( Figure 9 (The location marked in 122). Note that the voltage on the electrodes and wafer tends to track with a constant offset of approximately 2 kV. The waveform also shows how the voltage returns to DC value while the pulse generator is off, until the next burst begins at some later time.

[0169] Figure 12 This is a circuit diagram of a high-voltage pulse generating circuit 1200 according to some embodiments. The high-voltage pulse generating circuit 1200 is similar to the high-voltage pulse generating circuit 900. The pulse generator stage 110, the resistor output stage 102, and / or the bias compensation circuit 1214 may include the high-voltage pulse generating circuit.

[0170] In some embodiments, the bias compensation circuit 1214 may include four high-voltage switching stages (including switches 1220, 1225, 1230, and 1235) arranged across or in parallel with the bias compensation diode 505. Each switching stage includes a switch (e.g., switches 1220, 1225, 1230, and 1235) and voltage distribution resistors (e.g., resistors R15, R16, R17, and R18). One or both of resistor R11 and bias compensation inductor L4 are arranged in series with the switching stage. For example, the bias compensation inductor L4 may have an inductance of less than approximately 100 nH (e.g., approximately 250 nH, 100 nH, 50 nH, 25 nH, 10 nH, 5 nH, 1 nH, etc.).

[0171] In some embodiments, switches 1220, 1225, 1230, and 1235 can be turned on while pulse generator stage 110 is generating a pulse, and closed when pulse generator stage 110 is not generating a pulse. For example, when switches 1220, 1225, 1230, and 1235 are closed, current can be short-circuited across bias compensation diode 505. Short-circuiting this current allows the bias between the wafer and the clip to be less than 2 kV, which can be within acceptable tolerances.

[0172] Each switch 1220, 1225, 1230, and 1235 may include multiple switches arranged in series to jointly open and close a high voltage. For example, each switch 1220, 1225, 1230, and 1235 may jointly or individually include, for example, multiple switches. Figure 15 The high-voltage switch 1500 described herein. As another example, each of the switches 1220, 1225, 1230 and 1235 may collectively or individually include, for example, any switch described in U.S. Patent Application Serial No. 16 / 178,565, filed November 1, 2018, entitled “High Voltage Switch with Isolated Power,” which is fully incorporated herein for all purposes.

[0173] In some embodiments, the voltage distribution resistors (e.g., resistors R15, R16, R17, and R18) may have high resistance (e.g., such as approximately 1k ohms, 10k ohms, 100k ohms, 1M ohms, 10M ohms, 100M ohms, etc.).

[0174] This example shows four high-voltage switching stages, but any number of high-voltage switching stages can be used.

[0175] In this example, the bias compensation circuit 1214 includes a stray inductance L22 between diode 505 and the location marked 124, a stray inductance L23 between diode 505 and bias compensation capacitor 510, or a stray inductance L24 between bias compensation capacitor 510 and ground. The high-voltage pulse generation circuit 1200 includes a plasma-side inductance L... p and switch-side inductor L s For example, the plasma-side stray inductance L p This can include all inductors, regardless of whether they are stray, parasitic, or originate from any element between the bias compensation circuit 1214 and the plasma load 106 (e.g., such as L7) and any other stray inductors on that side of the circuit. For example, the switch-side inductor Ls can include all inductors, regardless of whether they are stray, parasitic, or originate from any element between the bias compensation circuit 1214 and the switch S1 (e.g., such as inductors L3, 1915, 1940, L2, and L6) and any other stray inductors on that side of the circuit.

[0176] In some embodiments, the switch-side inductance Ls should be greater than the plasma-side stray inductance Lp. In some embodiments, the plasma-side stray inductance Lp is 20% of the switch-side inductance Ls. In some embodiments, the plasma-side stray inductance Lp is less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc.

[0177] In some embodiments, stray inductance L22 has an inductance less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc. In some embodiments, stray inductance L23 has an inductance less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc. In some embodiments, stray inductance L24 has an inductance less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc. In some embodiments, the sum of stray inductances L22, L23, and L24 is less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc.

[0178] In some embodiments, stray inductances L22, L23, or L24 can be minimized in various ways. For example, the conductors along stray inductances L22, L23, or L24 can be wider than industry standards (e.g., greater than 1 / 8, 1 / 4, 3 / 8, 1 / 2, 1, 2.5, 5 inches, etc.). As another example, various circuit elements (e.g., diode 505 or bias compensation capacitor 510) can include multiple diodes or capacitors connected in parallel or series. In some embodiments, the top and bottom conductors between various bias compensation circuit elements can be separated by less than approximately 1, 2, 5, 15, 20, 25, 30, 35, or 40 cm.

[0179] In some embodiments, the bias compensation capacitor 510 may have a capacitance of less than about 1 μF or less than about 1 mF. The bias compensation capacitor 510 may have a stray inductance of less than about 1 nH, 10 nH, 100 nH, 1 μH, etc.

[0180] In some embodiments, for example, the bias compensation inductor L4 may have an inductance of less than about 100 μH (e.g., about 50 μH, 25 μH, 10 μH, 5 μH, 1 μH, 0.5 μH, 0.25 μH, etc.).

[0181] In embodiments, the volume of a discrete element including one or both of a diode 505 and / or a bias compensation capacitor 510 may be less than 1200, 1000, 750, or 500 cubic centimeters.

[0182] In some embodiments, a resistor 515 may be included across diode 505. In some embodiments, resistor 515 may have a resistance value of less than about 1 kΩ to 1 MΩ (e.g., less than about 100 kΩ).

[0183] In some embodiments, switches 1220, 2225, 1230, and 1235 may have some parasitic (or stray) capacitance. For example, this parasitic capacitance may combine with the bias compensation inductor L4 to produce some ringing. For example, this ringing may produce some voltage drop across the bias compensation capacitor 510. In some embodiments, the voltage drop across the bias compensation capacitor 510 can be minimized or eliminated by keeping the inductance of the bias compensation inductor L4 low. In some embodiments, a diode may be used in parallel with or instead of the bias compensation inductor L4 to further reduce or minimize any voltage drop across the bias compensation capacitor 510.

[0184] In some embodiments, pulse generator stage 110 can generate multiple high-voltage bursts, wherein each burst includes multiple high-voltage pulses. Switches 1220, 2225, 1230, and 1235 can be opened during each burst and closed between bursts.

[0185] Figure 13 This is a circuit diagram of a high-voltage pulse generating circuit 1300 according to some embodiments. The high-voltage pulse generating circuit 1300 is similar to the high-voltage pulse generating circuit 1200. The pulse generator stage 110, the resistor output stage 102, and / or the bias compensation circuit 1314 may include the high-voltage pulse generating circuit.

[0186] In this example, bias compensation circuit 1314 is similar to bias compensation circuit 1214. In this example, each switching module (1220, 1225, 1230, and 1235) having bias compensation circuit 1314 may include a corresponding snubber circuit. Each snubber circuit may include a snubber diode and a snubber capacitor. In some embodiments, the snubber diode may include a snubber resistor arranged across the snubber diode. Each switching module may include a resistor that ensures uniform voltage distribution among each of the switches arranged in series.

[0187] In this example, the bias compensation circuit 1314 includes a stray inductance L22 between diode 505 and the location marked 124, a stray inductance L23 between diode 505 and bias compensation capacitor 510, or a stray inductance L24 between bias compensation capacitor 510 and ground. The high-voltage pulse generation circuit 1300 includes a plasma-side inductance Lp and a switching-side inductance Ls. For example, the plasma-side stray inductance Lp can include all inductors, whether stray, parasitic, or originating from any element between the bias compensation circuit 1314 and the plasma load 106 (e.g., L7) and any other stray inductance on that side of the circuit. For example, the switch-side inductor Ls may include all inductors, regardless of stray, parasitic, or any element between the bias compensation circuit 1314 and the switch S1 (e.g., individually or in combination, inductors 1915, L1, 1940, L2, and / or L6) and any other stray inductors on that side of the circuit.

[0188] In some embodiments, the switch-side inductance Ls should be greater than the plasma-side stray inductance Lp. In some embodiments, the plasma-side stray inductance Lp is 20% of the switch-side inductance Ls. In some embodiments, the plasma-side stray inductance Lp is less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc.

[0189] In some embodiments, stray inductance L22 has an inductance less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc. In some embodiments, stray inductance L23 has an inductance less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc. In some embodiments, stray inductance L24 has an inductance less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc. In some embodiments, the sum of stray inductances L22, L23, and L24 is less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc.

[0190] In some embodiments, stray inductances L22, L23, or L24 can be minimized in various ways. For example, the conductors along stray inductances L22, L23, or L24 can be wider than industry standards (e.g., greater than 1 / 8, 1 / 4, 3 / 8, 1 / 2, 1, 2.5, 5 inches, etc.). As another example, various circuit elements (e.g., diode 505 or bias compensation capacitor 510) can include multiple diodes or capacitors connected in parallel or series. In some embodiments, the top and bottom conductors between various bias compensation circuit elements can be separated by less than approximately 1, 2, 5, 15, 20, 25, 30, 35, or 40 cm.

[0191] In some embodiments, the bias compensation capacitor 510 may have a capacitance of less than about 1 μF or less than about 1 mF. The bias compensation capacitor 510 may have a stray inductance of less than about 1 nH, 10 nH, 100 nH, 1 μH, etc.

[0192] In some embodiments, for example, the bias compensation inductor L4 may have an inductance of less than about 100 μH (e.g., about 50 μH, 25 μH, 10 μH, 5 μH, 1 μH, 0.5 μH, 0.25 μH, etc.).

[0193] In embodiments, the volume of a discrete element including one or both of a diode 505 and / or a bias compensation capacitor 510 may be less than 1200, 1000, 750, or 500 cubic centimeters.

[0194] In some embodiments, a resistor 515 may be included across diode 505. In some embodiments, resistor 515 may have a resistance value of less than about 1 kΩ to 1 MΩ (e.g., less than about 100 kΩ).

[0195] In some embodiments, switches 1220, 2225, 1230 and / or 1235 and / or diodes D10, D11, D12 and / or D13 may have some parasitic (or stray) capacitance. For example, this parasitic capacitance, possibly combined with capacitors C15, C16, C17 and / or C18, may combine with bias compensation inductor L4 to produce some ringing. For example, such ringing may produce some voltage drop across bias compensation capacitor 510. In some embodiments, the voltage drop across bias compensation inductor L4 can be minimized or eliminated by keeping the inductance of bias compensation inductor L4 low. In some embodiments, diodes may be used in parallel with or in place of bias compensation inductor L4 to further reduce or minimize any voltage drop across bias compensation capacitor 510.

[0196] In some embodiments, pulse generator stage 110 can generate multiple high-voltage bursts, wherein each burst includes multiple high-voltage pulses. Switches 1220, 2225, 1230, and 1235 can be opened during each burst and closed between bursts.

[0197] Figure 14 This is a circuit diagram of a high-voltage pulse generating circuit 1400 according to some embodiments. The pulse generator stage 110, the resistor output stage 102, and / or the bias compensation circuit 1414 may include the high-voltage pulse generating circuit. The high-voltage pulse generating circuit 1400 is similar to the high-voltage pulse generating circuit 900. In this example, the bias compensation circuit 1414 does not include a buffer circuit. In this example, the bias compensation circuit 1414 includes a bias compensation inductor arranged in series with the switch S4. The bias compensation inductor L4 may have an inductance less than approximately 300nH, 100nH, 1nH, etc.

[0198] In some embodiments, switch S4 may include Figure 15 The high-voltage switch 1500 described herein. As another example, switch S4 may include any switch described in U.S. Patent Application Serial No. 16 / 178,565, filed November 1, 2018, entitled “High Voltage Switch with Isolated Power,” which is fully incorporated herein for all purposes.

[0199] In this example, the bias compensation circuit 1414 includes a stray inductance L22 between diode 505 and the location marked 124, a stray inductance L23 between diode 505 and bias compensation capacitor 510, or a stray inductance L24 between bias compensation capacitor 510 and ground. The high-voltage pulse generation circuit 1400 includes a plasma-side inductance L... p and switch-side inductor L sFor example, the plasma-side stray inductance Lp can include all inductors, whether stray, parasitic, or originating from any element between the bias compensation circuit 1414 and the plasma load 106 (e.g., such as L7) and any other stray inductance on that side of the circuit. Similarly, the switch-side inductance Ls can include all inductors, whether stray, parasitic, or originating from any element between the bias compensation circuit 1414 and the switch S1 (e.g., individually or in combination, inductors 1915, L1, 1940, L2, and / or L6) and any other stray inductance on that side of the circuit.

[0200] In some embodiments, the switch-side inductance Ls should be greater than the plasma-side stray inductance Lp. In some embodiments, the plasma-side stray inductance Lp is 20% of the switch-side inductance Ls. In some embodiments, the plasma-side stray inductance Lp is less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc.

[0201] In some embodiments, stray inductance L22 has an inductance less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc. In some embodiments, stray inductance L23 has an inductance less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc. In some embodiments, stray inductance L24 has an inductance less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc. In some embodiments, the sum of stray inductances L22, L23, and L24 is less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc.

[0202] In some embodiments, stray inductances L22, L23, or L24 can be minimized in various ways. For example, the conductors along stray inductances L22, L23, or L24 can be wider than industry standards (e.g., greater than 1 / 8, 1 / 4, 3 / 8, 1 / 2, 1, 2.5, 5 inches, etc.). As another example, various circuit elements (e.g., diode 505 or bias compensation capacitor 510) can include multiple diodes or capacitors connected in parallel or series. In some embodiments, the top and bottom conductors between various bias compensation circuit elements can be separated by less than approximately 1, 2, 5, 15, 20, 25, 30, 35, or 40 cm.

[0203] In some embodiments, the bias compensation capacitor 510 may have a capacitance of less than about 1 μF or less than about 1 mF. The bias compensation capacitor 510 may have a stray inductance of less than about 1 nH, 10 nH, 100 nH, 1 μH, etc.

[0204] In some embodiments, for example, the bias compensation inductor L4 may have an inductance of less than about 100 μH (e.g., about 50 μH, 25 μH, 10 μH, 5 μH, 1 μH, 0.5 μH, 0.25 μH, etc.).

[0205] In embodiments, the volume of a discrete element including one or both of a diode 505 and / or a bias compensation capacitor 510 may be less than 1200, 1000, 750, or 500 cubic centimeters.

[0206] In some embodiments, a resistor 515 may be included across diode 505. In some embodiments, resistor 515 may have a resistance value of less than about 1 kΩ to 1 MΩ (e.g., less than about 100 kΩ).

[0207] In some embodiments, switch S4 may have some parasitic (or stray) capacitance. For example, this parasitic capacitance may combine with the bias compensation inductor L4 to produce some ringing. For example, this ringing may cause a voltage drop across the bias compensation capacitor 510. In some embodiments, the voltage drop across the bias compensation capacitor 510 can be minimized or eliminated by keeping the inductance of the bias compensation inductor L4 low. In some embodiments, a diode may be used in parallel with or instead of the bias compensation inductor L4 to further reduce or minimize any voltage drop across the bias compensation capacitor 510.

[0208] Figure 15 This is a block diagram of a high-voltage switch 1500 with an isolated power supply according to some embodiments. The high-voltage switch 1500 may include a plurality of switch modules 1505 (commonly or individually 1505, and individually 1505A, 1505B, 1505C, and 1505D), which can switch voltages from a high-voltage source 1560 by means of a fast rise time and / or a high frequency and / or by means of a variable pulse width. Each switch module 1505 may include a switch 1510 (e.g., such as a solid-state switch).

[0209] In some embodiments, switch 1510 may be electrically coupled to gate driver circuitry 1530, which may include power supply 1540 and / or isolation fiber optic trigger 1545 (also referred to as a gate trigger or switch trigger). For example, switch 1510 may include a collector, emitter, and gate (or drain, source, and gate), and power supply 1540 may drive the gate of switch 1510 via gate driver circuitry 1530. For example, gate driver circuitry 1530 may be isolated from other components of high-voltage switch 1500.

[0210] In some embodiments, for example, an isolation transformer may be used to isolate the power supply 1540. The isolation transformer may include a low-capacitance transformer. For example, the low capacitance of the isolation transformer allows the power supply 1540 to charge on a fast time scale without requiring significant current. For example, the isolation transformer may have a capacitance of less than approximately 100 pF. As another example, the isolation transformer may have a capacitance of less than approximately 30-100 pF. In some embodiments, the isolation transformer may provide voltage isolation up to 1 kV, 5 kV, 10 kV, 25 kV, 50 kV, etc.

[0211] In some embodiments, the isolation transformer may have low stray capacitance. For example, the isolation transformer may have stray capacitance of less than approximately 1,000 pF, 100 pF, 10 pF, etc. In some embodiments, low capacitance can minimize electrical coupling to low-voltage components (e.g., sources of input control power) and / or reduce EMI generation (e.g., electrical noise generation). In some embodiments, the transformer stray capacitance of the isolation transformer may include capacitance measured between the primary and secondary windings.

[0212] In some embodiments, the isolation transformer may be a DC-to-DC converter or an AC-to-DC transformer. In some embodiments, for example, the transformer may include a 110V AC transformer. Regardless, the isolation transformer can provide a power supply isolated from other components in the high-voltage switch 1500. In some embodiments, the isolation may be current-current, such that conductors on the primary side of the isolation transformer do not pass through or contact the secondary side of the isolation transformer.

[0213] In some embodiments, the transformer may include a primary winding that can be tightly wound or coiled around the transformer core. In some embodiments, the primary winding may include conductive sheets coiled around the transformer core. In some embodiments, the primary winding may include one or more windings.

[0214] In some embodiments, the secondary winding may be wound around the core as far away from it as possible. For example, the winding bundle including the secondary winding may be wound through the center of an aperture in the transformer core. In some embodiments, the secondary winding may include one or more windings. In some embodiments, the wire bundle including the secondary winding may include a circular or square cross-section, for example, to minimize stray capacitance. In some embodiments, an insulator (e.g., oil or air) may be deployed between the primary winding, the secondary winding, or the transformer core.

[0215] In some embodiments, keeping the secondary winding away from the transformer core can have several benefits. For example, it can reduce stray capacitance between the primary and secondary sides of the isolation transformer. As another example, it can allow high voltage isolation between the primary and secondary sides of the isolation transformer, so that corona and / or breakdown do not occur during operation.

[0216] In some embodiments, the spacing between the primary side (e.g., primary winding) and the secondary side (e.g., secondary winding) of the isolation transformer can be approximately 0.1 inch, 0.5 inch, 1 inch, 5 inch, or 10 inches. In some embodiments, a typical spacing between the core of the isolation transformer and the secondary side (e.g., secondary winding) of the isolation transformer can be approximately 0.1 inch, 0.5 inch, 1 inch, 5 inch, or 10 inches. In some embodiments, the gaps between the windings can be filled with the lowest possible dielectric material (e.g., a vacuum, air, any insulating gas or liquid, or a solid material having a relative permittivity of less than 3).

[0217] In some embodiments, power supply 1540 may include any type of power supply that can provide high-voltage isolation or has low capacitance (e.g., less than about 1,000 pF, 100 pF, 10 pF, etc.). In some embodiments, the control voltage power supply may provide 1520 V AC or 240 V AC at 60 Hz.

[0218] In some embodiments, each power source 1540 may be electrically coupled inductively to a single control voltage power source. For example, power source 1540A may be electrically coupled to the power source via a first transformer; power source 1540B may be electrically coupled to the power source via a second transformer; power source 1540C may be electrically coupled to the power source via a third transformer; and power source 1540D may be electrically coupled to the power source via a fourth transformer. For example, any type of transformer that can provide voltage isolation between the various power sources can be used.

[0219] In some embodiments, the first transformer, second transformer, third transformer, and fourth transformer may include different secondary windings around the core of a single transformer. For example, the first transformer may include a primary secondary winding, the second transformer may include a secondary secondary winding, the third transformer may include a tertiary secondary winding, and the fourth transformer may include a fourth secondary winding. Each of these secondary windings may be wound around the core of a single transformer. In some embodiments, the primary, secondary, tertiary, and fourth secondary windings or the primary winding may include a single winding or multiple windings wound around the transformer core.

[0220] In some embodiments, power supplies 1540A, 1540B, 1540C, and / or 1540D may not share a return to reference ground or local ground.

[0221] For example, the isolated fiber optic trigger 1545 can also be isolated from other components of the high-voltage switch 1500. The isolated fiber optic trigger 1545 may include a fiber optic receiver that allows each switch module 1505 to float relative to other switch modules 1505 and / or other components of the high-voltage switch 1500, and / or, for example, simultaneously allow active control of the gate of each switch module 1505.

[0222] In some embodiments, for example, the return reference ground, local ground, or public ground for each switch module 1505 can be isolated from each other, for example, using an isolation transformer.

[0223] For example, electrical isolation of each switch module 1505 from common ground allows multiple switches to be arranged in series for accumulating high-voltage switching. In some embodiments, a certain hysteresis in the timing of the switch modules can be permitted or designed. For example, each switch module 1505 can be configured or rated to switch 1kV, each switch module can be electrically isolated from each other, and / or the timing of closing each switch module 1505 does not need to be perfectly aligned to the time period defined by the capacitance of the buffer capacitor and / or the rated voltage of the switch.

[0224] In some embodiments, electrical isolation can provide numerous advantages. For example, one possible advantage may include minimizing switch-to-switch jitter and / or allowing arbitrary switch timing. For instance, each switch 1510 may have switch transition jitter of less than approximately 500 ns, 50 ns, 20 ns, 5 ns, etc.

[0225] In some embodiments, electrical isolation between two components (or circuits) may imply extremely high resistance between the two components, and / or may imply small capacitance between the two components.

[0226] Each switch 1510 may include any type of solid-state switching device (e.g., IGBT, MOSFET, SiCMOSFET, SiC junction transistor, FET, SiC switch, GaN switch, opto-switch, etc.). For example, switch 1510 may be capable of switching high voltages (e.g., voltages greater than approximately 1 kV) at high frequencies (e.g., greater than 1 kHz), high speeds (e.g., repetition rates greater than approximately 500 kHz), and / or fast rise times (e.g., rise times less than approximately 25 ns) and / or long pulse lengths (e.g., greater than approximately 10 ms). In some embodiments, each switch may be individually rated for switching 1,200 V–1,700 V, while in combination it may be used for switching greater than 4,800 V–6,800 V (for four switches). Switches with a variety of other rated voltages may be used.

[0227] Using a large number of lower-voltage switches instead of a few higher-voltage switches can have several advantages. For example, lower-voltage switches typically have better performance: they can switch faster, have quicker transition times, and / or switch more efficiently than higher-voltage switches. However, the larger the number of switches, the greater the potential timing issues that may arise.

[0228] Figure 15 The high-voltage switch 1500 shown comprises four switch modules 1505. Although four are shown in the figure, any number of switch modules 1505 can be used (e.g., two, eight, twelve, sixteen, twenty, twenty-four, etc.). For example, if each switch in each switch module 1505 is rated at 1200V and sixteen switches are used, the high-voltage switch can switch up to 19.2kV. As another example, if each switch in each switch module 1505 is rated at 1700V and sixteen switches are used, the high-voltage switch can switch up to 27.2kV.

[0229] In some embodiments, the high-voltage switch 1500 may include a fast capacitor 1555. For example, the fast capacitor 1555 may include one or more capacitors arranged in series and / or parallel. For example, these capacitors may include one or more polypropylene capacitors. The fast capacitor 1555 may store energy from the high-voltage source 1560.

[0230] In some embodiments, the fast capacitor 1555 may have a low capacitance. In some embodiments, the fast capacitor 1555 may have a capacitance value of about 1 μF, about 5 μF, between about 1 μF and about 5 μF, between about 100 nF and about 1,000 nF, etc.

[0231] In some embodiments, the high-voltage switch 1500 may or may not include a crowbar diode 1550. The crowbar diode 1550 may comprise multiple diodes arranged in series or parallel, which may be advantageous for driving inductive loads. In some embodiments, the crowbar diode 1550 may include one or more Schottky diodes (e.g., silicon carbide Schottky diodes). For example, the crowbar diode 1550 may sense whether the voltage from the switch in the high-voltage switch is higher than a certain threshold. If so, the crowbar diode 1550 may short-circuit the power from the switch module to ground. For example, the crowbar diode may allow the alternating current path to dissipate the energy stored in the inductive load after switching. For example, this may prevent large inductive voltage spikes. In some embodiments, the crowbar diode 1550 may have low inductance (e.g., 1nH, 10nH, 100nH, etc.). In some embodiments, the crowbar diode 1550 may have low capacitance (e.g., 100pF, 1nF, 10nF, 100nF, etc.).

[0232] In some embodiments, such as when the load 1565 is primarily resistive, the crowbar diode 1550 may not be used.

[0233] In some embodiments, each gate driver circuit 1530 may generate jitter of less than approximately 1000 ns, 100 ns, 10.0 ns, 5.0 ns, 3.0 ns, 1.0 ns, etc. In some embodiments, each switch 1510 may have a minimum on-time (e.g., less than approximately 10 μs, 1 μs, 500 ns, 100 ns, 50 ns, 10 ns, 5 ns, etc.) and a maximum on-time (e.g., greater than 25 s, 10 s, 5 s, 1 s, 500 ms, etc.).

[0234] In some embodiments, during operation, each of the high-voltage switches can be turned on and / or off within 1 ns of each other.

[0235] In some embodiments, each switch module 1505 may have the same or substantially the same (±5%) stray inductance. Stray inductance may include any inductance within the switch module 1505 that is not associated with an inductor (e.g., inductance in leads, diodes, resistors, switches 1510, and / or board traces, etc.). Stray inductance within each switch module 1505 may include low inductance (e.g., inductance less than approximately 300nH, 100nH, 10nH, 1nH, etc.). Stray inductance between each switch module 1505 may include low inductance (e.g., inductance less than approximately 300nH, 100nH, 10nH, 1nH, etc.).

[0236] In some embodiments, each switch module 1505 may have the same or substantially the same (±5%) stray capacitance. Stray capacitance may include any capacitance within the switch module 1505 that is not associated with a capacitor (e.g., capacitance in leads, diodes, resistors, switches 1510, and / or circuit board traces, etc.). Stray capacitance within each switch module 1505 may include low capacitance (e.g., less than approximately 1,000 pF, 100 pF, 10 pF, etc.). Stray capacitance between each switch module 1505 may include low capacitance (e.g., less than approximately 1,000 pF, 100 pF, 10 pF, etc.).

[0237] For example, voltage distribution defects can be addressed using passive snubber circuits (e.g., snubber diode 1515, snubber capacitor 1520, and / or freewheeling diode 1525). For instance, small timing differences or variations in inductance or capacitance between each of the on / off states in switch 1510 can cause voltage spikes. These spikes can be mitigated using various snubber circuits (e.g., snubber diode 1515, snubber capacitor 1520, and / or freewheeling diode 1525).

[0238] For example, a buffer circuit may include a buffer diode 1515, a buffer capacitor 1520, a buffer resistor 116, and / or a freewheeling diode 1525. In some embodiments, the buffer circuit may be arranged in parallel with 1510. In some embodiments, the buffer capacitor 1520 may have a low capacitance (e.g., less than about 100 pF).

[0239] In some embodiments, the high-voltage switch 1500 may be electrically coupled to or include a load 1565 (e.g., a resistive, capacitive, or inductive load). For example, the load 1565 may have a resistance from 50 ohms to 500 ohms. Alternatively or additionally, the load 1565 may be an inductive or capacitive load.

[0240] Figure 16 An example waveform 1600 from a high-voltage pulse generating circuit according to some embodiments is shown. Waveform 1600 is generated from a high-voltage pulse generating circuit that generates a positive 2kV bias (e.g., offsets the supply voltage V1 to generate 2kV) and outputs a signal with a peak voltage of 7kV. In this example, a high-voltage switch (e.g., high-voltage switch 905) is included for the high-voltage pulse generating circuit and is closed while the pulse generator stage is generating a pulse, and is open when the pulse generator stage is not generating a pulse.

[0241] Waveform 1605 represents the voltage from pulse generator stage 101. Waveform 1610 represents the electrode voltage measured from ground to circuit point 124. Waveform 1615 represents the wafer voltage measured from ground to circuit point 122. Waveform 1620 represents the current through bias compensation circuit 114.

[0242] Waveform 1600 shows the final pulse of the burst, and the circuit returns to a steady state after the burst. Waveform 1600 shows a continuous 2kV offset between the electrode voltage and the wafer voltage. The offset voltage is the clip voltage, and maintaining a continuous 2kV clip voltage, as shown, can keep it within the threshold required to avoid damage to the wafer.

[0243] Figure 17 An example waveform 1700 from a high-voltage pulse generating circuit according to some embodiments is shown. Waveform 1700 is generated from a high-voltage pulse generating circuit that generates a positive 2kV bias (e.g., offsets the supply voltage V1 to generate 2kV) and outputs a signal with a peak voltage of 6kV. In this example, a high-voltage switch (e.g., high-voltage switch 905) is included for the high-voltage pulse generating circuit and is closed while the pulse generator stage is generating a pulse, and is open when the pulse generator stage is not generating a pulse.

[0244] Waveform 1705 represents the voltage from pulse generator stage 101. Waveform 1710 represents the electrode voltage measured from ground to circuit point 124. Waveform 1715 represents the wafer voltage measured from ground to circuit point 122. Waveform 1720 represents the current through bias compensation circuit 114.

[0245] Waveform 1700 shows all the pulses within the burst.

[0246] Figure 18 An example waveform 1800 from a high-voltage pulse generation circuit according to some embodiments is shown. Waveform 1700 is generated from a high-voltage pulse generation circuit that generates a positive 2kV bias (e.g., offsets the supply voltage V1 to generate 2kV) and outputs a signal with a peak voltage of 6kV. In this example, a high-voltage switch (e.g., high-voltage switch 905) is not used. Without high-voltage switch enabling bias compensation, waveform 1800 shows that the constant 2kV clip voltage is not maintained at the end of the burst.

[0247] Waveform 1805 represents the voltage from pulse generator stage 101. Waveform 1810 represents the electrode voltage measured from ground to circuit point 124. Waveform 1815 represents the wafer voltage measured from ground to circuit point 122. Waveform 1820 represents the current through bias compensation circuit 114.

[0248] Waveform 1800 shows all the pulses within the burst.

[0249] Figure 19 This is a circuit diagram of a high-voltage pulse generating circuit 1900 according to some embodiments. The high-voltage pulse generating circuit 1900 is similar to... Figure 9 The high-voltage pulse generation circuit 900 is shown. In this example, the resistor output stage 102 has been removed from the high-voltage pulse generation circuit 900, and an energy recovery circuit 1905 has been added. The pulse generator stage 101 (which can be replaced by the pulse generator stage 110), the energy recovery circuit 1905, and / or the bias compensation circuit 914 may include the high-voltage pulse generation circuit.

[0250] In some embodiments, the high-voltage pulse generation circuit 1900 may include a pulse generator stage 101 coupled to an energy recovery circuit 1905. The pulse generator stage 101 and the energy recovery circuit 1905 may be coupled to a bias compensation circuit 914 and a plasma load 106. The plasma load 106 may include any type of load (e.g., any load described herein).

[0251] Energy recovery circuit 1905 may be located on or electrically coupled to the secondary side of transformer T1. For example, energy recovery circuit 1905 may include a diode 1930 (e.g., a crowbar diode) spanning the secondary side of transformer T1. Energy recovery circuit 1905 may also include a diode 1910 and an inductor 1915 (arranged in series) that allow current to flow from the secondary side of transformer T1 to charge power supply C7. Diode 1910 and inductor 1915 may be electrically connected to the secondary side of transformer T1 and power supply C7. In some embodiments, energy recovery circuit 1905 may include a diode 1935 and / or an inductor 1940 electrically coupled to the secondary side of transformer T1. Inductor 1940 may represent stray inductance and / or may include stray inductance of transformer T1.

[0252] When the nanosecond pulse generator is on, current can charge the plasma load 106 (e.g., charge capacitors C3, C2, or C9). For example, some current can flow through inductor 1915 when the voltage on the secondary side of transformer T1 rises above the charging voltage on power supply C7. When the nanosecond pulse generator is off, current can flow from the capacitors within plasma load 106 through inductor 1915 to charge power supply C7 until the voltage across inductor 1915 is zero. Diode 1930 prevents ringing of the capacitors within plasma load 106 with the inductors in plasma load 106 and / or bias compensation circuit 914.

[0253] For example, diode 1910 can prevent charge from flowing from power supply C7 to the capacitor within plasma load 106.

[0254] The value of inductor 1915 can be selected to control the current drop time. In some embodiments, inductor 1915 may have an inductance value between 1 μH and 500 μH.

[0255] In some embodiments, the energy recovery circuit 1905 may include a switch that can be used to control the flow of current through the inductor 1915. For example, the switch may be placed in series with the inductor 1915. In an embodiment, the switch may close when the switch S1 is open and / or when pulses cease to occur, to allow current to flow from the plasma load 106 back to the high-voltage load C7. For example, the switch may include a high-voltage switch (e.g., high-voltage switch 1500).

[0256] In some embodiments, pulse generator stage 101 may include a high-voltage switch 1500, which replaces or complements the various components shown in pulse generator stage 101. In some embodiments, using high-voltage switch 1500 may allow at least the removal of transformer T1 and switch S1.

[0257] In some embodiments, the bias compensation circuit 914 may include a high-voltage switch 905 coupled across the bias compensation diode 505 and coupled to the power supply V1. In some embodiments, the high-voltage switch 905 may include a plurality of switches 905 arranged in series to collectively open and close a high voltage. For example, the high-voltage switch 905 may include Figure 15 The high-voltage switch 1500 is described in the figure. In some embodiments, the high-voltage switch 905 may be coupled to a switch trigger V4.

[0258] The high-voltage switch 905 may be coupled in series with one or both of the bias compensation inductor L4, diode D10, and / or resistor R11. The bias compensation inductor L4 may limit the peak current through the high-voltage switch 905. For example, the bias compensation inductor L4 may have an inductance of less than approximately 100nH (e.g., approximately 250nH, 100nH, 50nH, 25nH, 10nH, 5nH, 1nH, etc.). For example, the resistor R11 may dissipate power to the resistive output stage 102. For example, the resistor R11 may have a resistance of less than approximately 1000 ohms, 500 ohms, 250 ohms, 100 ohms, 50 ohms, 10 ohms, etc. In some embodiments, the bias compensation inductor L4 is deployed in series with diode D10 and resistor R11.

[0259] In some embodiments, the high-voltage switch 905 may include a snubber circuit. The snubber circuit may include a resistor R9, a snubber diode D8, a snubber capacitor C15, and a snubber resistor R10.

[0260] In some embodiments, resistor R8 may represent a stray resistance offset from the supply voltage V1. For example, resistor R8 may have a high resistance (e.g., a resistor of approximately 10k ohms, 100k ohms, 1M ohms, 10M ohms, 100M ohms, 1G ohms, etc.).

[0261] In some embodiments, the high-voltage switch 905 may include a plurality of switches arranged in series to jointly open and close a high voltage. For example, the high-voltage switch 905 may include Figure 15 The high-voltage switch 1500 described herein. As another example, the high-voltage switch 905 may, for example, include any switch described in U.S. Patent Application Serial No. 16 / 178,565, filed November 1, 2018, entitled “High Voltage Switch with Isolated Power,” which is incorporated herein in its entirety for all purposes.

[0262] In some embodiments, the high-voltage switch 905 can be turned on while the pulse generator stage 101 is generating a pulse, and closed when the pulse generator stage 101 is not generating a pulse. For example, when the high-voltage switch 905 is closed, current can be short-circuited across the bias compensation diode 505. Short-circuiting this current allows the bias between the wafer and the clip to be less than 2kV, which can be within acceptable tolerances.

[0263] In some embodiments, the high-voltage switch 905 can allow the electrode voltage (marked at position 124) and wafer voltage (marked at position 122) to recover rapidly (e.g., less than approximately 100 ns, 200 ns, 500 ns, 1 μs) to the clip potential (marked at position 121). For example, in Figure 10 , Figure 11A and Figure 11B This situation is illustrated in the image.

[0264] In this example, the bias compensation circuit 914 includes a stray inductance L22 between diode 505 and the location marked 124, a stray inductance L23 between diode 505 and bias compensation capacitor 510, or a stray inductance L24 between bias compensation capacitor 510 and ground. The high-voltage pulse generation circuit 900 includes a plasma-side inductance Lp and a switching-side inductance Ls. For example, the plasma-side stray inductance Lp can include all inductors, whether stray, parasitic, or originating from any element between the bias compensation circuit 914 and the plasma load 106 (e.g., L7) and any other stray inductance on that side of the circuit. For example, the switch-side inductor Ls can include all inductors, regardless of stray, parasitic, or any element between the bias compensation circuit 914 and the switch S1 (e.g., individually or in combination, inductors 1915, L1, 1940, L2, and / or L6) and any other stray inductors on that side of the circuit.

[0265] In some embodiments, the switch-side inductance Ls should be greater than the plasma-side stray inductance Lp. In some embodiments, the plasma-side stray inductance Lp is 20% of the switch-side inductance Ls. In some embodiments, the plasma-side stray inductance Lp is less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc.

[0266] In some embodiments, stray inductance L22 has an inductance less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc. In some embodiments, stray inductance L23 has an inductance less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc. In some embodiments, stray inductance L24 has an inductance less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc. In some embodiments, the sum of stray inductances L22, L23, and L24 is less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc.

[0267] In some embodiments, stray inductances L22, L23, or L24 can be minimized in various ways. For example, the conductors along stray inductances L22, L23, or L24 can be wider than industry standards (e.g., greater than 1 / 8, 1 / 4, 3 / 8, 1 / 2, 1, 2.5, 5 inches, etc.). As another example, various circuit elements (e.g., diode 505 or bias compensation capacitor 510) can include multiple diodes or capacitors connected in parallel or series. In some embodiments, the top and bottom conductors between various bias compensation circuit elements can be separated by less than approximately 1, 2, 5, 15, 20, 25, 30, 35, or 40 cm.

[0268] In some embodiments, the bias compensation capacitor 510 may have a capacitance of less than about 1 μF or less than about 1 mF. The bias compensation capacitor 510 may have a stray inductance of less than about 1 nH, 10 nH, 100 nH, 1 μH, etc.

[0269] For example, the bias compensation inductor L4 may have an inductance of less than approximately 100 nH (e.g., approximately 250 nH, 100 nH, 50 nH, 25 nH, 10 nH, 5 nH, 1 nH, etc.). In embodiments, the volume of the discrete components including one or both of the diode 505 and / or the bias compensation capacitor 510 may be less than 1200, 1000, 750, or 500 cubic centimeters.

[0270] In some embodiments, a resistor 515 may be included across diode 505. In some embodiments, resistor 515 may have a resistance value of less than about 1 kΩ to 1 MΩ (e.g., less than about 100 kΩ).

[0271] In some embodiments, the high-voltage switch 905 and / or diode D8 may have some parasitic (or stray) capacitance. For example, this parasitic capacitance may combine with the bias compensation inductor L4 to produce some ringing. For example, this ringing may produce some voltage drop across the bias compensation capacitor 510. In some embodiments, the voltage drop across the bias compensation capacitor 510 can be minimized or eliminated by keeping the inductance of the bias compensation inductor L4 low. In some embodiments, diode D10 may be used with or in place of the bias compensation inductor L4 to further reduce or minimize any voltage drop across the bias compensation capacitor 510.

[0272] For example, certain values ​​and / or arrangements of the inductance can compensate for or correct for overshoot in capacitor C2 from inductor L5 ringing to capacitor C2, resonant ringing of capacitor C2 or capacitor C1 with inductor L5, or decrease in parasitic capacitance caused by the interaction of L4 with high-voltage switch 905 and / or diode D8.

[0273] Figure 20 This is a circuit diagram of a high-voltage pulse generation circuit 2000 according to some embodiments. The pulse generator stage 101 (which can be replaced by a pulse generator stage 110), energy recovery circuit 1905, and / or bias compensation circuit 1214 may include the high-voltage pulse generation circuit. The high-voltage pulse generation circuit 2000 is similar to... Figure 12 The high-voltage pulse generating circuit 1200 is shown. In this example, the resistor output stage 102 has been removed from the high-voltage pulse generating circuit 1200, and the energy recovery circuit 1905 has been added.

[0274] In some embodiments, the high-voltage pulse generation circuit 2000 may include a pulse generator stage 101 coupled to an energy recovery circuit 1905. The pulse generator stage 101 and the energy recovery circuit 1905 may be coupled to a bias compensation circuit 1214 and a plasma load 106. The plasma load 106 may include any type of load (e.g., any load described herein).

[0275] In this example, the energy recovery circuit 1905 may be located on or electrically coupled to the secondary side of transformer T1. For example, the energy recovery circuit 1905 may include a diode 1930 (e.g., a crowbar diode) spanning the secondary side of transformer T1. For example, the energy recovery circuit 1905 may include a diode 1910 and an inductor 1915 (arranged in series) that allow current to flow from the secondary side of transformer T1 to charge power supply C7. Diode 1910 and inductor 1915 may be electrically connected to the secondary side of transformer T1 and power supply C7. In some embodiments, the energy recovery circuit 1905 may include a diode 1935 and / or an inductor 1940 electrically coupled to the secondary side of transformer T1. Inductor 1940 may represent a stray inductance and / or may include the stray inductance of transformer T1.

[0276] When the nanosecond pulse generator is on, current can charge the plasma load 106 (e.g., charge capacitors C3, C2, or C9). For example, when the voltage on the secondary side of transformer T1 rises above the charging voltage on power supply C7, some current can flow through inductor 1915. When the nanosecond pulse generator is off, current can flow from the capacitors within plasma load 106 through inductor 1915 to charge power supply C7 until the voltage across inductor 1915 is zero. Diode 1930 prevents ringing of the capacitors within plasma load 106 with the inductors in plasma load 106 and / or bias compensation circuit 1214.

[0277] For example, diode 1910 can prevent charge from flowing from power supply C7 to the capacitor within plasma load 106.

[0278] The value of inductor 1915 can be selected to control the current drop time. In some embodiments, inductor 1915 may have an inductance value between 1 μH and 500 μH.

[0279] In some embodiments, the energy recovery circuit 1905 may include a switch that can be used to control the flow of current through the inductor 1915. For example, the switch may be placed in series with the inductor 1915. In an embodiment, the switch may close when the switch S1 is open and / or when pulses cease to occur, to allow current to flow from the plasma load 106 back to the high-voltage load C7. For example, the switch may include a high-voltage switch (e.g., high-voltage switch 1500).

[0280] In some embodiments, pulse generator stage 101 may include a high-voltage switch 1500, which replaces or complements the various components shown in pulse generator stage 101. In some embodiments, using high-voltage switch 1500 may allow at least the removal of transformer T1 and switch S1.

[0281] In this example, the bias compensation circuit 1214 includes a stray inductance L22 between diode 505 and the location marked 124, a stray inductance L23 between diode 505 and bias compensation capacitor 510, or a stray inductance L24 between bias compensation capacitor 510 and ground. The high-voltage pulse generation circuit 1200 includes a plasma-side inductance Lp and a switching-side inductance Ls. For example, the plasma-side stray inductance Lp can include all inductors, whether stray, parasitic, or originating from any element between the bias compensation circuit 1214 and the plasma load 106 (e.g., L7) and any other stray inductance on that side of the circuit. For example, the switch-side inductor Ls can include all inductors, regardless of stray, parasitic, or any element between the bias compensation circuit 1214 and the switch S1 (e.g., individually or in combination, inductors L3, 1915, 1940, L2, and L6) and any other stray inductors on that side of the circuit.

[0282] In some embodiments, the switch-side inductance Ls should be greater than the plasma-side stray inductance Lp. In some embodiments, the plasma-side stray inductance Lp is 20% of the switch-side inductance Ls. In some embodiments, the plasma-side stray inductance Lp is less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc.

[0283] In some embodiments, stray inductance L22 has an inductance less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc. In some embodiments, stray inductance L23 has an inductance less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc. In some embodiments, stray inductance L24 has an inductance less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc. In some embodiments, the sum of stray inductances L22, L23, and L24 is less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc.

[0284] In some embodiments, stray inductances L22, L23, or L24 can be minimized in various ways. For example, the conductors along stray inductances L22, L23, or L24 can be wider than industry standards (e.g., greater than 1 / 8, 1 / 4, 3 / 8, 1 / 2, 1, 2.5, 5 inches, etc.). As another example, various circuit elements (e.g., diode 505 or bias compensation capacitor 510) can include multiple diodes or capacitors connected in parallel or series. In some embodiments, the top and bottom conductors between various bias compensation circuit elements can be separated by less than approximately 1, 2, 5, 15, 20, 25, 30, 35, or 40 cm.

[0285] In some embodiments, the bias compensation capacitor 510 may have a capacitance of less than about 1 μF or less than about 1 mF. The bias compensation capacitor 510 may have a stray inductance of less than about 1 nH, 10 nH, 100 nH, 1 μH, etc.

[0286] In some embodiments, for example, the bias compensation inductor L4 may have an inductance of less than about 100 μH (e.g., about 50 μH, 25 μH, 10 μH, 5 μH, 1 μH, 0.5 μH, 0.25 μH, etc.).

[0287] In embodiments, the volume of a discrete element including one or both of a diode 505 and / or a bias compensation capacitor 510 may be less than 1200, 1000, 750, or 500 cubic centimeters.

[0288] In some embodiments, a resistor 515 may be included across diode 505. In some embodiments, resistor 515 may have a resistance value of less than about 1 kΩ to 1 MΩ (e.g., less than about 100 kΩ).

[0289] In some embodiments, switches 1220, 2225, 1230, and 1235 may have some parasitic (or stray) capacitance. For example, this parasitic capacitance may combine with the bias compensation inductor L4 to produce some ringing. For example, this ringing may produce some voltage drop across the bias compensation capacitor 510. In some embodiments, the voltage drop across the bias compensation capacitor 510 can be minimized or eliminated by keeping the inductance of the bias compensation inductor L4 low. In some embodiments, a diode may be used in parallel with or instead of the bias compensation inductor L4 to further reduce or minimize any voltage drop across the bias compensation capacitor 510.

[0290] In some embodiments, pulse generator stage 101 can generate multiple high-voltage bursts, wherein each burst includes multiple high-voltage pulses. Switches 1220, 2225, 1230, and 1235 can be opened during each burst and closed between bursts.

[0291] Figure 21 This is a circuit diagram of a high-voltage pulse generation circuit 2100 according to some embodiments. The pulse generator stage 101 (which can be replaced by a pulse generator stage 110), energy recovery circuit 1905, and / or bias compensation circuit 1314 may include the high-voltage pulse generation circuit. The high-voltage pulse generation circuit 2100 is similar to... Figure 13 The high-voltage pulse generating circuit 1300 is shown. In this example, the resistor output stage 102 has been removed from the high-voltage pulse generating circuit 1200, and the energy recovery circuit 1905 has been added.

[0292] In some embodiments, the high-voltage pulse generation circuit 2100 may include a pulse generator stage 101 coupled to an energy recovery circuit 1905. The pulse generator stage 101 and the energy recovery circuit 1905 may be coupled to a bias compensation circuit 1314 and a plasma load 106. The plasma load 106 may include any type of load (e.g., any load described herein).

[0293] In this example, the energy recovery circuit 1905 may be located on or electrically coupled to the secondary side of transformer T1. For example, the energy recovery circuit 1905 may include a diode 1930 (e.g., a crowbar diode) spanning the secondary side of transformer T1. For example, the energy recovery circuit 1905 may include a diode 1910 and an inductor 1915 (arranged in series) that allow current to flow from the secondary side of transformer T1 to charge power supply C7. Diode 1910 and inductor 1915 may be electrically connected to the secondary side of transformer T1 and power supply C7. In some embodiments, the energy recovery circuit 1905 may include a diode 1935 and / or an inductor 1940 electrically coupled to the secondary side of transformer T1. Inductor 1940 may represent a stray inductance and / or may include the stray inductance of transformer T1.

[0294] When the nanosecond pulse generator is on, current can charge the plasma load 106 (e.g., charge capacitors C3, C2, or C9). For example, when the voltage on the secondary side of transformer T1 rises above the charging voltage on power supply C7, some current can flow through inductor 1915. When the nanosecond pulse generator is off, current can flow from the capacitors within plasma load 106 through inductor 1915 to charge power supply C7 until the voltage across inductor 1915 is zero. Diode 1930 prevents the capacitors within plasma load 106 from ringing with the inductors in plasma load 106 and / or bias compensation circuit 1314.

[0295] For example, diode 1910 can prevent charge from flowing from power supply C7 to the capacitor within plasma load 106.

[0296] The value of inductor 1915 can be selected to control the current drop time. In some embodiments, inductor 1915 may have an inductance value between 1 μH and 500 μH.

[0297] In some embodiments, the energy recovery circuit 1905 may include a switch that can be used to control the flow of current through the inductor 1915. For example, the switch may be placed in series with the inductor 1915. In an embodiment, the switch may close when the switch S1 is open and / or when pulses cease to occur, to allow current to flow from the plasma load 106 back to the high-voltage load C7. For example, the switch may include a high-voltage switch (e.g., high-voltage switch 1500).

[0298] In some embodiments, pulse generator stage 101 may include a high-voltage switch 1500, which replaces or complements the various components shown in pulse generator stage 101. In some embodiments, using high-voltage switch 1500 may allow at least the removal of transformer T1 and switch S1.

[0299] In this example, bias compensation circuit 1314 is similar to bias compensation circuit 1214. In this example, each switching module (1220, 1225, 1230, and 1235) having bias compensation circuit 1314 may include a corresponding snubber circuit. Each snubber circuit may include a snubber diode and a snubber capacitor. In some embodiments, the snubber diode may include a snubber resistor arranged across the snubber diode. Each switching module may include a resistor that ensures uniform voltage distribution among each of the switches arranged in series.

[0300] In this example, the bias compensation circuit 1314 includes a stray inductance L22 between diode 505 and the location marked 124, a stray inductance L23 between diode 505 and bias compensation capacitor 510, or a stray inductance L24 between bias compensation capacitor 510 and ground. The high-voltage pulse generation circuit 1300 includes a plasma-side inductance Lp and a switching-side inductance Ls. For example, the plasma-side stray inductance Lp can include all inductors, whether stray, parasitic, or originating from any element between the bias compensation circuit 1314 and the plasma load 106 (e.g., L7) and any other stray inductance on that side of the circuit. For example, the switch-side inductor Ls may include all inductors, regardless of stray, parasitic, or any element between the bias compensation circuit 1314 and the switch S1 (e.g., individually or in combination, inductors 1915, L1, 1940, L2, and / or L6) and any other stray inductors on that side of the circuit.

[0301] In some embodiments, the switch-side inductance Ls should be greater than the plasma-side stray inductance Lp. In some embodiments, the plasma-side stray inductance Lp is 20% of the switch-side inductance Ls. In some embodiments, the plasma-side stray inductance Lp is less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc.

[0302] In some embodiments, stray inductance L22 has an inductance less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc. In some embodiments, stray inductance L23 has an inductance less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc. In some embodiments, stray inductance L24 has an inductance less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc. In some embodiments, the sum of stray inductances L22, L23, and L24 is less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc.

[0303] In some embodiments, stray inductances L22, L23, or L24 can be minimized in various ways. For example, the conductors along stray inductances L22, L23, or L24 can be wider than industry standards (e.g., greater than 1 / 8, 1 / 4, 3 / 8, 1 / 2, 1, 2.5, 5 inches, etc.). As another example, various circuit elements (e.g., diode 505 or bias compensation capacitor 510) can include multiple diodes or capacitors connected in parallel or series. In some embodiments, the top and bottom conductors between various bias compensation circuit elements can be separated by less than approximately 1, 2, 5, 15, 20, 25, 30, 35, or 40 cm.

[0304] In some embodiments, the bias compensation capacitor 510 may have a capacitance of less than about 1 μF or less than about 1 mF. The bias compensation capacitor 510 may have a stray inductance of less than about 1 nH, 10 nH, 100 nH, 1 μH, etc.

[0305] In some embodiments, for example, the bias compensation inductor L4 may have an inductance of less than about 100 μH (e.g., about 50 μH, 25 μH, 10 μH, 5 μH, 1 μH, 0.5 μH, 0.25 μH, etc.).

[0306] In embodiments, the volume of a discrete element including one or both of a diode 505 and / or a bias compensation capacitor 510 may be less than 1200, 1000, 750, or 500 cubic centimeters.

[0307] In some embodiments, a resistor 515 may be included across diode 505. In some embodiments, resistor 515 may have a resistance value of less than about 1 kΩ to 1 MΩ (e.g., less than about 100 kΩ).

[0308] In some embodiments, switches 1220, 2225, 1230 and / or 1235 and / or diodes D10, D11, D12 and / or D13 may have some parasitic (or stray) capacitance. For example, this parasitic capacitance, possibly combined with capacitors C15, C16, C17 and / or C18, may combine with bias compensation inductor L4 to produce some ringing. For example, such ringing may produce some voltage drop across bias compensation capacitor 510. In some embodiments, the voltage drop across bias compensation inductor L4 can be minimized or eliminated by keeping the inductance of bias compensation inductor L4 low. In some embodiments, diodes may be used in parallel with or in place of bias compensation inductor L4 to further reduce or minimize any voltage drop across bias compensation capacitor 510.

[0309] Figure 22 This is a circuit diagram of a high-voltage pulse generating circuit 2200 according to some embodiments. The high-voltage pulse generating circuit 2200 is similar to... Figure 14 The high-voltage pulse generation circuit 1400 is shown. In this example, the resistor output stage 102 has been removed from the high-voltage pulse generation circuit 1200, and an energy recovery circuit 1905 has been added. The pulse generator stage 101 (which can be replaced by the pulse generator stage 110), the energy recovery circuit 1905, and / or the bias compensation circuit 1414 may include the high-voltage pulse generation circuit.

[0310] In some embodiments, the high-voltage pulse generation circuit 2100 may include a pulse generator stage 101 coupled to an energy recovery circuit 1905. The pulse generator stage 101 and the energy recovery circuit 1905 may be coupled to a bias compensation circuit 1414 and a plasma load 106. The plasma load 106 may include any type of load (e.g., any load described herein).

[0311] In this example, the energy recovery circuit 1905 may be located on or electrically coupled to the secondary side of transformer T1. For example, the energy recovery circuit 1905 may include a diode 1930 (e.g., a crowbar diode) spanning the secondary side of transformer T1. For example, the energy recovery circuit 1905 may include a diode 1910 and an inductor 1915 (arranged in series) that allow current to flow from the secondary side of transformer T1 to charge power supply C7. Diode 1910 and inductor 1915 may be electrically connected to the secondary side of transformer T1 and power supply C7. In some embodiments, the energy recovery circuit 1905 may include a diode 1935 and / or an inductor 1940 electrically coupled to the secondary side of transformer T1. Inductor 1940 may represent a stray inductance and / or may include the stray inductance of transformer T1.

[0312] When the nanosecond pulse generator is on, current can charge the plasma load 106 (e.g., charge capacitors C3, C2, or C9). For example, when the voltage on the secondary side of transformer T1 rises above the charging voltage on power supply C7, some current can flow through inductor 1915. When the nanosecond pulse generator is off, current can flow from the capacitors within plasma load 106 through inductor 1915 to charge power supply C7 until the voltage across inductor 1915 is zero. Diode 1930 prevents the capacitors within plasma load 106 from ringing with the inductors in plasma load 106 and / or bias compensation circuit 1414.

[0313] For example, diode 1910 can prevent charge from flowing from power supply C7 to the capacitor within plasma load 106.

[0314] The value of inductor 1915 can be selected to control the current drop time. In some embodiments, inductor 1915 may have an inductance value between 1 μH and 500 μH.

[0315] In some embodiments, the energy recovery circuit 1905 may include a switch that can be used to control the flow of current through the inductor 1915. For example, the switch may be placed in series with the inductor 1915. In an embodiment, the switch may close when the switch S1 is open and / or when pulses cease to occur, to allow current to flow from the plasma load 106 back to the high-voltage load C7. For example, the switch may include a high-voltage switch (e.g., high-voltage switch 1500).

[0316] In some embodiments, pulse generator stage 101 may include a high-voltage switch 1500, which replaces or complements the various components shown in pulse generator stage 101. In some embodiments, using high-voltage switch 1500 may allow at least the removal of transformer T1 and switch S1.

[0317] In this example, the bias compensation circuit 1414 includes a stray inductance L22 between diode 505 and the location marked 124, a stray inductance L23 between diode 505 and bias compensation capacitor 510, or a stray inductance L24 between bias compensation capacitor 510 and ground. The high-voltage pulse generation circuit 1400 includes a plasma-side inductance Lp and a switching-side inductance Ls. For example, the plasma-side stray inductance Lp can include all inductors, whether stray, parasitic, or originating from any element between the bias compensation circuit 1414 and the plasma load 106 (e.g., L7) and any other stray inductance on that side of the circuit. For example, the switch-side inductor Ls may include all inductors, regardless of stray, parasitic, or any element between the bias compensation circuit 1414 and the switch S1 (e.g., individually or in combination, inductors 1915, L1, 1940, L2, and / or L6) and any other stray inductors on that side of the circuit.

[0318] In some embodiments, the switch-side inductance Ls should be greater than the plasma-side stray inductance Lp. In some embodiments, the plasma-side stray inductance Lp is 20% of the switch-side inductance Ls. In some embodiments, the plasma-side stray inductance Lp is less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc.

[0319] In some embodiments, stray inductance L22 has an inductance less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc. In some embodiments, stray inductance L23 has an inductance less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc. In some embodiments, stray inductance L24 has an inductance less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc. In some embodiments, the sum of stray inductances L22, L23, and L24 is less than approximately 1 nH, 10 nH, 100 nH, 1 μH, etc.

[0320] In some embodiments, stray inductances L22, L23, or L24 can be minimized in various ways. For example, the conductors along stray inductances L22, L23, or L24 can be wider than industry standards (e.g., greater than 1 / 8, 1 / 4, 3 / 8, 1 / 2, 1, 2.5, 5 inches, etc.). As another example, various circuit elements (e.g., diode 505 or bias compensation capacitor 510) can include multiple diodes or capacitors connected in parallel or series. In some embodiments, the top and bottom conductors between various bias compensation circuit elements can be separated by less than approximately 1, 2, 5, 15, 20, 25, 30, 35, or 40 cm.

[0321] In some embodiments, the bias compensation capacitor 510 may have a capacitance of less than about 1 μF or less than about 1 mF. The bias compensation capacitor 510 may have a stray inductance of less than about 1 nH, 10 nH, 100 nH, 1 μH, etc.

[0322] In some embodiments, for example, the bias compensation inductor L4 may have an inductance of less than about 100 μH (e.g., about 50 μH, 25 μH, 10 μH, 5 μH, 1 μH, 0.5 μH, 0.25 μH, etc.).

[0323] In embodiments, the volume of a discrete element including one or both of a diode 505 and / or a bias compensation capacitor 510 may be less than 1200, 1000, 750, or 500 cubic centimeters.

[0324] In some embodiments, a resistor 515 may be included across diode 505. In some embodiments, resistor 515 may have a resistance value of less than about 1 kΩ to 1 MΩ (e.g., less than about 100 kΩ).

[0325] In some embodiments, switch S4 may have some parasitic (or stray) capacitance. For example, this parasitic capacitance may combine with the bias compensation inductor L4 to produce some ringing. For example, this ringing may cause a voltage drop across the bias compensation capacitor 510. In some embodiments, the voltage drop across the bias compensation capacitor 510 can be minimized or eliminated by keeping the inductance of the bias compensation inductor L4 low. In some embodiments, a diode may be used in parallel with or instead of the bias compensation inductor L4 to further reduce or minimize any voltage drop across the bias compensation capacitor 510.

[0326] Unless otherwise specified, the term "substantially" means within 5% or 10% of the value referred to or within manufacturing tolerances. Unless otherwise specified, the term "approximately" means within 5% or 10% of the value referred to or within manufacturing tolerances.

[0327] The conjunction "or" is inclusive.

[0328] This document sets forth numerous specific details to provide a thorough understanding of the claimed subject matter. However, those skilled in the art will understand that the claimed subject matter can be practiced without these specific details. In other instances, methods, apparatus, or systems well-known to those skilled in the art have not been described in detail so as not to obscure the claimed subject matter.

[0329] The use of “applies to” or “configured to” in this document indicates an open and inclusive language that does not exclude applicability to or configuration for devices performing additional tasks or steps. Furthermore, the use of “based on” is open and inclusive in that a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may actually be based on additional conditions or values ​​beyond those stated. The headings, lists, and numbering included in this document are for ease of interpretation only and are not intended to be limiting.

[0330] While this subject matter has been described in detail with respect to specific embodiments thereof, it should be understood that modifications, variations, and equivalents of these embodiments can be readily made by those skilled in the art in implementing the foregoing understanding. Accordingly, it should be understood that this disclosure has been made for purposes of illustration rather than limitation, and does not exclude the inclusion of such modifications, variations, and / or additions to this subject matter as will be readily apparent to those skilled in the art.

Claims

1. A high-voltage pulse generating circuit, comprising: High-voltage pulse generator power supply; A transformer that is electrically coupled to the high-voltage pulse; The output is electrically coupled to the transformer and configured to output a high-voltage pulse with an amplitude greater than 1 kV and a pulse repetition frequency greater than 1 kHz. and A bias compensation circuit, coupled to the transformer, the output at one end, and ground at the other end, wherein the bias compensation circuit includes: A first inductor, comprising an inductor element and a stray inductance between the bias compensation circuit and the high-voltage pulse generating power supply; and The second inductor includes an inductor element and a stray inductance between the bias compensation circuit and the output; The stray inductance of the bias compensation circuit is less than 1μH. The first inductor is greater than the second inductor.

2. The high-voltage pulse generating circuit as described in claim 1, wherein, The bias compensation circuit includes a bias compensation diode, a DC power supply, and a bias compensation capacitor.

3. The high-voltage pulse generating circuit as described in claim 1, wherein, The second inductance is less than 1μH.

4. The high-voltage pulse generating circuit as described in claim 1, wherein, The second inductance is less than 20% of the first inductance.

5. A high-voltage pulse generating circuit, comprising: High-voltage pulse generator power supply; A transformer that is electrically coupled to the high-voltage pulse; The output is electrically coupled to the transformer and configured to output a high-voltage pulse with an amplitude greater than 1 kV and a pulse repetition frequency greater than 1 kHz. and A bias compensation circuit, coupled to the transformer, the output at one end, and ground at the other end, the bias compensation circuit comprising: The first inductor includes an inductor element and a stray inductance between the bias compensation circuit and the high-voltage pulse generating power supply; and The second inductor includes an inductor element and stray inductance between the bias compensation circuit and the output.

6. The high-voltage pulse generating circuit as described in claim 5, wherein, The second inductance is less than 1μH.

7. The high-voltage pulse generating circuit as described in claim 5, wherein, The first inductance is greater than the second inductance.

8. The high-voltage pulse generating circuit as described in claim 5, wherein, The second inductance is less than 20% of the first inductance.

9. The high-voltage pulse generating circuit as described in claim 5, wherein, The bias compensation circuit further includes: Bias compensation diode; DC power supply; and Multiple switches are arranged in parallel with the bias compensation diode.

10. The high-voltage pulse generating circuit as described in claim 9, wherein, The high-voltage pulse generating power supply generates multiple high-voltage bursts, wherein each burst includes multiple high-voltage pulses; and The plurality of switches are turned on during each burst.

11. A high-voltage pulse generating circuit, comprising: High-voltage pulse generator power supply; A transformer that is electrically coupled to the high-voltage pulse; The output is electrically coupled to the transformer and configured to output a high-voltage pulse with an amplitude greater than 1 kV and a pulse repetition frequency greater than 1 kHz. and A bias compensation circuit, coupled to the transformer, its output at one end, and ground at the other end, the bias compensation circuit comprising: Stray inductance, which is less than 1μH; Bias compensation diode; A DC power supply, which is arranged in series with the bias compensation diode; and An inductor is arranged in series with the bias compensation diode and the DC power supply.

12. The high-voltage pulse generating circuit as described in claim 11, further comprising: A bias compensation resistor is arranged across the bias compensation diode.

13. The high-voltage pulse generating circuit as described in claim 12, wherein, The bias compensation has a resistance of less than 100kΩ.

14. The high-voltage pulse generating circuit as described in claim 11, further comprising: The first stray inductance between the bias compensation diode and the point between the output and the transformer is less than 1 μH.

15. The high-voltage pulse generating circuit as described in claim 11, further comprising: The second stray inductance between the bias compensation diode and the capacitor is less than 1 μH.

16. The high-voltage pulse generating circuit as described in claim 15, further comprising: The first stray inductance between the capacitor and ground is less than 1 μH.

17. The high-voltage pulse generating circuit as described in claim 15, wherein, The capacitor has a capacitance of less than 1 mF.

18. The high-voltage pulse generating circuit as described in claim 11, wherein, The bias compensation circuit further includes: Bias compensation diode; DC power supply; and Multiple switches are arranged in parallel with the bias compensation diode.

19. The high-voltage pulse generating circuit as described in claim 18, wherein, The high-voltage pulse generating power supply generates multiple high-voltage bursts, wherein each burst includes multiple high-voltage pulses; and The plurality of switches are turned on during each burst.

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