Method and apparatus for smoothing dram bitline metal

Abstract

A process to smooth the top surface of bit line metal of a memory structure reduces the resistance of the bit line stack. The process includes depositing a titanium layer of about 30 Angstroms to 50 Angstroms on a polysilicon layer on a substrate, depositing a first titanium nitride layer of about 15 Angstroms to about 40 Angstroms on the titanium layer, annealing the substrate at a temperature of about 700 degrees Celsius to about 850 degrees Celsius, depositing a second titanium nitride layer of about 15 Angstroms to about 40 Angstroms on the first titanium nitride layer after annealing, and depositing a bit line metal layer of ruthenium on the second titanium nitride layer.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of electronic devices and the manufacture of electronic devices. More specifically, embodiments of the present invention provide an electronic device including bit lines having a smooth top surface and a method for manufacturing the same. Background Technology

[0002] The conductive interconnect layers of modern integrated circuits are typically characterized by very fine spacing and high density. Even a single small defect in the precursor metal film of the metal interconnect layers that ultimately form the integrated circuit can be positioned to severely compromise the operational integrity of the integrated circuit. Bit line stacking deposition suffers from several potential problems. Surface reactions between the metal and the silicon nitride hard mask occur due to the high deposition temperatures experienced during hard mask formation. Bit line resistance increases due to the interdiffusion of silicon into the bit lines and metal atoms into the silicon nitride hard mask. Furthermore, the roughness of the metal surface caused by the high temperatures during formation makes it difficult to grow metal using grain growth techniques.

[0003] Therefore, the inventors have provided a method and apparatus for smoothing the top surface of bit line metal. Summary of the Invention

[0004] Methods and apparatus for smoothing the top surface of bit line metal are provided herein.

[0005] In some embodiments, a method for smoothing the top surface of the bit line metal of a memory structure includes: depositing a titanium layer of about 30 to about 50 angstroms on a polysilicon layer on a substrate; depositing a first titanium nitride layer of about 15 to about 40 angstroms on the titanium layer; annealing the substrate at a temperature of about 700 degrees Celsius to about 850 degrees Celsius; depositing a second titanium nitride layer of about 15 to about 40 angstroms on the annealed first titanium nitride layer; and depositing a ruthenium bit line metal layer on the second titanium nitride layer.

[0006] In some embodiments, the method may further include: depositing a capping layer on a bitline metal layer at a deposition temperature of about 350°C to about 400°C and depositing a hard mask layer on the capping layer at a deposition temperature greater than about 500°C; wherein the capping layer comprises one or more of silicon nitride or silicon carbonitride; wherein the capping layer is about 30 angstroms to about 50 angstroms; wherein the capping layer is deposited by chemical vapor deposition (CVD) or atomic layer deposition (ALD); wherein the hard mask layer comprises silicon nitride; wherein the hard mask layer is deposited using low-pressure chemical vapor deposition (LPCVD); depositing a hard mask layer on a bitline metal layer at a deposition temperature less than about 400°C; wherein the hard mask layer comprises silicon nitride; and / or depositing the hard mask layer using low-pressure chemical vapor deposition (LPCVD).

[0007] In some embodiments, the method of forming a memory structure may include: forming a barrier metal layer on a polysilicon layer on a substrate, annealing the barrier metal layer at a temperature of about 700 degrees Celsius to about 850 degrees Celsius, forming a barrier layer on the barrier metal layer, and forming a bit line metal layer on the barrier layer.

[0008] In some embodiments, the method may further include: wherein the barrier metal layer is a titanium layer of approximately 30 to approximately 50 angstroms formed on a polysilicon layer and a titanium nitride layer of approximately 15 to approximately 40 angstroms formed on the titanium layer; wherein the step of annealing the barrier metal layer forms a titanium silicide layer on the polysilicon layer; wherein the barrier layer is a titanium nitride layer of approximately 15 to approximately 40 angstroms; wherein the bit line metal layer is a grain growth metal layer; forming a capping layer on the bit line metal layer using chemical vapor deposition (CVD) or atomic layer deposition (ALD) at a deposition temperature of approximately 350 to approximately 400 degrees Celsius and forming a hard mask layer on the capping layer using low-pressure chemical vapor deposition (LPCVD) at a deposition temperature greater than approximately 500 degrees Celsius; wherein the capping layer is approximately 30 to approximately 50 angstroms; and / or forming a hard mask layer on the bit line metal layer using low-pressure chemical vapor deposition (LPCVD) at a deposition temperature less than approximately 400 degrees Celsius.

[0009] In some embodiments, a method for smoothing the top surface of the bit line metal of a memory structure may include: depositing a titanium layer of about 30 to about 50 angstroms on a polysilicon layer on a substrate using a plasma vapor deposition (PVD) chamber; annealing the substrate at a temperature of about 700 to about 850 degrees Celsius without vacuum disruption between the deposition of the titanium layer and the annealing of the substrate; depositing a titanium nitride layer of about 15 to about 40 angstroms on the annealed titanium layer; and depositing a ruthenium bit line metal layer on the titanium nitride layer.

[0010] In some embodiments, the method may further include: depositing a capping layer on the bit line metal layer at a deposition temperature of about 350 degrees Celsius to about 400 degrees Celsius and depositing a hard mask layer on the capping layer at a deposition temperature greater than about 500 degrees Celsius or depositing a hard mask layer on the bit line metal layer at a deposition temperature less than about 400 degrees Celsius.

[0011] Other and further implementation methods are disclosed below. Attached Figure Description

[0012] By referring to the exemplary embodiments of the invention illustrated in the accompanying drawings, one can understand the embodiments of the invention briefly summarized above and discussed in detail below. However, the drawings only illustrate typical embodiments of the invention and are therefore not intended to limit the scope of the invention, as other equivalent embodiments are permissible.

[0013] Figure 1A circuit diagram depicting a dynamic memory cell in a DRAM memory with improved properties according to certain embodiments of the present invention.

[0014] Figure 2 A cross-sectional view depicting a membrane stack according to certain embodiments of the present invention.

[0015] Figure 3 This is a method for forming film stacks according to certain embodiments of the present invention.

[0016] Figure 4 This is a method for forming a film stack with a smooth bit line metal layer according to certain embodiments of the present invention.

[0017] Figure 5 This is a cross-sectional view of a barrier metal layer according to certain embodiments of the present invention.

[0018] Figure 6 This is a top view of a clustering tool according to certain embodiments of the present invention.

[0019] Figure 7 A method for manufacturing a substrate according to certain embodiments of the present invention.

[0020] Figure 8 This is a cross-sectional view of a substrate according to certain embodiments of the present invention.

[0021] For ease of understanding, the same element symbols have been used to refer to common elements in the drawings wherever possible. The drawings are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be advantageously incorporated into other embodiments without further explanation. Detailed Implementation

[0022] Methods for bitline stacking and forming bitline stacks with reduced resistance and bitline surface roughness are provided. Despite the need for node reduction, one or more embodiments of the present invention advantageously address the problem of resistance reduction. In some embodiments, the resistance of the bitlines is reduced by providing a cleaner interface with existing bitline metals and by reducing the surface roughness of the bitline metals. Certain embodiments of the present invention advantageously provide one or more of the following: flexibility in selecting bitline metals; flexibility in the temperature of silicon nitride hard mask deposition; ensuring a clean metal-dielectric interface that results in lower resistance; or minimizing or eliminating the risk of contamination of the high-temperature silicon nitride hard mask deposition chamber through new bitline metals.

[0023] Some embodiments of the present invention provide a low-temperature deposition method using a capping layer to prevent roughening of the bitline metal surface when the selected metal exhibits grain growth characteristics. In some embodiments, a high-density, non-porous film is used as a good diffusion barrier at high temperatures. Some embodiments provide a dielectric material, such as silicon nitride (SiN) or silicon carbonitride (SiCN), as a capping layer to minimize or eliminate negative effects on the RC time constant by acting as a good diffusion barrier between the bitline metal and the SiN hard mask. Some embodiments include annealing the metal layer prior to the deposition of the grain growth metal to reduce the surface roughness of the grain growth metal and lower the resistance. The RC time constant is the time associated with charging a capacitor to a percentage of full charge through the resistance or discharging a capacitor to a portion of its initial voltage. The RC time constant is equal to the product of the circuit resistance and the circuit capacitance. Some embodiments of the present invention advantageously provide a low-temperature (e.g., <500°C) deposition process. Some embodiments provide a deposition process compatible with the underlying bitline metal to minimize or eliminate surface reactions during film deposition.

[0024] One or more embodiments of the present invention generally provide one or more low-resistance features formed of a thin-film refractory metal (e.g., tungsten) that can be implemented in bit line structures and / or gate stacks. Some embodiments include a method of forming a bit line stack. As an example, the bit line stack structure formed according to embodiments of the present invention can be a memory-type semiconductor device, such as a DRAM-type integrated circuit.

[0025] Figure 1 A schematic circuit diagram 100 illustrates a transistor and a capacitor cell that can be used in a DRAM memory. Figure 1 The memory cell depicted includes a storage capacitor 110 and a select transistor 120. The select transistor 120 is formed as a field-effect transistor and has a first source / drain electrode 121 and a second source / drain electrode 123. An active region 122 is disposed between the first source / drain electrode 121 and the second source / drain electrode 123. Above the active region 122 is a gate insulating layer or dielectric layer 124 (typically thermally grown oxide) and a gate electrode / metal 125 (referred to as a character line in a memory device). The gate insulating layer or dielectric layer 124 and the gate electrode / metal 125 together act as a parallel plate capacitor and can affect the charge density in the active region 122 to form or block a conductive channel between the first source / drain electrode 121 and the second source / drain electrode 123.

[0026] The second source / drain electrode 123 of the select transistor 120 is connected to the first electrode 111 of the storage capacitor 110 via a metal line 114. The second electrode 112 of the storage capacitor 110 is connected to a capacitor plate common to storage capacitors arranged with DRAM memory cells. The second electrode 112 of the storage capacitor 110 can be connected to electrical ground via a metal line 115. The first source / drain electrode 121 of the select transistor 120 is further connected to a bit line 116 so that information stored in the storage capacitor 110 can be written to and read from by charge formation. The write or read operation is controlled via a character line 117 or the gate electrode 125 of the select transistor 120 and the bit line 116 connected to the first source / drain electrode 121. The write or read operation occurs by applying a voltage to create a conductive channel in the active region 122 between the first source / drain electrode 121 and the second source / drain electrode 123.

[0027] Figure 2 A portion of a memory device 200 according to one or more embodiments of the present invention is illustrated. Figure 3 Drawing for forming Figure 2 An example processing method 300 of a memory device 200 is illustrated in the figure. Those skilled in the art will recognize that the film stack illustrated in the figure represents an example portion (bit line portion) of the memory device. (See also...) Figure 2 and Figure 3 The formation of the memory device 200 includes providing a substrate 210 in operation 310, on which a film stack 205 may be formed. As used in this specification and the appended claims, the term “provide” means to make the substrate available for processing (e.g., positioned in a processing chamber).

[0028] As used in this specification and the appended claims, the term "substrate" refers to the surface or part of the surface on which the processing can be performed. Those skilled in the art will also understand that "substrate" may refer only to a portion of the substrate unless the context clearly indicates otherwise. Furthermore, "deposition on a substrate" may mean both a bare substrate and a substrate having one or more films or features deposited or formed on it. As used herein, "substrate" refers to any substrate or material surface formed on a substrate, where film processing is performed over the substrate during manufacturing processes. For example, substrate surfaces on which processing can be performed include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates are not limited to semiconductor wafers. Substrates may be exposed to pretreatment processes such as polishing, etching, reduction, oxidation, hydroxylation, annealing, and / or baking of the substrate surface. In addition to film treatments performed directly on the substrate surface, any film treatment steps disclosed in this invention may also be performed on an underlying layer formed on the substrate, as will be described in more detail later, and the term "substrate surface" is intended to include this underlying layer as indicated by the context. Thus, for example, in the case where a film / layer or a portion of a film / layer has already been deposited on the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0029] In some embodiments, the provided substrate 210 includes a film stack 205, which includes a polysilicon layer 215 and a bit line metal layer 240. In some embodiments, the provided substrate 210, including the polysilicon layer 215 and the bit line metal layer 240, is formed in part of method 300. In some embodiments, the substrate 210 includes an oxide layer (not shown) on a silicon wafer. In some embodiments, the oxide layer is a native oxide formed on the silicon wafer. In some embodiments, the oxide layer is intentionally formed on the silicon wafer and has a thickness greater than that of the native oxide film. The oxide layer can be formed by any suitable technique known to those skilled in the art, including but not limited to thermal oxidation, plasma oxidation, and exposure to atmospheric conditions.

[0030] In some embodiments, the substrate 210 provided in operation 310 further includes a barrier metal layer 220 (also referred to as a conductive layer) on the polysilicon layer 215. The barrier metal layer 220 may be any suitable conductive material. In some embodiments, the barrier metal layer 220 comprises one or more of titanium (Ti), tantalum (Ta), titanium silicide (TiSi), or tantalum silicide (TaSi). In some embodiments, the barrier metal layer 220 comprises titanium. In some embodiments, the barrier metal layer 220 is substantially composed of titanium. In some embodiments, the barrier metal layer 220 comprises tantalum or is substantially composed of tantalum. In some embodiments, the barrier metal layer 220 comprises titanium silicide or is substantially composed of titanium silicide. In some embodiments, the barrier metal layer 220 comprises tantalum silicide or is substantially composed of tantalum silicide. When used in this manner, the term "substantially composed of" means that the host film contains, on an atomic basis, greater than or equal to about 95%, 98%, 99%, or 99.9% of the stated components or composition. For example, the barrier metal layer 220, which is essentially composed of titanium, has a film of deposited titanium of about 95%, 98%, 99%, or 99.5%.

[0031] In some embodiments, the substrate 210 provided in operation 310 further includes a barrier layer 230 on the conductive layer (barrier metal layer 220). The barrier layer 230 may be formed between the barrier metal layer 220 and the bit line metal layer 240. In some embodiments, method 300 includes operations prior to operation 310, which forms the bit line metal layer 240 on the barrier layer 230. The barrier layer 230 may be any suitable barrier layer material. In some embodiments, the barrier layer 230 comprises one or more nitrides or oxides of the barrier metal layer 220. In some embodiments, the barrier layer 230 is substantially composed of nitrides of the barrier metal layer 220. For example, a barrier layer 230 substantially composed of titanium nitride means a deposited barrier layer 230 in which the total composition of titanium and nitrogen atoms in the film is greater than or equal to about 95%, 98%, 99%, or 99.5% on an atomic basis.

[0032] In some embodiments, the barrier metal layer 220 comprises titanium (Ti) and the barrier layer 230 comprises titanium nitride (TiN). In some embodiments, the barrier metal layer 220 is substantially composed of titanium and the barrier layer 230 is substantially composed of titanium nitride. In one or more embodiments, the barrier metal layer 220 comprises a metal selected from one or more of cobalt (Co), copper (Cu), nickel (Ni), ruthenium (Ru), manganese (Mn), silver (Ag), gold (Au), platinum (Pt), iron (Fe), molybdenum (Mo), rhodium (Rh), titanium (Ti), tantalum (Ta), silicon (Si), or tungsten (W). In one or more embodiments, the barrier metal layer 220 (conductive material) comprises one or more of titanium (Ti), copper (Cu), cobalt (Co), tungsten (W), or ruthenium (Ru). In some embodiments, the barrier layer 230 comprises a nitride, oxynitride, carbide, or carbon oxide of the metal in the barrier metal layer 220. In some embodiments, the barrier metal layer 220 comprises tantalum or tantalum silicide (or is substantially composed of tantalum or tantalum silicide) and the barrier layer 230 comprises tantalum nitride (or is substantially composed of tantalum nitride). In some embodiments, the barrier metal layer 220 comprises titanium or titanium silicide (or is substantially composed of titanium or titanium silicide) and the barrier layer 230 comprises titanium nitride (or is substantially composed of titanium nitride).

[0033] In some embodiments, the bit line metal layer 240 is included in the substrate provided in operation 310 of method 300. The bit line metal layer 240 can be deposited by any suitable technique known to those skilled in the art. In some embodiments, the bit line metal layer 240 comprises one or more of tungsten (W), ruthenium (Ru), iridium (Ir), platinum (Pt), rhodium (Rh), or molybdenum (Mo). In some particular embodiments, the bit line metal layer 240 comprises one or more of ruthenium or tungsten or is substantially composed of one or more of ruthenium or tungsten. The thickness of the bit line metal layer 240 can vary. In some embodiments, the bit line metal layer 240 has a thickness ranging from approximately to approximately Or within a range of approximately to approximately Or within a range of approximately to approximately Or within a range of approximately to approximately The bit line metal layer 240 can be deposited using any suitable technique known to those skilled in the art. In some embodiments, the bit line metal layer 240 is deposited by one or more of chemical vapor deposition, atomic layer deposition, or physical vapor deposition.

[0034] In operation 320, a capping layer 250 is formed on the bit line metal layer 240. In some embodiments, the capping layer 250 is deposited at a lower temperature than is typically used for the formation of the subsequent hard mask layer 260. Without being limited to any particular theory of the operation, the inventors believe that the lower deposition temperature minimizes the diffusion of elements from the capping layer 250 into the bit line metal layer 240. In some embodiments, the inventors believe that the low-temperature deposition of the capping layer 250 minimizes grain growth at the interface of the bit line metal layer 240 and minimizes the effects of grain size and roughness on the resistance of the resulting bit line metal layer 240.

[0035] The capping layer 250 can be deposited using any suitable technique known to those skilled in the art. In some embodiments, the capping layer 250 is deposited by one or more of chemical vapor deposition or atomic layer deposition. In some embodiments, the capping layer 250 comprises the same compound as the subsequent hard mask 260. In some embodiments, the capping layer 250 comprises one or more of silicon nitride, silicon carbide nitride, or silicon carbide. In some embodiments, the capping layer 250 is substantially composed of silicon nitride. In some embodiments, the capping layer 250 is substantially composed of silicon carbide nitride. In some embodiments, the capping layer 250 is substantially composed of silicon carbide. The thickness of the capping layer 250 can be varied to minimize the impact of the high temperatures formed by the hard mask 260. In some embodiments, the capping layer 250 has a thickness in the range of approximately to approximately The deposition temperature of the capping layer 250 can be controlled to, for example, maintain the thermal budget of the formed apparatus. In some embodiments, the capping layer 250 is formed at a temperature less than or equal to about 500°C, or about 450°C, or about 400°C, or about 350°C, or about 300°C. In some embodiments, the capping layer 250 is formed at a temperature ranging from about 350°C to about 550°C, or ranging from about 400°C to about 500°C.

[0036] In operation 330, a hard mask 260 is formed on the capping layer 250. In some embodiments, the hard mask 260 is formed in a furnace at a temperature greater than about 500°C, about 600°C, about 650°C, about 700°C, or about 750°C. In some embodiments, the hard mask 260 comprises the same composition as the capping layer 250. In some embodiments, both the capping layer 250 and the hard mask 260 comprise silicon nitride, silicon oxide, or silicon nitride, or are substantially composed of silicon nitride, silicon oxide, or silicon nitride. In some embodiments, the hard mask 260 has a different density than the capping layer 250. In some embodiments, the hard mask 260 has a different porosity than the capping layer 250. In some embodiments, the hard mask 260 has a different deposition temperature than the capping layer 250.

[0037] In some embodiments, the bit line metal layer 240 comprises or is substantially composed of tungsten, and one or more of the capping layer 250 or hard mask 260 comprises or is substantially composed of silicon nitride. In some embodiments, the bit line metal layer 240 comprises or is substantially composed of ruthenium, and one or more of the capping layer 250 or hard mask 260 comprises or is substantially composed of silicon oxide or silicon nitride. In some embodiments, elements of the hard mask 260 are substantially prevented from migrating into the bit line metal layer 240. For example, if the hard mask 260 comprises silicon and nitrogen atoms, the silicon or nitrogen atoms are substantially prevented from migrating into the bit line metal layer 240. When used in this manner, the term "substantially prevented" means that less than or equal to about 10% or 5% of the elements of the hard mask 260 migrate through the capping layer 250 into the bit line metal layer 240.

[0038] The inventors have discovered that when the grain growth metal is annealed before the formation of the cap layer 250 to reduce resistance, this annealing silicides the underlying barrier metal layer 220. Furthermore, silicon diffuses into the barrier layer 230. The additional stress caused by the annealing of the grain growth metal causes the surface 232 of the barrier layer 230 to crack. When the grain growth metal of the bit line metal layer 240 grows on the cracked surface of the barrier layer 230, the cracked surface of the barrier layer 230 causes the bit line metal layer 240 to also have a rough top surface 242. The roughness of the top surface 242 of the bit line metal layer 240 directly affects the resistance of the bit line metal layer 240. The inventors have discovered that by annealing the barrier metal layer 220 before the formation of the barrier layer 230, the silicide effect caused by the annealing of the grain growth metal of the bit line metal layer 240 is significantly reduced or eliminated, allowing for a smoother top surface 242 of the bit line metal layer 240 and reducing resistance.

[0039] Figure 4 This is a method 400 for forming a film stack with a smooth bit line metal layer 240. In operation 402, a barrier metal layer 220 is formed on a polysilicon layer 215 on a substrate 210. In some embodiments, the barrier metal layer 220 is formed by first depositing a conductive material 502 of about 30 to about 50 angstroms (e.g., titanium, tantalum, etc.) and then depositing an oxygen barrier layer 504 of about 15 to about 40 angstroms (see [link to documentation]). Figure 5 (View 500). In the process of using separate chambers for deposition and annealing, the substrate 210 is exposed to the atmosphere when transferred between chambers. While the substrate 210 is being transferred, an oxygen barrier layer 504 (e.g., titanium nitride, tantalum nitride, etc.) prevents the conductive material 502 from oxidizing. In some embodiments, such as... Figure 6The illustrated integrated tool 600 can be used to provide a process without an air break between deposition and annealing operations. In the embodiment with integrated tool 600, because the substrate is never exposed to the atmosphere and the deposited conductive material 502 is not oxidized, the oxygen barrier layer 504 can be removed during the deposition process.

[0040] In operation 404, the barrier metal layer 220 is annealed at a temperature of approximately 700°C to approximately 850°C. The temperature may vary depending on the composition of the barrier metal layer 220. During the annealing of the barrier metal layer 220, the conductive material 502 is silicided, and the oxygen barrier layer 504 allows silicon to migrate through the oxygen barrier layer 504, causing the surface 506 to crack. In operation 406, a barrier layer 230 is formed on the barrier metal layer 220. The thickness of the barrier layer 230 may be approximately 15 angstroms to approximately 40 angstroms. The deposition of the barrier layer 230 blocks defects on the surface 506, helping to reduce roughness and resistance. The barrier layer 230 may contain, for example, a nitride variant of the conductive material 502 used in the barrier metal layer 220. In operation 408, a bit line metal layer 240 is formed on the barrier layer 230. The bit line metal layer 240 contains grain-grown metal grown on the surface of the barrier layer 230. When grain growth is complete, the annealed metal layer 240 is applied as described above.

[0041] In operation 410, the capping layer 250 may optionally be formed on the bitline metal layer 240 at a temperature of approximately 350°C to approximately 400°C. The low processing temperature helps maintain the thermal budget of the film stack 205 and reduces the surface roughness of the bitline metal layer. The inventors have found that if the temperature is too low, the density of the capping layer 250 will be insufficient, and if the temperature is too high, the surface roughness of the bitline metal layer will increase. The temperature also depends on the bitline metal layer material and is therefore adjusted. In operation 412, when the capping layer 250 is present, the hard mask 260 is formed on the capping layer 250 at a temperature of approximately 650°C as described above. If the capping layer is not present, the hard mask 260 may be formed at a temperature below 400°C to maintain the thermal budget of the film stack 205. Due to the increased deposition time of the hard mask layer 260 (e.g., the hard mask can be about 1350 angstroms thick) and lower density, the lower temperature used to form the hard mask layer 260 when the capping layer 250 is not present is a tradeoff.

[0042] The methods described herein, which are performed in a separate processing chamber, can also be performed in a cluster tool, such as Cluster Tool 600 or later. Figure 6 The integrated tool described above. The advantage of using cluster tool 600 is that there is no vacuum disruption between deposition and processing, and no substantial processing delay. Examples of cluster tool 600 include... The integrated tooling is available from Applied Materials, Inc., Santa Clara, California. However, the methods described herein can be implemented using other clustering tools with suitable processing chambers or in other suitable processing chambers. For example, in some embodiments, the inventive methods described above can be advantageously performed in a clustering tool such that there is no vacuum disruption between processes. For example, eliminating vacuum disruption can limit or prevent substrate contamination (oxidation) between processes.

[0043] Figure 6 This is a diagram illustrating a clustering tool 600 used for substrate fabrication, such as post-polyplug fabrication. The clustering tool 600 includes one or more vacuum transfer modules (VTMs). Figure 6 The diagram shows VTM 601 and VTM 602), front-end module 604, multiple processing chambers / modules 606, 608, 610, 612, 614, 616, and 618, and processing controller 620 (controller 620). In embodiments with more than one VTM, such as Figure 6 As shown, one or more through-chambers can be provided to facilitate vacuum transfer from one VTM to another. In conjunction with... Figure 6 In the corresponding embodiment, two through-cavities may be provided (e.g., through-cavity 640 and through-cavity 642). The front-end module 604 includes a loading port 622 configured to receive one or more substrates, such as from a FOUP (Front-Open Wafer Container) or other suitable substrate-containing box or carrier, which will be processed using clustering tool 600. Loading port 622 may include three loading areas 624a-624c, which can be used to load one or more substrates. However, more or fewer loading areas may be used.

[0044] Front-end module 604 includes an atmospheric transfer module (ATM) 626 for transferring substrates that have been loaded into loading port 622. More specifically, 626 includes one or more robotic arms 628 (shown as dummy structures) configured to transfer substrates from loading areas 624a-624c through a door 635 (shown as dummy structures) to the ATM 626, which connects the ATM 626 to the loading port 622. Each loading port (624a-624c) typically has a door to allow substrates to be transferred from the corresponding loading port to the ATM 626. Robotic arm 628 is also configured to move the base plate from ATM 626 through doors 632 (shown as dummy structures, one door for each airlock) to airlocks 630a and 630b, with doors 632 connecting ATM 626 to airlocks 630a and 630b. The number of airlocks may be more or less than two, but for illustrative purposes only, two airlocks (630a and 630b) are shown, each with a door to connect to the airlock to ATM 626.

[0045] Under the control of controller 620, airlocks 630a and 630b can be maintained in an atmospheric pressure environment or a vacuum pressure environment, and serve as intermediate or temporary holding spaces for transfer to / from VTMs 601 and 602. VTM 601 includes a robotic arm 638 (shown as a dummy structure) configured to transfer the substrate from airlocks 630a and 630b to one or more of the plurality of processing chambers 606 and 608 or to one or more through chambers 640 and 642 without vacuum disruption, i.e., simultaneously maintaining the vacuum pressure environment within VTM 602 and the plurality of processing chambers 606 and 608 and through chambers 640 and 642. VTM 602 includes a robotic arm 638 (shown as a dummy structure) configured to transfer a substrate from airlocks 630a and 630b to one or more of a plurality of processing chambers 606, 608, 610, 612, 614, 616, and 618 without vacuum disruption, i.e., simultaneously maintaining a vacuum pressure environment within VTM 602 and the plurality of processing chambers 606, 608, 610, 612, 614, 616, and 618. In a particular embodiment, airlocks 630a and 630b may be omitted, and controller 620 may be configured to move the substrate directly from ATM 626 to VTM 602.

[0046] For example, slit valve gate 634 connects each of the respective airlocks 630a, 630b to VTM 601. Similarly, slit valve gate 636 connects each processing module to VTM, with each processing module coupled to VTM (e.g., VTM 601 or VTM 602). Multiple processing chambers 606, 608, 610, 612, 614, 616, and 618 are configured to perform one or more processes, as described herein, typically relating to post-substrate polysilicon plug fabrication.

[0047] The controller 620 controls all operations of the cluster tool 600 and includes a memory 621 to store data or instructions / instructions regarding the operation of the cluster tool 600. For example, the controller 620 controls the respective robotic arms 628, 638, and 639 of the ATM 626, VTM 601, and VTM 602 for transferring substrates to / from VTM 601 and between VTM 601 and VTM 602. The controller 620 controls the opening and closing of doors 632, 634, and 636, and controls the pressure of airlocks 630a and 630b, for example, maintaining an atmospheric pressure / vacuum pressure environment within airlocks 630a and 630b when either substrate transfer processing is desired. The controller 620 also controls the operation of the individual processing chambers 606, 608, 610, 612, 614, 616, and 618 to perform operations related to the individual processing chambers 606, 608, 610, 612, 614, 616, and 618, as will be described in more detail later.

[0048] Figure 7 This describes a method for using Cluster Tool 600 to perform one or more DRAM bit line stacking processes followed by polysilicon plug fabrication. (For illustrative purposes only.) Figure 8 This shows a cross-sectional view of a portion of a substrate 800 including a polycrystalline plug, for example, after the polycrystalline plug 802 has been formed on the substrate 800 outside the clustering tool 600. During execution Figure 7 Prior to this method, substrate 800 can be loaded into loading port 622 via one or more loading areas 624a-624c. Under the control of controller 620, robotic arm 628 of ATM 626 can transfer substrate 800 with polysilicon plug 802 from loading area 624a to ATM 626.

[0049] Depending on whether one or both of airlocks 630a and 630b are used, controller 620 can determine whether at least one of airlocks 630a and 630b is in an atmospheric pressure environment. For illustration, it is assumed that only airlock 630a is used. If controller 620 determines that airlock 630a is in an atmospheric pressure environment, controller 620 can open the door (part 632) connecting ATM 626 to airlock 630a. Conversely, if controller 620 determines that airlock 630a is not in an atmospheric pressure environment, controller 620 can adjust the pressure within airlock 630a to an atmospheric pressure environment (e.g., via a pressure control valve operably connected to airlocks 630a and 630b and controllable by controller 620), and can reconfirm the pressure within airlock 630a. The controller can instruct the robotic arm 628 to move the substrate 800 from the ATM 626 to the airlock 630a, close the door 632, and adjust the pressure inside the airlock 630a to a vacuum pressure environment, such as matching or substantially matching the vacuum pressure environment inside the VTM 601.

[0050] Controller 620 can determine whether airlock 630a is in a vacuum pressure environment. If controller 620 determines that airlock 630a is in a vacuum pressure environment, controller 620 can open door 634 connecting VTM 601 to airlock 630a. Conversely, if controller 620 determines that airlock 630a is not in a vacuum pressure environment, controller 620 can adjust the pressure inside airlock 630a to a vacuum pressure environment (e.g., via a pressure control valve operably connected to airlocks 630a and 630b and controllable by controller 620), and reconfirm the pressure inside airlock 630a.

[0051] The controller 620 controls the operation of the tool 600 either directly from the processing chamber or via a computer (or controller) associated with the processing chamber and the tool 600. During operation, the controller 620 can collect and receive feedback from the relevant chamber and system data to optimize the performance of the tool 600. The controller 620 typically includes a central processing unit (CPU) 619, memory 621, and support circuitry 625. The CPU 619 can be any type of general-purpose computer processor used in industrial settings. The support circuitry 625 is conventionally coupled to the CPU 619 and may include cache, clock circuitry, input / output subsystems, power supply, and the like. Software programs, such as those stored in memory 621, which, when executed by the CPU 619, transform the CPU 619 into a specific target computer (controller 620). Software programs can also be stored and / or executed via a second controller (not shown), located remotely to the tool 600.

[0052] Memory 621 is in the form of a computer-readable storage medium containing instructions that, when executed by CPU 619, cause semiconductor processing and device operation. The instructions in memory 621 are in the form of a program product, such as a program that performs the methods of the present invention. The program code may conform to any of several different programming languages. In one instance, the present invention can be implemented as a program product stored on a computer-readable storage medium for use by a computer system. The program product defines the function of the scheme (including the methods described herein). Examples of computer-readable storage media include, but are not limited to: non-writable storage media (e.g., read-only memory devices within a computer, such as CD-ROM discs readable by a CD-ROM drive, flash memory, ROM chips, or any type of solid-state non-volatile semiconductor memory), in which information is permanently stored; and writable storage media (e.g., floppy disks or hard disk drives within a disk drive or any type of solid-state random access semiconductor memory), in which variable information is stored. Such computer-readable storage media are aspects of the present invention when computer-readable instructions instructing the functions described herein are executed.

[0053] In operation 700, controller 620 instructs robotic arm 638 to move substrate 800 from airlock 630a through door 634 to VTM 601 and close door 634. Alternatively, door 634 may remain open, for example, to receive outward-facing substrates after processing within cluster tool 600 is complete. In operation 702, controller 620 instructs robotic arm 638 to move substrate 800 into one or more processing chambers such that processing of the substrate can be completed – i.e., completion of bit line stacking processing on top of polysilicon plugs 802 on substrate 800. For example, in operation 702, controller 620 may instruct robotic arm 638 to open door 636 corresponding to processing chamber 606. Once activated, controller 620 can instruct robotic arm 638 to transfer substrate 800 to a pre-cleaning chamber (e.g., processing chamber 606) (without vacuum disruption, i.e., the vacuum pressure environment is maintained in VTMs 601 and 602, while transferring substrate 800 between processing chambers 606, 608, 610, 612, and 614). Processing chamber 606 can be used to perform one or more pre-cleaning processes to remove contaminants that may be present on substrate 800, such as native oxides that may be present on substrate 800. One such pre-cleaning chamber is a SiCoNi™ processing tool, commercially available from Applied Materials, Inc., Santa Clara, California.

[0054] Next, in operation 704, controller 620 opens door 636 and instructs robotic arm 638 to move substrate 800 to the next processing chamber. For example, in operation 704, controller 620 may instruct robotic arm 638 to move substrate 800 from pre-cleaning chamber to barrier metal deposition chamber without vacuum disruption. For example, controller 620 may instruct robotic arm 638 to move substrate from processing chamber 606 to, for example, processing chamber 608 under vacuum. Processing chamber 608 is configured to perform barrier metal deposition on substrate 800 (e.g., depositing barrier metal 804 on top of clean substrate 800 and polysilicon plug 802). The barrier metal may be either titanium (Ti) or tantalum (Ta).

[0055] Next, in operation 706, controller 620 may instruct robotic arm 638 to transfer substrate 800 from the barrier metal deposition chamber to the barrier layer deposition chamber or annealing chamber without vacuum disruption. If substrate 800 is transferred to the annealing chamber, substrate 800 is brought back to the barrier metal deposition chamber for anti-oxidation deposition (e.g., a nitride variant of the barrier metal). After the barrier metal deposition chamber, substrate 800 is transferred to the barrier layer deposition chamber. For example, controller 620 may instruct robotic arm 638 to transfer substrate from processing chamber 608 to either of through chambers 640, 642 under vacuum, where robotic arm 639 within VTM 602 can pick up substrate 800 and move it to, for example, processing chamber 610. Processing chamber 610 is configured to perform a barrier layer deposition process on substrate 800 (e.g., depositing a barrier layer 806 on top of barrier metal 804). The barrier layer can be one of titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN).

[0056] Next, in operation 708, controller 620 may instruct robotic arm 639 to transfer substrate 800 from processing chamber 610 to, for example, processing chamber 612 without vacuum disruption. Processing chamber 612 is configured to perform bit line metal deposition on substrate 800 (e.g., depositing a bit line metal layer 808 on top of the barrier layer 806 deposited in operation 706). The bit line metal may be one of tungsten (W), molybdenum (Mo), ruthenium (Ru), iridium (Ir), or rhodium (Rh). Next, in operation 710, controller 620 may instruct robotic arm 639 to transfer substrate 800 from processing chamber 612 to, for example, processing chamber 614 without vacuum disruption. Processing chamber 614 is configured to perform hard mask deposition on substrate 800 (e.g., depositing a hard mask layer 810 on top of the bit line metal layer 808 deposited in operation 708). The hard mask can be one of silicon nitride (SiN), silicon oxide (SiO) or silicon carbide (SiC).

[0057] In some embodiments, an annealing process may be performed on the substrate 800 before or after the deposition of the barrier layer 806, as shown in operation 705. The annealing process can be any suitable annealing process, such as rapid thermal processing (RTP) annealing. For example, the substrate 800 may first be transferred to a processing chamber 616 before being transferred from processing chamber 608 to processing chamber 610. Processing chamber 616 is configured to perform the annealing process on the substrate 800. After the annealing process, the annealed substrate 800, including the barrier layer 806, may be transferred under vacuum, for example using a robotic arm 639, from the annealing chamber (e.g., processing chamber 616) to the barrier layer deposition chamber (e.g., processing chamber 610).

[0058] Alternatively or in combination, an annealing process may be performed on the substrate 800 after the deposition of the bit line metal layer 808 and before the deposition of the hard mask layer 810 on top of the bit line metal layer 808, as shown in operation 709a. For example, the substrate 800 may first be transferred to the processing chamber 616 (i.e., the annealing chamber) before being transferred from the processing chamber 612 to the processing chamber 614. The annealing process or another annealing process (if the annealing in operation 705 has been performed prior) may be performed on the substrate 800 having the bit line metal layer 808 deposited on the substrate 800 as described above. In some embodiments where the annealing process is performed in operation 709a, the annealed substrate 800 may be transferred to another processing chamber to have an optional capping layer 809 deposited on the bit line metal layer 808, as shown in operation 709b. For example, an annealed substrate 800 including bit line metal layer 808 can be transferred under vacuum from an annealing chamber (e.g., processing chamber 616) to a capping deposition chamber (e.g., processing chamber 618), for example, using a robotic arm 639 to deposit a capping layer on top of the annealed bit line metal layer 808.

[0059] In some embodiments, a metal such as ruthenium (Ru) is used as the grain growth material after the deposition of the bitline metal. The inventors have observed that subsequent deposition of a hard mask layer on top of this bitline metal at high temperatures undesirably results in poor surface roughness. The inventors have found that annealing the bitline metal layer after the deposition of a low-temperature capping layer and before the deposition of the hard mask layer advantageously improves the surface roughness of the bitline metal layer. Oxidation of the bitline metal during annealing for grain growth is further advantageously avoided by performing each of the above sequences in an integrated tool (e.g., cluster tool 600).

[0060] Additional processing not disclosed herein may also be performed on substrate 800, or some of the processing described herein may be omitted.

[0061] After the aforementioned processing of chambers 608, 610, 612, and 614 (and chambers 616 and 618, if used) has been performed on substrate 800, substrate 800 is transferred from VTM 602 back to loading port 622, for example, by using robotic arm 639 in VTM 602 to transfer substrate 800 to through chambers 640 and 642, and by using robotic arm 638 in VTM 601 to transfer substrate 800 from through chambers 640 and 642 to one of airlocks 630a and 630b. Robotic arm 628 may then be used to return substrate 800 to an empty slot in the FOUP in loading port 622.

[0062] The clustering tool 600 and its usage method described herein advantageously allow users to perform multiple DRAM bit line processes on a polysilicon plug using a single machine, which is configured to maintain a vacuum pressure environment throughout the DRAM bit line process. Therefore, the possibility of oxidation occurring on the substrate during the subsequent substrate 800 manufacturing process is reduced (if not eliminated). Furthermore, because a vacuum pressure environment is maintained throughout the DRAM bit line process, the choice of bit line metal material is not limited by the grain growth characteristics of the metal.

[0063] The use of the terms “a” and “an” and “described” and similar indicative terms in the context of the materials and methods described herein (especially in the context of the following claims) is to be construed as covering both single and multiple, unless clearly indicated in the context that this is not the case. Descriptions of numerical ranges herein are intended only as shorthand methods of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated into the specification as if it were mentioned separately herein. All methods described herein may be performed in any suitable order, unless otherwise indicated herein or clearly contradicted in the context. The use of any or all instances of language provided herein, or exemplary language (e.g., “such as”), is intended only to preferably describe the materials and methods and does not limit their scope, unless otherwise stated. No language in the specification should be construed as indicating that any non-declared component is necessary for the implementation of the disclosed materials and methods.

[0064] Throughout this specification, the references to "one embodiment," "some embodiments," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. Therefore, phrases such as "in one or more embodiments," "in some embodiments," "in one embodiment," or "in an embodiment" appearing in various places throughout this specification do not necessarily refer to the same embodiment of the invention. Furthermore, in one or more embodiments, the particular feature, structure, material, or characteristic may be combined in any suitable manner.

[0065] While the invention has been described herein with reference to specific embodiments, these embodiments are merely examples of the principles and applications of the invention. Those skilled in the art will understand that various modifications and variations can be made to the methods and apparatus of the invention without departing from the spirit and scope thereof. Therefore, the invention includes modifications and variations within the scope of the appended claims and their equivalents.

[0066] Embodiments of the invention can be implemented in hardware, firmware, software, or any combination of the foregoing. Embodiments can also be implemented as if instructions were stored using one or more computer-readable media, which can be read and executed by one or more processors. The computer-readable media may include any mechanism for storing or transferring information in a machine-readable form (e.g., a computing platform or a “virtual machine” implemented on one or more computing platforms). For example, the computer-readable media may include any suitable form of volatile or non-volatile memory. In some embodiments, the computer-readable media may include non-transitory computer-readable media.

[0067] Although the foregoing describes embodiments of the present invention, other and further embodiments of the present invention may be conceived without departing from the basic scope of the present invention.

Claims

1. A method for forming a memory structure, comprising: The roughness of the top surface of the bit line metal layer is reduced by the following steps: A titanium layer of 30 to 50 angstroms is deposited on a polycrystalline silicon layer on a substrate; A first titanium nitride layer of 15 to 40 angstroms is deposited on the titanium layer; Annealing the substrate, wherein the annealing is configured to reduce the roughness of the top surface of the bit line metal layer by reducing the silicide effect caused by subsequent annealing of the grain growth metal of the bit line metal layer; A second titanium nitride layer of 15 to 40 angstroms is deposited on the first titanium nitride layer after annealing; and The bit line metal layer is deposited on the second titanium nitride layer, wherein the grain growth metal of the bit line metal layer is ruthenium.

2. The method of claim 1, further comprising: A capping layer is deposited on the bitline metal layer at a deposition temperature of 350°C to 400°C; and A hard mask layer is deposited on the cap layer at a deposition temperature greater than 500 degrees Celsius.

3. The method of claim 2, wherein the capping layer comprises one or more of silicon nitride or silicon carbonitride.

4. The method of claim 2, wherein the capping layer is 30 to 50 angstroms.

5. The method of claim 2, wherein the capping layer is deposited by chemical vapor deposition (CVD) or atomic layer deposition (ALD).

6. The method of claim 2, wherein the hard mask layer comprises silicon nitride.

7. The method of claim 2, wherein the hard mask layer is deposited using low-pressure chemical vapor deposition (LPCVD).

8. The method of claim 1, further comprising the following steps: A hard mask layer is deposited on the bit line metal layer at a deposition temperature of less than 400 degrees Celsius.

9. The method of claim 8, wherein the hard mask layer comprises silicon nitride deposited using low-pressure chemical vapor deposition (LPCVD).

10. The method of claim 1, wherein the annealing is performed at a temperature of 700°C to 850°C.

11. A method for forming a memory structure, comprising: The roughness of the top surface of the bit line metal layer is reduced by the following steps: A barrier metal layer is formed on the polysilicon layer on the substrate; Annealing the barrier metal layer, wherein the annealing is configured to reduce the roughness of the top surface of the bit line metal layer by reducing the silicide effect caused by subsequent annealing of the grain growth metal of the bit line metal layer; A barrier layer is formed on the barrier metal layer; and The bit line metal layer is formed on the barrier layer, wherein the grain growth metal of the bit line metal layer is ruthenium.

12. The method of claim 11, wherein the barrier metal layer is a 30 to 50 angstrom titanium layer formed on the polycrystalline silicon layer and a 15 to 40 angstrom titanium nitride layer formed on the titanium layer.

13. The method of claim 12, wherein annealing the barrier metal layer forms a titanium silicide layer on the polycrystalline silicon layer.

14. The method of claim 11, wherein the barrier layer is a titanium nitride layer of 15 to 40 angstroms.

15. The method of claim 11, wherein the annealing is performed at a temperature of 700°C to 850°C.

16. The method of claim 11, further comprising the following steps: A capping layer is formed on the bitline metal layer using chemical vapor deposition (CVD) or atomic layer deposition (ALD) at a deposition temperature of 350°C to 400°C; and A hard mask layer is formed on the capping layer using low-pressure chemical vapor deposition (LPCVD) at a deposition temperature greater than 500 degrees Celsius.

17. The method of claim 16, wherein the capping layer is 30 to 50 angstroms.

18. The method of claim 11, further comprising the following steps: A hard mask layer was deposited on the bit line metal layer using low-pressure chemical vapor deposition (LPCVD) at a deposition temperature of less than 400 degrees Celsius.

19. A method for forming a memory structure, comprising: The roughness of the top surface of the bit line metal layer is reduced by the following steps: A titanium layer of 30 to 50 angstroms is deposited on a polycrystalline silicon layer on a substrate using a plasma vapor deposition (PVD) chamber; The substrate is annealed without vacuum disruption between the deposition of the titanium layer and the annealing of the substrate, wherein the annealing is configured to reduce the roughness of the top surface of the bit line metal layer by reducing the silicide effect caused by subsequent annealing of the grain growth metal of the bit line metal layer. A titanium nitride layer of 15 to 40 angstroms is deposited on the annealed titanium layer; and A ruthenium bitline metal layer is deposited on the titanium nitride layer, wherein the grain growth metal of the bitline metal layer is ruthenium.

20. The method of claim 19, further comprising: A capping layer is deposited on the bitline metal layer at a deposition temperature of 350°C to 400°C, and a hard mask layer is deposited on the capping layer at a deposition temperature greater than 500°C; or A hard mask layer is deposited on the bit line metal layer at a deposition temperature of less than 400 degrees Celsius.

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