Three-dimensional memory device with dielectric wall support structure and method for forming the same

Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and conductive layers positioned between linear trenches, a first memory array region and a second memory array region, and a pair of dielectric wall structures positioned between the first and second linear trenches and between the memory array regions. Each layer within the alternating stack extends continuously between the first and second memory array regions in a connection region. The conductive layers of the alternating stack have a lateral extent that decreases with distance from the substrate in a stepped region. Dielectric material plates interleaved with insulating plates or layers are provided between the dielectric wall structures.

Description

[0001] Related applications

[0002] This application claims the benefit of priority to U.S. non-provisional application No. 17 / 039,160, filed on September 30, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to the field of semiconductor devices, and in particular to a three-dimensional memory device including a dielectric wall support structure and a method of forming the same. Background Art

[0004] A three-dimensional memory device including three-dimensional vertical NAND strings with one bit per cell is disclosed in T. Endoh et al., “Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell,” IEDM Proc. (2001) 33-36. Summary of the Invention

[0005] According to an embodiment of the present disclosure, a three-dimensional memory device includes: an alternating stack of insulating layers and conductive layers, the alternating stack located between first and second line trenches, the first and second line trenches extending laterally in a first horizontal direction and above a substrate; a first memory array region and a second memory array region, the first and second memory array regions being laterally spaced apart in the first horizontal direction and including each layer of the alternating stack, wherein a corresponding set of memory stack structures, each including a vertical semiconductor channel and a memory film, extends vertically through the alternating stack within each of the first and second memory array regions; a first and second dielectric wall structures, the first and second dielectric wall structures located between the first and second line trenches and located between the first memory array region and the second memory array region, extending laterally in a first horizontal direction and having a lateral extent less than the lateral extent of the first and second line trenches, wherein a connection region is located between the first line trenches and the first dielectric wall structure, and each layer within the alternating stack extends continuously between the first and second memory array regions in the connection region, and a step region is located between the second line trenches and the second dielectric wall structure, and the alternating stack of conductive layers has a lateral extent that decreases with distance from the substrate in the first horizontal direction; and an alternating stack of dielectric material plates and insulating plates or layers, the alternating stack being located between the first and second dielectric wall structures, wherein the dielectric material plates have a horizontal cross-sectional area that decreases with vertical distance from the substrate.

[0006] According to another aspect of the present disclosure, a three-dimensional memory device includes: an alternating stack of insulating layers and conductive layers, the alternating stack being located between first and second line trenches, the first and second line trenches extending laterally in a first horizontal direction and above a substrate;

[0007] a first memory array region and a second memory array region, the first memory array region and the second memory array region being laterally spaced apart along a first horizontal direction and comprising each layer of the alternating stack, wherein a respective set of memory stack structures, each including a vertical semiconductor channel and a memory film, extends vertically through the alternating stack within each of the first memory array region and the second memory array region; at least one dielectric wall structure, the at least one dielectric wall structure being located between the first-line trench and the second-line trench and between the first memory array region and the second memory array region, extending through all layers of the alternating stack, extending laterally along the first horizontal direction, having a lateral extent smaller than a lateral extent of the first-line trench and the second-line trench along the first horizontal direction, and having a length along the first horizontal direction that is at least three times its width extending along a second horizontal direction perpendicular to the first horizontal direction; and a staircase region being located between the second-line trench and the at least one dielectric wall structure, and the conductive layers of the alternating stack having a lateral extent that decreases with distance from the substrate along the first horizontal direction in the staircase region.

[0008] According to another aspect of the present disclosure, a method for forming a three-dimensional memory device is provided, the method comprising: forming an alternating layer stack of a continuous insulating layer and a continuous sacrificial material layer; forming a stepped surface below a stepped cavity by patterning the alternating layer stack in an inter-array region between a first memory array region and a second memory array region; forming a dielectric cavity filling material portion above the stepped surface of the alternating layer stack; forming a first dielectric wall structure and a second dielectric wall structure, the first dielectric wall structure and the second dielectric wall structure extending laterally in a first horizontal direction through the alternating layer stack and the dielectric cavity filling material portion in the inter-array region, wherein the dielectric cavity filling The material portion is divided into a rearward stepped dielectric material portion covering the stepped surface of the alternating layer stack and a dielectric filler material portion located between the first dielectric wall structure and the second dielectric wall structure; forming a first linear trench and a second linear trench through the alternating layer stack, wherein the first linear trench and the second linear trench extend laterally along a first horizontal direction and are laterally spaced apart by the first dielectric wall structure and the second dielectric wall structure along a second horizontal direction; and replacing a remaining portion of the continuous sacrificial material layer outside the area between the first dielectric wall structure and the second dielectric wall structure with a conductive layer, wherein the remaining portion of the continuous sacrificial material layer within the area between the first dielectric wall structure and the second dielectric wall structure comprises a stack of dielectric material plates. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a plan view of an exemplary semiconductor die including multiple three-dimensional memory array regions according to an embodiment of the present disclosure.

[0010] Figure 2 is a vertical cross-sectional view of an exemplary structure for forming a semiconductor die after forming an optional semiconductor device, an optional lower level dielectric layer, an optional lower metal interconnect structure, a semiconductor material layer, and a first alternating layer stack of a first continuous insulating layer and a first continuous sacrificial material layer in accordance with an embodiment of the present disclosure.

[0011] Figure 3A is a vertical cross-sectional view of an exemplary structure after forming a first layer of dielectric cavity fill material portion according to an embodiment of the present disclosure.

[0012] Figure 3B yes Figure 3A The top cross-sectional view of the exemplary structure of FIG. The hinged vertical plane AA' is Figure 3A A vertical section of a plane.

[0013] Figure 3C It is along Figure 3B A vertical cross-sectional view taken along the vertical plane C-C'.

[0014] Figure 3D It is along Figure 3B A vertical cross-sectional view taken along the vertical plane D-D'.

[0015] Figure 3E It is along Figure 3B A vertical cross-sectional view taken along the vertical plane EE'.

[0016] Figure 3F It is along Figure 3B A vertical cross-sectional view taken along the vertical plane F-F'.

[0017] Figure 4A is a vertical cross-sectional view of an exemplary structure after forming a first layer of moat trenches according to an embodiment of the present disclosure.

[0018] Figure 4B yes Figure 4A The top cross-sectional view of the exemplary structure of FIG. The hinged vertical plane AA' is Figure 4A A vertical section of a plane.

[0019] Figure 4C It is along Figure 4B A vertical cross-sectional view taken along the vertical plane C-C'.

[0020] Figure 4D It is along Figure 4B A vertical cross-sectional view taken along the vertical plane D-D'.

[0021] Figure 4E It is along Figure 4B A vertical cross-sectional view taken along the vertical plane EE'.

[0022] Figure 5A is a vertical cross-sectional view of an exemplary structure after forming a first-layer moat-shaped dielectric wall structure according to an embodiment of the present disclosure.

[0023] Figure 5B yes Figure 5A The top cross-sectional view of the exemplary structure of FIG. The hinged vertical plane AA' is Figure 5A A vertical section of a plane.

[0024] Figure 5C It is along Figure 5B A vertical cross-sectional view taken along the vertical plane C-C'.

[0025] Figure 5D It is along Figure 5B A vertical cross-sectional view taken along the vertical plane D-D'.

[0026] Figure 5E It is along Figure 5B A vertical cross-sectional view taken along the vertical plane EE'.

[0027] Figure 6A is a vertical cross-sectional view of an exemplary structure after forming a first-level memory opening filling structure and a first-level support pillar structure according to an embodiment of the present disclosure.

[0028] Figure 6B yes Figure 6A The top cross-sectional view of the exemplary structure of FIG. The hinged vertical plane AA' is Figure 6A A vertical section of a plane.

[0029] Figure 6C It is along Figure 6B A vertical cross-sectional view taken along the vertical plane C-C'.

[0030] Figure 6D It is along Figure 6B A vertical cross-sectional view taken along the vertical plane D-D'.

[0031] Figure 6E It is along Figure 6B A vertical cross-sectional view taken along the vertical plane EE'.

[0032] Figure 7Ais a vertical cross-sectional view of an exemplary structure after forming a second alternating layer stack of a second continuous insulating layer and a second continuous sacrificial material layer and a second layer of dielectric cavity fill material portion according to an embodiment of the present disclosure.

[0033] Figure 7B yes Figure 7A The top cross-sectional view of the exemplary structure of FIG. The hinged vertical plane AA' is Figure 7A A vertical section of a plane.

[0034] Figure 7C It is along Figure 7B A vertical cross-sectional view taken along the vertical plane C-C'.

[0035] Figure 7D It is along Figure 7B A vertical cross-sectional view taken along the vertical plane D-D'.

[0036] Figure 7E It is along Figure 7B A vertical cross-sectional view taken along the vertical plane EE'.

[0037] Figure 8A is a vertical cross-sectional view of an exemplary structure after forming a second-layer moat-shaped dielectric wall structure according to an embodiment of the present disclosure.

[0038] Figure 8B yes Figure 8A The top cross-sectional view of the exemplary structure of FIG. The hinged vertical plane AA' is Figure 8A A vertical section of a plane.

[0039] Figure 8C It is along Figure 8B A vertical cross-sectional view taken along the vertical plane C-C'.

[0040] Figure 8D It is along Figure 8B A vertical cross-sectional view taken along the vertical plane D-D'.

[0041] Figure 8E It is along Figure 8B A vertical cross-sectional view taken along the vertical plane EE'.

[0042] Figure 9A is a vertical cross-sectional view of an exemplary structure after forming inter-layer memory openings and support openings according to an embodiment of the present disclosure.

[0043] Figure 9B yes Figure 9A The top cross-sectional view of the exemplary structure of FIG. The hinged vertical plane AA' is Figure 9A A vertical section of a plane.

[0044] Figure 9CIt is along Figure 9B A vertical cross-sectional view taken along the vertical plane C-C'.

[0045] Figure 9D It is along Figure 9B A vertical cross-sectional view taken along the vertical plane D-D'.

[0046] Figure 9E It is along Figure 9B A vertical cross-sectional view taken along the vertical plane EE'.

[0047] 10A to 10D Sequential vertical cross-sectional views of a memory opening during formation of a memory opening filling structure are shown according to an embodiment of the present disclosure.

[0048] Figure 11A is a vertical cross-sectional view of an exemplary structure after forming a memory opening filling structure, a support pillar structure, and a contact-level dielectric layer according to an embodiment of the present disclosure.

[0049] Figure 11B yes Figure 11A The top cross-sectional view of the exemplary structure of FIG. The hinged vertical plane AA' is Figure 11A A vertical section of a plane.

[0050] Figure 11C It is along Figure 11B A vertical cross-sectional view taken along the vertical plane C-C'.

[0051] Figure 11D It is along Figure 11B A vertical cross-sectional view taken along the vertical plane D-D'.

[0052] Figure 11E It is along Figure 11B A vertical cross-sectional view taken along the vertical plane EE'.

[0053] Figure 12A is a vertical cross-sectional view of an exemplary structure after forming linear trenches and source regions according to an embodiment of the present disclosure.

[0054] Figure 12B yes Figure 12A The top cross-sectional view of the exemplary structure of FIG. The hinged vertical plane AA' is Figure 12A A vertical section of a plane.

[0055] Figure 12C It is along Figure 12B A vertical cross-sectional view taken along the vertical plane C-C'.

[0056] Figure 12D It is along Figure 12B A vertical cross-sectional view taken along the vertical plane D-D'.

[0057] Figure 12E It is along Figure 12B A vertical cross-sectional view taken along the vertical plane EE'.

[0058] Figure 13A is a vertical cross-sectional view of an exemplary structure after forming a backside recess according to an embodiment of the present disclosure.

[0059] Figure 13B yes Figure 13A The top cross-sectional view of the exemplary structure of FIG. The hinged vertical plane AA' is Figure 13A A vertical section of a plane.

[0060] Figure 13C It is along Figure 13B A vertical cross-sectional view taken along the vertical plane C-C'.

[0061] Figure 13D It is along Figure 13B A vertical cross-sectional view taken along the vertical plane D-D'.

[0062] Figure 13E It is along Figure 13B A vertical cross-sectional view taken along the vertical plane EE'.

[0063] Figure 14A is a vertical cross-sectional view of an exemplary structure after forming a conductive layer and a line trench-fill structure according to an embodiment of the present disclosure.

[0064] Figure 14B yes Figure 14A The top cross-sectional view of the exemplary structure of FIG. The hinged vertical plane AA' is Figure 14A A vertical section of a plane.

[0065] Figure 14C It is along Figure 14B A vertical cross-sectional view taken along the vertical plane C-C'.

[0066] Figure 14D It is along Figure 14B A vertical cross-sectional view taken along the vertical plane D-D'.

[0067] Figure 14E It is along Figure 14B A vertical cross-sectional view taken along the vertical plane EE'.

[0068] Figure 15A is a vertical cross-sectional view of an exemplary structure after forming a conductive via structure according to an embodiment of the present disclosure.

[0069] Figure 15B yes Figure 15A The top cross-sectional view of the exemplary structure of FIG. The hinged vertical plane AA' is Figure 15A A vertical section of a plane.

[0070] Figure 15C It is along Figure 15B A vertical cross-sectional view taken along the vertical plane C-C'.

[0071] Figure 15D It is along Figure 15B A vertical cross-sectional view taken along the vertical plane D-D'.

[0072] Figure 15E It is along Figure 15B A vertical cross-sectional view taken along the vertical plane EE'.

[0073] Figure 16A is a vertical cross-sectional view of an exemplary structure after forming a higher level metal interconnect structure including metal lines according to an embodiment of the present disclosure.

[0074] Figure 16B yes Figure 16A The top cross-sectional view of the exemplary structure of FIG. The hinged vertical plane AA' is Figure 16A A vertical section of a plane.

[0075] Figure 16C It is along Figure 16B A vertical cross-sectional view taken along the vertical plane C-C'.

[0076] Figure 16D It is along Figure 16B A vertical cross-sectional view taken along the vertical plane D-D'.

[0077] Figure 16E It is along Figure 16B A vertical cross-sectional view taken along the vertical plane EE'.

[0078] Figure 17A is a vertical cross-sectional view of a first alternative configuration of an exemplary structure according to an embodiment of the present disclosure, wherein each moat-shaped dielectric wall structure is replaced by a pair of discrete dielectric wall structures.

[0079] Figure 17B yes Figure 17A The top cross-sectional view of the exemplary structure of FIG. The hinged vertical plane AA' is Figure 17A A vertical section of a plane.

[0080] Figure 17C It is along Figure 17B A vertical cross-sectional view taken along the vertical plane C-C'.

[0081] Figure 17D It is along Figure 17B A vertical cross-sectional view taken along the vertical plane D-D'.

[0082] Figure 17E It is along Figure 17B A vertical cross-sectional view taken along the vertical plane EE'.

[0083] Figure 18 is a top cross-sectional view of a second alternative configuration of an exemplary structure including a monolithic dielectric wall structure according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0084] As described above, embodiments of the present disclosure relate to a three-dimensional memory device including a dielectric wall support structure located in or adjacent to a stepped region for reducing lateral connection resistance of a word line and a method for forming the same, various aspects of which are now described in detail.

[0085] The drawings are not drawn to scale. Where a single instance of an element is shown, multiple instances of the element may be repeated unless explicitly described or otherwise clearly indicated that there is no repetition of the element. Sequence numbers such as "first," "second," and "third" are used only to identify similar elements, and different sequence numbers may be used throughout the specification and claims of this disclosure. The term "at least one" element refers to all possibilities, including the possibility of a single element and the possibility of multiple elements.

[0086] The same reference numerals represent the same or similar elements. Unless otherwise specified, elements with the same reference numerals are assumed to have the same composition and the same function. Unless otherwise specified, "contact" between elements refers to direct contact between elements providing an edge or surface shared by the elements. If two or more elements are not in direct contact with each other or with each other, the two elements are "separated" from each other or "separated" from each other. As used herein, a first element positioned "on" a second element can be positioned on the outside of the surface of the second element or on the inside of the second element. As used herein, if there is physical contact between the surface of the first element and the surface of the second element, the first element is "directly" positioned on the second element. As used herein, if there is a conductive path consisting of at least one conductive material between the first element and the second element, the first element is "electrically connected to" the second element. As used herein, a "prototype" structure or an "in-process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one of its components.

[0087] As used herein, a "layer" refers to a portion of a material that includes an area having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent that is less than the extent of an underlying or overlying structure. Additionally, a layer may be an area of ​​a uniform or non-uniform continuous structure that has a thickness that is less than the thickness of a first continuous structure. For example, a layer may be positioned between the top and bottom surfaces of a first continuous structure or between any pair of horizontal planes at the top and bottom surfaces of the first continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above, and / or below.

[0088] As used herein, a first surface and a second surface are “vertically coincident” with each other if the second surface is above or below the first surface and if there is a vertical plane or a substantially vertical plane that includes the first surface and the second surface. A substantially vertical plane is a plane that extends straight along a direction that deviates from vertical by an angle of less than 5 degrees. A vertical plane or a substantially vertical plane is straight along the vertical direction or the substantially vertical direction and may or may not include curvature along a direction perpendicular to the vertical direction or the substantially vertical direction.

[0089] As used herein, a "memory level" or "memory array level" refers to a level corresponding to the general area between a first horizontal plane (i.e., a plane parallel to the top surface of the substrate) including the topmost surface of the memory element array and a second horizontal plane including the bottommost surface of the memory element array. As used herein, a "through-stack" element refers to an element that extends vertically through the memory level.

[0090] As used herein, "semiconductor material" refers to a material having a -5 S / m to 1.0×10 5 As used herein, "semiconductor material" refers to a material having an electrical conductivity in the range of 1.0×10 -5 S / m to 1.0 S / m and can produce materials with electrical conductivity in the range of 1.0 S / m to 1.0×10 7 S / m. As used herein, "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the energy band structure, or an n-type dopant that adds electrons to the conduction band within the energy band structure. As used herein, "conductive material" refers to a material having an electrical conductivity greater than 1.0×10 5 As used herein, "insulator material" or "dielectric material" refers to a material having an electrical conductivity of less than 1.0×10 -5As used herein, a "heavily doped semiconductor material" refers to a material that is doped with electrical dopants at a sufficiently high atomic concentration to provide a conductive material (i.e., a material having an electrical conductivity greater than 1.0×10 5 S / m) of semiconductor material. The "doped semiconductor material" may be a heavily doped semiconductor material, or may include a semiconductor material that provides a conductivity of 1.0×10 -5 S / m to 1.0×10 7 S / m) in the range of 100 Å / s. "Intrinsic semiconductor material" refers to a semiconductor material that is not doped with electrical dopants. Thus, a semiconductor material can be semiconducting or conductive, and can be an intrinsic semiconductor material or a doped semiconductor material. Doped semiconductor materials can be semiconducting or conductive, depending on the atomic concentration of the electrical dopant therein. As used herein, "metallic material" refers to a conductive material that includes at least one metal element therein. All conductivity measurements are performed under standard conditions.

[0091] A monolithic three-dimensional memory array is a memory array in which multiple memory levels are formed above a single substrate (such as a semiconductor wafer) without an intervening substrate. The term "monolithic" means that the layers of each level of the array are deposited directly on the layers of each lower level of the array. In contrast, two-dimensional arrays can be formed separately and then packaged together to form a non-monolithic memory device. For example, as described in U.S. Patent 5,915,177, entitled "Three-dimensional Structure Memory", a non-monolithic stacked memory is constructed by forming memory levels on separate substrates and vertically stacking the memory levels. The substrate can be thinned or removed from the memory levels before bonding, but because the memory levels are initially formed above separate substrates, such memories are not true monolithic three-dimensional memory arrays. The substrate may include integrated circuits manufactured thereon, such as driver circuits for the memory device.

[0092] Various three-dimensional memory devices disclosed herein include single-unit three-dimensional NAND string memory devices and can be manufactured using various embodiments described herein. A single-unit three-dimensional NAND string is positioned in a single-unit three-dimensional NAND string array located above a substrate. At least one memory cell in a first device level of the three-dimensional NAND string array is located above another memory cell in a second device level of the three-dimensional NAND string array.

[0093] Generally speaking, a semiconductor package (or "package") refers to a unit semiconductor device that can be attached to a circuit board via a set of pins or solder balls. A semiconductor package may include one or more semiconductor chips (or "chips") that are bonded together, for example, by flip-chip bonding or another chip-to-chip bonding. A package or chip may include a single semiconductor die (or "die") or multiple semiconductor dies. A die is the smallest unit that can independently execute external commands or report status. Typically, a package or chip with multiple dies is capable of simultaneously executing as many external commands as the total number of dies therein. Each die includes one or more planes. The same concurrent operation can be performed in each plane within the same die, but there may be some limitations. In the case where the die is a memory die (i.e., a die that includes memory elements), concurrent read operations, concurrent write operations, or concurrent erase operations can be performed in each plane within the same memory die. In a memory die, each plane contains multiple memory blocks (or "blocks"), which are the smallest units that can be erased by a single erase operation. Each memory block contains multiple pages, which are the smallest units that can be selected for programming and the smallest units that can be selected for read operations.

[0094] refer to Figure 1 , illustrates an exemplary semiconductor die 1000 according to an embodiment of the present disclosure. The exemplary semiconductor die 1000 includes multiple three-dimensional memory array regions and multiple inter-array regions. A first exemplary semiconductor die 1000 may include multiple planes, each plane including two memory array regions 100, such as a first memory array region 100A and a second memory array region 100B, laterally separated by a corresponding inter-array region 200. Generally speaking, semiconductor die 1000 may include a single plane or multiple planes. The total number of planes in semiconductor die 1000 may be selected based on performance requirements for semiconductor die 1000. A pair of memory array regions 100 within a plane may be laterally separated along a first horizontal direction hd1 (which may be a wordline direction). For example, each pair of memory array regions 100 within a plane may include a first memory array region 100A and a second memory array region 100B laterally separated along the first horizontal direction hd1 by an inter-array region 200. A second horizontal direction hd2 (which may be a bitline direction) may be perpendicular to the first horizontal direction hd1.

[0095] Can be manufactured using a sequence of processing steps Figure 1 An exemplary semiconductor die 1000 is shown. Figure 2 During the manufacturing step Figure 1A vertical cross-sectional view of region M1 in an exemplary structure of FIG. A substrate 8 is provided, which may include a substrate semiconductor layer 9. Substrate 8 may be a single crystal silicon wafer, a silicon-on-insulator (SOI) substrate, or an insulating (e.g., glass or quartz) substrate. Substrate semiconductor layer 9 may be a layer of single crystal semiconductor material, such as a single crystal silicon layer epitaxially grown on a silicon wafer or SOI substrate, or a doped well in an upper portion of a silicon wafer or SOI substrate. A semiconductor device 720 may be formed on the top surface of substrate semiconductor layer 9. For example, semiconductor device 720 may include a field effect transistor, a resistor, a capacitor, a diode, and / or various other semiconductor devices known in the art. In one embodiment, semiconductor device 720 may include peripheral (i.e., driver) circuitry for controlling the operation of a three-dimensional memory array subsequently formed thereon. A metal interconnect structure embedded in a dielectric material layer may be formed above the semiconductor device. The metal interconnect structure is referred to herein as a lower-level metal interconnect structure 780, and the dielectric material layer is referred to herein as a lower-level dielectric material layer 760. Lower-level metal interconnect structures 780 are electrically connected to various nodes of semiconductor device 720 and may include metal line structures and metal via structures at various levels of lower-level dielectric material layers 760. Lower-level metal interconnect structures 780 may include metal pads 786, which may subsequently serve as components of conductive paths.

[0096] A semiconductor material layer 110 may be formed on the top surface of the lower-level dielectric material layer 760. The semiconductor material layer 110 may be single crystalline or polycrystalline and may be formed by layer transfer from a source substrate (such as a single crystalline silicon layer including a buried hydrogen implant layer) or may be formed by deposition of a semiconductor material (which may be a polycrystalline semiconductor material, such as polycrystalline silicon).

[0097] A first alternating layer stack of a first continuous insulating layer 132L and a first continuous sacrificial material layer 142L may be formed over the semiconductor material layer 110. As used herein, an alternating stack refers to a sequence of multiple instances of a first element and multiple instances of a second element, the sequence arranged such that an instance of the second element is positioned between each vertically adjacent pair of instances of the first element, and an instance of the first element is positioned between each vertically adjacent pair of instances of the second element. An alternating layer stack refers to a sequence of multiple instances of a first material layer and multiple instances of a second material layer, such that the instances of the first material layer and the instances of the second material layer are interleaved.

[0098] The first continuous insulating layer 132L may be composed of a first material, and the first continuous sacrificial material layer 142L may be composed of a second material different from the first material. Each of the first continuous insulating layers 132L is an insulating layer that extends continuously over the entire area of ​​the substrate 8 and may have a uniform thickness overall. Each of the first continuous sacrificial material layers 142L includes a sacrificial material layer that includes a dielectric material and extends continuously over the entire area of ​​the substrate 8 and may have a uniform thickness overall. Insulating materials that can be used for the first continuous insulating layer 132L include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides commonly referred to as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and their silicates, dielectric metal oxynitrides and their silicates, and organic insulating materials. In one embodiment, the first material of the first continuous insulating layer 132L may be silicon oxide.

[0099] The second material of the first continuous sacrificial material layer 142L is a dielectric material that is a sacrificial material that is selectively removable with respect to the first material of the first continuous insulating material layer 132L. As used herein, the removal of a first material is "selective with respect to" a second material if the removal process removes the first material at a rate that is at least twice the removal rate of the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material relative to the second material. The second material of the first continuous sacrificial material layer 142L can then be replaced with a conductive electrode that can be used, for example, as a control gate electrode for a vertical NAND device. In one embodiment, the first continuous sacrificial material layer 142L can be a layer of material comprising silicon nitride.

[0100] See also Figures 3A to 3F, a first stepped surface can be simultaneously formed within the inter-array region 200. A hard mask layer (not shown), such as a metal or dielectric mask material layer, can be formed above the first alternating layer stack and can be patterned to form a plurality of rectangular openings. The area of ​​the openings within the hard mask layer corresponds to the area where the first stepped surface will subsequently be formed. Each opening through the hard mask layer can be rectangular and can have a pair of sides parallel to the first horizontal direction hd1 and a pair of sides parallel to the second horizontal direction hd2. The rectangular openings through the hard mask layer can be arranged along the second horizontal direction hd2 and can alternatively be staggered along the first horizontal direction hd1. Therefore, when the rectangular openings are numbered sequentially along the second horizontal direction hd2, each odd-numbered rectangular opening passing through the hard mask layer can be formed into a first one-dimensional array arranged along the second horizontal direction hd2 and aligned along the first horizontal direction hd1 (i.e., having the same lateral extent along the first horizontal direction), and each even-numbered rectangular opening passing through the hard mask layer can be formed into a second one-dimensional array arranged along the second horizontal direction hd2 and aligned along the first horizontal direction hd1.

[0101] A tunable mask layer (not shown) may be applied over the first alternating layer stack. The tunable mask layer may include a tunable photoresist layer that can be controllably tunable by a timed ashing process. The tunable mask layer may be patterned with an initial pattern such that a section of the hard mask layer closest to each rectangular opening in the memory array region 100 is not masked by the tunable mask layer, while the remainder of each rectangular opening is covered by the tunable mask layer. For example, the tunable mask layer may have a rectangular shape having straight edges parallel to the second horizontal direction hd2, such that the straight edges are positioned above the vertical steps of the corresponding first stepped surface closest to one of the memory array regions in the memory array region 100.

[0102] The first stepped surface can be formed within the rectangular opening in the hard mask layer by repeatedly performing a set of layer patterning steps, the number of which is equal to the total number of first continuous sacrificial material layers 142L in the first alternating layer stack minus one. The set of layer patterning steps includes an anisotropic etching process that etches unmasked portions of a pair of first continuous insulating layers 132L and first continuous sacrificial material layers 142L; and a mask trimming process in which a tunable mask layer is isotropically trimmed to provide shifted sidewalls that are shifted away from the nearest memory array region 100. A final anisotropic etching process can be performed after the final mask trimming process, and the tunable mask layer can be removed, for example, by ashing. The hard mask layer can be removed, for example, selectively with respect to the material of the first alternating layer stack (132L, 142L) by an isotropic etching process, such as a wet etching process.

[0103] A first stepped cavity may be formed within each region of the rectangular opening in the hard mask layer. Each first stepped cavity may include a steep-walled region where the tapered sidewalls of the first alternating layer stack extend vertically from the bottommost layer of the first alternating layer stack (132L, 142L) to the topmost layer of the first alternating layer stack (132L, 142L). Each first stepped cavity has a corresponding first stepped surface as a stepped bottom surface. Each first stepped cavity has a pair of stepped sidewalls extending laterally along a first horizontal direction hd1. Each stepped sidewall of the first stepped cavity abuts the first stepped surface at its bottom edge and extends to the top surface of the topmost layer of the first alternating layer stack (132L, 142L). The first stepped surface is located below each first stepped cavity. Generally, the first stepped surface can be formed by patterning the first alternating layer stack (132L, 142L) in each inter-array region 200 located between the corresponding first memory array region 100A and the second memory array region 100B. A first dielectric fill material (such as undoped silicate glass (i.e., silicon oxide) or doped silicate glass) can be deposited in each first stepped cavity. The first dielectric fill material can be planarized to remove excess portions of the first dielectric fill material from above a horizontal plane including the topmost surface of the first alternating layer stack (132L, 142L). Each remaining portion of the first dielectric fill material filling the corresponding first stepped cavity constitutes a first layer dielectric cavity filling material portion 163. Each first layer dielectric cavity filling material portion 163 is formed above the first stepped surface of the first alternating layer stack (132L, 142L). It should be noted that the first stepped cavity can be symmetrical, such as Figure 3F However, the first stepped cavity Figure 3D It appears asymmetrical because Figure 3D express Figure 3D The curved view plane makes the first stepped cavity Figure 3D Appears asymmetrical.

[0104] refer to Figures 4A to 4E Various first layer moat trenches (175, 185) and first layer support openings 19 may be formed through the first alternating layer stack (132L, 142L) within the inter-array region 200. For example, a photoresist layer (not shown) may be applied over the first alternating layer stack (132L, 142L) and may be photolithographically patterned to form moat-shaped openings and discrete openings (which may be circular openings). As used herein, a "moat-shaped" element refers to an element having a closed outer sidewall and a closed inner sidewall, such that the element extends only between the closed outer sidewall and the closed inner sidewall, and the closed outer sidewall has a shape that follows the general contour of the closed inner sidewall. In some embodiments, the lateral spacing between the closed outer sidewall and the closed inner sidewall may be uniform.

[0105] An anisotropic etching process can be performed to transfer a pattern of moat-shaped openings and discrete openings through the first alternating layer stack (132L, 142L) and the first layer of dielectric cavity fill material portion 163. First layer moat trenches (175, 185) are formed below the moat-shaped openings in the photoresist layer. First layer support openings 19 are formed below the discrete openings in the photoresist layer. Generally, first layer support openings 19 are formed in areas of the inter-array region 200 that are not filled with first layer moat trenches (175, 185). First layer support openings 19 can be cylindrical and have a circular horizontal cross-sectional shape. Optionally, additional first layer support openings (not shown) can be formed in portions of the memory array region 100 where no memory stack structure is subsequently formed. In alternative embodiments, first layer support openings 19 can be formed in an earlier or later photolithography and etching step separate from the first layer moat trenches (175, 185).

[0106] The top surface of the semiconductor material layer 110 can be physically exposed at the bottom of the first layer moat trenches (175, 185) and the bottom of each first layer support opening 19. Each of the first layer moat trenches (175, 185) can be formed within the inter-array region 200 and can have a pair of longitudinal outer sidewalls and a pair of longitudinal inner sidewalls extending laterally along a first horizontal direction hd1, and a pair of lateral outer sidewalls and a pair of lateral inner sidewalls extending laterally along a second horizontal direction hd2. In some embodiments, the longitudinal sidewalls and lateral sidewalls of the first layer moat trenches (175, 185) can directly abut each other or can be indirectly abutted via curved sidewall segments. The lateral distance between opposing pairs of first layer moat trenches (175, 185) can be in the range of 50 nm to 1,000 nm, such as 100 nm to 500 nm, although smaller and larger lateral distances can also be used.

[0107] The first-layer moat trenches (175, 185) may include a first-type first-layer moat trench 175 that intersects a corresponding one of the first-layer dielectric cavity filling material portions 163. In one embodiment, each first-layer dielectric cavity filling material portion 163 may intersect a pair of first-type first-layer moat trenches 175, such that each first-layer dielectric cavity filling material portion 163 is divided into three dielectric material portions. Each remaining portion of the first-layer dielectric cavity filling material portion 163 that is laterally enclosed by the first-type first-layer moat trench 175 is referred to herein as a first dielectric filling material portion 165'. Each remaining portion of the first-layer dielectric cavity filling material portion 163 that is located outside the first-type first-layer moat trench 175 is referred to herein as a first-layer backward-stepped dielectric material portion 165. In one embodiment, each first-layer backward-stepped dielectric material portion 165 may extend laterally along and abut two first-type first-layer moat trenches 175.

[0108] The first layer moat trenches (175, 185) may optionally include a second type of first layer moat trench 185 that does not intersect the first layer dielectric cavity fill material portion 163. In one embodiment, the second type of first layer moat trench 185 may be laterally offset from the first type of first layer moat trench 175 along the first horizontal direction hd1 within the same inter-array region 200. Generally speaking, the size and shape of the second type of first layer moat trench 185 may be comparable to the size and shape of the first type of first layer moat trench 175.

[0109] In one embodiment, a first-type first-layer moat trench 175 may laterally enclose a patterned portion of the first alternating layer stack (132L, 142L). In one embodiment, the first continuous sacrificial material layer 142L comprises a dielectric material, such as silicon nitride. In this case, each patterned portion of the first continuous insulating layer 132L is referred to herein as a first insulating plate 132', and each patterned portion of the first continuous sacrificial material layer 142L is referred to herein as a first dielectric material plate 142'. A vertically alternating sequence of first insulating plates 132' and first dielectric material plates 142' may be formed within each first-type first-layer moat trench 175. The first insulating plates 132' and the first continuous insulating layer 132L have the same material composition. Each horizontal surface of the first continuous insulating layer 132L may lie within a horizontal plane that includes a horizontal surface of a corresponding one of the first insulating plates 132' within the vertically alternating sequence of first insulating plates 132' and first dielectric material plates 142'.

[0110] Generally speaking, the sidewalls of each first dielectric filling material portion 165' that does not contact the first type first level moat trench 175 are tapered so that the horizontal cross-sectional area of ​​each first dielectric filling material portion 165' increases with the vertical distance from the substrate 8, as shown in FIG. Figure 4D As shown. This is because the anisotropic etching process that forms the first stepped cavity etches the sidewalls of the first alternating layer stack (132L, 142L) with a taper angle that can be in the range of 1 degree to 15 degrees, such as in the range of 2 degrees to 8 degrees. Therefore, the first insulating plate 132' and the first dielectric material plate 142' within each first-type first-level moat trench 175 can have a first lateral extent that decreases with vertical distance from the substrate 8 along the first horizontal direction hd1. In addition, the first insulating plate 132' and the first dielectric material plate 142' within each first-type first-level moat trench 175 can have a second lateral extent that decreases with vertical distance from the substrate 8 along the second horizontal direction hd2. In one embodiment, at least one lateral sidewall of each first dielectric filler material portion 165' is not in contact with the first-type first-level moat trench 175 and is in contact with the corresponding first vertical alternating sequence of first insulating plates 132' and first dielectric material plates 142'.

[0111] The first dielectric filler material portions 165' can cover and contact the first vertical alternating sequence of first insulating plates 132' and first dielectric material plates 142'. The first dielectric filler material portions 165' can extend laterally between a pair of inner longitudinal sidewalls of the first type of first layer moat trench 175. Due to the tapered angle extending laterally along the first horizontal direction in the longitudinal sidewalls of each first dielectric filler material portion 165', a larger surface area of ​​the first dielectric filler material portions 165' can be physically exposed to one longitudinal section of the first type of first layer moat trench 175 than to another longitudinal section of the first type of first layer moat trench.

[0112] refer to Figures 5A to 5E, a first dielectric fill material (such as silicon oxide) can be deposited in the first-layer moat trenches (175, 185) and in the first-layer support openings 19 by a conformal deposition process such as a chemical mechanical deposition process. Excess portions of the first dielectric fill material can be removed from above the topmost layer of the first alternating layer stack (132L, 142L). Each remaining portion of the first dielectric fill material filling the first-layer moat trenches (175, 185) includes a first-layer moat-shaped dielectric wall structure (176, 186). Each remaining portion of the first dielectric fill material filling the first-layer support openings 19 includes a first-layer support post structure 201. The first-layer moat-shaped dielectric wall structures (176, 186) include a first-type first-layer moat-shaped dielectric wall structure 176 filling the first-type first-layer moat trenches 175 and a second-type first-layer moat-shaped dielectric fill structure 186 filling the second-type first-layer moat trenches 185. In an alternative embodiment, if the first layer support opening 19 is formed in an earlier or later photolithography and etching step separate from the first layer moat trench (175, 185), the first layer support column structure 201 can be formed before or after the first layer moat trench (175, 185) is formed and the moat trench is filled to form the first layer moat-shaped dielectric wall structure (176, 186).

[0113] The first layer support column structure 201 may have a cylindrical shape (or a tapered cylindrical shape, such as a truncated conical shape), and the first layer trench-shaped dielectric wall structure (176, 186) may have a non-cylindrical and non-truncated conical shape, such as a ring-shaped polygonal shape or another suitable shape. For example, each first layer trench-shaped dielectric wall structure (176, 186) includes four segments, and the four segments include two longitudinal dielectric wall structures extending transversely along the first horizontal direction hd1 and two transverse dielectric wall structures extending transversely along the second horizontal direction hd2. The two longitudinal dielectric wall segments of each first layer trench-shaped dielectric wall structure (176, 186) are referred to herein as the first dielectric wall structure W1 and the second dielectric wall structure W2, as shown in FIG. Figure 5BAs shown. The first dielectric wall structure W1 and the second dielectric wall structure W2 include portions of the first layer moat dielectric wall structure (176, 186) extending laterally along the first horizontal direction hd2, and these portions are connected to each other by a pair of lateral dielectric wall portions of the first layer moat-shaped dielectric wall structure (176, 186). Generally speaking, the first dielectric wall structure W1 and the second dielectric wall structure W2 extending laterally along the first horizontal direction hd1 can be formed through the material of the first alternating layer stack (132L, 142L) and the first dielectric cavity filling material portion 163 within the inter-array region 200. Each first dielectric cavity filling material portion 163 can be divided into at least a first rear stepped dielectric material portion 165 covering the stepped surface of the alternating layer stack (132L, 142L) and a first dielectric filling material portion 165' located between the first dielectric wall structure W1 and the second dielectric wall structure W2. The first dielectric wall structure W1 and the second dielectric wall structure W2 may be parts of a moat-shaped dielectric material filling two laterally extending portions of the moat trench and may be connected to each other by a pair of lateral dielectric wall portions.

[0114] refer to Figures 6A to 6E A photoresist layer may be applied over the first alternating layer stack (132L, 142L) and photolithographically patterned to form an array of discrete openings within each memory array region 100. The opening pattern in the photoresist layer may be transferred through the first alternating layer stack (132L, 142L) into the upper portion of the semiconductor material layer 110 by a first anisotropic etching process to form first-level memory openings. First-level memory openings are formed in the memory array region 100. Each cluster of first-level memory openings may be formed into a two-dimensional array of first-level memory openings.

[0115] A sacrificial first layer of fill material may be deposited in each of the first layer of memory openings. The sacrificial first layer of fill material comprises a material that can be subsequently removed selectively to the material of the first continuous insulating layer 132L and the first continuous sacrificial material layer 142L. In one embodiment, the sacrificial first layer of fill material may comprise a semiconductor material such as silicon (e.g., a-Si or polysilicon), a silicon-germanium alloy, germanium, a III-V compound semiconductor material, or a combination thereof. Optionally, a thin etch stop liner (such as a silicon oxide layer or a silicon nitride layer having a thickness in the range of 1 nm to 3 nm) may be used prior to depositing the sacrificial first layer of fill material. The sacrificial first layer of fill material may be formed by non-conformal deposition or conformal deposition methods.

[0116] In another embodiment, the sacrificial first layer fill material may include a silicon oxide material having a higher etch rate than the material of the first continuous insulating layer 132L. For example, the sacrificial first layer fill material may include borosilicate glass or porous or non-porous organosilicate glass having an etch rate at least 100 times higher than the etch rate of dense TEOS oxide (i.e., a silicon oxide material formed by decomposing tetraethyl orthosilicate glass in a chemical vapor deposition process and subsequently densifying in an annealing process) in 100:1 diluted hydrofluoric acid. In this case, a thin etch stop liner (such as a silicon nitride layer having a thickness in the range of 1 nm to 3 nm) may be used before depositing the sacrificial first layer fill material. The sacrificial first layer fill material may be formed by non-conformal deposition or conformal deposition methods. In yet another embodiment, the sacrificial first layer fill material may include a carbon-containing material (such as amorphous carbon or diamond-like carbon) that can be subsequently removed by ashing, or a silicon-based polymer that can be subsequently removed selectively to the material of the first alternating layer stack (132L, 142L).

[0117] Portions of the deposited sacrificial material may be removed from above the topmost layer of the first alternating layer stack (132L, 142L), such as from above the topmost first continuous insulating layer 132L. For example, the sacrificial first layer fill material may be recessed to the top surface of the topmost first continuous insulating layer 132L using a planarization process. The planarization process may include recess etching, chemical mechanical planarization (CMP), or a combination thereof. The top surface of the topmost first continuous insulating layer 132L may serve as an etch stop or a planarization stop.

[0118] The remaining portion of the sacrificial first layer of fill material comprises a sacrificial first layer of memory opening filling portion 148. The top surface of sacrificial first layer of memory opening filling portion 148 may be coplanar with the top surface of the topmost first continuous insulating layer 132L. Each of sacrificial first layer of memory opening filling portion 148 may or may not include a cavity therein. The collection of all structures positioned between the bottommost surface of the first alternating layer stack (132L, 142L) and the topmost surface of the first alternating layer stack (132L, 142L) or embedded within the first alternating layer stack (132L, 142L) constitutes a first layer of structures.

[0119] refer to 7A to 7E, a second alternating layer stack of second continuous insulating layers 232L and second continuous sacrificial material layers 242L may be formed. Each of the second continuous insulating layers 232L is an insulating layer that extends continuously over the entire area of ​​substrate 8 and may have a uniform thickness throughout. Each of the second continuous sacrificial material layers 242L includes a sacrificial material layer that includes a dielectric material and extends continuously over the entire area of ​​substrate 8 and may have a uniform thickness throughout. The second continuous insulating layer 232L may have the same material composition and the same thickness as the first continuous insulating layer 132L. The second continuous sacrificial material layer 242L may have the same material composition and the same thickness as the first continuous sacrificial material layer 142L.

[0120] Generally, at least one additional alternating layer stack of an additional continuous insulating layer and an additional continuous sacrificial material layer may optionally be formed over the first alternating layer stack ( 132L, 142L) and the first layer of dielectric cavity filling material portion 163 .

[0121] A second stepped surface can be simultaneously formed within the inter-array region 200. The areas of the second stepped surfaces are laterally offset from the corresponding proximal first stepped surfaces along the first horizontal direction hd1, such that a set of first stepped surfaces and a set of second stepped surfaces that are laterally spaced apart along the first horizontal direction hd1 and not offset along the second horizontal direction hd2 can provide a continuously ascending step or a continuously descending step. For example, a hard mask layer (not shown), such as a metal or dielectric mask material layer, can be formed over the second alternating layer stack and patterned to form a plurality of rectangular openings that are laterally offset from the corresponding first layer dielectric cavity filling material portions 163 along the first horizontal direction hd1 and aligned with (i.e., not laterally offset from) the corresponding first layer dielectric cavity filling material portions 163 along the second horizontal direction hd2. The areas of the openings within the hard mask layer correspond to the areas where the second stepped surfaces will subsequently be formed. Each opening through the hard mask layer can be rectangular and can have a pair of sides parallel to the first horizontal direction hd1 and a pair of sides parallel to the second horizontal direction hd2. The rectangular openings through the hard mask layer can be arranged along the second horizontal direction hd1 and can alternatively be staggered along the second horizontal direction hd2. Thus, when the rectangular openings are sequentially numbered along the second horizontal direction hd2, each odd-numbered rectangular opening through the hard mask layer can be formed into a first one-dimensional array arranged along the second horizontal direction hd2 and aligned along the first horizontal direction hd1 (i.e., having the same lateral extent along the first horizontal direction), and each even-numbered rectangular opening through the hard mask layer can be formed into a second one-dimensional array arranged along the second horizontal direction hd2 and aligned along the first horizontal direction hd1.

[0122] A tunable mask layer (not shown) may be applied over the second alternating layer stack. The tunable mask layer may include a tunable photoresist layer that can be controllably tunable via a timed ashing process. The tunable mask layer may be patterned with an initial pattern such that a portion of each rectangular opening in the hard mask layer farthest from the memory array region 100 is not masked by the tunable mask layer, while the remainder of each rectangular opening is covered by the tunable mask layer. For example, the tunable mask layer may have a rectangular shape having straight edges parallel to the second horizontal direction hd2, such that the straight edges are positioned above a vertical step of the corresponding second stepped surface farthest from one of the memory array regions 100.

[0123] A second stepped surface can be formed within the rectangular opening in the hard mask layer by repeatedly performing a set of layer patterning steps, the number of which is equal to the total number of second continuous sacrificial material layers 242L in the second alternating layer stack minus one. The set of layer patterning steps includes an anisotropic etching process that etches unmasked portions of a pair of second continuous insulating layers 232L and second continuous sacrificial material layers 242L, and a mask trimming process in which a tunable mask layer is isotropically trimmed to provide shifted sidewalls that are shifted away from the nearest memory array region 100. A final anisotropic etching process can be performed after the final mask trimming process, and the tunable mask layer can be removed, for example, by ashing. The hard mask layer can be removed, for example, selectively with respect to the material of the second alternating layer stack (232L, 242L) by an isotropic etching process, such as a wet etching process.

[0124] A second stepped cavity may be formed within each region of the rectangular opening in the hard mask layer. Each second stepped cavity may include a steep-walled region in which the tapered sidewalls of the second alternating layer stack extend vertically from the bottommost layer of the second alternating layer stack (232L, 242L) to the topmost layer of the second alternating layer stack (232L, 242L). Each second stepped cavity has a corresponding second stepped surface as a stepped bottom surface. Each second stepped cavity has a pair of stepped sidewalls extending laterally along a first horizontal direction hd1. Each stepped sidewall of the second stepped cavity abuts the second stepped surface at a bottom edge and extends to the top surface of the topmost layer of the second alternating layer stack (232L, 242L). Each second stepped cavity defines the lateral extent of the corresponding second stepped surface.

[0125] The array of second stepped regions can be arranged along a second horizontal direction hd2 with alternating lateral offsets along the first horizontal direction hd1 to provide the second stepped regions with a staggered configuration. In other words, after numerically labeling the second stepped regions sequentially along the second horizontal direction hd2 with positive integers starting from 1, each even-numbered second stepped region can be closer to the first memory array region 100A than to the second memory array region 100B, and each odd-numbered second stepped region can be closer to the second memory array region 100B than to the first memory array region 100A. The second stepped cavity can extend through each layer within the second alternating layer stack (232L, 242L).

[0126] A second dielectric filler material (such as undoped silicate glass or doped silicate glass) may be deposited in each second stepped cavity. The second dielectric filler material may be planarized to remove excess portions of the second dielectric filler material above a horizontal plane including the topmost surface of the second alternating layer stack (232L, 242L). Each remaining portion of the second dielectric filler material filling the corresponding second stepped cavity constitutes a second layer dielectric cavity filler material portion 263. Thus, a second layer dielectric cavity filler material portion 263 is formed through the second alternating layer stack (232L, 242L).

[0127] refer to Figures 8A to 8E Various second-layer moat trenches and second-layer support openings may be formed through the second alternating layer stack (232L, 242L) within the inter-array region 200. For example, a photoresist layer (not shown) may be applied over the second alternating layer stack (232L, 242L) and may be photolithographically patterned to form moat-shaped openings and discrete openings (which may be circular openings). The second-layer moat trenches and second-layer support openings may be formed during the same photolithography and etching steps or during different photolithography and etching steps.

[0128] An anisotropic etching process may be performed to impart a pattern of moat-shaped openings and discrete openings through the second alternating layer stack (232L, 242L) and the second layer of dielectric cavity fill material portion 263. A second layer of moat trenches is formed beneath the moat-shaped openings in the photoresist layer. Second layer of support openings are formed beneath the discrete openings in the photoresist layer. Generally, the second layer of support openings are formed in areas of the inter-array region 200 that are not filled with the second layer of moat trenches. Optionally, additional second layer of support openings (not shown) may be formed in portions of the memory array region 100 where no memory stack structure is subsequently formed.

[0129] Each second layer moat trench may extend vertically to the topmost layer of the first alternating layer stack (132L, 142L). Each second layer support opening may extend vertically to the top surface of the first layer support column structure 201. Each of the second layer moat trenches may be formed in the inter-array region 200 and may have a pair of longitudinal outer sidewalls and a pair of longitudinal inner sidewalls extending laterally along the first horizontal direction hd1, and a pair of lateral outer sidewalls and a pair of lateral inner sidewalls extending laterally along the second horizontal direction hd2. In some embodiments, the longitudinal sidewalls and lateral sidewalls of the second layer moat trenches may be directly adjacent to each other, or may be indirectly adjacent to each other through curved sidewall segments. The lateral distance between opposing second layer moat trench pairs may be in the range of 50nm to 2,000nm, such as 200nm to 500nm, but smaller and larger lateral distances may also be used.

[0130] The second-layer moat trenches may include a first-type second-layer moat trench that intersects a corresponding one of the second-layer dielectric cavity-filling material portions 263. In one embodiment, each second-layer dielectric cavity-filling material portion 263 may intersect a pair of the first-type second-layer moat trenches, such that each second-layer dielectric cavity-filling material portion 263 is divided into three dielectric material portions. Each remaining portion of the second-layer dielectric cavity-filling material portion 263 that is laterally enclosed by the first-type second-layer moat trenches is referred to herein as a second dielectric filling material portion 265'. Each remaining portion of the second-layer dielectric cavity-filling material portion 263 that is located outside the first-type second-layer moat trenches is referred to herein as a second-layer backward-stepped dielectric material portion 265. In one embodiment, each second-layer backward-stepped dielectric material portion 265 may extend laterally and abut two first-type second-layer moat trenches.

[0131] The second-layer moat trenches may include a second type of second-layer moat trenches that do not intersect the second-layer dielectric cavity-filling material portion 263. In one embodiment, the second type of second-layer moat trenches may be laterally offset from the first type of second-layer moat trenches along the second horizontal direction hd2 within the same inter-array region 200. Generally, the size and shape of the second type of second-layer moat trenches may be comparable to the size and shape of the first type of second-layer moat trenches.

[0132] In one embodiment, the first type second layer moat trench may laterally enclose the patterned portion of the second alternating layer stack (232L, 242L). In one embodiment, the second continuous sacrificial material layer 242L comprises a dielectric material, such as silicon nitride. In this case, each patterned portion of the second continuous insulating layer 232L is referred to herein as a second insulating plate 232', and each patterned portion of the second continuous sacrificial material layer 242L is referred to herein as a second dielectric material plate 242'. A vertically alternating sequence of second insulating plates 232' and second dielectric material plates 242' may be formed within each first type second layer moat trench. The second insulating plates 232' and the second continuous insulating layer 232L have the same material composition. Each horizontal surface of the second continuous insulating layer 232L may lie within a horizontal plane that includes a horizontal surface of a corresponding one of the second insulating plates 232' within the vertically alternating sequence of second insulating plates 232' and second dielectric material plates 242'.

[0133] Generally speaking, the sidewalls of each second dielectric filler material portion 265' that does not contact the first-type second-level moat trench are tapered such that the horizontal cross-sectional area of ​​each second dielectric filler material portion 265' increases with vertical distance from substrate 8. This is because the anisotropic etching process that forms the second stepped cavity etches the sidewalls of the second alternating layer stack (232L, 242L) with a taper angle, which may be in the range of 2 degrees to 25 degrees, such as in the range of 2 degrees to 8 degrees. Therefore, the second insulating plate 232' and the second dielectric material plate 242' within each first-type second-level moat trench may have a second lateral extent that decreases along the second horizontal direction hd2 with vertical distance from substrate 8. Furthermore, the second insulating plate 232' and the second dielectric material plate 242' within each first-type second-level moat trench may have a second lateral extent that decreases along the second horizontal direction hd2 with vertical distance from substrate 8. In one embodiment, at least one lateral sidewall of each second dielectric fill material portion 265' is not in contact with the first type second level moat trench and is in contact with a respective second vertical alternating sequence of second insulating plates 232' and second dielectric material plates 242'.

[0134] The second dielectric filler material portions 265' can cover and contact the second vertical alternating sequence of the second insulating plates 232' and the second dielectric material plates 242'. The second dielectric filler material portions 265' can extend laterally between a pair of inner longitudinal sidewalls of the first type of second layer moat trench. Due to the tapered angle of the longitudinal sidewalls of each second dielectric filler material portion 265' extending laterally along the second horizontal direction, a greater surface area of ​​the second dielectric filler material portions 265' can be physically exposed to one longitudinal section of the first type of second layer moat trench than to another longitudinal section of the first type of second layer moat trench.

[0135] A second dielectric fill material (such as silicon oxide) can be deposited in the second layer moat trenches and in the second layer support openings by a conformal deposition process such as a chemical mechanical deposition process. Excess portions of the second dielectric fill material can be removed from above the topmost layer of the second alternating layer stack (232L, 242L). Each remaining portion of the second dielectric fill material filling the second layer moat trenches comprises a second layer moat-shaped dielectric wall structure (276, 286). Each remaining portion of the second dielectric fill material filling the second layer support openings comprises a second layer support post structure 202. The second layer moat-shaped dielectric wall structure (276, 286) and the second layer support post structure 202 can be formed during the same or separate deposition steps. Each continuous combination of the first layer support post structure 201 and the second layer support post structure 202 constitutes an interlayer support post structure 20. A first subset of the second layer support post structure 202 can be a component of a corresponding interlayer support post structure 20, and a second subset of the second layer support post structure 202 can not contact any first layer support post structure 201. In addition, a first subset of the first-layer support column structures 201 may be components of the corresponding inter-layer support column structures 20, and a second subset of the first-layer support column structures 201 may not contact any second-layer support column structures 202. The second-layer trench-shaped dielectric wall structures (276, 286) include a first-type second-layer trench-shaped dielectric wall structure 276 filling the first-type second-layer trench grooves and a second-type second-layer trench-shaped dielectric filling structure 286 filling the second-type second-layer trench grooves.

[0136] Each second-layer moat-shaped dielectric wall structure (276, 286) includes four segments, each of which includes two longitudinal dielectric wall structures extending transversely along a first horizontal direction hd1 and two transverse dielectric wall structures extending transversely along a second horizontal direction hd2. The two longitudinal dielectric wall segments of each second-layer moat-shaped dielectric wall structure (276, 286) are referred to herein as a first dielectric wall structure W1 and a second dielectric wall structure W2. The first dielectric wall structure W1 and the second dielectric wall structure W2 include portions of the second-layer moat-shaped dielectric wall structure (276, 286) extending transversely along the first horizontal direction hd1, which are connected to each other by a pair of transverse dielectric wall portions of the second-layer moat-shaped dielectric wall structure (276, 286). Generally speaking, the first dielectric wall structure W1 and the second dielectric wall structure W2 extending transversely along the first horizontal direction hd1 can be formed through the material of the second alternating layer stack (232L, 242L) and the second dielectric cavity filling material portion 263 within the inter-array region 200. Each second dielectric cavity-filling material portion 263 can be divided into at least a second rearward stepped dielectric material portion 265 covering the stepped surface of the alternating layer stack ( 232L, 242L) and a second dielectric filling material portion 265′ located between the first dielectric wall structure W1 and the second dielectric wall structure W2. The first dielectric wall structure W1 and the second dielectric wall structure W2 can be portions of a moat-shaped dielectric material that fills two lateral extensions of the moat trench and can be connected to each other by a pair of lateral dielectric wall portions.

[0137] refer to Figures 9A to 9E A photoresist layer may be applied over the second alternating layer stack (232L, 242L) and may be photolithographically patterned to form an array of discrete openings within each memory array region 100. The pattern of openings in the photoresist layer may be the same as the pattern of the first layer memory openings, which is the same as the pattern of the sacrificial first layer memory opening fill portion 148. The pattern of openings in the photoresist layer may be transferred through the second alternating layer stack (232L, 242L) by a second anisotropic etching process to form second layer memory openings. Second layer memory openings are formed in the memory array region 100. Each cluster of second layer memory openings may be formed as a two-dimensional array of second layer memory openings.

[0138] An etching process may be performed to selectively remove sacrificial first-level memory opening fill portion 148 from the material of the first alternating layer stack (132L, 142L) and the second alternating layer stack (232L, 242L). Each cavity of the vertical stack that includes the volume of the second-level memory opening and the first-level memory opening is referred to herein as an inter-level memory opening 49 or memory opening 49. The photoresist layer may then be removed, for example, by ashing.

[0139] refer to Figure 10A, showing an inter-layer memory opening 49 in an enlarged view. Memory opening 49 extends through the first layer structure and the second layer structure. Generally speaking, memory opening 49 can be formed within each memory array region 100 where there is each layer of the first alternating layer stack (132L, 142L) and each layer within the second alternating layer stack (232L, 242L). In other words, each memory opening 49 can extend vertically through and can have sidewalls laterally bounded by each layer within the first alternating layer stack (132L, 142L) and each layer within the second alternating layer stack (232L, 242L).

[0140] See also Figure 10B , a layer stack including a blocking dielectric layer 52, a charge storage layer 54, a tunneling dielectric layer 56, and a semiconductor channel material layer 60L may be sequentially deposited in the interlayer memory opening 49. The blocking dielectric layer 52 may include a single dielectric material layer or a stack of multiple dielectric material layers. In one embodiment, the blocking dielectric layer may include a dielectric metal oxide layer that consists essentially of a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material comprising at least one metal element and at least oxygen. The dielectric metal oxide may consist essentially of at least one metal element and oxygen, or may consist essentially of at least one metal element, oxygen, and at least one non-metallic element such as nitrogen. In one embodiment, the blocking dielectric layer 52 may include a dielectric metal oxide having a dielectric constant greater than 7.9 (i.e., having a dielectric constant greater than the dielectric constant of silicon nitride). The thickness of the dielectric metal oxide layer may be in the range of 1 nm to 20 nm, but smaller and larger thicknesses may also be used. Subsequently, the dielectric metal oxide layer may serve as a dielectric material portion that blocks the stored charge from leaking to the control gate electrode. In one embodiment, the blocking dielectric layer 52 includes aluminum oxide. Alternatively or additionally, the blocking dielectric layer 52 can include a dielectric semiconductor compound, such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof.

[0141] Subsequently, a charge storage layer 54 may be formed. In one embodiment, the charge storage layer 54 may be a continuous layer or patterned discrete portions of a charge trapping material including a dielectric charge trapping material (e.g., which may be silicon nitride). Alternatively, the charge storage layer 54 may include a continuous layer or patterned discrete portions of a conductive material (such as doped polysilicon or a metallic material) that is patterned into a plurality of electrically isolated portions (e.g., floating gates), for example, by being formed as a continuous sacrificial material layer (142L, 242L) within a lateral recess. In one embodiment, the charge storage layer 54 includes a silicon nitride layer. In one embodiment, the continuous sacrificial material layer (142L, 242L) and the continuous insulating layer (132L, 232L) may have vertically overlapping sidewalls, and the charge storage layer 54 may be formed as a single continuous layer. Alternatively, the continuous sacrificial material layer (142L, 242L) can be laterally recessed relative to the sidewalls of the continuous insulating layer (132L, 232L), and a combination of a deposition process and anisotropic etching process can be used to form the charge storage layer 54 as a plurality of vertically spaced memory material portions. The thickness of the charge storage layer 54 can be in the range of 2 nm to 20 nm, although lesser and greater thicknesses can also be used.

[0142] The tunneling dielectric layer 56 comprises a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions. Charge tunneling can be performed by hot carrier injection or by Fowler-Nordheim tunneling induced charge transfer, depending on the operating mode of the single three-dimensional NAND string memory device to be formed. The tunneling dielectric layer 56 may include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitrides, dielectric metal silicates, alloys thereof, and / or combinations thereof. In one embodiment, the tunneling dielectric layer 56 may include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which stack is generally referred to as an ONO stack. In one embodiment, the tunneling dielectric layer 56 may include a substantially carbon-free silicon oxide layer or a substantially carbon-free silicon oxynitride layer. The thickness of the tunneling dielectric layer 56 may be in the range of 2 nm to 20 nm, but smaller and larger thicknesses may also be used. The stack of the blocking dielectric layer 52 , the charge storage layer 54 , and the tunneling dielectric layer 56 constitutes a memory film 50 that stores memory bits.

[0143] The semiconductor channel material layer 60L comprises a p-doped semiconductor material, such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel material layer 60L may have uniform doping. In one embodiment, the semiconductor channel material layer 60L has p-type doping, wherein the p-type dopant (such as boron atoms) is present at a concentration of 1.0×10 12 / cm 3 to 1.0×10 18 / cm 3 Such as 1.0×10 14 / cm 3 to 1.0×10 17 / cm 3 In one embodiment, the semiconductor channel material layer 60L includes boron-doped amorphous silicon or boron-doped polysilicon and / or consists essentially of boron-doped amorphous silicon or boron-doped polysilicon. In another embodiment, the semiconductor channel material layer 60L has n-type doping, wherein the n-type dopant (such as phosphorus atoms or arsenic atoms) is present at an atomic concentration of 1.0×10 12 / cm 3 to 1.0×10 18 / cm 3 Such as 1.0×10 14 / cm 3 to 1.0×10 17 / cm 3 The semiconductor channel material layer 60L exists at an atomic concentration within a range of 100 nm to 100 nm. The semiconductor channel material layer 60L may be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the semiconductor channel material layer 60L may be in the range of 2 nm to 10 nm, although smaller and larger thicknesses may also be used. A cavity 49 ′ is formed in the volume of each interlayer memory opening 49 that is not filled with the deposited material layer ( 52 , 54 , 56 , 60L).

[0144] See also Figure 10C, in the case where the cavity 49' in each memory opening is not completely filled with the semiconductor channel material layer 60L, a dielectric core layer can be deposited in the cavity 49' to fill any remaining portion of the cavity 49' within each memory opening. The dielectric core layer includes a dielectric material, such as silicon oxide or organosilicate glass. The dielectric core layer can be deposited by a conformal deposition method (such as low pressure chemical vapor deposition (LPCVD)) or by a self-planarization deposition process (such as spin coating). The horizontal portion of the dielectric core layer covering the top second continuous insulating layer 232L can be removed, for example, by recess etching. The recess etching continues until the top surface of the remaining portion of the dielectric core layer is recessed to a height between the top surface and the bottom surface of the topmost second insulating layer 232L. Each remaining portion of the dielectric core layer constitutes a dielectric core 62.

[0145] See also Figure 10D A doped semiconductor material having a second conductivity type can be deposited in a cavity overlying the dielectric core 62. The second conductivity type is opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The deposited doped semiconductor material, semiconductor channel material layer 60L, tunneling dielectric layer 56, charge storage layer 54, and portions of blocking dielectric layer 52 overlying the horizontal plane (which includes the top surface of the topmost second continuous insulating layer 232L) can be removed by a planarization process such as a chemical mechanical planarization (CMP) process.

[0146] Each remaining portion of the second conductivity type doped semiconductor material constitutes a drain region 63. The dopant concentration in the drain region 63 may be 5.0×10 19 / cm 3 to 2.0×10 21 / cm 3 The doped semiconductor material may be, for example, doped polysilicon.

[0147] Each remaining portion of the semiconductor channel layer 60L constitutes a vertical semiconductor channel 60, through which current can flow when the vertical NAND device including the vertical semiconductor channel 60 is turned on. The tunneling dielectric layer 56 is surrounded by the charge storage layer 54 and laterally surrounds the vertical semiconductor channel 60. Each set of adjacent blocking dielectric layers 52, charge storage layers 54, and tunneling dielectric layers 56 together constitute a memory film 50 that can store charge for a macroscopic retention time. In some embodiments, the blocking dielectric layer 52 may not be present in the memory film 50 at this step, and the blocking dielectric layer may be subsequently formed after forming the backside recess. As used herein, the macroscopic retention time refers to a retention time suitable for the operation of a memory device as a permanent memory device, such as a retention time exceeding 24 hours.

[0148] Each combination of the memory film 50 and the vertical semiconductor channel 60 (which is a vertical semiconductor channel) within the interlayer memory opening 49 constitutes a memory stack structure 55. The memory stack structure 55 is a combination of the vertical semiconductor channel 60, the tunneling dielectric layer 56, a plurality of memory elements including portions of the charge storage layer 54, and an optional blocking dielectric layer 52. The memory stack structure 55 can be formed across the memory array region 100 of the first alternating layer stack and the second alternating layer stack, wherein all layers of the first alternating layer stack and the second alternating layer stack are present. Each combination of the memory stack structure 55, the dielectric core 62, and the drain region 63 within the interlayer memory opening 49 constitutes a memory opening filling structure 58. Generally speaking, the memory opening filling structure 58 is formed within the memory opening 49. Each of the memory opening filling structures 58 includes a corresponding memory film 50 and a corresponding vertical semiconductor channel 60.

[0149] The semiconductor material layer 110 , the first layer structure ( 132L, 142L, 132 ′, 142 ′, 165 , 165 ′, 176 , 186 ), the second layer structure ( 232L, 242L, 232 ′, 242 ′, 265 , 265 ′, 276 , 286 ), the memory opening filling structure 58 and the support pillar structure 20 together constitute a memory level assembly.

[0150] refer to Figures 11A to 11E A contact-level dielectric layer 280 may be formed over the second alternating layer stack (232L, 242L). The contact-level dielectric layer 280 comprises a dielectric material such as silicon oxide and may be formed by a conformal or non-conformal deposition process. For example, the contact-level dielectric layer 280 may comprise undoped silicate glass and may have a thickness in the range of 100 nm to 600 nm, although lesser and greater thicknesses may also be used.

[0151] See also 12A to 12E A photoresist layer (not shown) may be applied over the contact-level dielectric layer 280 and photolithographically patterned to form linear openings extending laterally along a first horizontal direction hd1 and laterally spaced apart along a second horizontal direction hd2. The linear openings in the photoresist layer may be formed in areas where no memory opening fill structures 58 or support pillar structures 20 are present.

[0152] Line trench 79 may be formed by transferring a pattern in a photoresist layer (not shown) into semiconductor material layer 110 through contact-level dielectric layer 280 , second layer structures ( 232L, 242L, 232′, 242′, 265, 265′, 276, 286 ), and first layer structures ( 132L, 142L, 132′, 142′, 165, 165′, 176, 186 ). The contact-level dielectric layer 280, (132L, 142L, 132', 142', 165, 165', 176, 186), the second layer structure (232L, 242L, 232', 242', 265, 265', 276, 286), and the portion below the linear opening in the photoresist layer of the semiconductor material layer 110 can be removed by an anisotropic etching process to form line trenches 79. In one embodiment, line trenches 79 can be formed between clusters of the memory stack structure 55. The clusters of the memory stack structure 55 can be laterally separated by the line trenches 79 along the second horizontal direction hd2.

[0153] The line grooves 79 may be formed as a periodic one-dimensional array having a periodicity along the second horizontal direction hd2. The line grooves 79 may be numerically numbered in sequence of positive integers from one side to the other along the second horizontal direction hd2. In one embodiment, each odd-numbered line groove 79 may extend through the second alternating layer stack (232L, 242L) and the first alternating layer stack (132L, 142L) without etching through the first backward stepped dielectric material portion 165 or the second backward stepped dielectric material portion 265. Each even-numbered line groove 79 may extend through the second alternating layer stack (232L, 242L) and the first alternating layer stack (132L, 142L) and cut through the corresponding first backward stepped dielectric material portion 165 and the corresponding second backward stepped dielectric material portion 265. Although the drawings show only two odd-numbered line grooves 79 and one even-numbered line groove 79, it should be understood that Figure 12B The pattern shown in the Figure 1 The pattern of semiconductor dies 1000 shown is repeated along a second horizontal direction hd2.

[0154] Each alternating layer stack {(132L, 142L), (232L, 242L)} is divided into a plurality of alternating stacks (corresponding to the volume of the memory block) of insulating layer (132 or 232) and sacrificial material layer (142, 242) by line trenches 79. Each line trench 79 may extend laterally along a first horizontal direction hd1 through the inter-array region 200 and a pair of memory array regions 100 adjacent to the inter-array region 200. Additionally, each line trench 79 may extend vertically through the entire thickness of the alternating layer stack {(132L, 142L), (232L, 242L)}. Each patterned portion of the first alternating layer stack (132L, 142L) positioned between adjacent pairs of line trenches 79 constitutes a first layer alternating stack of first insulating layer 132 and first sacrificial material layer 142. Each patterned portion of the second alternating layer stack positioned between adjacent pairs of line trenches 79 constitutes a second layer alternating stack of a second continuous insulating layer 232L and a second continuous sacrificial material layer 242. Multiple alternating stacks of insulating layers (132 or 232) and sacrificial material layers (which may be first sacrificial material layers 142 or second sacrificial material layers 242) may be formed.

[0155] Each first backward stepped dielectric material portion 165 is divided into two separate first layer dielectric cavity filling material portions 163 by a line groove 79. Each second backward stepped dielectric material portion 265 is divided into two separate second layer dielectric cavity filling material portions 265 by a line groove 79. Each consecutive combination of the first layer alternating stack (132, 142) and the second layer alternating stack (232, 242) can be laterally bounded by adjacent pairs of line grooves 79. One of the adjacent pairs of line grooves 79 can divide the first backward stepped dielectric material portion 165 into two discrete dielectric material portions, such as a first portion of the first backward stepped dielectric material portion 165 and a second portion of the first backward stepped dielectric material portion 165. Additionally, one of the adjacent pairs of line trenches 79 may separate the second backward stepped dielectric material portion 265 into two discrete dielectric material portions, such as a first portion of the second backward stepped dielectric material portion 265 and a second portion of the second backward stepped dielectric material portion 265 .

[0156] In one embodiment, the semiconductor material layer 110 may have a doping with the same conductivity type (i.e., the first conductivity type) as the vertical semiconductor channel 60, and a source region 61 with a second conductivity type doping (the same conductivity type as the doping of the drain region 63) may be formed under each linear trench 79 by injecting a second conductivity type dopant.

[0157] See also 13A to 13EThe sacrificial material layer (142, 242) is selectively removed relative to the insulating layer (132, 232), the contact-level dielectric layer 280, and the semiconductor material layer 110. For example, an isotropic etching process may be used to introduce an etchant that selectively etches the material of the sacrificial material layer (142, 242) relative to the material of the insulating layer (132, 232), the material of the backward stepped dielectric material portion (165, 265), and the material of the outermost layer of the memory film 50 into the line trench 79. For example, the sacrificial material layer (142, 242) may include silicon nitride, and the material of the insulating layer (132, 232), the backward stepped dielectric material portion (165, 265), and the outermost layer of the memory film 50 may include silicon oxide.

[0158] The isotropic etching process may be a wet etching process using a wet etching solution, or may be a vapor phase (dry) etching process in which an etchant is introduced into the line trench 79 in a vapor phase. For example, if the sacrificial material layer (142, 242) comprises silicon nitride, the etching process may be a wet etching process in which the exemplary structure is immersed in a wet etching bath comprising phosphoric acid, which selectively etches silicon nitride over silicon oxide, silicon, and various other materials used in the art.

[0159] A backside recess (143, 243) is formed in the volume from which the sacrificial material layer (142, 242) is removed. The backside recess (143, 243) includes a first backside recess 143 formed in the volume from which the first sacrificial material layer 142 is removed and a second backside recess 243 formed in the volume from which the second sacrificial material layer 242 is removed. Each of the backside recesses (143, 243) can be a laterally extending cavity having a lateral dimension that is greater than the vertical extent of the cavity. In other words, the lateral dimension of each of the backside recesses (143, 243) can be greater than the height of the corresponding backside recess. Multiple backside recesses (143, 243) can be formed in the volume from which the material of the sacrificial material layer (142, 242) is removed. Each of the backside recesses (143, 243) may extend substantially parallel to the top surface of the substrate semiconductor layer 9. The backside recesses (143, 243) may be vertically bounded by the top surface of the underlying insulating layer (132, 232) and the bottom surface of the overlying insulating layer (132, 232). In one embodiment, each of the backside recesses (143, 243) may have a uniform height throughout.

[0160] Generally, the backside recesses (143, 243) can be formed by selectively removing the patterned portions of the first continuous sacrificial material layer 142L and the second continuous sacrificial material layer 242L from the patterned portions of the first continuous insulating layer 132L and the second continuous insulating layer 232L after forming the line trenches 79. The backside recesses (143, 243) can be formed by performing an isotropic etching process that provides an isotropic etchant that selectively etches the patterned portions of the first continuous insulating layer 132L and the second continuous insulating layer 232L and selectively etches the patterned portions of the first continuous sacrificial material layer 142L and the second continuous sacrificial material layer 242L from the moat-shaped dielectric wall structures (176, 186, 276, 286). After the isotropic etching process, the surface of the moat-shaped dielectric wall structure (176, 186, 276, 286) is physically exposed to the backside recess (143, 243).

[0161] See also 14A to 14E An optional backside blocking dielectric layer (not shown) may be optionally deposited in the backside recesses (143, 243) and the line trenches 79 and over the contact-level dielectric layer 280. The backside blocking dielectric layer comprises a dielectric material such as a dielectric metal oxide (e.g., aluminum oxide), silicon oxide, or a combination thereof.

[0162] At least one conductive material may be deposited in the plurality of backside recesses (143, 243), on the sidewalls of the line trenches 79, and above the contact-level dielectric layer 280. The at least one conductive material may be deposited by a conformal deposition method, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. The at least one conductive material may include an elemental metal, an intermetallic alloy of at least two elemental metals, a conductive nitride of at least one elemental metal, a conductive metal oxide, a conductive doped semiconductor material, a conductive metal semiconductor alloy such as a metal silicide, alloys thereof, and combinations or stacks thereof.

[0163] In one embodiment, the at least one conductive material may include at least one metallic material, i.e., a conductive material comprising at least one metallic element. Non-limiting exemplary metallic materials that may be deposited in the backside recess (143, 243) include tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, and ruthenium. For example, the at least one conductive material may include a conductive metal nitride liner comprising a conductive metal nitride material such as TiN, TaN, WN, or a combination thereof, and a conductive filler material such as W, Co, Ru, Mo, Cu, or a combination thereof. In one embodiment, the at least one conductive material used to fill the backside recess (143, 243) may be a combination of a titanium nitride layer and a tungsten filler material.

[0164] A conductive layer (146, 246) can be formed in the backside recess (143, 243) by depositing at least one conductive material. A plurality of first conductive layers 146 can be formed in the plurality of first backside recesses 143, a plurality of second conductive layers 246 can be formed in the plurality of second backside recesses 243, and a continuous metal material layer (not shown) can be formed on the sidewalls of each linear trench 79 and above the contact-level dielectric layer 280. Each of the first conductive layer 146 and the second conductive layer 246 can include a corresponding conductive metal nitride liner and a corresponding conductive filler material. Therefore, the first sacrificial material layer and the second sacrificial material layer (142, 242) can be replaced with the first conductive layer and the second conductive layer (146, 246), respectively. Specifically, each first sacrificial material layer 142 can be replaced with an optional portion of the backside blocking dielectric layer and the first conductive layer 146, and each second sacrificial material layer 242 can be replaced with an optional portion of the backside blocking dielectric layer and the second conductive layer 246. A backside cavity exists within the portion of each linear trench 79 that is not filled with the continuous layer of metal material.

[0165] Residual conductive material can be removed from the interior of the linear trenches 79. Specifically, the deposited metal material of the continuous metal material layer can be etched back from the sidewalls of each linear trench 79 and from above the contact-level dielectric layer 280, for example, by anisotropic or isotropic etching. Each remaining portion of the deposited metal material in the first backside recess constitutes a first conductive layer 146. Each remaining portion of the deposited metal material in the second backside recess constitutes a second conductive layer 246. The sidewalls of the first conductive layer 146 and the second conductive layer 246 can be physically exposed to the corresponding linear trench 79. The linear trenches 79 can have a pair of curved sidewalls having a non-periodic width variation along the first horizontal direction hd1 and a nonlinear width variation along the vertical direction.

[0166] Each conductive layer (146, 246) may be a conductive sheet including openings therein. A first subset of the openings through each conductive layer (146, 246) may be filled with a memory opening filling structure 58. A second subset of the openings through each conductive layer (146, 246) may be filled with a support pillar structure 20.

[0167] A subset of the conductive layers (146, 246) may include word lines for memory elements. The semiconductor devices in the semiconductor device 720 below may include word line switching devices (the word line switching devices are configured to control the bias voltage to the corresponding word lines) and / or bit line driver devices, such as sense amplifiers. The memory level assembly is positioned above the substrate semiconductor layer 9. The memory level assembly includes at least one alternating stack (132, 146, 232, 246) and a memory stack structure 55 vertically extending through the at least one alternating stack (132, 146, 232, 246). Each of the memory stack structures 55 includes a vertical stack of memory elements positioned at each level of the conductive layers (146, 246).

[0168] Generally, the patterned portions of the first continuous sacrificial material layer 142L and the second continuous sacrificial material layer 242L are replaced with the conductive layer (146, 246). A first layer alternating stack of the first insulating layer 132 and the first conductive layer 146 can be formed between each adjacent pair of line trenches 79. The first insulating layer 132 includes the patterned portion of the first continuous insulating layer 132L, and the first conductive layer 146 includes a first subset of the conductive layer (146, 246) and is interleaved with the first insulating layer 132. A second layer alternating stack of the second insulating layer 232 and the second conductive layer 246 is formed between adjacent pairs of line trenches 79. The second insulating layer 232 includes the patterned portion of the second continuous insulating layer 232L, and the second conductive layer 246 includes a second subset of the conductive layer (146, 246) interleaved with the second insulating layer 246.

[0169] Generally speaking, the remaining portion of the continuous sacrificial material layer (142L, 242L) located outside the region between the first dielectric wall structure W1 and the second dielectric wall structure W2 of each moat-shaped dielectric wall structure (176, 186, 276, 286) that remains after forming the linear trench 79 can be replaced with the conductive layer (146, 246). The remaining portion of each alternating layer stack located between the first dielectric wall structure W1 and the second dielectric wall structure W2 of each moat-shaped dielectric wall structure (176, 186, 276, 286) that remains after forming the linear trench 79 includes a vertical alternating sequence of insulating plates (132' or 232') and dielectric material plates (142' or 242'). The remaining portion of the continuous insulating layer (132L, 232L) and the conductive layer (146, 246) after forming the conductive layer (146, 246) includes an alternating stack of insulating layers (132 and / or 232) and conductive layers (146, 246). Each layer within the alternating stack {(132, 146) and / or (232, 246)} is present in a connection region between the first dielectric wall structure W1 and the first linear trench 791, which is the closest linear trench 79 for the first dielectric wall structure W1. A portion of the conductive layer (146, 246) may be located in a stepped region between the second dielectric wall structure W2 and the second linear trench 792, which is the closest linear trench 79 for the second dielectric wall structure W2. The stepped region may have a lateral extent that decreases with vertical distance from the substrate 8.

[0170] A line trench fill structure 76 may be formed in each line trench 79 . In one embodiment, a dielectric liner layer comprising a dielectric material, such as silicon oxide, may be conformally deposited around the perimeter of each line trench 79 and anisotropically etched to form a dielectric spacer 76A within each line trench 79 . At least one conductive material may be deposited in the remaining volume of the backside trench 79 , and excess portions of the at least one conductive material may be removed from above the top surface of the contact-level dielectric layer 280 by a planarization process. Each remaining portion of the at least one conductive material that contacts the source region 61 and is laterally surrounded by a corresponding dielectric spacer 76A constitutes a source contact via structure 76B extending laterally along a first horizontal direction hd1. Each continuous combination of dielectric spacers 76A and source contact via structures 76B filling the line trenches 79 constitutes a line trench fill structure 76.

[0171] Alternatively, at least one dielectric material, such as silicon oxide, can be conformally deposited in line trench 79 by a conformal deposition process. Each portion of the deposited dielectric material that fills line trench 79 constitutes a line trench filling structure 76. In this case, each line trench filling structure can fill the entire volume of line trench 79 and can be essentially composed of at least one dielectric material. In this alternative embodiment, source region 61 can be omitted, and horizontal source lines (e.g., direct stripe contact layers) can contact the sides of the lower portion of semiconductor channel 60.

[0172] In one embodiment, each first backward stepped dielectric material portion 165 , each second backward stepped dielectric material portion 265 , and each moat-shaped dielectric wall structure ( 176 , 186 , 276 , 286 ) may be located between adjacent pairs of line trench filling structures 76 .

[0173] See also Figures 15A to 15E Various metal via structures (88, 86A, 86B, 486A, 486B) may be formed through the contact-level dielectric layer 280 and, optionally, through underlying material portions on corresponding underlying conductive structures. The various contact via structures (88, 86A, 86B, 486A, 486B) may include drain contact via structures 88 formed through the contact-level dielectric layer 280 on the top surfaces of corresponding drain regions 63 in the memory array region 100. The various contact via structures (88, 86A, 86B, 486A, 486B) may include layer contact via structures (e.g., word line and select gate contact via structures) (86A, 86B) formed in the inter-array region 200. The layer contact via structures (86A, 86B) may include a first contact via structure 86A that contacts the corresponding first conductive layer (e.g., a lower word line or a source select gate electrode) 146 and a second contact via structure 86B that contacts the corresponding second conductive layer (e.g., an upper word line or a drain select gate electrode) 246. Additionally, the various contact via structures (88, 86A, 86B, 486A, 486B) may include a connecting via structure (486A, 486B) formed in the inter-array region 200. The connecting via structures (486A, 486B) extend vertically through the second layer structure, the first layer structure, and the opening in the semiconductor material layer 110, and contact the top surface of a lower-level metal interconnect structure (such as a metal pad 786).

[0174] The metal via structures (88, 86A, 86B, 486A, 486B) can be formed by forming via cavities extending vertically downward through openings in the contact-level dielectric layer 280 and / or the second layer structure and / or the first layer structure and / or the semiconductor material layer 110 to the corresponding conductive structures, and by filling these via cavities with at least one conductive material. The various via cavities can be formed using a single photolithographic patterning process that forms a patterned photoresist layer as an etch mask and a single anisotropic etching process that selectively removes unmasked portions of the exemplary structure for the underlying conductive structure (which can be a metal structure, such as the conductive layer (146, 246) or the metal pad 786 or the drain region 63). Alternatively, various combinations of photolithographic patterning processes and anisotropic etching processes can be used to form the various via cavities. The via cavities include drain contact vias extending to a top surface of a corresponding one of the drain regions 63, layer contact via cavities extending to a top surface of a corresponding one of the conductive layers (146, 246), and connection via cavities extending to a top surface of a corresponding one of the metal pads 786. The at least one conductive material filling the via cavities may include, for example, a combination of a metal nitride liner (which may include TiN, TaN, and / or WN) and a metal fill material (such as W, Cu, Co, Ru, Mo, and / or another metal).

[0175] Each layer contact via structure (86A, 86B) extends vertically through the corresponding rear stepped dielectric material portion (165 or 265) and contacts the top surface of one of the conductive layers (146, 246). Each first layer contact via structure 86A may extend vertically through the vertical alternating sequence of second insulating plates 232' and second dielectric material plates 242' and through the first rear stepped dielectric material portion 165 and may contact the top surface of the corresponding first conductive layer 146. Each second layer contact via structure 86B may extend vertically through the second rear stepped dielectric material portion 265 and may contact the top surface of the corresponding first conductive layer 146. Figure 15B The illustrated stepped region SR contacts the top surface of the corresponding second conductive layer 246 .

[0176] Each connecting via structure (486A, 486B) extends vertically through a corresponding vertical alternating sequence of insulating plates and dielectric material plates and may contact the top surface of a corresponding metal pad 786. For example, each first connecting via structure 486A may extend vertically through each plate within the vertical alternating sequence of second insulating plates 232' and second dielectric material plates 242', first dielectric filler material portion 165', and a subset of plates within the vertical alternating sequence of first insulating plates 132' and first dielectric material plates 142'. Each second connecting via structure 486B may extend vertically through second dielectric filler material portion 265', a subset of plates within the vertical alternating sequence of second insulating plates 232' and second dielectric material plates 242', and each plate within the vertical alternating sequence of first insulating plates 132' and first dielectric material plates 142'.

[0177] Generally speaking, the connecting via structures (486A, 486B) extend vertically through a respective vertical alternating sequence of insulating plates (132' or 232') and dielectric material plates (142' or 242') and contact a respective one of the lower-level metal interconnect structures 780. Where the exemplary structure includes multiple layers, additional alternating stacks of additional insulating layers (132 or 232) and additional conductive layers (146 or 246) may be located between the first line-trench 791 and the second line-trench 792, with the respective connecting via structures (486a, 486b) located between the first line-trench and the second line-trench. Additional alternating stacks of additional insulating layers (132 or 232) and additional conductive layers (146 or 246) may be located above or below the alternating stacks of insulating layers (132 or 232) and conductive layers (146 or 246) that laterally surround the corresponding vertical alternating sequence of insulating plates (132' or 232') and plates of dielectric material (142' or 242'). For example, if a connecting via structure, such as first connecting via structure 486A, extends vertically through a subset of plates within the corresponding vertical alternating sequence of first insulating plates 132' and first dielectric material plates 142' that are laterally surrounded by the first alternating stack of first insulating layers 132 and first conductive layers 146, the additional alternating stack may be a second alternating stack (232, 246) of second insulating layers 232 and second conductive layers 246. If a connecting via structure such as the second connecting via structure 486B extends vertically through a subset of the plates within the corresponding vertical alternating sequence of second insulating plates 232' and second dielectric material plates 242' that are laterally surrounded by a second alternating stack of second insulating layers 232 and second conductive layers 246, the additional alternating stack can be the first alternating stack (132, 146) of the first insulating layer 132 and the first conductive layer 146.

[0178] Additional vertically alternating sequences of additional insulating plates (132' or 232') and additional dielectric material plates (142' or 242') may be embedded within additional alternating stacks of additional insulating layers (132 or 232) and additional conductive layers (146 or 246). Connecting via structures (486A or 486B) may extend vertically through each of the additional insulating plates (132' or 232') and each of the additional dielectric material plates (142' or 242'). For example, first connecting via structure 486A may extend vertically through and contact each plate within the vertically alternating sequence of second insulating plate 232' and second dielectric material plate 242'. Second connecting via structure 486B may extend vertically through and contact each plate within the vertically alternating sequence of first insulating plate 132' and first dielectric material plate 142'.

[0179] Each trench-shaped dielectric wall structure (176, 186, 276, 286) may include a corresponding first dielectric wall structure W1 and a second dielectric wall structure W2 located between a first linear trench 791 and a second linear trench 792. The first linear trench 791 is the closest linear trench to the corresponding first dielectric wall structure W1, and the second linear trench 792 is the closest linear trench to the corresponding second dielectric wall structure W2. The pair of first and second dielectric wall structures W1 and W2 may be located between the first and second memory array regions 100A and 100B and may extend laterally along the first horizontal direction hd1 and may have a lateral extent smaller than the lateral extent of the first and second linear trenches 791 and 792 along the first horizontal direction hd1. Figure 15B As shown, the connection region CR is located between the first linear trench 791 and the first dielectric wall structure W1, and each layer within the alternating stack of insulating layers (132 or 232) and conductive layers (146 or 246) extends continuously between the first memory array area 100A and the second memory array area 100B in the connection region CR. The stepped region SR is located between the second linear trench 792 and the second dielectric wall structure W2, and the alternating stack of conductive layers (146 or 246) has a lateral extent that decreases with distance from the substrate 8 along the first horizontal direction hd1 due to the presence of the stepped surface.

[0180] In the case of multiple layers within the exemplary structure, additional alternating stacks of additional insulating layers (132 or 232) and additional conductive layers (146 or 246) are located above or below the alternating stacks embedded in the first dielectric wall structure W1 and the second dielectric wall structure W2. The first additional dielectric wall structure and the second additional dielectric wall structure can be disposed within the upper or lower structure and can contact the additional alternating stacks and the additional vertical alternating sequence of additional insulating plates (132' or 232') and additional plates of dielectric material (142' or 242'). The additional vertical alternating sequence can be laterally bounded by the first additional dielectric wall structure and the second additional dielectric wall structure along a second horizontal direction hd2 (which is perpendicular to the first horizontal direction hd1). In one embodiment, an additional vertical alternating sequence of additional insulating plates 232' and additional dielectric material plates 242' covers the stepped region of the alternating stack (132, 146), and the layer contact via structure 86A extends vertically through each of the additional insulating plates 232' and each of the additional dielectric material plates 242', as shown. Figure 15D shown.

[0181] refer to 16A to 16E , a higher level metal interconnect structure may be formed above the contact level dielectric layer 280. The higher level metal interconnect structure may include many levels of metal lines and many levels of metal via structures. The higher level metal interconnect structure is embedded in a higher level dielectric material layer (such as the first line level dielectric material layer 290). Although only first metal lines (98, 296) are shown at the first metal line level, it should be understood that additional metal lines and additional metal via structures may be provided as needed. The first metal lines (98, 296) may include a bit line 98 that electrically contacts the drain contact via structure 88 and a word line connection metal line 296 that electrically connects a corresponding pair of level contact via structures (86A or 86B) and a connecting via structure (486A or 486B). The word line connection metal line 296 extends a relatively short distance between the corresponding pair of level contact via structures (86A or 86B) and the connecting via structure (486A or 486B), which reduces the overall resistance of the electrical connection. For example, a connecting via structure (486A or 486B) may connect the corresponding word line (86A or 86B) with its word line switching circuit device (eg, transistor) 720 located below the alternating stack.

[0182] The first metal lines may include additional metal lines that may provide electrical connections to various additional via structures (not shown) extending through the contact-level dielectric layer 280. Generally, a higher-level dielectric material layer is formed over the alternating stacks of insulating layers (132, 232) and conductive layers (146, 246), the vertical alternating sequence of insulating plates (132', 232') and dielectric material plates (142', 242'), and the connecting via structures (486A, 486B) and the layer contact via structures (86A, 86B). In one embodiment, the layer contact via structures (86A, 86B) may be electrically connected to a respective one of the connecting via structures (486A, 486B) through a respective metal line of a higher-level metal interconnect structure, such as a wordline connection metal line 296.

[0183] See also 17A to 17E , showing a first alternative configuration of the exemplary structure. In an alternative configuration of the exemplary structure, the trench-shaped dielectric wall structure (176, 186, 276, 286) can be replaced with a pair of discrete dielectric wall structures {(376A, 376B) or (366A, 366B)}. In this case, a pair of linear openings that are laterally spaced apart and separated from each other along the second horizontal direction hd2 can be formed through the corresponding alternating layer stack of continuous insulating layers (132L or 232L) and continuous sacrificial material layers (142L or 242L) to replace one, each, or all of the trench-shaped openings. The first dielectric wall structure (376A or 366A) and the second dielectric wall structure (376B or 366B) can be formed by filling the pair of linear openings with a dielectric filler material when forming the first layer support column structure 201 or the second column support column structure 202.

[0184] Each pair of first dielectric wall structures (376A or 366A) and second dielectric wall structures (376B or 366B) may extend laterally along a first horizontal direction hd1 across the corresponding alternating layer stack {(132L, 142L) or (232L, 242L)} and the corresponding dielectric cavity filling material portion (163 or 263) within the inter-array region 200. The dielectric cavity filling material portion (163 or 263) is divided into a rearward stepped dielectric material portion (165 or 265) covering the stepped surface of the alternating layer stack and a dielectric filling material portion (165' or 265') located between the first dielectric wall structure (376A or 366A) and the second dielectric wall structure (376B or 366B). In this case, the first dielectric wall structure (376A or 366A) and the second dielectric wall structure (376B or 366B) are two separate material portions that are not in direct contact with each other.

[0185] exist 13A to 13EDuring the process step of forming the backside recess (143, 243), the duration of the isotropic etching process for removing material of the continuous sacrificial material layer (142L, 242L) is controlled so that the portion of the continuous sacrificial material layer (142L, 242L) located between each adjacent pair of first dielectric wall structures (376A or 366A) and second dielectric wall structures (376B or 366B) is not removed by the isotropic etching process. Each remaining portion of the continuous sacrificial material layer (142L, 242L) constitutes a dielectric material plate (142', 242'), which includes the first dielectric material plate 142' and the second dielectric material plate 142'. Each portion of the insulating layer (132, 232) that has an area overlap with one of the directly overlying dielectric material plates (142', 242') or with one of the directly underlying dielectric material plates (142', 242') constitutes an insulating plate (132' or 232'). In this case, each insulating plate (132' or 232') directly abuts a respective one of the insulating layers (132, 232). The vertically alternating sequence of insulating plates 132' and dielectric material plates 142' can be embedded within the alternating stack of insulating layers (132, 232) and conductive layers (146, 246). The conductive layers (146, 246) of the alternating stack {(132, 146) or (232, 246)} and the dielectric material plates (142', 242') of the vertical alternating sequence {(132', 142') or (232', 242')} may contact each other at a vertical interface located within two vertically extending planes laterally spaced apart along the first horizontal direction hd1.

[0186] See also Figure 18 , shows a second alternative configuration of the exemplary structure. In the second alternative configuration of the exemplary structure, the pair of discrete dielectric wall structures {(376A, 376B) or (366A, 366B)} can be replaced by a single dielectric wall structure 476. The single dielectric wall structure 476 can have the same thickness as one of the pair of discrete dielectric wall structures, or can be thicker than one of the pair of discrete dielectric wall structures. After removing the sacrificial material layer (142L, 242L), the single dielectric wall structure 476 provides additional support to the insulating layer (132L, 232L). The single dielectric wall structure 476 has an elongated shape, the horizontal length of which in one horizontal direction (e.g., hd1) is at least 3 times longer than its horizontal width in the perpendicular horizontal direction (e.g., hd2), such as 5 to 100 times longer. Thus, the dielectric wall structure 476 has a non-cylindrical and non-truncated conical shape. In this embodiment, the layer contact via structure 86A may be surrounded by dielectric spacers to avoid electrically contacting all but a corresponding one of the conductive layers.

[0187] The single dielectric wall structure 476 has a higher mechanical strength than the cylindrical support post structure 20. The dielectric wall structure 476 does not bend under compressive stress and can suppress compressive stress and allow for wider spacing of the support post structure 20 without bending the insulating layer (132L, 232L) after removing the sacrificial material layer (142L, 242L). The wider spacing (i.e., pitch) of the support post structure 20 reduces the likelihood that the layer contact via structure 86 will overlap with the support post structure 20 and interfere with the support post structure, and allows a larger volume of the conductive layer (146, 246) to be present in the inter-array region 200. This reduces the overall resistivity of the conductive layer. In addition, the total area of ​​the staircase region in the inter-array region 200 can be reduced, which reduces the chip area.

[0188] Although various dielectric wall structures are described above as being located in the inter-array region 200, the dielectric wall structures may be located in other stepped regions. For example, the dielectric wall structures may be located in the stepped region at the edge of the die, near the end of the last memory array region 100 of the die.

[0189] With reference to all drawings and in accordance with all embodiments of the present disclosure, a three-dimensional memory device includes: an alternating stack of insulating layers (132, 232) and conductive layers (146, 246), the alternating stack being located between first and second line trenches 791, 792, the first and second line trenches extending laterally along a first horizontal direction hd1 and above a substrate 8;

[0190] A first memory array region 100A and a second memory array region 100B are laterally spaced apart along a first horizontal direction hd1 and include each layer of the alternating stack, wherein a corresponding set of memory stack structures 55, each including a vertical semiconductor channel 60 and a memory film 50, extends vertically through the alternating stack within each of the first memory array region 100A and the second memory array region 100B; at least one dielectric wall structure (W1, 376A, 366A, or 476) located between the first line trench and the second line trench and located in the first memory array region; between the memory array region and the second memory array region, extending through all layers of the alternating stack, extending laterally along the first horizontal direction hd1, having a lateral extent smaller than the lateral extent of the first line groove and the second line groove along the first horizontal direction hd1, and a length along the first horizontal direction being at least three times its width extending along the second horizontal direction hd2 perpendicular to the first horizontal direction hd1; and a step region SR is located between the second line groove 792 and the at least one dielectric wall structure, and the alternatingly stacked conductive layers (146, 246) have a lateral extent in the stair region that decreases with distance from the substrate along the first horizontal direction.

[0191] exist 16A to 16E In an embodiment, the at least one dielectric wall structure includes a portion of a trench-shaped dielectric material, the alternating stack of dielectric material plates (142', 242') and insulating plates (132', 232') is surrounded by the trench-shaped dielectric material, and the connecting through-hole structure (486A, 486B) extends vertically through the alternating stack of dielectric material plates and insulating plates and contacts a corresponding one of the lower-level metal interconnect structures 786 and a corresponding one of the higher-level metal interconnect structures 296.

[0192] exist 17A to 17E In an embodiment, the at least one dielectric wall structure includes a pair of dielectric wall structures, an alternating stack of dielectric material plates (142', 242') and insulating layers (132, 232) is located between the pair of dielectric wall structures, and a connecting through-hole structure (486A, 486B) extends vertically through the alternating stack of dielectric material plates and insulating layers and contacts a corresponding one of the lower-level metal interconnect structures and a corresponding one of the higher-level metal interconnect structures.

[0193] exist Figure 18 In the embodiment, the at least one dielectric wall structure includes a single dielectric wall structure 476 , and a plurality of support post structures 20 having a cylindrical or truncated conical shape are located between the single dielectric wall structure 476 and the second linear trench 792 .

[0194] With reference to all drawings and according to Figures 1 to 17ESome embodiments of the present disclosure provide a three-dimensional memory device, the three-dimensional memory device comprising: an alternating stack of insulating layers (132 or 232) and conductive layers (146 or 246), the alternating stack being located between first and second line trenches 791 and 792, the first and second line trenches extending laterally above a substrate 8 along a first horizontal direction hd1; a first memory array region 100A and a second memory array region 100B, the first and second memory array regions being laterally spaced apart along the first horizontal direction hd1 and comprising the alternating stack {(132, 146) or (232, 246)}. 6)}, wherein a corresponding set of memory stack structures 55 each including a vertical semiconductor channel 60 and a memory film 50 extends vertically through the alternating stack {(132, 146) or (232, 246)} within each of the first memory array region 100A and the second memory array region 100B; a first dielectric wall structure (W1, 376A or 366A) and a second dielectric wall structure (W2, 376B or 366B) located between the first line trench 791 and the second line trench 792 and located between the first memory array region 100A and the second memory array region The first memory array region 100A and the second memory array region 100B are connected to each other, extending laterally along the first horizontal direction hd1 and having a lateral extent smaller than the lateral extent of the first linear trench 791 and the second linear trench 792, wherein the connection region CR is located between the first linear trench 791 and the first dielectric wall structure (W1, 376A or 366A), and each layer within the alternating stack {(132, 146) or (232, 246)} extends continuously between the first memory array region 100A and the second memory array region 100B of the connection region, and the step region SR is located between the second linear trench 792 and the second dielectric wall structure (W2, 376B or 366B). between the first dielectric wall structure (W1, 376A or 366A) and the second dielectric wall structure (W2, 376B or 366B), wherein the conductive layers (146 or 246) of the alternating stack {(132, 146) or (232, 246)} have a lateral extent that decreases with the distance from the substrate 8 along the first horizontal direction hd1; and an alternating stack of dielectric material plates (142', 242') and insulating plates (132', 232') or layers (132, 232), the alternating stack being located between the first dielectric wall structure (W1, 376A or 366A) and the second dielectric wall structure (W2, 376B or 366B), wherein the dielectric material plates (142' or 242') have a horizontal cross-sectional area that decreases with the vertical distance from the substrate 8.

[0195] In one embodiment, the plate of dielectric material (142', 242') has a first lateral extent that decreases with vertical distance from the substrate 8 along a first horizontal direction hd1. In one embodiment, the plate of dielectric material (142' or 2142') has a second lateral extent that decreases with vertical distance from the substrate 8 along a second horizontal direction hd2, wherein the second horizontal direction hd2 is perpendicular to the first horizontal direction hd1. In one embodiment, a three-dimensional memory device includes a dielectric filling material portion (165' or 265') overlying a dielectric material plate (142' or 242') and contacting a first dielectric wall structure (W1, 376A or 366A) and a second dielectric wall structure (W2, 376B or 366B), wherein the dielectric filling material portion (165' or 265') has a greater contact area with the second dielectric wall structure (W2, 376B or 366B) than with the first dielectric wall structure (W1, 376A or 366A) (due to a stepped cavity and a taper angle in the dielectric cavity filling material portion (163 or 263) employed during a fabrication process).

[0196] In one embodiment, the three-dimensional memory device includes: a lower-level dielectric material layer 760 located between the substrate 8 and the combination of the alternating stack {(132, 146) or (232, 246)} and the dielectric material plate (142' or 242') and embedded in the lower-level metal interconnect structure 780; a higher-level dielectric material layer (which may include a first line-level dielectric material layer 290) located between the alternating stack {(132, 146) or (232, 246)} and the dielectric material plate (142' or 242'); and a lower-level metal interconnect structure 780 embedded in the lower-level metal interconnect structure 780. , 246)} and the combination of the dielectric material plate (142' or 242') and embedded in the higher level metal interconnect structure (such as the first metal line (98, 296)); and connecting via structures (486A, 486B) that extend vertically through the dielectric material plate (142' or 242') and contact a corresponding one of the lower level metal interconnect structures 780 (such as the metal pad 786) and a corresponding one of the higher level metal interconnect structures (such as the word line connecting metal line 296).

[0197] In one embodiment, a three-dimensional memory device includes layer contact via structures (86A, 86B) that contact a top surface of a respective one of the conductive layers (146 or 246) within the region of the stepped region SR. In one embodiment, the layer contact via structures (86A, 86B) are electrically connected to a respective one of the connection via structures (486A, 486B) through a respective metal line of a higher-level metal interconnect structure (such as a word line connection metal line 296).

[0198] In one embodiment, a three-dimensional memory device includes: an additional alternating stack {(232, 246) or (132, 146)} of additional insulating layers (132 or 232) and additional conductive layers (146 or 246), the additional alternating stack being located between the first line trenches 791 and the second line trenches 792 and being located above or below the alternating stack {(132, 146) or (232, 246)}; and additional dielectric material plates (242' or 142') embedded within the additional alternating stack {(232, 246) or (132, 146)}, wherein a connecting via structure (486A, 486B) extends vertically through each of the additional dielectric material plates (242' or 142'). In one embodiment, the three-dimensional memory device includes a first additional dielectric wall structure (W1, 376A or 366A) and a second additional dielectric wall structure (W2, 376B or 366B) that contact the additional dielectric material plate. (242' or 142') , wherein the additional dielectric material plate (242' or 242') contacts the additional dielectric wall structure (W1, 376A or 366A) and the second additional dielectric wall structure (W2, 376B or 366B) and is laterally bounded by the additional dielectric wall structure and the second additional dielectric wall structure along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1.

[0199] In one embodiment, the additional dielectric material plate 242' covers the stepped region SR of the alternating stack (132, 146); and the layer contact via structure 86A extends vertically through each of the additional dielectric material plates 242'. In one embodiment, the three-dimensional memory device includes a moat trench that laterally surrounds the dielectric material plate (142' or 242') and is laterally surrounded by the alternating stack {(132, 146) or 9232, 246}}, wherein the first dielectric wall structure W1 and the second dielectric wall structure W2 are parts of two laterally extending portions of the moat-shaped dielectric material filling the moat trench and are directly or indirectly connected to each other through a pair of lateral dielectric wall portions.

[0200] In one embodiment, the first dielectric wall structure (376A, 366A) and the second dielectric wall structure (376B, 366B) are two separate material portions that are not in direct contact with each other; and the conductive layers (146 or 246) and the dielectric material plates (142' or 242') of the alternating stacks {(132, 146) or (232, 246)} are in contact at a vertical interface located in two vertically extending planes spaced laterally apart along a first horizontal direction hd1. The vertically extending planes may have a curvature in a horizontal cross-sectional view, such as Figure 17B shown.

[0201] In one embodiment, the dielectric material plates (142' or 242') are staggered with the insulating plates (132' or 232') in a vertical direction; the insulating layer (132 or 232) and the insulating plates (132' or 232') have the same material composition; and each horizontal surface of the insulating layer (132 or 232) is located within a horizontal plane that includes a horizontal surface of a corresponding one of the insulating plates (132' or 232').

[0202] By replacing some of the discrete support post structures 20 around each region with dielectric wall structures {(W1, W2), (376A, 366A, 376B, 366B) and / or 476}, various embodiments of the present disclosure can be used to provide wider conductive paths in the connection region CR through which the layer contact via structures (86A, 86B) or the connection via structures (486A, 486B) are formed. The dielectric wall structures provide more structural support per length along the first horizontal direction hd1 and reduce the variation in the collapse of the insulating layer (132L, 242L) after the sacrificial material layer (142L, 242L) is removed. As a result, the total number and density of support post structures 20 located within the connection region CR and the step region SR can be reduced, and a greater percentage of the inter-array region 200 can be utilized to provide conductive paths that include the strip portions of the conductive layer (146, 246) present within the connection region CR. This reduces the overall resistance of the conductive layer (eg, word line) ( 146 , 246 ) and reduces the likelihood that the support post structure 20 will interfere with and overlap the layer contact structure 86 .

[0203] Although specific embodiments have been mentioned above, it should be understood that the present disclosure is not limited thereto. It will be appreciated by those skilled in the art that various modifications may be made to the disclosed embodiments, and such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless expressly stated otherwise, the words "comprising" or "including" contemplate all embodiments in which the words "consisting essentially of" or the words "consisting of" replace the words "comprising" or "including." Where embodiments using specific structures and / or configurations are shown in the present disclosure, it should be understood that the present disclosure can be practiced with any other compatible structures and / or configurations that are functionally equivalent, provided that such substitution is not expressly prohibited or otherwise deemed impossible by those skilled in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A three-dimensional memory device, characterized in that: The three-dimensional memory device comprises: an alternating stack of insulating layers and conductive layers, the alternating stack being located between first linear trenches and second linear trenches, the first linear trenches and the second linear trenches extending laterally above the substrate in a first horizontal direction; a first memory array region and a second memory array region, the first memory array region and the second memory array region being laterally spaced apart along the first horizontal direction and comprising each layer of the alternating stack, wherein a respective set of memory stack structures each including a vertical semiconductor channel and a memory film extends vertically through the alternating stack within each of the first memory array region and the second memory array region; a first dielectric wall structure and a second dielectric wall structure, the first dielectric wall structure and the second dielectric wall structure being located between the first linear trench and the second linear trench and between the first memory array region and the second memory array region, extending laterally along the first horizontal direction, and having a lateral extent in the first horizontal direction that is smaller than a lateral extent of the first linear trench along the first horizontal direction and smaller than a lateral extent of the second linear trench along the first horizontal direction, wherein a connection region is located between the first linear trench and the first dielectric wall structure, and a step region is located between the second linear trench and the second dielectric wall structure, and the alternatingly stacked conductive layers have a lateral extent that decreases in the vertical direction as the vertical distance from the substrate increases along the first horizontal direction; and an alternating stack of plates of dielectric material and insulating plates or layers, said alternating stack being located between said first dielectric wall structure and said second dielectric wall structure, wherein said plates of dielectric material have a horizontal cross-sectional area that decreases in a vertical direction with increasing said vertical distance from said substrate; and wherein the three-dimensional memory device further comprises: a lower level dielectric material layer positioned between the substrate and the combination of the alternating stacks and the dielectric material plates and embedding a lower level metal interconnect structure; a higher level dielectric material layer overlying said combination of said alternating stacks and said dielectric material plates and embedding a higher level metal interconnect structure; a connecting via structure extending vertically through the dielectric material plate and contacting a respective one of the lower-level metal interconnect structures and a respective one of the higher-level metal interconnect structures; and a layer contact via structure contacting a top surface of a corresponding one of the conductive layers within a region of the stepped region; and wherein the three-dimensional memory device further comprises: an additional alternating stack of additional insulating layers and additional conductive layers, the additional alternating stack being located between the first and second line trenches and above or below the alternating stack; and Additional plates of dielectric material are embedded within the additional alternating stack, wherein the connecting via structure extends vertically through each of the additional plates of dielectric material.

2. The three-dimensional memory device according to claim 1, wherein: the plate of dielectric material having a first lateral extent that decreases with the vertical distance from the substrate along the first horizontal direction; and The plate of dielectric material has a second lateral extent that decreases with the vertical distance from the substrate along a second horizontal direction, wherein the second horizontal direction is perpendicular to the first horizontal direction.

3. The three-dimensional memory device according to claim 2 , further comprising a dielectric filling material portion covering the dielectric material plate and contacting the first dielectric wall structure and the second dielectric wall structure, wherein a contact area of ​​the dielectric filling material portion with the second dielectric wall structure is larger than a contact area with the first dielectric wall structure. 4 . The three-dimensional memory device of claim 1 , wherein the layer contact via structure is electrically connected to a corresponding one of the connection via structures through a corresponding metal line of the higher-level metal interconnect structure.

5. The three-dimensional memory device of claim 1 , further comprising a first additional dielectric wall structure and a second additional dielectric wall structure in contact with the additional dielectric material plate, wherein the additional dielectric material plate is laterally bounded by the first additional dielectric wall structure and the second additional dielectric wall structure along a second horizontal direction perpendicular to the first horizontal direction.

6. The three-dimensional memory device according to claim 1 , wherein: The additional dielectric material sheet covers the stepped regions of the alternating stacks; and The layer contact via structure extends vertically through each of the plates of additional dielectric material.

7. The three-dimensional memory device of claim 1 , further comprising a moat trench laterally surrounding the dielectric material plate and laterally surrounded by the alternating stack, wherein the first dielectric wall structure and the second dielectric wall structure are portions of a moat-shaped dielectric material filling two laterally extending portions of the moat trench and are directly or indirectly connected to each other through a pair of lateral dielectric wall portions.

8. The three-dimensional memory device according to claim 1, wherein: The first dielectric wall structure and the second dielectric wall structure are two separate material portions that are not in direct contact with each other; and The alternating stacks of the conductive layers and the dielectric material plates are in contact at vertical interfaces located within two vertically extending planes that are laterally spaced apart along the first horizontal direction.

9. The three-dimensional memory device according to claim 1 , wherein: The dielectric material plates are interlaced with the insulating plates along the vertical direction; The insulating layer and the insulating plate have the same material composition; and Each horizontal surface of the insulating layer lies within a horizontal plane including a horizontal surface of a corresponding one of the insulating plates.

10. A three-dimensional memory device, characterized in that: The three-dimensional memory device comprises: an alternating stack of insulating layers and conductive layers, the alternating stack being located between first linear trenches and second linear trenches, the first linear trenches and the second linear trenches extending laterally above the substrate in a first horizontal direction; a first memory array region and a second memory array region, the first memory array region and the second memory array region being laterally spaced apart along the first horizontal direction and comprising each layer of the alternating stack, wherein a respective set of memory stack structures each including a vertical semiconductor channel and a memory film extends vertically through the alternating stack within each of the first memory array region and the second memory array region; at least one dielectric wall structure, the at least one dielectric wall structure being located between the first linear trench and the second linear trench and between the first memory array region and the second memory array region, extending through all layers of the alternating stack, extending laterally along the first horizontal direction, having a lateral extent smaller than a lateral extent of the first linear trench and the second linear trench along the first horizontal direction, and having a length along the first horizontal direction that is at least three times its width extending along a second horizontal direction perpendicular to the first horizontal direction; and a stepped region between the second linear trench and the at least one dielectric wall structure, and the alternatingly stacked conductive layers have a lateral extent in the stepped region that decreases with distance from the substrate along the first horizontal direction; and wherein the at least one dielectric wall structure comprises a portion of a moat-shaped dielectric material; an alternating stack of dielectric material plates and insulating plates surrounded by the trench-shaped dielectric material; and connecting via structures extending vertically through the alternating stack of dielectric material plates and insulating plates and contacting a respective one of the lower level metal interconnect structures and a respective one of the higher level metal interconnect structures; and wherein the three-dimensional memory device further comprises: a lower level dielectric material layer located between the substrate and the combination of the alternating stacks and the dielectric material plates and embedding the lower level metal interconnect structure; a higher-level dielectric material layer overlying the combination of the alternating stacks and the dielectric material plates and embedding the higher-level metal interconnect structure; a connecting via structure extending vertically through the dielectric material plate and contacting a respective one of the lower-level metal interconnect structures and a respective one of the higher-level metal interconnect structures; and a layer contact via structure contacting a top surface of a corresponding one of the conductive layers within a region of the stepped region; and wherein the three-dimensional memory device further comprises: an additional alternating stack of additional insulating layers and additional conductive layers, the additional alternating stack being located between the first and second line trenches and above or below the alternating stack; and Additional plates of dielectric material are embedded within the additional alternating stack, wherein the connecting via structure extends vertically through each of the additional plates of dielectric material.

11. The three-dimensional memory device according to claim 10, wherein: The at least one dielectric wall structure includes a pair of dielectric wall structures; an alternating stack of dielectric material plates and insulating layers located between the pair of dielectric wall structures; and A connecting via structure extends vertically through the alternating stack of dielectric material plates and insulating layers and contacts a respective one of the lower level metal interconnect structures and a respective one of the higher level metal interconnect structures.

12. The three-dimensional memory device according to claim 10, wherein: said at least one dielectric wall structure comprising a monolithic dielectric wall structure; and A plurality of support pillar structures having a cylindrical or frusto-conical shape are located between the single dielectric wall structure and the second linear trench.

13. A method for forming a semiconductor structure, characterized in that: The method comprises: forming an alternating layer stack of continuous insulating layers and continuous sacrificial material layers; forming a stepped surface beneath the stepped cavity by patterning the alternating layer stack in an inter-array region between a first memory array region and a second memory array region; forming a dielectric cavity fill material portion over the stepped surface of the alternating layer stack; forming a first dielectric wall structure and a second dielectric wall structure, the first dielectric wall structure and the second dielectric wall structure extending laterally in a first horizontal direction through the material of the alternating layer stack and the dielectric cavity filling material portion within the region of the inter-array region, wherein the dielectric cavity filling material portion is divided into a rearward stepped dielectric material portion covering the stepped surface of the alternating layer stack and a dielectric filling material portion located between the first dielectric wall structure and the second dielectric wall structure; forming first and second linear trenches through the alternating layer stack, wherein the first and second linear trenches extend laterally along the first horizontal direction and are laterally spaced apart by the first and second dielectric wall structures along a second horizontal direction; and A remaining portion of the continuous sacrificial material layer outside the region between the first and second dielectric wall structures is replaced with a conductive layer, wherein the remaining portion of the continuous sacrificial material layer within the region between the first and second dielectric wall structures comprises a stack of dielectric material plates.

14. The method according to claim 13, further comprising: forming a moat trench through the alternating layer stack; as well as A moat-shaped dielectric wall structure is formed by filling the moat trench with a dielectric filling material, wherein the first dielectric wall structure and the second dielectric wall structure include portions of the moat-shaped dielectric wall structure extending laterally along the first horizontal direction, and the portions are directly or indirectly connected to each other through a pair of lateral dielectric wall portions of the moat-shaped dielectric wall structure.

15. The method according to claim 13, further comprising: forming a pair of linear openings laterally spaced apart from each other and separated from each other through the stack of alternating layers; as well as The first and second dielectric wall structures are formed by filling the pair of linear openings with a dielectric filling material. 16 . The method of claim 13 , further comprising forming memory stack structures through the alternating layer stacks in each of the first memory array region and the second memory array region, each memory stack structure comprising a vertical semiconductor channel and a memory film.

17. The method according to claim 13, further comprising: forming a lower level dielectric material layer over a substrate embedding a lower level metal interconnect structure, wherein the alternating layer stack is formed over the lower level dielectric material layer; forming a connecting via structure through the dielectric material plate on one of the lower level metal interconnect structures; forming a higher level dielectric material layer over the dielectric material plate and over the connecting via structure; as well as A layer contact via structure is formed through the backward stepped dielectric material portion directly on the top surface of one of the conductive layers.

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