Three-dimensional memory device with depletion region position control and method of erasing the same using gate-induced leakage

Abstract

A gate-induced leakage current that is independent of the location of the physical p-n junction between the semiconductor channel and the source / drain regions can be provided within a NAND string of a three-dimensional memory device by employing at least one leakage current control circuit activated during an erase operation. During the erase operation, an accumulation region and an inversion region can be formed between a pair of vertically adjacent conductive layers, with a depletion region therebetween. During the erase operation, the depletion region can generate and inject majority charge carriers into the semiconductor channel. The depletion region can be formed in the source region or the drain region and may not overlap with the physical p-n junction. Thus, the charge injection location can be independent of the location of the physical p-n junction.

Description

[0001] Related applications

[0002] This patent application claims the benefit of priority to U.S. non-provisional patent application No. 16 / 832,320, filed on March 27, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention generally relates to the field of semiconductor devices, and more particularly to a three-dimensional memory device including depletion region position control to enhance gate induced leakage current generation during erase and a method of operating the same. Background Art

[0004] A three-dimensional memory device including three-dimensional vertical NAND strings with one bit per cell is disclosed in an article by T. Endoh et al. entitled "Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell" (IEDM Proc. (2001) 33-36). Summary of the Invention

[0005] According to one embodiment of the present disclosure, a three-dimensional memory device is provided, the three-dimensional memory device comprising: an alternating stack of insulating layers and conductive layers, the alternating stack being located above a source contact layer; a NAND string extending vertically through the alternating stack and comprising a semiconductor material stack, the semiconductor material stack comprising, from bottom to top, a source region, a semiconductor channel, and a drain region, and comprising a memory film laterally surrounding the semiconductor material stack, wherein the source region contacts the source contact layer, and wherein a first physical pn junction is located between the source region and the semiconductor channel, and a second physical pn junction is located between the semiconductor channel and the drain region; and a source select gate control circuit, the source The source select gate control circuit is configured to apply a first source select gate bias voltage to a first source side subset of the conductive layer during an erase operation and to apply a second source select gate bias voltage to a second source side subset of the conductive layer overlying the first source side subset of the conductive layer during an erase operation, wherein the first source select gate bias voltage has a magnitude and polarity to produce an accumulation region at a middle portion of the source region laterally surrounded by the first source side subset of the conductive layer, and the second source select gate bias voltage has a magnitude and polarity to produce an inversion region at an upper end portion of the source region laterally surrounded by the second source side subset of the conductive layer and a depletion region between the inversion region and the accumulation region.

[0006] According to another embodiment of the present disclosure, a three-dimensional memory device is provided, the three-dimensional memory device comprising: an alternating stack of insulating layers and conductive layers, the alternating stack being located above a source contact layer; a NAND string extending vertically through the alternating stack and comprising a semiconductor material stack, the semiconductor material stack comprising, from bottom to top, a source region, a semiconductor channel, and a drain region, and comprising a memory film laterally surrounding the semiconductor material stack, wherein the source region contacts the source contact layer, and wherein a first physical pn junction is located between the source region and the semiconductor channel, and a second physical pn junction is located between the semiconductor channel and the drain region; and drain select gate control circuitry, the The drain select gate control circuit is configured to apply a first drain select gate bias voltage to a first drain side subset of the conductive layer during an erase operation and to apply a second drain side subset of the conductive layer below the first drain side subset of the conductive layer during an erase operation, wherein the first drain select gate bias voltage has a magnitude and polarity to produce an accumulation region at a middle portion of the drain region laterally surrounded by the first drain side subset of the conductive layer, and the second drain select gate bias voltage has a magnitude and polarity to produce an inversion region at a lower end portion of the drain region laterally surrounded by the second drain side subset of the conductive layer and a depletion region between the inversion region and the accumulation region.

[0007] According to another embodiment of the present disclosure, a method of erasing a NAND string includes a channel, a memory film located near the channel, and a first active region and a second active region located near opposite respective first and second ends of the channel, the method including applying a first voltage to at least one first select gate electrode located near the first active region to generate an accumulation region in a first portion of the first active region; and applying a second voltage different from the first voltage to at least one second select gate electrode located near the first active region to generate an inversion region in a second portion of the first active region located between the first portion and the channel, and generating a depletion region in the first active region between the inversion region and the accumulation region.

[0008] According to yet another embodiment of the present disclosure, a method of operating a semiconductor device is provided, the method comprising: providing a three-dimensional memory device, the three-dimensional memory device comprising an alternating stack of insulating layers and conductive layers, the alternating stack being located above a source contact layer; a NAND string, the NAND string vertically extending through the alternating stack, and a source select gate control circuit, wherein the NAND string comprises a semiconductor material stack, the semiconductor material stack comprising, from bottom to top, a source region, a semiconductor channel, and a drain region, and comprising a memory film laterally surrounding the semiconductor material stack, wherein the source region contacts the source contact layer, wherein a first physical pn junction is located between the source region and the semiconductor channel, and a second physical pn junction is located between the source region and the semiconductor channel. The junction is located between the semiconductor channel and the drain region; and an erase operation is performed by applying an erase channel bias voltage to the semiconductor channel, by applying a first source select gate bias voltage to the first source side subset of the conductive layer, and by applying a second source select gate bias voltage to the second source side subset of the conductive layer covering the first source side subset of the conductive layer, wherein the first source select gate bias voltage and the second source select gate bias voltage form an accumulation region at a middle portion of the source region laterally surrounded by the first source side subset of the conductive layer, an inversion region at an upper end portion of the source region laterally surrounded by the second source side subset of the conductive layer, and a depletion region between the inversion region and the accumulation region. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A is a vertical cross-sectional view of an exemplary structure after forming a semiconductor device, a lower-level dielectric layer, a lower metal interconnect structure, and a source-level material layer in a process on a semiconductor substrate according to one embodiment of the present disclosure.

[0010] Figure 1B yes Figure 1A The top view of the exemplary structure of FIG. The hinged vertical plane A-A' is Figure 1A A vertical section of a plane.

[0011] Figure 1C It is along Figure 1B Magnified view of the source level material layer during the process on the vertical plane CC'.

[0012] Figure 2 is a vertical cross-sectional view of an exemplary structure after forming a first layer of alternating stacks of first insulating layers and first spacer material layers according to an embodiment of the present disclosure.

[0013] Figure 3 is a vertical cross-sectional view of an exemplary structure after patterning a first level staircase region, a first backward stepped dielectric material portion, and an interlayer dielectric layer according to an embodiment of the present disclosure.

[0014] Figure 4Ais a vertical cross-sectional view of an exemplary structure after forming a first-level memory opening and a first-level support opening according to an embodiment of the present disclosure.

[0015] Figure 4B yes Figure 4A Horizontal cross-sectional view of an exemplary structure of FIG. The hinged vertical plane A-A' corresponds to Figure 4A A vertical section of a plane.

[0016] Figure 5 is a vertical cross-sectional view of an exemplary structure after forming various sacrificial fill structures according to an embodiment of the present disclosure.

[0017] Figure 6 is a vertical cross-sectional view of an exemplary structure after forming a second alternating stack of a second insulating layer and a second spacer material layer, a second stepped surface, and a second backward stepped dielectric material portion according to an embodiment of the present disclosure.

[0018] Figure 7A is a vertical cross-sectional view of an exemplary structure after forming a second-level memory opening and a second-level support opening according to an embodiment of the present disclosure.

[0019] Figure 7B It is along Figure 7A The horizontal cross-sectional view of the exemplary structure is taken along the horizontal plane BB'. The hinged vertical plane AA' corresponds to Figure 7A A vertical section of a plane.

[0020] Figure 8 is a vertical cross-sectional view of an exemplary structure after forming an inter-layer memory opening and an inter-layer support opening according to an embodiment of the present disclosure.

[0021] 9A to 9D Sequential vertical cross-sectional views of a memory opening during formation of a memory opening filling structure are shown according to an embodiment of the present disclosure.

[0022] Figure 10 is a vertical cross-sectional view of an exemplary structure after forming a memory opening filling structure and a support pillar structure according to an embodiment of the present disclosure.

[0023] Figure 11A is a vertical cross-sectional view of an exemplary structure after forming a post cavity according to an embodiment of the present disclosure.

[0024] Figure 11B It is along Figure 11A The horizontal cross-sectional view of the exemplary structure is taken along the horizontal plane BB'. The hinged vertical plane AA' corresponds to Figure 11A A vertical section of a plane.

[0025] Figure 12 is a vertical cross-sectional view of an exemplary structure after forming a dielectric post structure according to an embodiment of the present disclosure.

[0026] Figure 13A is a vertical cross-sectional view of an exemplary structure after forming a first contact level dielectric layer and backside trenches according to an embodiment of the present disclosure.

[0027] Figure 13B It is along Figure 13A The horizontal cross-sectional view of the exemplary structure is taken along the horizontal plane BB'. The hinged vertical plane AA' corresponds to Figure 13A A vertical section of a plane.

[0028] Figure 14 is a vertical cross-sectional view of an exemplary structure after forming backside trench spacers according to an embodiment of the present disclosure.

[0029] Figures 15A to 15E Sequential vertical cross-sectional views of a memory opening filling structure and a backside trench during formation of a source level material layer according to an embodiment of the present disclosure are shown.

[0030] Figure 16 is a vertical cross-sectional view of an exemplary structure after forming a source level material layer according to an embodiment of the present disclosure.

[0031] Figure 17 is a vertical cross-sectional view of an exemplary structure after forming a backside recess according to an embodiment of the present disclosure.

[0032] Figure 18A is a vertical cross-sectional view of an exemplary structure after forming a conductive layer according to an embodiment of the present disclosure.

[0033] Figure 18B It is along Figure 18A The horizontal cross-sectional view of the exemplary structure is taken along the horizontal plane BB'. The hinged vertical plane AA' corresponds to Figure 18A A vertical section of a plane.

[0034] Figure 19A is a vertical cross-sectional view of an exemplary structure after forming a backside trench fill structure in the backside trench according to an embodiment of the present disclosure.

[0035] Figure 19B It is along Figure 19A The horizontal cross-sectional view of the exemplary structure is taken along the horizontal plane BB'. The hinged vertical plane AA' corresponds to Figure 19A A vertical section of a plane.

[0036] Figure 19C It is along Figure 19BA vertical cross-sectional view of the exemplary structure taken along a vertical plane CC'.

[0037] Figure 19D It is along Figure 19B A vertical cross-sectional view of a region of the exemplary structure taken along a vertical plane DD'.

[0038] Figure 20A is a vertical cross-sectional view of an exemplary structure after forming a second contact level dielectric layer and various contact via structures according to an embodiment of the present disclosure.

[0039] Figure 20B It is along Figure 20A The horizontal cross-sectional view of the exemplary structure is taken along the vertical plane BB'. The hinged vertical plane AA' corresponds to Figure 20A A vertical section of a plane.

[0040] Figure 21 is a vertical cross-sectional view of an exemplary structure after forming a through-memory level via structure and an upper metal line structure according to an embodiment of the present disclosure.

[0041] Figure 22 According to the embodiment of the present disclosure Figure 21 FIG. 1 is a combination of a vertical cross-sectional view of the area surrounding a NAND string of an exemplary structure and a schematic diagram of the control circuitry used to control the various conductive layers.

[0042] Figure 23 is a magnified view of the bottom end of a NAND string during an erase operation according to an embodiment of the present invention.

[0043] Figure 24 is a magnified view of the top of a NAND string during an erase operation according to an embodiment of the present invention. DETAILED DESCRIPTION

[0044] Embodiments of the present disclosure may be used to form various semiconductor devices, such as a three-dimensional single-body memory array device including multiple NAND memory strings with depletion region control to enhance gate induced leakage ("GIDL") current during erase operations. The drawings are not drawn to scale.

[0045] The drawings are not drawn to scale. Where a single instance of an element is shown, multiple instances of the element may be repeated unless explicitly described or otherwise clearly indicated that there is no repetition of the element. Sequence numbers such as "first," "second," and "third" are used only to identify similar elements, and different sequence numbers may be used throughout the specification and claims of this disclosure. The term "at least one" element refers to all possibilities, including the possibility of a single element and the possibility of multiple elements.

[0046] The same reference numerals represent the same or similar elements. Unless otherwise specified, elements with the same reference numerals are assumed to have the same composition and the same function. Unless otherwise specified, "contact" between elements refers to direct contact between elements providing an edge or surface shared by the elements. If two or more elements are not in direct contact with each other, the two elements are "separated" from each other. As used herein, a first element positioned "on" a second element can be positioned on the outside of the surface of the second element or on the inside of the second element. As used herein, if there is physical contact between the surface of the first element and the surface of the second element, the first element is "directly" positioned on the second element. As used herein, if there is a conductive path consisting of at least one conductive material between the first element and the second element, the first element is "electrically connected to" the second element. As used herein, a "prototype" structure or an "in-process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one of its components.

[0047] As used herein, a "layer" refers to a portion of a material that includes an area having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent that is less than the extent of an underlying or overlying structure. Additionally, a layer may be an area of ​​a continuous structure, whether uniform or non-uniform, having a thickness that is less than the thickness of the continuous structure. For example, a layer may be positioned between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above, and / or below.

[0048] As used herein, a first surface and a second surface are "vertically coincident" with each other if the second surface is above or below the first surface and if there is a vertical plane or a substantially vertical plane that includes the first surface and the second surface. A substantially vertical plane is a plane that extends straight along a direction that deviates from vertical by an angle of less than 5 degrees. A vertical plane or a substantially vertical plane is straight along the vertical direction or the substantially vertical direction and may or may not include curvature along a direction perpendicular to the vertical direction or the substantially vertical direction.

[0049] As used herein, a "memory level" or "memory array level" refers to a level corresponding to the general area between a first horizontal plane (i.e., a plane parallel to the top surface of the substrate) including the topmost surface of the memory element array and a second horizontal plane including the bottommost surface of the memory element array. As used herein, a "through-stack" element refers to an element that extends vertically through a memory level.

[0050] As used herein, "semiconductor material" refers to a material having a-5 S / m to 1.0×10 5 As used herein, "semiconductor material" refers to a material having an electrical conductivity in the range of 1.0×10 -5 S / m to 1.0 S / m and can produce materials with electrical conductivity in the range of 1.0 S / m to 1.0×10 7 S / m. As used herein, "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the energy band structure, or an n-type dopant that adds electrons to the conduction band within the energy band structure. As used herein, "conductive material" refers to a material having an electrical conductivity greater than 1.0×10 5 As used herein, "insulator material" or "dielectric material" refers to a material having an electrical conductivity of less than 1.0×10 -5 As used herein, a "heavily doped semiconductor material" refers to a material that is doped with electrical dopants at a sufficiently high atomic concentration to become conductive (i.e., provide a conductivity greater than 1.0×10 5 S / m) of semiconductor material. The "doped semiconductor material" may be a heavily doped semiconductor material, or may include a semiconductor material that provides a conductivity of 1.0×10 -5 S / m to 1.0×10 7 S / m) in the range of 100 Å / s. "Intrinsic semiconductor material" refers to a semiconductor material that is not doped with electrical dopants. Thus, a semiconductor material can be semiconducting or conductive, and can be an intrinsic semiconductor material or a doped semiconductor material. Doped semiconductor materials can be semiconducting or conductive, depending on the atomic concentration of the electrical dopant therein. As used herein, "metallic material" refers to a conductive material that includes at least one metal element therein. All conductivity measurements are performed under standard conditions.

[0051] A monolithic three-dimensional memory array is a memory array in which multiple memory levels are formed above a single substrate (such as a semiconductor wafer) without an intervening substrate. The term "monolithic" means that the layers of each level of the array are deposited directly on the layers of each lower level of the array. In contrast, two-dimensional arrays can be formed separately and then packaged together to form a non-monolithic memory device. For example, as described in U.S. Patent 5,915,167, entitled "Three-dimensional Structure Memory," a non-monolithic stacked memory is constructed by forming memory levels on separate substrates and vertically stacking the memory levels. The substrate can be thinned or removed from the memory levels before bonding, but because the memory levels are initially formed above separate substrates, such memories are not true monolithic three-dimensional memory arrays. The substrate may include integrated circuits manufactured thereon, such as driver circuits for the memory device.

[0052] Various three-dimensional memory devices disclosed herein include single-unit three-dimensional NAND string memory devices and can be manufactured using various embodiments described herein. A single-unit three-dimensional NAND string is positioned in a single-unit three-dimensional NAND string array located above a substrate. At least one memory cell in a first device level of the three-dimensional NAND string array is located above another memory cell in a second device level of the three-dimensional NAND string array.

[0053] Generally speaking, a semiconductor package (or "package") refers to a unit semiconductor device that can be attached to a circuit board via a set of pins or solder balls. A semiconductor package may include one or more semiconductor chips (or "chips") that are bonded together, for example, by flip-chip bonding or another chip-to-chip bonding. A package or chip may include a single semiconductor die (or "die") or multiple semiconductor dies. A die is the smallest unit that can independently execute external commands or report status. Typically, a package or chip with multiple dies is capable of simultaneously executing as many external commands as the total number of dies therein. Each die includes one or more planes. The same concurrent operation can be performed in each plane within the same die, but there may be some limitations. In the case where the die is a memory die (i.e., a die that includes memory elements), concurrent read operations, concurrent write operations, or concurrent erase operations can be performed in each plane within the same memory die. In a memory die, each plane contains multiple memory blocks (or "blocks"), which are the smallest units that can be erased by a single erase operation. Each memory block contains multiple pages, which are the smallest units that can be selected for programming and the smallest units that can be selected for read operations.

[0054] See also Figures 1A to 1C , showing an exemplary structure according to an embodiment of the present disclosure. Figure 1C yes Figure 1A and Figure 1B An enlarged view of the source level material layer 110' during the process is shown. The exemplary structure includes a substrate 8 and a semiconductor device 710 formed thereon. The substrate 8 includes a substrate semiconductor layer 9 at least at its upper portion. A shallow trench isolation structure 720 can be formed in the upper portion of the substrate semiconductor layer 9 to provide electrical isolation from other semiconductor devices. The semiconductor device 710 can include, for example, field effect transistors, which include corresponding transistor active regions 742 (i.e., source and drain regions), channel regions 746, and gate structures 750. The field effect transistors can be arranged in a CMOS configuration. Each gate structure 750 can include, for example, a gate dielectric 752, a gate electrode 754, a dielectric gate spacer 756, and a gate cap dielectric 758. The semiconductor device 710 can include any semiconductor circuit to support the operation of the memory structure to be formed subsequently, which is generally referred to as a driver circuit, which is also referred to as a peripheral circuit. As used herein, the term "peripheral circuit" refers to any one, each, or all of a word line decoder circuit, a word line switching circuit, a bit line decoder circuit, a bit line sensing and / or switching circuit, a power supply / distribution circuit, a data buffer, and / or a latch, or any other semiconductor circuit that can be implemented outside the memory array structure of a memory device. For example, a semiconductor device may include a word line switching device for electrically biasing word lines of a three-dimensional memory structure to be subsequently formed.

[0055] A dielectric material layer is formed over the semiconductor device, referred to herein as a lower-level dielectric material layer 760. The lower-level dielectric material layer 760 may include, for example, a dielectric liner 762 (such as a silicon nitride liner that blocks the diffusion of mobile ions and / or applies appropriate stress to the underlying structure), a first dielectric material layer 764 overlying the dielectric liner 762, a silicon nitride layer (e.g., a hydrogen diffusion barrier) 766 overlying the first dielectric material layer 764, and at least one second dielectric layer 768.

[0056] The dielectric layer stack (which includes the lower-level dielectric material layer 760) serves as a matrix for lower-level metal interconnect structures 780 that provide electrical routing to and from various nodes of the semiconductor device and landing pads of subsequently formed through-memory level contact via structures. The lower-level metal interconnect structures 780 are formed within the dielectric layer stack of the lower-level dielectric material layer 760 and include lower-level metal line structures positioned below and optionally contacting the bottom surface of the silicon nitride layer 766.

[0057] For example, the lower-level metal interconnect structure 780 may be formed within the first dielectric material layer 764. The first dielectric material layer 764 may be a plurality of dielectric material layers in which various elements of the lower-level metal interconnect structure 780 are sequentially formed. Each dielectric material layer selected from the first dielectric material layer 764 may include any one of doped silicate glass, undoped silicate glass, organosilicate glass, silicon nitride, silicon oxynitride, and a dielectric metal oxide (such as aluminum oxide). In one embodiment, the first dielectric material layer 764 may include or consist essentially of a dielectric material layer having a dielectric constant no greater than 3.9, which is the dielectric constant of undoped silicate glass (silicon oxide). The lower level metal interconnect structure 780 may include various device contact via structures 782 (e.g., source and drain electrodes contacting corresponding source and drain nodes or gate electrodes of the contact device), intermediate lower level metal line structures 784, lower level metal via structures 786, and landing pad level metal line structures 788, wherein the landing pad level metal line structures are configured to serve as landing pads for subsequently formed through memory level via structures.

[0058] A landing pad-level metal line structure 788 may be formed within the topmost dielectric material layer of the first dielectric material layer 764 (which may be a plurality of dielectric material layers). Each of the lower-level metal interconnect structures 780 may include a metal nitride liner and a metal fill structure. The top surface of the landing pad-level metal line structure 788 and the topmost surface of the first dielectric material layer 764 may be planarized by a planarization process such as chemical mechanical planarization. A silicon nitride layer 766 may be formed directly on the top surface of the landing pad-level metal line structure 788 and the topmost surface of the first dielectric material layer 764.

[0059] The at least one second dielectric material layer 768 may include a single dielectric material layer or a plurality of dielectric material layers. Each dielectric material layer selected from the at least one second dielectric material layer 768 may include any one of doped silicate glass, undoped silicate glass, and organosilicate glass. In one embodiment, the at least one second dielectric material layer 768 may include or consist essentially of a dielectric material layer having a dielectric constant not exceeding the dielectric constant of undoped silicate glass (silicon oxide), which is 3.9.

[0060] Optional layers of metal material and semiconductor material may be deposited over at least one second dielectric material layer 768 or within patterned recesses therein and photolithographically patterned to provide an optional conductive plate layer 6 and an in-process source-level material layer 110'. Optional conductive plate layer 6, if present, provides a highly conductive conduction path for current flowing into or out of the in-process source-level material layer 110'. Optional conductive material layer 6 comprises a conductive material such as a metal or a heavily doped semiconductor material. Optional conductive plate layer 6 may, for example, comprise a tungsten layer having a thickness in the range of 3 nm to 100 nm, although smaller and greater thicknesses may also be used. A metal nitride layer (not shown) may be provided on top of conductive plate layer 6 as a diffusion barrier. Conductive plate layer 6 may serve as a specialized source line in the completed device. Furthermore, conductive plate layer 6 may comprise an etch stop layer and may comprise any suitable conductive, semiconductor, or insulating layer. Optional conductive plate layer 6 may comprise a metal compound material, such as a conductive metal nitride (e.g., TiN) and / or a metal (e.g., W). The thickness of the optional conductive plate layer 6 may be in the range of 5 nm to 100 nm, although lesser and greater thicknesses may also be used.

[0061] During the process, source-level material layer 110' may include various layers that are subsequently modified to form the source-level material layer. The source-level material layer, when formed, includes a source contact layer that serves as a common source region for the vertical field-effect transistors of the three-dimensional memory device. In one embodiment, during the process, source-level material layer 110' may include, from bottom to top, a lower source-level semiconductor layer 112, a lower sacrificial liner 103, a source-level sacrificial layer 104, an upper sacrificial liner 105, an upper source-level semiconductor layer 116, and a source-level insulating layer 117.

[0062] The lower source level semiconductor layer 112 and the higher source level semiconductor layer 116 may include a doped semiconductor material, such as doped polysilicon or doped amorphous silicon. The conductivity type of the lower source level semiconductor layer 112 and the higher source level semiconductor layer 116 may be opposite to the conductivity of the semiconductor channel to be formed later. For example, if the semiconductor channel to be formed later has a first conductivity type of doping, the lower source level semiconductor layer 112 and the higher source level semiconductor layer 116 may have a second conductivity type of doping opposite to the first conductivity type. The thickness of each of the lower source level semiconductor layer 112 and the higher source level semiconductor layer 116 may be in the range of 10 nm to 300 nm, such as 20 nm to 150 nm, although smaller and larger thicknesses may also be used.

[0063] The source-level sacrificial layer 104 comprises a sacrificial material that can be selectively removed from the lower sacrificial liner 103 and the upper sacrificial liner 105. In one embodiment, the source-level sacrificial layer 104 can comprise a semiconductor material, such as undoped amorphous silicon or a silicon-germanium alloy having an atomic concentration of germanium greater than 20%. The thickness of the source-level sacrificial layer 104 can be in the range of 30 nm to 400 nm, such as 60 nm to 200 nm, although smaller and larger thicknesses can also be used.

[0064] The lower sacrificial liner 103 and the upper sacrificial liner 105 comprise a material that can be used as an etch stop material during the removal of the source level sacrificial layer 104. For example, the lower sacrificial liner 103 and the upper sacrificial liner 105 can comprise silicon oxide, silicon nitride, and / or a dielectric metal oxide. In one embodiment, each of the lower sacrificial liner 103 and the upper sacrificial liner 105 can comprise a silicon oxide layer having a thickness in the range of 2 nm to 30 nm, although smaller and larger thicknesses can also be used.

[0065] The source-level insulating layer 117 may include a dielectric material, such as silicon oxide. The thickness of the source-level insulating layer 117 may be in a range of 20 nm to 400 nm, such as 40 nm to 200 nm, although lesser and greater thicknesses may also be used.

[0066] During the process, source-level material layer 110' may be formed directly above a subset of semiconductor devices on substrate 8 (e.g., a silicon wafer). As used herein, a first element is positioned "directly above" a second element if the first element is positioned above a horizontal plane that includes the topmost surface of the second element and an area of ​​the first element, and the area of ​​the second element has an area overlap in plan view (i.e., along a vertical plane or direction perpendicular to the top surface of substrate 8).

[0067] The optional conductive plate layer 6 and the in-process source level material layer 110' can be patterned to provide openings in areas where through-memory level contact via structures and through-dielectric contact via structures are subsequently formed. A patterned portion of the stack of conductive plate layer 6 and in-process source level material layer 110' is present in each memory array region 100 where a three-dimensional memory stack structure will subsequently be formed.

[0068] The optional conductive plate layer 6 and the in-process source level material layer 110' can be patterned so that the opening extends above the staircase region 200 where the contact via structure for contacting the word line conductive layer will be subsequently formed. In one embodiment, the staircase region 200 can be laterally spaced apart from the memory array region 100 along a first horizontal direction hd1. The horizontal direction perpendicular to the first horizontal direction hd1 is referred to herein as the second horizontal direction hd2. In one embodiment, additional openings in the optional conductive plate layer 6 and the in-process source level material layer 110' can be formed within the region of the memory array region 100 where a three-dimensional memory array including a memory stack structure will subsequently be formed. A peripheral device region 400, which is subsequently filled with a portion of the field dielectric material, can be provided adjacent to the staircase region 200.

[0069] The region of the semiconductor device 710 and the combination of the lower-level dielectric material layer 760 and the lower-level metal interconnect structure 780 is referred to herein as the underlying peripheral device region 700, which is positioned below the memory level components to be formed later and includes peripheral devices for the memory level components. The lower-level metal interconnect structure 780 is formed in the lower-level dielectric material layer 760.

[0070] The lower-level metal interconnect structure 780 can be electrically connected to an active node (e.g., a transistor active area 742 or a gate electrode 754) of the semiconductor device 710 (e.g., a CMOS device) and is positioned at the level of the lower-level dielectric material layer 760. A through-memory level contact via structure can subsequently be formed directly on the lower-level metal interconnect structure 780 to provide an electrical connection to a subsequently formed memory device. In one embodiment, the pattern of the lower-level metal interconnect structure 780 can be selected so that a landing pad level metal line structure 788 (which is a subset of the lower-level metal interconnect structure 780 positioned at the topmost portion of the lower-level metal interconnect structure 780) can provide a landing pad structure for a through-memory level contact via structure to be subsequently formed.

[0071] See also Figure 2 , subsequently forming an alternating stack of first and second material layers. Each first material layer may comprise a first material, and each second material layer may comprise a second material different from the first material. Where at least one further alternating stack of material layers is subsequently formed above the alternating stack of first and second material layers, the alternating stack is referred to herein as a first-layer alternating stack. A level of the first-layer alternating stack is referred to herein as a first-layer level, and a level of the alternating stack to be subsequently formed immediately above the first-layer level is referred to herein as a second-layer level, and so on.

[0072] The first layer alternating stack may include a first insulating layer 132 as a first material layer and a first spacer material layer as a second material layer. In one embodiment, the first spacer material layer may be a sacrificial material layer that is subsequently replaced by a conductive layer. In another embodiment, the first spacer material layer may be a conductive layer that is not subsequently replaced by another layer. Although the present disclosure is described using an embodiment in which the sacrificial material layer is replaced by a conductive layer, embodiments in which the spacer material layer is formed as a conductive layer (thereby eliminating the need to perform a replacement process) are expressly contemplated herein.

[0073] In one embodiment, the first material layer and the second material layer may be a first insulating layer 132 and a first sacrificial material layer 142, respectively. In one embodiment, each first insulating layer 132 may include a first insulating material, and each first sacrificial material layer 142 may include a first sacrificial material. During the process, a plurality of alternating first insulating layers 132 and first sacrificial material layers 142 are formed above the source-level material layer 110'. As used herein, "sacrificial material" refers to a material that is removed during subsequent processing steps.

[0074] As used herein, an alternating stack of a first element and a second element refers to a structure in which instances of the first element and instances of the second element alternate. Each instance of the first element that is not an end element of the alternating plurality of elements is adjacent to two instances of the second element on both sides, and each instance of the second element that is not an end element of the alternating plurality of elements is adjacent to two instances of the first element on both ends. The first element may have the same thickness throughout, or may have different thicknesses. The second element may have the same thickness throughout, or may have different thicknesses. The alternating plurality of first and second material layers may begin with an instance of the first material layer or an instance of the second material layer, and may end with an instance of the first material layer or an instance of the second material layer. In one embodiment, the instances of the first element and the second element may form units that are periodically repeated within the alternating plurality of elements.

[0075] The first layer alternating stack (132, 142) may include a first insulating layer 132 composed of a first material and a first sacrificial material layer 142 composed of a second material, the second material being different from the first material. The first material of the first insulating layer 132 may be at least one insulating material. Insulating materials that can be used for the first insulating layer 132 include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organic silicate glass (OSG), spin-on dielectric materials, dielectric metal oxides commonly referred to as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and their silicates, dielectric metal oxynitrides and their silicates, and organic insulating materials. In one embodiment, the first material of the first insulating layer 132 may be silicon oxide.

[0076] The second material of the first sacrificial material layer 142 is a sacrificial material that can be removed selectively with respect to the first material of the first insulating layer 132. As used herein, removal of a first material is "selective with respect to" a second material if the removal process removes the first material at a rate that is at least twice the removal rate of the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material relative to the second material.

[0077] The first sacrificial material layer 142 may comprise an insulating material, a semiconductor material, or a conductive material. The second material of the first sacrificial material layer 142 may subsequently be replaced with a conductive electrode, which may serve as, for example, a control gate electrode of a vertical NAND device. In one embodiment, the first sacrificial material layer 142 may be a material layer comprising silicon nitride.

[0078] In one embodiment, the first insulating layer 132 may include silicon oxide, and the sacrificial material layer may include a silicon nitride sacrificial material layer. The first material of the first insulating layer 132 may be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is used for the first insulating layer 132, tetraethyl orthosilicate (TEOS) may be used as a precursor material for the CVD process. The second material of the first sacrificial material layer 142 may be formed, for example, by CVD or atomic layer deposition (ALD).

[0079] The thickness of the first insulating layer 132 and the first sacrificial material layer 142 can be in the range of 20 nm to 50 nm, although smaller and larger thicknesses can be used for each first insulating layer 132 and each first sacrificial material layer 142. The number of repetitions of the first insulating layer 132 and the first sacrificial material layer 142 pair can be in the range of 32 to 1,024, and typically in the range of 8 to 256, although greater repetitions can also be used. In one embodiment, each first sacrificial material layer 142 in the alternating stack of first layers (132, 142) can have a uniform thickness that is substantially constant within each respective first sacrificial material layer 142.

[0080] A first insulating capping layer 170 may then be formed over the first alternating stack (132, 142). The first insulating capping layer 170 comprises a dielectric material, which may be any dielectric material that may be used for the first insulating layer 132. In one embodiment, the first insulating capping layer 170 comprises the same dielectric material as the first insulating layer 132. The thickness of the first insulating capping layer 170 may range from 20 nm to 300 nm, although lesser and greater thicknesses may also be used.

[0081] See also Figure 3, the first insulating capping layer 170 and the first layer alternating stack (132, 142) can be patterned to form a first stepped surface in the staircase region 200. The staircase region 200 may include a corresponding first stepped area and a second stepped area, in which the first stepped surface is formed, and in the second stepped area, additional stepped surfaces are subsequently formed in the second layer structure (which is subsequently formed above the first layer structure) and / or additional layer structure. The first stepped surface can be formed, for example, by forming a mask layer (not shown) having an opening therein, etching a cavity within the level of the first insulating capping layer 170 and iteratively expanding the etched area, and vertically recessing the cavity by etching each first insulating layer 132 and first sacrificial material layer 142 pair directly below the bottom surface of the etched cavity positioned in the etched area. In one embodiment, the top surface of the first sacrificial material layer 142 can be physically exposed at the first stepped surface. The cavity covering the first stepped surface is referred to herein as a first stepped cavity.

[0082] A dielectric fill material (such as undoped silicate glass or doped silicate glass) may be deposited to fill the first stepped cavity. Excess portions of the dielectric fill material may be removed from above a horizontal plane including the top surface of the first insulating cap layer 170. The remaining portion of the dielectric fill material filling the area overlying the first stepped surface constitutes a first backward stepped dielectric material portion 165. As used herein, a "backward stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that increases monotonically with the vertical distance from the top surface of the substrate on which the element is located. The first layer of alternating stacks (132, 142) and the first backward stepped dielectric material portion 165 together constitute a first layer structure, which is an in-process structure that is subsequently modified.

[0083] An interlayer dielectric layer 180 may optionally be deposited over the first layer structure (132, 142, 170, 165). Interlayer dielectric layer 180 comprises a dielectric material, such as silicon oxide. In one embodiment, interlayer dielectric layer 180 may comprise doped silicate glass, which has a greater etch rate than the material of first insulating layer 132 (which may comprise undoped silicate glass). For example, interlayer dielectric layer 180 may comprise phosphosilicate glass. The thickness of interlayer dielectric layer 180 may be in the range of 30 nm to 300 nm, although smaller and larger thicknesses may also be used.

[0084] See also Figure 4A and Figure 4B, various first layer openings (149, 129) may be formed through the interlayer dielectric layer 180 and the first layer structure (132, 142, 170, 165) and into the in-process source level material layer 110'. A photoresist layer (not shown) may be applied over the interlayer dielectric layer 180 and may be photolithographically patterned to form various openings therethrough. The pattern of the openings in the photoresist layer may be transferred through the interlayer dielectric layer 180 and the first layer structure (132, 142, 170, 165) and into the in-process source level material layer 110' by a first anisotropic etching process to form the various first layer openings (149, 129) simultaneously (i.e., during the first isotropic etching process). The various first layer openings (149, 129) may include a first layer memory opening 149 and a first layer support opening 129. In Figure 4B The location of the step S in the first alternating stack (132, 142) is shown in dashed lines.

[0085] First-layer memory openings 149 are openings formed in memory array region 100 through each layer within the first alternating stack (132, 142) and are subsequently used to form a memory stack structure therein. First-layer memory openings 149 can be formed as clusters of first-layer memory openings 149 spaced laterally along a second horizontal direction hd2. Each cluster of first-layer memory openings 149 can be formed as a two-dimensional array of first-layer memory openings 149.

[0086] First level support openings 129 are openings formed in stair region 200 and are subsequently used to form support post structures. A subset of first level support openings 129 formed through first rearward stepped dielectric material portion 165 may be formed through corresponding horizontal surfaces of the first stepped surface.

[0087] In one embodiment, the first anisotropic etching process may include an initial step in which the material of the first layer alternating stack (132, 142) is etched simultaneously with the material of the first backward stepped dielectric material portion 165. The chemistry of the initial etching step may be alternating to optimize the etching of the first material and the second material in the first layer alternating stack (132, 142) while providing an average etching rate comparable to the material of the first backward stepped dielectric material portion 165. The first anisotropic etching process may use, for example, a series of reactive ion etching processes or a single reactive etching process (e.g., CF4 / O2 / Ar etching). The sidewalls of the various first layer openings (149, 129) may be substantially vertical or may be tapered.

[0088] After etching through the alternating stacks (132, 142) and the first backward stepped dielectric material portion 165, the chemistry of the terminal portion of the first anisotropic etch process can be selected to etch through the one or more dielectric materials of the at least one second dielectric layer 768 at a higher etch rate than the average etch rate of the source level material layer 110' during the process. For example, the terminal portion of the anisotropic etch process can include a step of etching the one or more dielectric materials of the at least one second dielectric layer 768 that are selective to the semiconductor material within the component layer in the source level material layer 110' during the process. In one embodiment, the terminal portion of the first anisotropic etch process can etch through the source level insulating layer 117, the upper source level semiconductor layer 116, the upper sacrificial liner 105, the source level sacrificial layer 104, and the lower sacrificial liner 103, and at least partially into the lower source level semiconductor layer 112. The terminal portion of the first anisotropic etching process may include at least one etching chemistry for etching the various semiconductor materials of the source level material layer 110' in the process.The photoresist layer may then be removed, for example, by ashing.

[0089] Optionally, the portions of the first-layer memory opening 149 and the first-layer support opening 129 at the level of the interlayer dielectric layer 180 can be laterally expanded by isotropic etching. In this case, the interlayer dielectric layer 180 can include a dielectric material (such as borosilicate glass) that has a greater etching rate in dilute hydrofluoric acid than the first insulating layer 132 (which may include undoped silicate glass). An isotropic etch (such as a wet etch using HF) can be used to expand the lateral dimensions of the first-layer memory opening 149 at the level of the interlayer dielectric layer 180. The portion of the first-layer memory opening 149 located at the level of the interlayer dielectric layer 180 can optionally be widened to provide a larger landing pad for the second-layer memory opening that will be subsequently formed through the second-layer alternating stack (subsequently formed before forming the second-layer memory opening).

[0090] See also Figure 5 A sacrificial first layer opening fill portion (148, 128) may be formed in the various first layer openings (149, 129). For example, a sacrificial first layer fill material may be deposited simultaneously in each of the first layer openings (149, 129). The sacrificial first layer fill material includes a material that can be selectively removed from the first insulating layer 132 and the first sacrificial material layer 142.

[0091] In one embodiment, the sacrificial first layer fill material may include a semiconductor material such as silicon (e.g., a-Si or polysilicon), a silicon-germanium alloy, germanium, a III-V compound semiconductor material, or a combination thereof. Optionally, a thin etch stop liner (such as a silicon oxide layer or a silicon nitride layer having a thickness in the range of 1 nm to 3 nm) may be used before depositing the sacrificial first layer fill material. The sacrificial first layer fill material may be formed by non-conformal deposition or conformal deposition methods.

[0092] In another embodiment, the sacrificial first layer fill material may include a silicon oxide material having a higher etch rate than the material of the first insulating layer 132, the first insulating capping layer 170, and the interlayer dielectric layer 180. For example, the sacrificial first layer fill material may include borosilicate glass or porous or non-porous organosilicate glass having an etch rate at least 100 times higher than the etch rate of dense TEOS oxide (i.e., a silicon oxide material formed by decomposing tetraethyl orthosilicate glass in a chemical vapor deposition process and subsequently densifying in an annealing process) in 100:1 diluted hydrofluoric acid. In this case, a thin etch stop liner (such as a silicon nitride layer having a thickness in the range of 1 nm to 3 nm) may be used before depositing the sacrificial first layer fill material. The sacrificial first layer fill material may be formed by non-conformal deposition or conformal deposition methods.

[0093] In yet another embodiment, the sacrificial first layer fill material may include amorphous silicon or a carbon-containing material (such as amorphous carbon or diamond-like carbon) that may be subsequently removed by ashing, or a silicon-based polymer that may be subsequently removed selectively to the material of the first alternating stack (132, 142).

[0094] Portions of the deposited sacrificial material may be removed from above the topmost layer of the first alternating stack (132, 142), such as above the interlayer dielectric layer 180. For example, the sacrificial first layer fill material may be recessed into the top surface of the interlayer dielectric layer 180 using a planarization process. The planarization process may include recess etching, chemical mechanical planarization (CMP), or a combination thereof. The top surface of the interlayer dielectric layer 180 may serve as an etch stop layer or a planarization stop layer.

[0095] The remaining portions of the sacrificial first layer fill material comprise sacrificial first layer opening fill portions (148, 128). Specifically, each remaining portion of the sacrificial material in the first layer memory opening 149 constitutes a sacrificial first layer memory opening fill portion 148. Each remaining portion of the sacrificial material in the first layer support opening 129 constitutes a sacrificial first layer support opening fill portion 128. The various sacrificial first layer opening fill portions (148, 128) are formed simultaneously, i.e., during the same set of processes, including a deposition process that deposits the sacrificial first layer fill material and a planarization process that removes the first layer deposition process from above the first alternating stack (132, 142), such as from above the top surface of the interlayer dielectric layer 180. The top surface of the sacrificial first layer opening fill portions (148, 128) may be coplanar with the top surface of the interlayer dielectric layer 180. Each of the sacrificial first layer opening fill portions (148, 128) may or may not include a cavity therein.

[0096] See also Figure 6 , a second layer structure may be formed above the first layer structure (132, 142, 170, 148). The second layer structure may include additional alternating stacks of insulating layers and spacer material layers, which may be sacrificial material layers. For example, a second alternating stack (232, 242) of material layers may then be formed on the top surface of the first alternating stack (132, 142). The second alternating stack (232, 242) includes alternating multiple third material layers and fourth material layers. Each third material layer may include a third material, and each fourth material layer may include a fourth material different from the third material. In one embodiment, the third material may be the same as the first material of the first insulating layer 132, and the fourth material may be the same as the second material of the first sacrificial material layer 142.

[0097] In one embodiment, the third material layer may be the second insulating layer 232, and the fourth material layer may be a second spacer material layer that provides a vertical spacing between each pair of vertically adjacent second insulating layers 232. In one embodiment, the third material layer and the fourth material layer may be the second insulating layer 232 and the second sacrificial material layer 242, respectively.

[0098] The third material of the second insulating layer 232 can be at least one insulating material. The fourth material of the second sacrificial material layer 242 can be a sacrificial material that can be removed selectively to the third material of the second insulating layer 232. The second sacrificial material layer 242 can include an insulating material, a semiconductor material, or a conductive material. The fourth material of the second sacrificial material layer 242 can then be replaced with a conductive electrode, which can be used as a control gate electrode of a vertical NAND device, for example.

[0099] In one embodiment, each second insulating layer 232 may include a second insulating material, and each second sacrificial material layer 242 may include a second sacrificial material. In this case, the second alternating stack (232, 242) may include alternating multiple second insulating layers 232 and second sacrificial material layers 242. The third material of the second insulating layer 232 may be deposited, for example, by chemical vapor deposition (CVD). The fourth material of the second sacrificial material layer 242 may be formed, for example, by CVD or atomic layer deposition (ALD).

[0100] The third material of the second insulating layer 232 may be at least one insulating material. The insulating material that can be used for the second insulating layer 232 may be any material that can be used for the first insulating layer 132. The fourth material of the second sacrificial material layer 242 is a sacrificial material that can be removed selectively with respect to the third material of the second insulating layer 232. The sacrificial material that can be used for the second sacrificial material layer 242 may be any material that can be used for the first sacrificial material layer 142. In one embodiment, the second insulating material may be the same as the first insulating material, and the second sacrificial material may be the same as the first sacrificial material.

[0101] The thickness of the second insulating layer 232 and the second sacrificial material layer 242 can be in the range of 20 nm to 50 nm, although smaller and larger thicknesses can be used for each second insulating layer 232 and each second sacrificial material layer 242. The number of repetitions of the second insulating layer 232 and the second sacrificial material layer 242 pair can be in the range of 2 to 1,024, and typically in the range of 8 to 256, although higher numbers of repetitions can also be used. In one embodiment, each second sacrificial material layer 242 in the second alternating stack (232, 242) can have a uniform thickness that is substantially constant within each respective second sacrificial material layer 242.

[0102] A second stepped surface in the second stepped region can be formed in the staircase region 200 using the same set of processing steps as used to form the first stepped surface in the first stepped region, with appropriate adjustments to the pattern of at least one mask layer. A second backward stepped dielectric material portion 265 can be formed over the second stepped surface in the staircase region 200.

[0103] A second insulating capping layer 270 may then be formed over the second alternating stack (232, 242). The second insulating capping layer 270 comprises a dielectric material that is different from the material of the second sacrificial material layer 242. In one embodiment, the second insulating capping layer 270 may comprise silicon oxide. In one embodiment, the first and second sacrificial material layers (142, 242) may comprise silicon nitride.

[0104] Generally speaking, at least one alternating stack of insulating layers (132, 232) and spacer material layers (such as sacrificial material layers (142, 242)) can be formed above the source level material layer 110' during the process, and at least one backward stepped dielectric material portion (165, 265) can be formed above the staircase region on the at least one alternating stack (132, 142, 232, 242).

[0105] Optionally, a drain select level isolation structure 72 may be formed through a subset of layers in the upper portion of the second alternating stack (232, 242). The second sacrificial material layer 242 cut by the drain select level isolation structure 72 corresponds to a level at which the drain select level conductive layer is subsequently formed. The drain select level isolation structure 72 comprises a dielectric material, such as silicon oxide. The drain select level isolation structures 72 may extend laterally along a first horizontal direction hd1 and may be laterally spaced apart along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. The combination of the second alternating stack (232, 242), the second backward stepped dielectric material portion 265, the second insulating capping layer 270, and the optional drain select level isolation structure 72 together constitute the second layer structure (232, 242, 265, 270, 72).

[0106] See also Figure 7A and Figure 7B Various second layer openings (249, 229) may be formed through the second layer structure (232, 242, 265, 270, 72). A photoresist layer (not shown) may be applied over the second insulating cap layer 270 and may be photolithographically patterned to form various openings therethrough. The pattern of the openings may be the same as the pattern of the various first layer openings (149, 129), which are the same as the sacrificial first layer opening-filling portions (148, 128). Thus, the photoresist layer may be patterned using the photolithographic mask used to pattern the first layer openings (149, 129).

[0107] The pattern of openings in the photoresist layer can be transferred through the second layer structure (232, 242, 265, 270, 72) by a second anisotropic etching process to simultaneously (i.e., during the second anisotropic etching process) form various second layer openings (249, 229). The various second layer openings (249, 229) can include second layer memory openings 249 and second layer support openings 229.

[0108] The second layer memory opening 249 is formed directly on the top surface of a corresponding one of the sacrificial first layer memory opening filling portions 148. The second layer support opening 229 is formed directly on the top surface of a corresponding one of the sacrificial first layer support opening filling portions 128. In addition, each second layer support opening 229 can be formed to pass through a horizontal surface within the second stepped surfaces, including the interfacial surface between the second alternating stacks (232, 242) and the second backward stepped dielectric material portion 265. Figure 7B The positions of the steps S in the first layer of alternating stacking (132, 142) and the second layer of alternating stacking (232, 242) are shown by dotted lines.

[0109] The second anisotropic etching process may include an etching step in which the material of the second layer alternating stack (232, 242) is etched simultaneously with the material of the second backward stepped dielectric material portion 265. The chemistry of the etching steps may be alternating to optimize the etching of the material in the second layer alternating stack (232, 242) while providing an average etching rate comparable to the material of the second backward stepped dielectric material portion 265. The second anisotropic etching process may use, for example, a series of reactive ion etching processes or a single reactive etching process (e.g., CF4 / O2 / Ar etching). The sidewalls of the various second layer openings (249, 229) may be substantially vertical or may be tapered. The bottom perimeter of each second layer opening (249, 229) may be laterally offset and / or may be completely positioned within the perimeter of the top surface of the underlying sacrificial first layer opening fill portion (148, 128). The photoresist layer may then be removed, for example, by ashing.

[0110] See also Figure 8 The sacrificial first layer filling material of the sacrificial first layer opening filling portion (148, 128) can be removed using an etching process that etches the sacrificial first layer filling material selectively to the materials of the first and second insulating layers (132, 232), the first and second sacrificial material layers (142, 242), the first and second insulating capping layers (170, 270), and the interlayer dielectric layer 180. A memory opening 49 (also referred to as an interlayer memory opening 49) is formed in each combination of the second layer memory opening 249 and the volume from which the sacrificial first layer memory opening filling portion 148 was removed. A support opening 19 (also referred to as an interlayer support opening 19) is formed in each combination of the second layer support opening 229 and the volume from which the sacrificial first layer support opening filling portion 128 was removed.

[0111] 9A to 9D Sequential cross-sectional views of the memory opening 49 during formation of the memory opening filling structure are provided. The same structural changes occur in each of the memory opening 49 and the support opening 19.

[0112] See also Figure 9A , showing Figure 8 The memory opening 49 extends through the first layer structure and the second layer structure.

[0113] See also Figure 9B , a layer stack including a blocking dielectric layer 52, a charge storage layer 54, a tunneling dielectric layer 56, and a semiconductor channel material layer 60L can be sequentially deposited in the memory opening 49. The blocking dielectric layer 52 can include a single dielectric material layer or a stack of multiple dielectric material layers. In one embodiment, the blocking dielectric layer can include a dielectric metal oxide layer, which is essentially composed of a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material including at least one metal element and at least oxygen. The dielectric metal oxide can be essentially composed of at least one metal element and oxygen, or can be essentially composed of at least one metal element, oxygen, and at least one non-metallic element such as nitrogen. In one embodiment, the blocking dielectric layer 52 can include a dielectric metal oxide having a dielectric constant greater than 7.9 (i.e., having a dielectric constant greater than the dielectric constant of silicon nitride). The thickness of the dielectric metal oxide layer can be in the range of 1 nm to 20 nm, but smaller and larger thicknesses can also be used. Subsequently, the dielectric metal oxide layer can be used as a dielectric material portion that blocks the stored charge from leaking to the control gate electrode. In one embodiment, the blocking dielectric layer 52 includes aluminum oxide. Alternatively or additionally, the blocking dielectric layer 52 can include a dielectric semiconductor compound, such as silicon oxide, silicon oxynitride, silicon nitride, or a combination thereof.

[0114] Subsequently, a charge storage layer 54 may be formed. In one embodiment, the charge storage layer 54 may be a continuous layer or patterned discrete portions of a charge trapping material including a dielectric charge trapping material (e.g., which may be silicon nitride). Alternatively, the charge storage layer 54 may include a continuous layer or patterned discrete portions of a conductive material (such as doped polysilicon or a metallic material) that is patterned into a plurality of electrically isolated portions (e.g., floating gates), for example, by being formed as a sacrificial material layer (142, 242) within a lateral recess. In one embodiment, the charge storage layer 54 includes a silicon nitride layer. In one embodiment, the sacrificial material layer (142, 242) and the insulating layer (132, 232) may have vertically coinciding sidewalls, and the charge storage layer 54 may be formed as a single continuous layer. Alternatively, the sacrificial material layer (142, 242) can be laterally recessed relative to the sidewalls of the insulating layer (132, 232), and a combination of a deposition process and an anisotropic etching process can be used to form the charge storage layer 54 as a plurality of vertically spaced memory material portions. The thickness of the charge storage layer 54 can be in the range of 2 nm to 20 nm, although lesser and greater thicknesses can also be used.

[0115] The tunneling dielectric layer 56 comprises a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions. Charge tunneling can be performed by hot carrier injection or by Fowler-Nordheim tunneling induced charge transfer, depending on the operating mode of the single three-dimensional NAND string memory device to be formed. The tunneling dielectric layer 56 may include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitrides, dielectric metal silicates, alloys thereof, and / or combinations thereof. In one embodiment, the tunneling dielectric layer 56 may include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which stack is generally referred to as an ONO stack. In one embodiment, the tunneling dielectric layer 56 may include a substantially carbon-free silicon oxide layer or a substantially carbon-free silicon oxynitride layer. The thickness of the tunneling dielectric layer 56 may be in the range of 2 nm to 20 nm, but smaller and larger thicknesses may also be used. The stack of the blocking dielectric layer 52 , the charge storage layer 54 , and the tunneling dielectric layer 56 constitutes a memory film 50 that stores memory bits.

[0116] The semiconductor channel material layer 60L comprises a p-doped semiconductor material, such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel material layer 60L may have uniform doping. In one embodiment, the semiconductor channel material layer 60L has p-type doping, wherein the p-type dopant (such as boron atoms) is present at a concentration of 1.0×10 12 / cm 3 to 1.0×10 18 / cm 3 Such as 1.0×10 14 / cm 3 to 1.0×10 17 / cm 3 In one embodiment, the semiconductor channel material layer 60L includes boron-doped amorphous silicon or boron-doped polysilicon and / or consists essentially of boron-doped amorphous silicon or boron-doped polysilicon. In another embodiment, the semiconductor channel material layer 60L has n-type doping, wherein the n-type dopant (such as phosphorus atoms or arsenic atoms) is present at an atomic concentration of 1.0×10 12 / cm 3 to 1.0×10 18 / cm 3 Such as 1.0×10 14 / cm 3 to 1.0×10 17 / cm 3The semiconductor channel material layer 60L may be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the semiconductor channel material layer 60L may be in the range of 2 nm to 10 nm, although smaller and larger thicknesses may also be used. A cavity 49' is formed in the volume of each memory opening 49 that is not filled with the deposited material layer (52, 54, 56, 60L).

[0117] See also Figure 9C In the event that the cavity 49' in each memory opening is not completely filled with the semiconductor channel material layer 60L, a dielectric core layer may be deposited in the cavity 49' to fill any remaining portion of the cavity 49' within each memory opening. The dielectric core layer comprises a dielectric material, such as silicon oxide or organosilicate glass. The dielectric core layer may be deposited by a conformal deposition method, such as low pressure chemical vapor deposition (LPCVD), or by a self-planarizing deposition process, such as spin coating. The horizontal portion of the dielectric core layer overlying the second insulating cap layer 270 may be removed, for example, by recess etching. The recess etching continues until the top surface of the remaining portion of the dielectric core layer is recessed to a height below the top surface of the second insulating cap layer 270 (such as between the top surface of the second insulating cap layer 270 and the bottom surface of the second insulating cap layer 270) or below the bottom surface of the second insulating cap layer 270. Each remaining portion of the dielectric core layer constitutes a dielectric core 62.

[0118] See also Figure 9D A doped semiconductor material having a second conductivity type can be deposited in a cavity overlying the dielectric core 62. The second conductivity type is opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. Portions of the deposited doped semiconductor material, semiconductor channel material layer 60L, tunneling dielectric layer 56, charge storage layer 54, and blocking dielectric layer 52 overlying the horizontal plane (which includes the top surface of the second insulating cap layer 270) can be removed by a planarization process such as a chemical mechanical planarization (CMP) process.

[0119] Each remaining portion of the second conductivity type doped semiconductor material constitutes a drain region 63. The dopant concentration in the drain region 63 may be 5.0×10 19 / cm 3 to 2.0×10 21 / cm 3 The doped semiconductor material may be, for example, doped polysilicon.

[0120] Each remaining portion of the semiconductor channel layer 60L constitutes a semiconductor channel 60, through which current can flow when the vertical NAND device including the semiconductor channel 60 is turned on. The tunneling dielectric layer 56 is surrounded by the charge storage layer 54 and laterally surrounds the semiconductor channel 60. Each set of adjacent blocking dielectric layers 52, charge storage layers 54, and tunneling dielectric layers 56 together constitute a memory film 50 that can store charge for a macroscopic retention time. In some embodiments, the blocking dielectric layer 52 may not be present in the memory film 50 at this step, and the blocking dielectric layer may be subsequently formed after forming the backside recess. As used herein, the macroscopic retention time refers to a retention time suitable for the operation of a memory device as a permanent memory device, such as a retention time exceeding 24 hours.

[0121] Each combination of the memory film 50 and the semiconductor channel 60 (which is a semiconductor channel) within the memory opening 49 constitutes a memory stack structure 55. The memory stack structure 55 is a combination of the semiconductor channel 60, the tunneling dielectric layer 56, a plurality of memory elements including portions of the charge storage layer 54, and an optional blocking dielectric layer 52. Each combination of the memory stack structure 55, the dielectric core 62, and the drain region 63 within the memory opening 49 constitutes a memory opening filling structure 58. In the process, the source level material layer 110', the first layer structure (132, 142, 170, 165), the second layer structure (232, 242, 270, 265, 72), the interlayer dielectric layer 180, and the memory opening filling structure 58 collectively constitute a memory level component.

[0122] See also Figure 10 , shows an exemplary structure after forming the memory opening filling structure 58. While forming the memory opening filling structure 58, the support pillar structures 20 are formed in the support openings 19. Each support pillar structure 20 may have the same set of components as the memory opening filling structure 58.

[0123] See also Figure 11A and Figure 11B A first contact-level dielectric layer 280 may be formed over the second layer structure (232, 242, 270, 265, 72). The first contact-level dielectric layer 280 includes a dielectric material such as silicon oxide and may be formed by a conformal or non-conformal deposition process. For example, the first contact-level dielectric layer 280 may include undoped silicate glass and may have a thickness in the range of 100 nm to 600 nm, although smaller and larger thicknesses may also be used.

[0124] A photoresist layer (not shown) may be applied over the first contact level dielectric layer 280 and may be photolithographically patterned to form discrete openings in the memory array region 100 where the memory opening fill structure 58 is not present. Anisotropic etching may be performed to form vertical interconnect region cavities 585 having substantially vertical sidewalls extending through the first contact level dielectric layer 280. The second layer structures (232, 242, 270, 265, 72) and the first layer structures (132, 142, 170, 165) may be formed below the openings in the photoresist layer. The top surface of the lower level metal interconnect structure 780 may be physically exposed at the bottom of each vertical interconnect region cavity 585. The photoresist layer may be removed, for example, by ashing.

[0125] See also Figure 12 A dielectric material, such as silicon oxide, can be deposited in the vertical interconnect region cavity 585 by a conformal deposition process (such as low pressure chemical vapor deposition) or a self-planarizing deposition process (such as spin coating). Excess portions of the deposited dielectric material can be removed from above the top surface of the first contact level dielectric layer 280 by a planarization process. The remaining portion of the dielectric material in the vertical interconnect region cavity 585 constitutes the interconnect region dielectric fill material portion 584.

[0126] See also Figure 13A and Figure 13B A photoresist layer may be applied over the first contact-level dielectric layer 280 and may be photolithographically patterned to form elongated openings extending along a first horizontal direction hd1 between the clusters of memory opening fill structures 58. Backside trenches 79 may be formed by transferring a pattern in a photoresist layer (not shown) through the first contact-level dielectric layer 280, the second layer structures (232, 242, 270, 265, 72), and the first layer structures (132, 142, 170, 165), and into the in-process source-level material layer 110'. Portions of the first contact-level dielectric layer 280, the second layer structures (232, 242, 270, 265, 72), the first layer structures (132, 142, 170, 165), and the in-process source-level material layer 110' below the openings in the photoresist layer may be removed to form backside trenches 79. In one embodiment, backside trenches 79 can be formed between clusters of memory stack structures 55. The clusters of memory stack structures 55 can be laterally spaced apart by the backside trenches 79 along the second horizontal direction hd2.

[0127] See also Figure 14 and Figure 15A, backside trench spacers 77 may be formed on the sidewalls of each backside trench 79. For example, a conformal spacer material layer may be deposited in the backside trench 79 and over the first contact-level dielectric layer 280, and may be anisotropically etched to form the backside trench spacers 77. The backside trench spacers 77 include a material different from that of the source-level sacrificial layer 104. For example, the backside trench spacers 77 may include silicon nitride.

[0128] See also Figure 15B In an isotropic etching process, an etchant that etches the material of the source-level sacrificial layer 104 selectively to the material of the first alternating stacks (132, 142), the second alternating stacks (232, 242), the first and second insulating capping layers (170, 270), the first contact-level dielectric layer 280, the upper sacrificial substrate 105, and the lower sacrificial substrate 103 can be introduced into the backside trenches. For example, if the source-level sacrificial layer 104 comprises undoped amorphous silicon or an undoped amorphous silicon-germanium alloy, the backside trench spacers 77 comprise silicon nitride, and the upper and lower sacrificial liners (105, 103) comprise silicon oxide, a wet etching process using hot trimethyl-2-hydroxyethylammonium hydroxide ("hot TMY") or tetramethylammonium hydroxide (TMAH) can be used to remove the source-level sacrificial layer 104 selectively to the backside trench spacers 77 and the upper and lower sacrificial liners (105, 103). A source cavity 109 is formed in the volume from which the source level sacrificial layer 104 is removed.

[0129] Wet etching chemistries such as thermal TMY and TMAH are selective for doped semiconductor materials, such as the p-doped semiconductor material and / or the n-doped semiconductor material of the upper source level semiconductor layer 116 and the lower source level semiconductor layer 112. Therefore, the use of selective wet etching chemistries such as thermal TMY and TMAH in the wet etching process for forming the source cavity 109 provides a larger process window that resists etch depth variations during the formation of the backside trench 79. Specifically, when forming the source cavity 109 and / or the backside trench spacer 77, even if the sidewalls of the upper source level semiconductor layer 116 are physically exposed or even if the surface of the lower source level semiconductor layer 112 is physically exposed, incidental etching of the upper source level semiconductor layer 116 and / or the lower source level semiconductor layer 112 is minimal, and structural changes in the exemplary structure caused by the unintended physical exposure of the surface of the upper source level semiconductor layer 116 and / or the lower source level semiconductor layer 112 during the manufacturing steps do not lead to device failure. Each of the memory opening filling structures 58 is physically exposed to the source cavity 109 . Specifically, each of the memory opening filling structures 58 includes a sidewall that is physically exposed to the source cavity 109 .

[0130] See also Figure 15C , a sequence of isotropic etchants (such as wet etchants) can be applied to the physically exposed portions of the memory film 50 to sequentially etch the various component layers of the memory film 50 from the outside to the inside, and physically expose the cylindrical surface of the semiconductor channel 60 at the level of the source cavity 109. The upper and lower sacrificial liners (105, 103) can be incidentally etched during the removal of the portion of the memory film 50 positioned at the level of the source cavity 109. The volume of the source cavity 109 can be expanded by removing portions of the memory film 50 at the level of the source cavity 109 and the upper and lower sacrificial liners (105, 103). The top surface of the lower source-level semiconductor layer 112 and the bottom surface of the higher source-level semiconductor layer 116 can be physically exposed to the source cavity 109. The source cavity 109 is formed by isotropically etching the source level sacrificial layer 104 and a bottom portion of each memory film 50 selectively to at least one source level semiconductor layer, such as the lower source level semiconductor layer 112 and the upper source level semiconductor layer 116 , and the semiconductor channel 60 .

[0131] See also Figure 15D , a semiconductor material having a dopant of the second conductivity type may be deposited on physically exposed semiconductor surfaces surrounding the source cavity 109. The physically exposed semiconductor surfaces include the bottom portion of the outer sidewalls of the semiconductor channel 60 and the horizontal surface of the at least one source-level semiconductor layer (such as the bottom surface of the higher source-level semiconductor layer 116 and / or the top surface of the lower source-level semiconductor layer 112). For example, the physically exposed semiconductor surfaces may include the bottom portion of the outer sidewalls of the semiconductor channel 60, the top horizontal surface of the lower source-level semiconductor layer 112, and the bottom surface of the higher source-level semiconductor layer 116.

[0132] In one embodiment, a doped semiconductor material of the second conductivity type can be deposited on the physically exposed semiconductor surface around the source cavity 109 by a selective semiconductor deposition process. During the selective semiconductor deposition process, a semiconductor precursor gas, an etchant, and a dopant gas can be simultaneously flowed into a processing chamber including the exemplary structure. For example, the semiconductor precursor gas can include silane, disilane, or dichlorosilane, the etchant gas can include gaseous hydrogen chloride, and the dopant gas can include a hydride of a dopant atom such as phosphine, arsine, antimony, or diborane. In this case, the selective semiconductor deposition process grows a doped semiconductor material having a second conductivity type doping from the physically exposed semiconductor surface around the source cavity 109. The deposited doped semiconductor material forms a source contact layer 114, which can contact the sidewalls of the semiconductor channel 60. The atomic concentration of the second conductivity type dopant in the deposited semiconductor material can be between 1.0×1020 / cm 3 to 2.0×10 21 / cm 3 In the range of 2.0×10 20 / cm 3 to 8.0×10 20 / cm 3 The initially formed source contact layer 114 may consist essentially of semiconductor atoms of the second conductivity type and dopant atoms. Alternatively, the source contact layer 114 may be formed using at least one non-selective doped semiconductor material deposition process. Optionally, one or more etch-back processes may be used in combination with multiple selective or non-selective deposition processes to provide a seamless and / or void-free source contact layer 114.

[0133] The duration of the selective semiconductor deposition process can be selected such that the source cavity 109 is filled with the source contact layer 114, and the source contact layer 114 contacts the bottom portion of the inner sidewall of the back trench spacer 77. In one embodiment, the source contact layer 114 can be formed by selectively depositing a doped semiconductor material having a second conductivity type from the semiconductor surface surrounding the source cavity 109. In one embodiment, the doped semiconductor material can include doped polysilicon. Thus, the source-level sacrificial layer 104 can be replaced by the source contact layer 114.

[0134] The layer stack including the lower source-level semiconductor layer 112, the source contact layer 114, and the upper source-level semiconductor layer 116 constitutes the buried source layer (112, 114, 116). The layer group including the buried source layer (112, 114, 116) and the source-level insulating layer 117 constitutes the source-level material layer 110, which replaces the source-level material layer 110' during the replacement process.

[0135] See also Figure 15E and Figure 16 The backside trench spacers 77 may be removed using an isotropic etching process that is selective to the insulating layer (132, 232), the first and second insulating capping layers (170, 270), the first contact-level dielectric layer 280, and the source contact layer 114. For example, if the backside trench spacers 77 comprise silicon nitride, a wet etching process using hot phosphoric acid may be performed to remove the backside trench spacers 77. In one embodiment, the isotropic etching process that removes the backside trench spacers 77 may be combined with a subsequent isotropic etching process that etches the sacrificial material layer (142, 242) selective to the insulating layer (132, 232), the first and second insulating capping layers (170, 270), the first contact-level dielectric layer 280, and the source contact layer 114.

[0136] An oxidation process may be performed to convert physically exposed surface portions of the semiconductor material into dielectric semiconductor oxide portions. For example, surface portions of the source contact layer 114 and the upper source level semiconductor layer 116 may be converted into dielectric semiconductor oxide slabs 122.

[0137] An annealing process may be performed before, after, or simultaneously with the oxidation process to induce the second conductivity type dopant to diffuse from the source contact layer 114 to the lower portion of the semiconductor channel 60, and to induce the second conductivity type dopant to diffuse from the drain region 63 to the upper portion of the semiconductor channel 60. The average atomic concentration of the first conductivity type dopant in the semiconductor channel 60 is lower than the average atomic concentration of the second conductivity type dopant in the source contact layer 114 or the drain region 63. Figure 15D In the processing step of , the physical pn junction at the cylindrical interface between the source contact layer 114 and the semiconductor channel 60 moves inward and then upward along the vertical semiconductor channel 60, as shown in FIG. Figure 15E As shown. The lower portion of each semiconductor channel 60 is converted into a corresponding source region 61 having a net doping of the second conductivity type. Figure 15D In the processing step of , the physical pn junction at the cylindrical interface between the drain region 63 and the semiconductor channel 60 moves outward and then downward along the vertical semiconductor channel 60, as shown in FIG. Figure 15E The upper portion of each semiconductor channel 60 is converted into an additional portion of the corresponding drain region 63 having a net doping of the second conductivity type.

[0138] The net atomic concentration of the second conductivity type dopant in the source region 61 and the drain region 63 is defined as the atomic concentration of the second conductivity type dopant minus the atomic concentration of the first conductivity type dopant. The maximum value of the net atomic concentration of the second conductivity type dopant in each source region 61 may be within 5.0×10 19 / cm 3 to 2.0×10 21 / cm 3 The net atomic concentration of the second conductivity type dopant in each source region 61 may gradually decrease with vertical distance from the top surface of the substrate 8 until the net atomic concentration reaches zero at the first physical pn junction 612 with the corresponding overlying semiconductor channel 60, as shown in FIG. Figure 15E Each first physical pn junction 612 may have a circular horizontal surface or a circular tapered surface having a tapered angle between the vertical and horizontal directions. The net atomic concentration of the second conductivity type dopant changes from positive to negative in an upward direction at each first physical pn junction 612 .

[0139] The maximum value of the net atomic concentration of the second conductivity type dopant in each drain region 63 may be 5.0×10 18 / cm 3 to 2.0×10 21 / cm 3 The net atomic concentration of the second conductivity type dopant in each drain region 63 may gradually decrease with vertical distance from a horizontal plane including the topmost surface of the drain region 63 until the net atomic concentration reaches zero at the second physical pn junction 614 with the corresponding underlying semiconductor channel 60, as shown in FIG. Figure 15E Each second physical pn junction 614 may have a circular horizontal surface or a circular tapered surface having a tapered angle between the vertical and horizontal directions. The net atomic concentration of the second conductivity type dopant changes from positive to negative in the downward direction at each second physical pn junction 614.

[0140] According to one aspect of the present disclosure, the atomic concentration of semiconductor conductivity type dopants in the source contact layer 114, the thicknesses of the source contact layer 114, the upper source-level semiconductor layer 116, and the source-level insulating layer 117, and the process conditions of the annealing process may be selected so that a first physical junction 612 may be formed over a first source-side subset 142A of the sacrificial material layers (142, 242). The first source-side subset 142A of the sacrificial material layers (142, 242) includes at least a bottommost sacrificial material layer of the first sacrificial material layers 142 and may additionally include one or more first sacrificial material layers 142 overlying the bottommost sacrificial material layer of the first sacrificial material layers 142 without omitting any intervening first sacrificial material layers 142 between a topmost sacrificial material layer and a bottommost sacrificial material layer of the first sacrificial material layers 142 within the first source-side subset 142A. In one embodiment, the first physical junction 612 can be located between a horizontal plane comprising a top surface of a topmost sacrificial material layer 142 within a first source-side subset 142A of sacrificial material layers (142, 242) and a horizontal plane comprising the first sacrificial material layer 142 directly overlying the topmost first sacrificial material layer 142 within the first source-side subset 142A of sacrificial material layers (142, 242). A second source-side subset 142B of sacrificial material layers (142, 242) overlies the first source-side subset 142A of sacrificial material layers (142, 242). The first sacrificial material within the first source-side subset 142A and the second source-side subset 142B of the sacrificial material layers (142, 242) corresponds to a level at which a source select gate electrode will subsequently be formed when the sacrificial material layer (142, 242) is replaced with a conductive layer.

[0141] According to one aspect of the present disclosure, the atomic concentration of the second conductivity type dopant in the drain region 63, the size of the drain region 63, and the process conditions of the annealing process can be selected so that the second physical junction 614 can be formed below the first drain side subset 242A of the sacrificial material layer (142, 242), as shown in FIG. Figure 15E As shown. The first drain-side subset 242A of the sacrificial material layers (142, 242) includes at least the topmost sacrificial material layer of the second sacrificial material layers 242 and may additionally include one or more second sacrificial material layers 242 that are located below the topmost sacrificial material layer of the second sacrificial material layers 242, without omitting any intervening second sacrificial material layers 242 between the bottommost sacrificial material layer of the second sacrificial material layers 242 and the topmost sacrificial material layer of the second sacrificial material layers 242 within the first drain-side subset 242A. In one embodiment, the second physical junction 614 may be located between a horizontal plane including the bottom surface of the bottommost second sacrificial material layer 242 within the first drain-side subset 242A of the sacrificial material layers (142, 242) and a horizontal plane including the second sacrificial material layer 242 that is directly below the bottommost sacrificial material layer 242 within the first drain-side subset 242A of the sacrificial material layers (142, 242). The second drain-side subset 242B of the sacrificial material layer (142, 242) is located below the first drain-side subset 242A of the sacrificial material layer (142, 242). The second sacrificial material layer 242 within the first drain-side subset 242A and the second drain-side subset 242B of the sacrificial material layer (142, 242) corresponds to a level where a drain select gate electrode will be subsequently formed when the sacrificial material layer (142, 242) is replaced with a conductive layer.

[0142] See also Figure 17 The sacrificial material layer (142, 242) can be removed selectively to the insulating layer (132, 232), the first and second insulating capping layers (170, 270), the first contact-level dielectric layer 280, the source contact layer 114, and the dielectric semiconductor oxide plate 122. For example, an etchant that selectively etches the material of the sacrificial material layer (142, 242) relative to the material of the insulating layer (132, 232), the first and second insulating capping layers (170, 270), the backward stepped dielectric material portion (165, 265), and the outermost layer of the memory film 50 can be introduced into the backside trench 79, for example, using an isotropic etching process. For example, the sacrificial material layer (142, 242) may include silicon nitride, and the insulating layer (132, 232), the first and second insulating capping layers (170, 270), the backward stepped dielectric material portion (165, 265) and the outermost layer of the memory film 50 may include silicon oxide.

[0143] The isotropic etching process may be a wet etching process using a wet etching solution, or may be a vapor phase (dry) etching process in which the etchant is introduced into the backside trench 79 in the vapor phase. For example, if the sacrificial material layer (142, 242) comprises silicon nitride, the etching process may be a wet etching process in which the exemplary structure is immersed in a wet etching bath comprising phosphoric acid, which selectively etches silicon nitride over silicon oxide, silicon, and various other materials used in the art.

[0144] A backside recess (143, 243) is formed in the volume from which the sacrificial material layer (142, 242) is removed. The backside recess (143, 243) includes a first backside recess 143 formed in the volume from which the first sacrificial material layer 142 is removed and a second backside recess 243 formed in the volume from which the second sacrificial material layer 242 is removed. Each of the backside recesses (143, 243) can be a laterally extending cavity having a lateral dimension that is greater than the vertical extent of the cavity. In other words, the lateral dimension of each of the backside recesses (143, 243) can be greater than the height of the corresponding backside recess (143, 243). Multiple backside recesses (143, 243) can be formed in the volume from which the material of the sacrificial material layer (142, 242) is removed. Each of the backside recesses (143, 243) may extend substantially parallel to the top surface of the substrate semiconductor layer 9. The backside recesses (143, 243) may be vertically bounded by the top surface of the underlying insulating layer (132, 232) and the bottom surface of the overlying insulating layer (132, 232). In one embodiment, each of the backside recesses (143, 243) may have a uniform height throughout.

[0145] See also Figure 18A 18E , a backside blocking dielectric layer (not shown) may optionally be deposited in the backside recesses (143, 243) and the backside trenches 79 and over the first contact level dielectric layer 280. The backside blocking dielectric layer comprises a dielectric material, such as a dielectric metal oxide, silicon oxide, or a combination thereof. For example, the backside blocking dielectric layer may comprise aluminum oxide. The backside blocking dielectric layer may be formed by a conformal deposition process such as atomic layer deposition or chemical vapor deposition. The thickness of the backside blocking dielectric layer may be in the range of 1 nm to 20 nm, such as 2 nm to 10 nm, although smaller and larger thicknesses may also be used.

[0146] At least one conductive material may be deposited in the plurality of backside recesses (143, 243), on the sidewalls of the backside trenches 79, and above the first contact level dielectric layer 280. The at least one conductive material may be deposited by a conformal deposition method, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. The at least one conductive material may include an elemental metal, an intermetallic alloy of at least two elemental metals, a conductive nitride of at least one elemental metal, a conductive metal oxide, a conductive doped semiconductor material, a conductive metal semiconductor alloy such as a metal silicide, alloys thereof, and combinations or stacks thereof.

[0147] In one embodiment, the at least one conductive material may include at least one metallic material, i.e., a conductive material comprising at least one metallic element. Non-limiting exemplary metallic materials that may be deposited in the backside recess (143, 243) include tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, and ruthenium. For example, the at least one conductive material may include a conductive metal nitride liner comprising a conductive metal nitride material such as TiN, TaN, WN, or a combination thereof, and a conductive filler material such as W, Co, Ru, Mo, Cu, or a combination thereof. In one embodiment, the at least one conductive material used to fill the backside recess (143, 243) may be a combination of a titanium nitride layer and a tungsten filler material.

[0148] A conductive layer (146, 246) can be formed in the backside recess (143, 243) by depositing at least one conductive material. A plurality of first conductive layers 146 can be formed in the plurality of first backside recesses 143, a plurality of second conductive layers 246 can be formed in the plurality of second backside recesses 243, and a continuous metal material layer (not shown) can be formed on the sidewalls of each backside trench 79 and above the first contact-level dielectric layer 280. Each of the first conductive layer 146 and the second conductive layer 246 can include a corresponding conductive metal nitride liner and a corresponding conductive filler material. Thus, the first and second sacrificial material layers (142, 242) can be replaced with the first and second conductive layers (146, 246), respectively. Specifically, each first sacrificial material layer 142 can be replaced with an optional portion of the backside blocking dielectric layer and the first conductive layer 146, and each second sacrificial material layer 242 can be replaced with an optional portion of the backside blocking dielectric layer and the second conductive layer 246. A backside cavity exists within the portion of each backside trench 79 that is not filled with the continuous layer of metallic material.

[0149] Residual conductive material can be removed from the interior of the backside trenches 79. Specifically, the deposited metal material of the continuous metal material layer can be etched back from the sidewalls of each backside trench 79 and from above the first contact-level dielectric layer 280, for example, by anisotropic or isotropic etching. Each remaining portion of the deposited metal material in the first backside recess constitutes a first conductive layer 146. Each remaining portion of the deposited metal material in the second backside recess constitutes a second conductive layer 246. The sidewalls of the first conductive material layer 146 and the second conductive layer can be physically exposed to the corresponding backside trench 79. The backside trenches can have a pair of curved sidewalls having a non-periodic width variation along the first horizontal direction hd1 and a nonlinear width variation along the vertical direction.

[0150] Each conductive layer (146, 246) can be a conductive sheet including openings therein. A first subset of the openings through each conductive layer (146, 246) can be filled with a memory opening filling structure 58. A second subset of the openings through each conductive layer (146, 246) can be filled with a support pillar structure 20. Due to the first stepped surface and the second stepped surface, each conductive layer (146, 246) can have a smaller area than any underlying conductive layer (146, 246). Due to the first stepped surface and the second stepped surface, each conductive layer (146, 246) can have a larger area than any overlying conductive layer (146, 246).

[0151] In some embodiments, a drain select level isolation structure 72 can be provided at the topmost level of the second conductive layer 246. A subset of the second conductive layer 246 positioned at the level of the drain select level isolation structure 72 constitutes a drain select gate electrode. A subset of the conductive layers (146, 246) positioned below the drain select gate electrode can serve as a combination of a control gate and a word line positioned at the same level. The control gate electrode within each conductive layer (146, 246) is a control gate electrode for a vertical memory device comprising the memory stack structure 55.

[0152] Each of the memory stack structures 55 includes a vertical stack of memory elements positioned at each level of the conductive layers (146, 246). A subset of the conductive layers (146, 246) may include word lines for the memory elements. The semiconductor devices in the peripheral device area 700 below may include word line switching devices configured to control bias voltages to corresponding word lines. The memory level assembly is positioned above the substrate semiconductor layer 9. The memory level assembly includes at least one alternating stack (132, 146, 232, 246) and a memory stack structure 55 extending vertically through the at least one alternating stack (132, 146, 232, 246).

[0153] See also 19A to 19D A dielectric fill material can be conformally deposited in the backside trench 79 by a conformal deposition process. The dielectric material can include, for example, silicon oxide. Each portion of the dielectric fill material filling the backside trench 79 constitutes a dielectric wall structure 76. The horizontally extending portion of the dielectric fill material overlying the first contact-level dielectric layer 280 constitutes a second contact-level dielectric layer 282. The second contact-level dielectric layer 282 can have a thickness in the range of 100 nm to 600 nm, although smaller and larger thicknesses can also be used.

[0154] A photoresist layer (not shown) can be applied over the second contact level dielectric layer 282 and can be photolithographically patterned to form various contact via openings. For example, an opening for forming a drain contact via structure can be formed in the memory array region 100, and an opening for forming a stepped area contact via structure can be formed in the staircase region 200. An anisotropic etching process is performed to transfer the pattern in the photoresist layer through the second and first contact level dielectric layers (282, 280) and the dielectric material portions below. The drain region 63 and the conductive layer (146, 246) can serve as an etch stop structure. A drain contact via cavity can be formed over each drain region 63, and a staircase area contact via cavity can be formed over each conductive layer (146, 246) at the stepped surface below the first and second backward stepped dielectric material portions (165, 265). The photoresist layer can then be removed, for example, by ashing.

[0155] Drain contact via structures 88 are formed in the drain contact via cavities and on the top surface of a corresponding one of the drain regions 63. Staircase area contact via structures 86 are formed in the staircase area contact via cavities and on the top surface of a corresponding one of the conductive layers (146, 246). The step area contact via structures 86 may include drain select level contact via structures that contact a subset of the second conductive layer 246 that serves as a drain select level gate electrode. In addition, the step area contact via structures 86 may include word line contact via structures that contact the conductive layer (146, 246) below the drain select level gate electrode and serve as word lines for the memory stack structure 55.

[0156] See also Figure 21A peripheral region via cavity can be formed through the second and first contact level dielectric layers (282, 280), the second and first backward stepped dielectric material portions (265, 165), and the drain side dielectric layer 768 to the top surface of a first subset of lower level metal interconnect structures 780 in the peripheral device region 400. A through memory region via cavity can be formed through the interconnect region dielectric fill material portion 584 and the drain side dielectric layer 768 to the top surface of a second subset of lower level metal interconnect structures 780. At least one conductive material can be deposited in the peripheral region via cavity and in the through memory region via cavity. Excess portions of the at least one conductive material can be removed from a horizontal plane above the top surface of the second contact level dielectric layer 282. Each remaining portion of the at least one conductive material in the peripheral region via cavity constitutes a peripheral region contact via structure 488. Each remaining portion of the at least one conductive material in the through memory region via cavity constitutes a through memory region via structure 588.

[0157] At least one additional dielectric layer may be formed over the contact-level dielectric layers (280, 282), and additional metal interconnect structures (referred to herein as higher-level metal interconnect structures) may be formed in the at least one additional dielectric layer. For example, the at least one additional dielectric layer may include a line-level dielectric layer 290 formed over the contact-level dielectric layers (280, 282). The higher-level metal interconnect structures may include a bit line 98 contacting a corresponding one of the drain contact via structures 88, and an interconnect line structure 96 contacting and / or electrically connected to at least one of the stepped region contact via structures 86 and / or the peripheral region contact via structures 488 and / or the through-memory level via structures 588. The word line contact via structures (provided as a subset of the stepped region contact via structures 86) may be electrically connected to word line driver circuitry through a subset of the lower-level metal interconnect structures 780 and through a subset of the peripheral region contact via structures 488.

[0158] In one embodiment, a three-dimensional memory device comprises a single three-dimensional NAND memory device, the conductive strips (146, 246) comprising or electrically connected to respective word lines of the single three-dimensional NAND memory device, the substrate 8 comprising a silicon substrate, the single three-dimensional NAND memory device comprising a single three-dimensional NAND string array over the silicon substrate, at least one memory cell in a first device level of the single three-dimensional NAND string array being positioned over another memory cell in a second device level of the single three-dimensional NAND string array. The silicon substrate may contain an integrated circuit including driver circuitry for the memory device located thereon, the conductive strips (146, 246) comprising a plurality of control gate electrodes having a strip shape extending substantially parallel to a top surface of the substrate 8, the plurality of control gate electrodes comprising at least a first control gate electrode positioned in the first device level and a second control gate electrode positioned in the second device level. The single three-dimensional NAND string array comprises a plurality of semiconductor channels 60, wherein at least one end of each of the plurality of semiconductor channels 60 extends substantially perpendicular to the top surface of the substrate 8, and one of the plurality of semiconductor channels comprising the semiconductor channel 60. The single three-dimensional NAND string array includes a plurality of charge storage elements (including portions of the memory film 50 ), each charge storage element being located adjacent a respective one of the plurality of semiconductor channels 60 .

[0159] Each combination of the semiconductor channel 60, the source region 61, the drain region 63, the memory film 50, and the portion of the conductive layer (146, 246) laterally surrounding the memory film 50 constitutes a NAND string 102. Current flows through the NAND string 102 only when there is a continuous conductive path through the combination of the semiconductor channel 60, the source region 61, and the drain region 63.

[0160] See also Figure 22 , showing Figure 21 Schematic diagram of the area around the NAND string 102 and the control circuits (156, 256, 356) for controlling the various conductive layers (146, 246). Figure 22 Clearly shown in.

[0161] The first conductive layer 146 includes a source select gate conductive layer (i.e., source select gate electrode) (146Si, 1≤i≤Ns), which is a set of continuous first conductive material layers 146, including the bottommost one in the first conductive layer 146. In one embodiment, the total number Ns of the source select gate conductive layers (146Si, 1≤i≤Ns) can be in the range of 2 to 8. Figure 22An embodiment is shown in which the total number Ns of source select gate conductive layers is 4. The source select gate conductive layers (146Si, 1≤i≤Ns) are used to select or unselect the NAND string 102 by enabling or disabling current flow through the corresponding laterally surrounding portions of the source region 61 or semiconductor channel 60. Current flows through the NAND string only when each of the source select gate conductive layers (146Si, 1≤i≤Ns) is supplied with a corresponding bias voltage that turns on the corresponding laterally surrounding portion of the source region 61 or semiconductor channel 60. The source select gate conductive layer (146Si, 1≤i≤Ns) includes a first source side subset 146A of the conductive layer (146, 246) located at the bottom end of the alternating stack {(132, 146), (232, 246)}, and a second source side subset 146B of the conductive layer (146, 246) directly covering the first source side subset 146A.

[0162] The second conductive layer 246 includes drain select gate conductive layers (i.e., drain select gate electrodes) (246Dj, 1≤j≤Nd), which are a set of continuous second conductive material layers 246, including a topmost conductive layer in the second conductive layer 246. In one embodiment, the total number Nd of drain select gate conductive layers (246Dj, 1≤j≤Nd) may be in the range of 2 to 8. Figure 22 An embodiment is shown in which the total number Ns of drain select gate conductive layers is 4. The drain select gate conductive layers (246Dj, 1≤j≤Nd) are used to select or unselect the NAND string 102 by enabling or disabling current flow through the drain region 63 or the corresponding laterally surrounding portion of the semiconductor channel 60. Current flows through the NAND string 102 only when each of the drain select gate conductive layers (146Dj, 1≤j≤Ns) is supplied with a corresponding bias voltage that turns on the corresponding laterally surrounding portion of the drain region 63 or the semiconductor channel 60. The drain select gate conductive layer (246Dj, 1≤j≤Nd) includes a first drain side subset 246A of the conductive layer (146, 246) located at the top of the alternating stack {(132, 146), (232, 246)}, and a second drain side subset 246B of the conductive layer (146, 246) located directly below the first drain side subset 246A.

[0163] A set of all other conductive layers (146, 246) between the source select gate conductive layer (146Si, 1≤i≤Ns) and the drain select gate conductive layer (246Dj, 1≤j≤Nd) may constitute a word line.

[0164] A first source-side subset 146A of conductive layers (146, 246) includes at least a bottom-most conductive layer of first conductive layers 146 and may include a contiguous set of first conductive layers 146 including the bottom-most conductive layer of first conductive layers 146. The first source-side subset 146A of conductive layers (146, 246) may or may not include one or more first conductive layers 146 overlying the bottom-most conductive layer of first conductive layers 146. Any intervening first conductive layers 146 (if any) between the top-most conductive layer of first conductive layers 146 and the bottom-most conductive layer of first conductive layers 146 within the first source-side subset 146A are included in the first source-side subset 146A. In one embodiment, a first physical junction 612 can be located between a horizontal plane comprising a top surface of a topmost conductive layer 146 within a first source-side subset 146A of conductive layers (146, 246) and a horizontal plane comprising first conductive layers 146 directly overlying a topmost first sacrificial conductive layer 146 of the first source-side subset 146A of conductive layers (146, 246). A second source-side subset 146B of conductive layers (146, 246) overlies the first source-side subset 146A of conductive layers (146, 246). The second source-side subset 146B of conductive layers (146, 246) includes a set of continuous first conductive layers 146, the set of continuous first conductive layers including a first conductive layer 146 directly overlying a topmost first conductive layer 146 of the first source-side subset 146A. The first conductive layer 146 within the first source-side subset 146A and the second source-side subset 146B of the conductive layer (146, 246) includes respective lower and upper source select gate electrodes.

[0165] A first drain-side subset 246A of conductive layers (146, 246) includes at least a topmost conductive layer of second conductive layers 246 and may include a set of contiguous second conductive layers 246 including the topmost conductive layer of second conductive layers 246. The first drain-side subset 246A of conductive layers (146, 246) may or may not include one or more second conductive layers 246 located below the topmost conductive layer of second conductive layers 246. Any intervening second conductive layers 246 (if any) between the bottommost conductive layer of second conductive layers 246 and the topmost conductive layer of second conductive layers 246 within the first drain-side subset 246A are included in the first drain-side subset 264A. In one embodiment, second physical junction 614 may be located between a horizontal plane comprising a bottom surface of bottommost second conductive layer 246 within first drain-side subset 246A of conductive layers (146, 246) and a horizontal plane comprising second conductive layers 246 directly below bottommost conductive layer 246 of first drain-side subset 246A of conductive layers (146, 246). Second drain-side subset 246B of conductive layers (146, 246) is located below first drain-side subset 246A of conductive layers (146, 246). Second drain-side subset 246B of conductive layers (146, 246) includes a set of continuous second conductive layers 246, including second conductive layers 246 directly below bottommost second conductive layer 246 of first drain-side subset 246A. The second conductive layer 246 within the first drain-side subset 246A and the second drain-side subset 246B of the conductive layers (146, 246) includes upper and lower drain select gate electrodes, respectively.

[0166] Each of the source select gate conductive layers (146Si, 1≤i≤Ns) can be electrically biased by a corresponding source select gate control transistor (SSTi, 1≤i≤Ns) disposed within the source select gate control circuit 156. Each of the drain select gate conductive layers (246Dj, 1≤j≤Nd) can be electrically biased by a corresponding drain select gate control transistor (SDTj, 1≤j≤Ng) disposed within the drain select gate control circuit 256. Each word line can be electrically biased by a corresponding word line driver transistor (WLNTk, 1≤k≤N). For example, if the total number of word lines is N, the total number of word line driver transistors (WLNTk, 1≤k≤N) can be N. The number N can be in the range of 2 to 1,024, such as 64 to 512. The word line driver transistors (WLNTk, 1≤k≤N) can be disposed within the word line driver circuit 356. The source select gate control circuit 156, the drain select gate control circuit 256, and the word line driver circuit 356 may include Figure 1AA corresponding subset of semiconductor devices 710 is shown.

[0167] Joint participation Figure 21 and Figure 22 A three-dimensional memory device is provided. The three-dimensional memory device includes an alternating stack of insulating layers (132, 232) and conductive layers (146, 246) located above a source contact layer 114, a NAND string (102) vertically extending through the alternating stack {(132, 146), (232, 246)} and including a semiconductor material stack (61, 60, 63), the semiconductor material stack including a source region 61, a semiconductor channel 60, and a drain region 63 from bottom to top, and a memory film 50 laterally surrounding the semiconductor material stack (61, 60, 63). The source region 61 contacts the source contact layer 114. A first physical pn junction 612 is located between the source region 61 and the semiconductor channel 60. A second physical pn junction 614 is located between the semiconductor channel 60 and the drain region 63.

[0168] The source select gate control circuit 156 may be configured to apply a first source select gate bias voltage to a first source side subset 146A of the conductive layer (146, 246) during an erase operation, and to apply a second source select gate bias voltage to a second source side subset 146B of the conductive layer (146, 246) overlying the first source side subset 146A of the conductive layer during an erase operation. The drain select gate control circuit 256 may be configured to apply a first drain select gate bias voltage to the first drain side subset 246A of the conductive layer (146, 246) during an erase operation, and to apply a second drain select gate bias voltage to the second drain side subset 246B of the conductive layer (146, 246) underlying the first drain side subset 246A of the conductive layer (146, 246) during an erase operation.

[0169] Thus, if source-side gate-induced leakage current (e.g., gate-induced source leakage current) is used to erase charge storage regions in memory cells, source select gate control circuitry 156 is configured to apply a first source select gate bias voltage to a first source-side subset 146A of the conductive layer (e.g., the lower source select gate electrode) during an erase operation of the vertical NAND string 102, and to apply a second source select gate bias voltage to a second source-side subset 146B of the conductive layer overlying the first source-side subset of the conductive layer (e.g., the upper source select gate electrode) during an erase operation. The first source select gate bias voltage has a magnitude and polarity that produces an accumulation region 260 at a central portion of the source region 61 laterally surrounded by the first source-side subset 146A of the conductive layer. The second source select gate bias voltage has a magnitude and polarity that produces an inversion zone 360 ​​at an upper portion of the source region laterally surrounded by the second source-side subset 146B of the conductive layer and a depletion region 160 between the inversion zone and the accumulation region.

[0170] If drain-side gate-induced leakage current (e.g., gate-induced drain leakage current) is used to erase the charge storage region in the memory cell, the drain select gate control circuit 256 is configured to apply a first drain select gate bias voltage to the first drain-side subset 246A of the conductive layer (e.g., the upper drain select gate electrode) during an erase operation, and to apply a second drain select gate bias voltage to the second drain-side subset 246B of the conductive layer (e.g., the lower drain select gate electrode) located below the first drain-side subset 246A of the conductive layer during an erase operation. The first drain select gate bias voltage has a magnitude and polarity that produces an accumulation region 960 at a central portion of the drain region 63 laterally surrounded by the first drain-side subset 246A of the conductive layer. The second drain select gate bias voltage has a magnitude and polarity that produces an inversion zone 860 at a lower portion of drain region 63 laterally surrounded by the second drain side subset 246B of the conductive layer and a depletion region 660 between the inversion zone and the accumulation region.

[0171] See also Figure 23 If source-side gate-induced leakage current (e.g., gate-induced source leakage current) is used to erase the charge storage region in the memory cell, the first source select gate bias voltage can have a magnitude and polarity that produces an accumulation region 260 at least at a middle portion of the source region 61 laterally surrounded by the first source-side subset 146A of the conductive layer (146, 246), and the second source select gate bias voltage has a magnitude and polarity that produces an inversion region 360 at an upper end portion of the source region 61 laterally surrounded by the second source-side subset 146B of the conductive layer (146, 246) and produces a depletion region 160 between the inversion region 360 and the accumulation region 260.

[0172] An accumulation region is a region in which the additional charge carriers that disrupt the charge neutrality of the region have the same conductivity type as the doping type of the region. An inversion region is a region in which the additional charge carriers that disrupt the charge neutrality of the region have a conductivity type opposite to the doping type of the region. A depletion region is a region in which free charge carriers are depleted and may not exist. In an illustrative example, if the semiconductor channel 60 has p-type doping (i.e., the first conductivity type is p-type), and if the source region 61 and the source contact layer 114 have n-type doping (i.e., the second conductivity type is n-type), the majority charge carriers in the source region 61 are electrons, and the majority charge carriers in the semiconductor channel 60 are holes. The accumulation region 260 within the source region 61 has additional electrons as free carriers, the inversion region 360 within the source region 61 has additional holes as free carriers, and the depletion region 160 is depleted of free charge carriers.

[0173] In one embodiment, the first physical pn junction 612 may be located above a horizontal plane comprising the topmost surface of the first source-side subset 146A of the conductive layers (146, 246). Figure 23 In the example shown, the first source-side subset 146A may include a first source select gate conductive layer 146S1, which is the bottommost conductive layer in the first conductive layer 146, and may optionally include a second source select gate conductive layer 146S2, which directly overlies the first source select gate conductive layer 146S1. In this case, the first physical pn junction 612 may be located above a horizontal plane HPS1 including the topmost surface of the second source select gate conductive layer 146S2.

[0174] In one embodiment, the first physical pn junction 612 may be located above a horizontal plane HPS2 that includes the top surface of the bottommost conductive layer within the second source-side subset 146B of conductive layers (146, 246). Figure 23 In the example shown, the second source-side subset 146B may include a third source select gate conductive layer 146S3 and an optional fourth source select gate conductive layer 146S4 directly overlying the second source select gate conductive layer 146S2. In this case, the first physical pn junction 612 may be located below a horizontal plane HPS2 including the top surface of the third source select gate conductive layer 146S3.

[0175] In one embodiment, a first source-side subset 146A of the conductive layers (146, 246) includes a first plurality of source-select level conductive layers (e.g., lower source-select gate electrodes) (146S1, 146S2), and a second source-side subset 146B of the conductive layers (146, 246) includes a second plurality of source-select level conductive layers (e.g., upper source-select gate electrodes) (146S3, 146S4).

[0176] In one embodiment, the semiconductor channel 60 has a p-type doping, and the source region 61, the drain region 63, and the source contact layer 114 have a corresponding n-type doping. In this case, the first source select gate bias voltage can be more positive than the second source select gate bias voltage. In one embodiment, the three-dimensional memory device can be configured to apply an erase channel bias voltage to the channel region 60 during an erase operation, for example, through the source region 61, the first source select gate bias voltage is different from the erase channel bias voltage, and the second source select gate bias voltage can be more negative than the erase channel bias voltage. In one embodiment, the first source select gate bias voltage can be more positive than the erase channel bias voltage. In another embodiment, the first source select gate bias voltage can be more negative than or equal to the erase channel bias voltage. For example, to accumulate the lower portion of the semiconductor channel adjacent to the lower source select gate electrode, the first source select gate bias voltage may be greater than the channel voltage (which is equal to the erase channel bias voltage) plus the threshold voltage at the level of the lower source select gate electrode. When the threshold voltage is negative, to accumulate the lower portion of the semiconductor channel, the first source select gate bias voltage may be lower (i.e., more negative) than the erase channel bias voltage.

[0177] In an illustrative example, the erase channel bias voltage (Vera) may be 0V to 30V, such as 20V, the second source select gate bias voltage may be (Vera-10V), and if the threshold voltage is less than zero (e.g., for an n-type channel), the first source select gate bias voltage may be equal to Vera, or if the threshold voltage is greater than zero, the first source select gate bias voltage may be equal to Vera+X, where X is greater than the threshold voltage. For example, if the threshold voltage is a positive number less than 2V, then X=2V. For example, for a negative threshold voltage, the erase channel bias voltage (Vera) may be 20V, the second source select gate bias voltage may be 10V, and the first source select gate bias voltage may be 20V. For a positive threshold voltage, the erase channel bias voltage (Vera) may be 20V, the second source select gate bias voltage may be 10V, and the first source select gate bias voltage may be 22V.

[0178] A positive voltage may be applied to the lower source select gate electrode, and a negative voltage may be applied to the upper source select gate electrode, to provide electrons to flow from the depletion region 160 into the source region 61 and to provide holes to flow from the depletion region into the channel region 60. The holes flow through the channel region 60 into the memory film 50 (e.g., into the charge storage layer 54) to erase the charge stored in the memory film (e.g., by recombination with electrons stored as charge storage in the memory film).

[0179] In one embodiment, the entire depletion region 160 may be located between a horizontal plane HPS3 including the bottommost surface of the second source-side subset 146B of the conductive layers (146, 246) and a horizontal plane HPS1 including the topmost surface of the first source-side subset 146A of the conductive layers (146, 246). In one embodiment, the thickness of the first insulating layer 132 located between the second source-side subset 146B of the conductive layers (146, 246) and the first source-side subset 146A of the conductive layers (146, 246) may be less than the thickness of each first insulating layer 132 between vertically adjacent pairs of first conductive layers 146 within the first source-side subset 146A, and may be less than the thickness of each first insulating layer 132 between vertically adjacent pairs of first conductive layers 146 within the second source-side subset 146B. In this case, the space between subsets 146A, 146B of conductive layer 146 is reduced and the vertical thickness of depletion region 160 may be reduced, and charge carriers may be more efficiently generated in depletion region 160 during an erase operation.

[0180] In one embodiment, a semiconductor substrate such as substrate 8 may be located below source contact layer 114. A field effect transistor may be located on the top surface of the semiconductor substrate. A dielectric material layer (such as lower dielectric material layer 760) overlying the field effect transistor may be located between the semiconductor substrate and source contact layer 114.

[0181] See also Figure 24 If drain-side gate-induced leakage current (e.g., gate-induced drain leakage current) is used to erase the charge storage region in the memory cell, the first drain select gate bias voltage may have a magnitude and polarity that produces an accumulation region 960 at least at a middle portion of the drain region 63 laterally surrounded by the first drain-side subset 246A of the conductive layer (146, 246). The second drain select gate bias voltage may have a magnitude and polarity that produces an inversion region 860 at a lower end portion of the drain region 63 laterally surrounded by the second drain-side subset 246B of the conductive layer (146, 246) and a depletion region 660 between the inversion region 860 and the accumulation region 960.

[0182] In one embodiment, the second physical pn junction 614 may be located below a horizontal plane HPD1 including the bottommost surface of the first drain-side subset 246A of the conductive layers (146, 246). Figure 24 In the example shown, the first drain-side subset 246A may include a first drain select gate conductive layer 246D1, which is the topmost conductive layer in the second conductive layer 246, and may optionally include a second drain select gate conductive layer 246D2, which is directly below the first drain select gate conductive layer 246D1. In this case, the second physical pn junction 614 may be located below a horizontal plane HPD1 including the bottommost surface of the second source select gate conductive layer 246D2.

[0183] In one embodiment, the second physical pn junction 614 can be located above a horizontal plane HPD2 that includes the bottom surface of the topmost conductive layer within the second drain-side subset of conductive layers. Figure 24 In the example shown, the second drain-side subset 246B may include a third drain select gate conductive layer 146D3 and an optional fourth drain select gate conductive layer 146D4 directly below the second drain select gate conductive layer 146D2. In this case, the second physical pn junction 614 may be located above a horizontal plane HPD2 including the bottom surface of the third drain select gate conductive layer 146S3.

[0184] In one embodiment, a first drain-side subset 246A of the conductive layer (146, 246) includes a first plurality of drain-select level conductive layers (e.g., upper drain-select gate electrodes) (246D1, 246D2), and a second drain-side subset 246B of the conductive layer (146, 246) includes a second plurality of drain-select level conductive layers (e.g., lower drain-select gate electrodes) (246D3, 246D4).

[0185] In one embodiment, the semiconductor channel 60 has a p-type doping, and the source region 61, the drain region 63, and the source contact layer 114 have a corresponding n-type doping. In this case, the first drain select gate bias voltage can be more positive than the second drain select gate bias voltage. In one embodiment, the three-dimensional memory device can be configured to apply an erase channel bias voltage to the channel region 60 during an erase operation. For example, through the drain region 63 and the corresponding bit line, the first drain select gate bias voltage can be more positive than the erase channel bias voltage, and the second drain select gate bias voltage can be more negative than the erase channel bias voltage. In an illustrative example, the erase channel bias voltage can be 0V, the first drain select gate bias voltage can be 8V, and the second drain select gate bias voltage can be -10V.

[0186] In one embodiment, the entire depletion region 660 may be located between a horizontal plane HPD3 including the topmost surface of the second drain-side subset 246B of the conductive layer (146, 246) and a horizontal plane HPD1 including the bottommost surface of the first drain-side subset 246A of the conductive layer (146, 246). In one embodiment, the thickness of the second insulating layer 232 located between the second drain-side subset 246B of the conductive layer (146, 246) and the first drain-side subset 246A of the conductive layer (146, 246) may be less than the thickness of each second insulating layer 232 between vertically adjacent pairs of second conductive layers 246 within the first drain-side subset 246A, and may be less than the thickness of each second insulating layer 232 between vertically adjacent pairs of second conductive layers 246 within the second drain-side subset 246B. In this case, the space between subsets 246A, 246B of conductive layer 246 is reduced, the vertical thickness of depletion region 660 can be reduced, and charge carriers can be more efficiently generated in depletion region 660 during an erase operation.

[0187] Referring to all figures and in accordance with various embodiments of the present disclosure, a method of erasing a NAND string 102 includes a channel 60, a memory film 50 located near the channel, and first and second active regions (61, 63) located near opposing respective first and second ends of the channel 60. The method includes applying a first voltage to at least one first select gate electrode (146S1, 246D1) (e.g., at least one electrode from a first set 146A, 246A) located near the first active region (61, 63) to generate an accumulation region (260, 960) in a first portion of the first active region (61, 63). The method also includes applying a second voltage different from the first voltage to at least one second select gate electrode (145S3, 246D3) located near the first active region (61, 63) (e.g., at least one electrode from the second set 146B, 246B) to generate an inversion region (360, 860) in a second portion of the first active region located between the first portion and the channel, and to generate a depletion region (160, 660) located in the first active region between the inversion region and the accumulation region.

[0188] In one embodiment, the NAND string 102 comprises a vertical NAND string in which the channel 60 is positioned perpendicular to the top surface of the substrate 8. A physical pn junction (612, 614) is located between the channel 60 and the first active region (61, 63). The position of the depletion region (160, 660) is controlled by the relative position of the at least one first select gate electrode and the at least one second select gate electrode with respect to the channel, rather than by the position of the physical pn junction.

[0189] In one embodiment, the channel 60 comprises a semiconductor channel having p-type doping, the first active region and the second active region (61, 63) comprise semiconductor active regions having n-type doping, the first voltage is a positive voltage, and the second voltage is a negative voltage. Electrons flow from the depletion region (160, 660) into the first active region (61, 63), and holes flow from the depletion region (160, 660) through the semiconductor channel 60 into the memory film 50 to erase negative charges stored in the memory film 50.

[0190] In one embodiment, the first active region includes a source region 61 located below the semiconductor channel 60. The at least one first select gate electrode includes at least one lower source select gate electrode 146S1 (e.g., which is part of set 146A), the at least one second select gate electrode includes at least one upper source select gate electrode 146S3 (e.g., part of set 146B) located above the at least one lower source select gate electrode, and a depletion region 160 is located below the at least one upper source select gate electrode 146S3 and above the at least one lower source select gate electrode 146S1.

[0191] In another embodiment, the first active region includes a drain region 63 located above the semiconductor channel 60, the at least one first selection gate electrode includes at least one higher drain selection gate electrode 246D1, the at least one second selection gate electrode includes at least one lower drain selection gate electrode 246D3 located below the at least one higher drain selection gate electrode 246D1, and the depletion region 660 is located above the at least one lower drain selection gate electrode 246D3 and below the at least one higher drain selection gate electrode 246D1.

[0192] In another embodiment, a method of operating a semiconductor device is provided. A three-dimensional memory device is provided, comprising an alternating stack of insulating layers (132, 232) and conductive layers (146, 246), the alternating stack being located above a source contact layer 114; a NAND string 102 vertically extending through the alternating stack {(132, 146), (232, 246)} and a source select gate control circuit 156. The NAND string 102 comprises a semiconductor material stack (61, 60, 63) including a source region 61, a semiconductor channel 60, and a drain region 63 from bottom to top, and a memory film 50 laterally surrounding the semiconductor material stack (61, 60, 63). The source region 61 contacts the source contact layer 114. A first physical pn junction 612 is located between the source region 61 and the semiconductor channel 60, and a second physical pn junction 614 is located between the semiconductor channel 60 and the drain region 63.

[0193] If source-side gate sensing of leakage current is used during an erase operation, the method includes performing an erase operation by applying an erase channel bias voltage to the semiconductor channel 60 (e.g., through the source region 61), by applying a first source select gate bias voltage to a first source-side subset 146A of the conductive layer (146, 246), and by applying a second source select gate bias voltage to a second source-side subset 146B of the conductive layer (146, 246) overlying the first source-side subset 146A of the conductive layer. The first source select gate bias voltage and the second source select gate bias voltage form an accumulation region 260 at least in the middle portion of the source region 61 laterally surrounded by the first source side subset 146A of the conductive layer (146, 246), form an inversion region 360 at the upper end portion of the source region 61 laterally surrounded by the second source side subset 146B of the conductive layer (146, 246), and form a depletion region 160 between the inversion region 360 and the accumulation region 260.

[0194] In one embodiment, the first physical pn junction 612 is located above a horizontal plane HPS1 of the topmost surface of the first source-side subset 146A including the conductive layer (146, 246); and the first physical pn junction 612 is located above a horizontal plane HPS2 of the top surface of the bottommost conductive layer within the second source-side subset 146B including the conductive layer (146, 246).

[0195] In one embodiment, the semiconductor channel 60 has p-type doping; the source region 61, the drain region 63 and the source contact layer 114 have corresponding n-type doping; the first source select gate bias voltage is more positive than the second source select gate bias voltage; the first source select gate bias voltage is more positive than the erase channel bias voltage; and the second source select gate bias voltage is more negative than the erase channel bias voltage.

[0196] In one embodiment, if drain-side gate sensing is used during an erase operation, the method includes applying a first drain-side select gate bias voltage to a first drain-side subset 246A of the conductive layer (146, 246) and applying a second drain-side select gate bias voltage to a second drain-side subset 246B of the conductive layer (146, 246) located below the first drain-side subset 246A of the conductive layer (146, 246) during the erase operation. The first drain-side select gate bias voltage and the second drain-side select gate bias voltage form an accumulation region 960 at least in a middle portion of the drain region 63 laterally surrounded by the first drain-side subset 246A of the conductive layer (146, 246), form an inversion region 860 at a lower end portion of the drain region 63 laterally surrounded by the second drain-side subset 246B of the conductive layer (146, 246), and form a depletion region 660 between the inversion region 860 and the accumulation region 960.

[0197] Various embodiments of the present disclosure can be used to provide a NAND string in which a high gate-induced leakage current can be generated in each depletion region (360, 660). During an erase operation, the position of the depletion region (360, 660) is independent of changes in the vertical diffusion distribution of the second conductivity type dopant from the source contact layer 114 or from the drain region 63. Therefore, regardless of how the height of the first physical pn junction 612 and the height of the second physical pn junction 614 vary, and regardless of the vertical distribution of the atomic concentration of the second conductivity type dopant in the source region 61 and the drain region 63, the rate of generation of electron-hole pairs in the depletion region (360, 660) during an erase operation can be uniform. Regardless of how the vertical distribution of the atomic concentration of the second conductivity type dopant in the source region 61 and the drain region 63 varies, the bit line current, which measures the rate at which majority charge carriers are injected from the depletion region (360, 660) into the semiconductor channel 60 during an erase operation, can be uniform. Therefore, a reliable erase operation that is insensitive to process variations that determine vertical dopant concentration profiles in the source and drain regions 61 and 63 may be performed.

[0198] Although specific embodiments have been mentioned above, it should be understood that the present disclosure is not limited thereto. It will be appreciated by those skilled in the art that various modifications may be made to the disclosed embodiments, and such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words "comprising" or "including" contemplate all embodiments in which the words "consisting essentially of" or the words "consisting of" replace the words "comprising" or "including." Where embodiments using specific structures and / or configurations are shown in the present disclosure, it should be understood that the present disclosure can be practiced with any other compatible structures and / or configurations that are functionally equivalent, provided that such substitution is not expressly prohibited or otherwise deemed impossible by those skilled in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A three-dimensional memory device, characterized in that: The three-dimensional memory device comprises: an alternating stack of insulating layers and conductive layers, the alternating stack being located above the source contact layer; a NAND string extending vertically through the alternating stack and comprising a semiconductor material stack including, from bottom to top, a source region, a semiconductor channel, and a drain region, and comprising a memory film laterally surrounding the semiconductor material stack, wherein the source region contacts the source contact layer, and wherein a first physical pn junction is located between the source region and the semiconductor channel, and a second physical pn junction is located between the semiconductor channel and the drain region; and a source select gate control circuit configured to apply a first source select gate bias voltage to a first source side subset of the conductive layer during an erase operation and to apply a second source select gate bias voltage to a second source side subset of the conductive layer overlying the first source side subset of the conductive layer during the erase operation, wherein the first source select gate bias voltage has a magnitude and polarity to produce an accumulation region at a middle portion of the source region laterally surrounded by the first source side subset of the conductive layer, and the second source select gate bias voltage has a magnitude and polarity to produce an inversion region at an upper end portion of the source region laterally surrounded by the second source side subset of the conductive layer and a depletion region between the inversion region and the accumulation region. 2 . The three-dimensional memory device of claim 1 , wherein the first physical pn junction is located above a horizontal plane including a topmost surface of the first source-side subset of the conductive layer. 3 . The three-dimensional memory device of claim 2 , wherein the first physical pn junction is located below a horizontal plane including a top surface of a bottommost conductive layer within the second source-side subset of the conductive layers.

4. The three-dimensional memory device according to claim 1 , wherein: said first source side subset of said conductive layers comprises a first plurality of source select level conductive layers; and The second source-side subset of the conductive layers includes a second plurality of source select level conductive layers.

5. The three-dimensional memory device according to claim 1 , wherein: The semiconductor channel has p-type doping; and The source region, the drain region and the source contact layer have corresponding n-type doping. 6 . The three-dimensional memory device of claim 5 , wherein the first source select gate bias voltage is more positive than the second source select gate bias voltage.

7. The three-dimensional memory device according to claim 6, wherein: The three-dimensional memory device is configured to apply an erase channel bias voltage to a channel region during the erase operation; the first source select gate bias voltage being more positive than the erase channel bias voltage; and The second source select gate bias voltage is more negative than the erase channel bias voltage.

8. The three-dimensional memory device of claim 1 , wherein the entire depletion region is located between a horizontal plane including a bottommost surface of the second source-side subset of the conductive layer and a horizontal plane including a topmost surface of the first source-side subset of the conductive layer.

9. The three-dimensional memory device according to claim 1 , further comprising: a semiconductor substrate, the semiconductor substrate being located below the source contact layer; a field effect transistor located on a top surface of the semiconductor substrate; and A dielectric material layer covers the field effect transistor and is located between the semiconductor substrate and the source contact layer.

10. The three-dimensional memory device of claim 1 , further comprising a drain select gate control circuit configured to apply a first drain select gate bias voltage to a first drain-side subset of the conductive layer during the erase operation and to apply a second drain select gate bias voltage to a second drain-side subset of the conductive layer located below the first drain-side subset of the conductive layer during the erase operation, wherein the first drain select gate bias voltage has a magnitude and polarity that generates an additional accumulation region at a middle portion of the drain region laterally surrounded by the first drain-side subset of the conductive layer, and the second drain select gate bias voltage has a magnitude and polarity that generates an additional inversion region at a lower end portion of the drain region laterally surrounded by the second drain-side subset of the conductive layer and generates an additional depletion region between the additional inversion region and the additional accumulation region. 11 . The three-dimensional memory device of claim 10 , wherein the second physical pn junction is located below a horizontal plane including a bottommost surface of the first drain-side subset of the conductive layer. 12 . The three-dimensional memory device of claim 11 , wherein the second physical pn junction is located above a horizontal plane including a bottom surface of a topmost conductive layer within the second drain-side subset of the conductive layers.

13. A three-dimensional memory device, characterized in that: The three-dimensional memory device comprises: an alternating stack of insulating layers and conductive layers, the alternating stack being located above the source contact layer; a NAND string extending vertically through the alternating stack and comprising a semiconductor material stack including, from bottom to top, a source region, a semiconductor channel, and a drain region, and comprising a memory film laterally surrounding the semiconductor material stack, wherein the source region contacts the source contact layer, and wherein a first physical pn junction is located between the source region and the semiconductor channel, and a second physical pn junction is located between the semiconductor channel and the drain region; and a drain select gate control circuit configured to apply a first drain select gate bias voltage to a first drain side subset of the conductive layer during an erase operation and to apply a second drain select gate bias voltage to a second drain side subset of the conductive layer below the first drain side subset of the conductive layer during the erase operation, wherein the first drain select gate bias voltage has a magnitude and polarity to produce an accumulation region at a middle portion of the drain region laterally surrounded by the first drain side subset of the conductive layer, and the second drain select gate bias voltage has a magnitude and polarity to produce an inversion region at a lower end portion of the drain region laterally surrounded by the second drain side subset of the conductive layer and a depletion region between the inversion region and the accumulation region.

14. The three-dimensional memory device of claim 13 , wherein the second physical pn junction is located below a horizontal plane including a topmost surface of the second source-side subset of the conductive layers and is located above a horizontal plane including a bottom surface of a topmost conductive layer within the second source-side subset of the conductive layers.

15. The three-dimensional memory device of claim 14 , wherein the entire depletion region is located between the horizontal plane including the topmost surface of the second source-side subset of the conductive layers and the horizontal plane including the bottom surface of the topmost conductive layer within the second source-side subset of the conductive layers.

16. The three-dimensional memory device of claim 13 , further comprising a source select gate control circuit configured to apply a first source select gate bias voltage to a first source-side subset of the conductive layer during the erase operation and to apply a second source select gate bias voltage to a second source-side subset of the conductive layer overlying the first source-side subset of the conductive layer during the erase operation, wherein the first source select gate bias voltage has a magnitude and polarity that produces an additional accumulation region at a middle portion of the source region laterally surrounded by the first source-side subset of the conductive layer, and the second source select gate bias voltage has a magnitude and polarity that produces an additional inversion region at an upper end portion of the source region laterally surrounded by the second source-side subset of the conductive layer and produces an additional depletion region between the additional inversion region and the additional accumulation region.

17. A method for erasing a NAND string, characterized in that: The NAND string includes a channel, a memory film located near the channel, a first active region located near a first end of the channel, and a second active region located near a second end of the channel opposite the first end, the method comprising: applying a first voltage to at least one first select gate electrode located adjacent to the first active region to generate an accumulation region in a first portion of the first active region; and applying a second voltage different from the first voltage to at least one second select gate electrode located near the first active region to generate an inversion region in a second portion of the first active region located between the first portion and the channel, and generating a depletion region in the first active region between the inversion region and the accumulation region; and A physical pn junction is located between the channel and the first active region.

18. The method according to claim 17, wherein: The NAND string comprises a vertical NAND string wherein the channel is positioned perpendicular to a top surface of a substrate; The position of the depletion region is controlled by the relative positions of the at least one first select gate electrode and the at least one second select gate electrode with respect to the channel, rather than by the position of the physical pn junction; The channel includes a semiconductor channel having p-type doping; The first active region and the second active region include semiconductor active regions having n-type doping; Electrons flow from the depletion region into the first active region; and Holes flow from the depletion region into the memory film through the semiconductor channel to erase negative charges stored in the memory film.

19. The method according to claim 18, wherein: The first active region includes a source region located below the semiconductor channel; the at least one first select gate electrode including at least one lower source select gate electrode; The at least one second select gate electrode includes at least one upper source select gate electrode positioned above the at least one lower source select gate electrode; and The depletion region is located below the at least one upper source select gate electrode and above the at least one lower source select gate electrode.

20. The method of claim 18, wherein: The first active region includes a drain region located above the semiconductor channel; the at least one first select gate electrode including at least one upper drain select gate electrode; The at least one second select gate electrode includes at least one lower drain select gate electrode below the at least one upper drain select gate electrode; and The depletion region is located above the at least one lower drain select gate electrode and below the at least one upper drain select gate electrode.

Images