High-switch-ratio vertical transistor based on graphene and preparation method of high-switch-ratio vertical transistor

Abstract

The invention relates to a graphene-based high-switch-ratio vertical organic transistor and a preparation method thereof, and belongs to the technical field of organic semiconductor devices. The transistor comprises a first metal electrode, a rubrene single-crystal active layer, a second metal electrode, a single-layer graphene electrode, a silicon dioxide dielectric layer and a silicon substrate which are sequentially stacked from top to bottom, wherein the silicon substrate is also used as a grid electrode. The graphene electrode is prepared by a mechanical stripping method, and is transferred to the surface of silicon dioxide at a low temperature of 50-120 DEG C after being pretreated by ozone or plasma to form a porous structure so as to improve the vertical charge injection performance; the rubrene single crystal active layer is deposited through a two-step sublimation method, high crystal quality is obtained through annealing treatment, then the rubrene single crystal active layer is transferred to the surface of the graphene electrode by means of the flexible polymer microneedle, and interface defects are reduced. And finally, respectively depositing metal electrodes with the thickness of 20-80nm above and below the rubrene to construct a vertical organic transistor structure. The device shows excellent switching performance under the condition of low power consumption, the switching ratio is larger than 2.5 * 10 < 6 >, the off-state current density is not larger than 10 [mu] A / cm < 2 >, and the device is suitable for flexible logic devices and neuromorphic calculation application.

Description

Technical Field

[0001] This invention relates to the field of semiconductor transistor devices, and more particularly to a graphene-based high on / off ratio vertical organic transistor and its fabrication method. Background Technology

[0002] In recent years, the rapid development of artificial intelligence and high-performance computing technologies has placed higher demands on novel semiconductor devices, especially low-power, high-switching-ratio organic transistors. Traditional silicon-based transistors are limited by high power consumption and size miniaturization bottlenecks, making it difficult to meet the needs of future high-performance computing and flexible electronic devices. To address this, researchers are actively exploring novel device architectures and material systems to achieve more efficient charge transport and lower energy consumption.

[0003] Organic field-effect transistors (OFETs) have shown great potential in flexible electronics, display drivers, and other fields due to their wide availability of materials, low-temperature processing capabilities, and mechanical flexibility. However, traditional organic field-effect transistors (OFETs) mostly adopt horizontal channel structures, which limit the device channel length and result in a long carrier transport path. This leads to insufficient on / off ratio and high operating voltage, making it difficult to meet the requirements of high-density integration and energy efficiency optimization.

[0004] Vertical organic transistors (vOFETs), due to their short-channel structure and high current density, offer significant advantages in improving device switching speed, integration, and power consumption control, gradually becoming an important candidate architecture for flexible electronics and novel computing hardware. Among these devices, graphene, with its atomic-level thickness, high conductivity, and good interface tunability, is widely used as an injection electrode in vertical structures. However, the following problems in existing technologies urgently need to be addressed: weak adhesion between graphene and inorganic dielectric layers (such as SiO2), leading to easy interface delamination or poor electrical contact; the quality of organic crystals such as fluorene is limited by the crystallization method, and incomplete crystallization or numerous defects will affect device turn-off performance; stress or damage is easily generated during crystal transfer, and excessive interface stress can induce leakage or interface defects; improper control of electrode layer thickness may lead to increased series resistance or uneven thermal stress, affecting the overall device performance.

[0005] Therefore, there is an urgent need to provide a new type of vertical organic transistor with optimized device structure, feasible interface quality control, and repeatable fabrication process to meet the application requirements of high performance and low power consumption. Summary of the Invention

[0006] The purpose of this invention is to provide a graphene-based high on / off ratio vertical organic transistor and its fabrication method, so as to solve the problems of unstable electrode interface, poor organic field quality, large transfer stress and insufficient device switching performance in the prior art.

[0007] To achieve the above objectives, the present invention proposes the following technical solution: The present invention provides a graphene-based vertical organic transistor, comprising, from top to bottom, the following layers stacked sequentially: a first metal electrode; a fluorene single-crystal active layer; a second metal electrode; a monolayer of graphene; a silicon dioxide dielectric layer; and a silicon substrate, which also serves as the gate. Specifically: the monolayer of graphene has a porous structure with a thickness of 1±0.2 nm and a porosity of 5%-20% to enhance vertical charge transport capability; the graphene is prepared by mechanical exfoliation and pretreated with ozone or plasma before transfer to enhance its adhesion to SiO2, followed by transfer at a low temperature of 50-120℃; the fluorene single-crystal active layer is formed by a two-step sublimation method, first sublimating at a high temperature of 330-350℃, then depositing crystals at a temperature of 210-230℃, followed by annealing at 80-150℃; the fluorene single crystal is transferred to the graphene surface using a highly flexible polymer-tipped microneedle tool to reduce interfacial stress and improve bonding quality. With a drain voltage of 2.0V and a gate voltage of 40V, the switching ratio of this device is not less than 2.5 × 10⁻⁶. 6 The off-state current density is no greater than 10 μA / cm. 2 .

[0008] Compared with the prior art, the present invention has the following advantages: by introducing porous monolayer graphene and red fluorene single crystal to form a vertical structure, the carrier transport path is effectively shortened and the conduction current is improved; the flexible microneedle transfer technology relieves crystal stress and reduces interface defects; the preparation method has strong controllability and is suitable for large-area preparation of flexible devices; the device has a high on / off ratio and low off-state current density, which is suitable for low-power logic devices and neuromorphic electronic platform applications. Attached Figure Description

[0009] Figure 1 This is a schematic diagram of the structure of the graphene-based organic vertical transistor described in this invention. Detailed Implementation

[0010] To more clearly illustrate the technical content of this invention, the structural composition and preparation process of this invention will be described in detail below with reference to the accompanying drawings and specific embodiments. This invention is not limited to the following embodiments; any modifications and substitutions falling within the substantial inventive concept of this invention should be covered within the protection scope of this invention.

[0011] like Figure 1 As shown, the present invention provides a graphene-based vertical organic transistor, comprising, from top to bottom, stacked components:

[0012] The first metal electrode (1) is made of gold (Au) material with a thickness of 20-80nm. It is deposited in the mask area by thermal evaporation to inject charge carriers into the organic field, reduce series resistance, and improve charge injection efficiency.

[0013] Red fluorene single crystal active layer (2): The thickness is controlled at 285±5nm. As an organic semiconductor channel material, it has good carrier mobility.

[0014] The second metal electrode (3) is made of the same material as the first metal electrode and has the same thickness (20-80nm). It is used for symmetrical injection to improve the uniformity of charge injection and the stability of the device.

[0015] Monolayer graphene electrode (4): The thickness is 1±0.2 nm, and the porosity is 5%-20%, which is beneficial to the vertical growth of red fluorene single crystals and charge transport. The graphene is a monolayer porous structure and is obtained by mechanical exfoliation.

[0016] The silicon dioxide dielectric layer (5) is SiO2 formed by thermal oxidation. Its thickness can be adjusted according to the specific application. It provides gate electric field control and supports the graphene film.

[0017] Silicon substrate (6): also serves as gate electrode. When the device is working, the transport behavior of organic semiconductor carriers is regulated by applying gate voltage.

[0018] The method for fabricating vertical organic transistors includes the following steps:

[0019] Graphene electrode fabrication and transfer. High-quality natural graphite was selected as the starting material, and a single-layer graphene film was obtained by mechanical exfoliation. To enhance its adhesion to SiO2, the graphene was pretreated with ozone or plasma before transfer. Graphene was transferred to the surface of a silica dielectric layer using dry or wet methods. The transfer process was controlled within a low temperature range (50-120℃) to avoid thermal damage and ensure complete coverage and good interfacial adhesion. The graphene electrode has a porous structure with a porosity controlled between 5% and 20%, which is beneficial for the vertical growth of fluorescein single crystals and charge transport.

[0020] A two-step sublimation preparation of rubrene single crystals. Rubrene powder with a purity ≥99% was placed in a dry quartz boat and placed in the high-temperature zone of a tube furnace. High-purity argon gas (flow rate 20 sccm) was introduced as the carrier gas, and the temperature of the high-temperature zone was set to 330-350℃ for sublimation for 30-40 minutes. Rubrene then deposited as a crystalline film in a low-temperature zone at 210-230℃. After cooling, it underwent annealing at 80-150℃ for 10-30 minutes to improve crystal integrity and crystal quality.

[0021] Red fluorene single crystal transfer. Highly flexible polymer microneedles (e.g., made of PDMS, model MicroToolsT1-L25-A1) were used to transfer red fluorene single crystals from the growth substrate to the surface of pretreated monolayer graphene. During the transfer process, precise positioning, force, and angle were controlled using a microscope to ensure tight adhesion between the crystal and graphene and to minimize interfacial stress and defects.

[0022] Metal electrode deposition. Using thermal evaporation, first and second metal electrodes (both gold) are deposited above and below the rubrene single crystal, with thicknesses controlled between 20 and 80 nm. The electrode regions are defined using metal masks, ensuring that the electrode layer only covers the active areas.

[0023] Device integration and packaging. After fabrication, the device is electrode-welded and packaged to prevent environmental humidity from causing instability in device performance.

[0024] The fabricated device was then subjected to electrical testing at room temperature using a semiconductor parameter analyzer (such as Keysight B1500A).

[0025] Test voltage: Drain voltage V D Set to 2.0V, gate voltage V G Scanning within the 0-40V range; On-state current density: Current density in the device's on-state is higher than 0.1A / cm². 2 Off-state current density: V G At 0V, the off-state current density is less than 10μA / cm. 2 On / off ratio: J ON / J OFF Greater than 2.5×10 6 The device showed no significant performance degradation during multiple switching tests, demonstrating good stability and repeatability.

Claims

1. A graphene-based high on-off ratio vertical organic transistor, characterized in that, The vertical organic transistor comprises, from top to bottom, a first metal electrode (1), a rubrene single crystal (2), a second metal electrode (3), a single-layer graphene (4), a silicon dioxide (5), and a silicon substrate (6) serving as a gate electrode.

2. The vertical organic transistor according to claim 1, wherein The thickness of the first metal electrode and the second metal electrode is 20-80 nm.

3. The vertical organic transistor according to claim 2, wherein The single-layer graphene electrode is prepared by a mechanical exfoliation method, and the graphene is pretreated by ozone or plasma before being transferred, so as to enhance the adhesion of the graphene to the SiO2, and the graphene is transferred to the surface of the SiO2 medium layer under a low temperature condition (50-120 ℃).

4. The vertical organic transistor according to claim 3, wherein The thickness of the single-layer graphene is 1±0.2 nm, and the porosity is 5%-20%, so as to improve the vertical charge transmission performance.

5. The vertical organic transistor according to claim 4, wherein The rubrene single crystal active layer is prepared by a two-step sublimation method, specifically including: sublimation of rubrene powder at 330-350 ℃ in an inert atmosphere for 30-40 minutes; deposition of the crystal in a region at 210-230 ℃; and annealing of the crystal at 80-150 ℃ for 10-30 minutes after deposition.

6. The vertical organic transistor according to claim 5, wherein The rubrene single crystal is transferred to the surface of the graphene by a high-flexibility polymer tip tool, so as to buffer the stress of the crystal and improve the interface bonding quality.

7. The vertical organic transistor according to claim 6, wherein The switch ratio of the transistor is not less than 2.5×10 6 , and the off-state current density is not greater than 10 μA / cm 2 .

8. A preparation method of a graphene-based vertical organic transistor, the method comprising the following steps: a. providing a silicon substrate and forming a silicon dioxide medium layer; b. preparing a single-layer graphene by a mechanical exfoliation method, and pretreating the graphene by ozone or plasma before being transferred, so as to enhance the adhesion of the graphene to the SiO2, and transferring the graphene to the surface of the medium layer under a temperature condition of 50-120 ℃; c. preparing a rubrene single crystal by a two-step sublimation method, including: i. sublimation of rubrene powder at 330-350 ℃ in an inert atmosphere for 30-40 minutes; ii. deposition of the rubrene crystal in a region at 210-230 ℃; iii. annealing of the crystal at 80-150 ℃ for 10-30 minutes; d. transferring the rubrene single crystal to the surface of the single-layer graphene by a high-flexibility polymer microneedle tool; e. forming metal electrodes above and below the rubrene single crystal, and the thickness of the metal electrodes is 20-80 nm, so as to construct a vertical organic transistor structure.

9. The method of claim 8, wherein, The single-layer graphene is a porous structure, and the porosity is 5%-20%.

10. The method according to claim 8 or 9, characterized in that, The microneedle is made of a flexible polymer, and is selected from polydimethylsiloxane (PDMS).

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