Three-dimensional memory devices having dual-sided stepped surfaces and methods of manufacturing the same

Abstract

A memory die can include an alternating stack of insulating layers and electrically conductive layers located above a substrate, and a memory stack structure extending vertically through the alternating stack. A first tier stack within the alternating stack includes a first stepped region in which first electrically conductive layers have respective lateral extents that increase with a vertical distance from the substrate to provide a first stepped surface. A second tier stack within the alternating stack includes a second stepped region in which second electrically conductive layers have respective lateral extents that decrease with the vertical distance from the substrate to provide a second stepped surface. The second tier stack can be farther from the substrate than the first tier stack. A contact via structure can be formed from a top side and a bottom side of the alternating stack.

Description

[0001] Related applications

[0002] This application claims the benefit of priority to U.S. non-provisional application No. 16 / 985,305, filed on August 5, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure generally relates to the field of semiconductor devices, and in particular, to a three-dimensional memory device employing a double-sided stepped surface and a method for manufacturing the same. Background Art

[0004] Three-dimensional vertical NAND strings with one bit per cell are disclosed in an article by T. Endoh et al., “Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell,” IEDM Proc. (2001) 33-36. Summary of the Invention

[0005] According to one aspect of the present disclosure, a semiconductor structure including a memory die is provided. The memory die includes: an alternating stack of insulating layers and conductive layers, the alternating stack being located above a substrate; and a memory stack structure extending vertically through the alternating stack, wherein: the alternating stack includes a first layer stack including a first insulating layer and a first conductive layer, and a second layer stack including a second insulating layer and a second conductive layer and vertically spaced from the substrate by the first alternating stack; the first layer stack includes a first stepped region, wherein the first conductive layer has a corresponding lateral extent that increases with vertical distance from the substrate to provide a first stepped surface; and the second layer stack includes a second stepped region, wherein the second conductive layer has a corresponding lateral extent that decreases with the vertical distance from the substrate to provide a second stepped surface.

[0006] According to another aspect of the disclosure, a method of forming a semiconductor structure is provided that includes forming an alternating stack of insulating layers and spacer material layers over a substrate including a semiconductor material layer, the alternating stack including a first stack of a first insulating layer and a first spacer material layer and a second stack of a second insulating layer and a second spacer material layer, the second stack being farther from the substrate than the first stack, and the first and second spacer material layers being formed as or subsequently replaced by first and second electrically conductive layers, respectively; forming a distal stepped surface by patterning the second stack, wherein a lateral extent of the second spacer material layer decreases with vertical distance from the substrate in forming the distal stepped surface; forming memory stack structures through the alternating stack, wherein each of the memory stack structures includes a vertical semiconductor channel and a memory film; forming an opening through the semiconductor material layer; forming a proximal stepped surface by patterning a portion of the first stack within an area of the opening through the semiconductor material layer with a plurality of masked anisotropic etch processes that etch unmasked regions of the portion of the first stack in a direction pointing from the substrate toward the alternating stack; and forming an upright stepped dielectric material portion on the proximal stepped surface of the first stack. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 is a schematic vertical cross-sectional view of an exemplary structure after forming an alternating stack of insulating layers and spacer material layers over a substrate according to an embodiment of the disclosure.

[0008] Figure 2A is a top-down view of an exemplary structure after forming a back-stepped dielectric material layer at a level of a second stack including a second insulating layer and a second sacrificial material layer.

[0009] Figure 2B is a vertical cross-sectional view of an exemplary structure taken along the hinged vertical plane B-B' of Figure 2A .

[0010] Figure 3A is a top-down view of an exemplary structure after forming memory openings according to an embodiment of the disclosure.

[0011] Figure 3B is a vertical cross-sectional view of an exemplary structure taken along the hinged vertical plane B-B' of Figure 3A .

[0012] Figures 4A to 4Hare sequential schematic vertical cross-sectional views of a memory opening within an exemplary structure during formation of a memory stack structure, an optional dielectric core, and a drain region therein according to an embodiment of the present disclosure.

[0013] Figure 5A is a top-down view of an exemplary structure after forming a memory opening fill structure according to an embodiment of the present disclosure.

[0014] Figure 5B It is along Figure 5A A vertical sectional view of the exemplary structure taken along the hinged vertical plane BB'.

[0015] Figure 5C It is along Figure 5A A vertical cross-sectional view of the exemplary structure taken along the hinged vertical plane CC'.

[0016] Figure 6A is a top-down view of the exemplary structure after forming a contact-level dielectric layer, attaching a first substrate, and thinning the backside of the semiconductor material layer in the substrate according to an embodiment of the present disclosure.

[0017] Figure 6B It is along Figure 6A A vertical sectional view of the exemplary structure taken along the hinged vertical plane BB'.

[0018] Figure 6C It is along Figure 6A A vertical cross-sectional view of the exemplary structure taken along the hinged vertical plane CC'.

[0019] Figure 7A is a top-down view of an exemplary structure after forming a through-substrate opening through a layer of semiconductor material according to an embodiment of the present disclosure.

[0020] Figure 7B It is along Figure 7A A vertical sectional view of the exemplary structure taken along the hinged vertical plane BB'.

[0021] Figure 7C It is along Figure 7A A vertical cross-sectional view of the exemplary structure taken along the hinged vertical plane CC'.

[0022] Figure 8A is a top-down view of an exemplary structure after forming a patterned hard mask layer according to an embodiment of the present disclosure.

[0023] Figure 8B It is along Figure 8A A vertical sectional view of the exemplary structure taken along the hinged vertical plane BB'.

[0024] Figure 8C It is along Figure 8A A vertical cross-sectional view of the exemplary structure taken along the hinged vertical plane CC'.

[0025] Figure 9A is a top-down view of an exemplary structure after forming a trimmable etch mask layer and a first anisotropic etch process according to an embodiment of the present disclosure.

[0026] Figure 9B It is along Figure 9A A vertical sectional view of the exemplary structure taken along the hinged vertical plane BB'.

[0027] Figure 9C It is along Figure 9A A vertical cross-sectional view of the exemplary structure taken along the hinged vertical plane CC'.

[0028] Figure 10A is a top-down view of an exemplary structure after a terminal anisotropic etch process within an alternating series of an etch mask trim process and an anisotropic etch process to form a nearside stepped surface, according to an embodiment of the present disclosure.

[0029] Figure 10B It is along Figure 10A A vertical sectional view of the exemplary structure taken along the hinged vertical plane BB'.

[0030] Figure 10C It is along Figure 10A A vertical cross-sectional view of the exemplary structure taken along the hinged vertical plane CC'.

[0031] Figure 11A is a top-down view of an exemplary structure after forming an upstanding stepped dielectric material portion according to an embodiment of the present disclosure.

[0032] Figure 11B It is along Figure 11A A vertical sectional view of the exemplary structure taken along the hinged vertical plane BB'.

[0033] Figure 11C It is along Figure 11A A vertical cross-sectional view of the exemplary structure taken along the hinged vertical plane CC'.

[0034] Figure 12A is a top-down view of an exemplary structure after forming a through-stack connecting via cavity according to an embodiment of the present disclosure.

[0035] Figure 12B It is along Figure 12A A vertical sectional view of the exemplary structure taken along the hinged vertical plane BB'.

[0036] Figure 12C is a vertical cross-sectional view of the exemplary structure taken along the hinged vertical plane B-B’ of Figure 12A

[0037] Figure 13A is a top-down view of an exemplary structure after forming a through- stack connection via structure laterally isolated in a process that includes a respective combination of a sacrificial via structure and a tubular dielectric spacer in accordance with an embodiment of the present disclosure.

[0038] Figure 13B is a vertical cross-sectional view of the exemplary structure taken along the hinged vertical plane B-B’ of Figure 13A

[0039] Figure 13C is a vertical cross-sectional view of the exemplary structure taken along the hinged vertical plane B-B’ of Figure 13A

[0040] Figure 14A is a top-down view of an exemplary structure after forming a line trench vertically extending through a semiconductor material layer, an upstanding stepped dielectric material portion, and an alternating stack in accordance with an embodiment of the present disclosure.

[0041] Figure 14B is a vertical cross-sectional view of the exemplary structure taken along the hinged vertical plane B-B’ of Figure 14A

[0042] Figure 14C is a vertical cross-sectional view of the exemplary structure taken along the hinged vertical plane B-B’ of Figure 14A

[0043] Figure 15A is a top-down view of an exemplary structure after forming a lateral recess by removing a sacrificial material layer in accordance with an embodiment of the present disclosure.

[0044] Figure 15B is a vertical cross-sectional view of the exemplary structure taken along the hinged vertical plane B-B’ of Figure 15A

[0045] Figure 15C is a vertical cross-sectional view of the exemplary structure taken along the hinged vertical plane B-B’ of Figure 15A

[0046] Figure 16A is a top-down view of an exemplary structure after forming a conductive layer in accordance with an embodiment of the present disclosure.

[0047] Figure 16B is a vertical cross-sectional view of the exemplary structure taken along the hinged vertical plane B-B’ of Figure 16A ​​​​​​​A vertical sectional view of the exemplary structure taken along the hinged vertical plane BB'.

[0048] Figure 16C It is along Figure 16A A vertical cross-sectional view of the exemplary structure taken along the hinged vertical plane CC'.

[0049] Figure 17A is a top-down view of an exemplary structure after forming a dielectric line trench-fill structure according to an embodiment of the present disclosure.

[0050] Figure 17B It is along Figure 17A A vertical sectional view of the exemplary structure taken along the hinged vertical plane BB'.

[0051] Figure 17C It is along Figure 17A A vertical cross-sectional view of the exemplary structure taken along the hinged vertical plane CC'.

[0052] Figure 18A is a top-down view of an exemplary structure after forming a substrate-side contact via structure according to an embodiment of the present disclosure.

[0053] Figure 18B It is along Figure 18A A vertical sectional view of the exemplary structure taken along the hinged vertical plane BB'.

[0054] Figure 18C It is along Figure 18A A vertical cross-sectional view of the exemplary structure taken along the hinged vertical plane CC'.

[0055] Figure 19A According to the embodiment of the present disclosure, Figure 19B A partial perspective top-down view of the exemplary structure after forming a substrate-side metal interconnect structure along horizontal plane AA'.

[0056] Figure 19B It is along Figure 19A A vertical sectional view of the exemplary structure taken along the hinged vertical plane BB'.

[0057] Figure 19C It is along Figure 19A A vertical cross-sectional view of the exemplary structure taken along the hinged vertical plane CC'.

[0058] Figure 20 is a vertical cross-sectional view of an exemplary structure after forming a backside insulating layer, attaching a second carrier substrate to the backside insulating layer, and separating the first carrier substrate according to an embodiment of the present disclosure.

[0059] Figure 21is a vertical cross-sectional view of an exemplary structure after forming a through substrate via cavity and an interconnect side contact via cavity according to an embodiment of the present disclosure.

[0060] Figure 22 is a vertical cross-sectional view of an exemplary structure after forming an interconnect-level dielectric layer embedding a memory-side metal interconnect structure and a memory-side metal bond pad according to an embodiment of the present disclosure.

[0061] Figure 23 is a vertical cross-sectional view of a logic die including logic circuits and a logic-side dielectric material layer embedding a logic-side metal interconnect structure and logic-side metal bonding pads according to an embodiment of the present disclosure.

[0062] Figure 24 According to an embodiment of the present disclosure, after separating the second carrier substrate Figure 22 A vertical cross-sectional view of a bonded assembly of a logic die and a memory die.

[0063] Figure 25 is a vertical cross-sectional view of a bonded assembly after forming backside external bond pads according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0064] As discussed above, the present disclosure relates to three-dimensional memory devices employing double-sided stepped surfaces and methods for fabricating the same, various aspects of which are described below. Embodiments of the present disclosure can be used to form various structures, including multi-level memory structures, non-limiting examples of which include semiconductor devices such as three-dimensional memory array devices comprising multiple NAND memory strings. A memory die incorporating the three-dimensional memory device can be bonded to a logic die to provide a bonded assembly of the memory die and logic die.

[0065] The drawings are not drawn to scale. Where a single instance of an element is shown, multiple instances of the element may be repeated unless explicitly described or otherwise clearly indicated that there is no repetition of the element. Sequence numbers such as "first," "second," and "third" are used only to identify similar elements, and different sequence numbers may be used throughout the specification and claims of this disclosure. The term "at least one" element refers to all possibilities, including the possibility of a single element and the possibility of multiple elements.

[0066] The same reference numerals represent the same or similar elements. Unless otherwise specified, elements with the same reference numerals are assumed to have the same composition and the same function. Unless otherwise specified, "contact" between elements refers to direct contact between elements providing an edge or surface shared by the elements. If two or more elements are not in direct contact with each other, the two elements are "separated" from each other. As used herein, a first element positioned "on" a second element can be positioned on the outside of the surface of the second element or on the inside of the second element. As used herein, if there is physical contact between the surface of the first element and the surface of the second element, the first element is "directly" positioned on the second element. As used herein, if there is a conductive path consisting of at least one conductive material between the first element and the second element, the first element is "electrically connected to" the second element. As used herein, a "prototype" structure or an "in-process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one of its components.

[0067] As used herein, a "layer" refers to a portion of a material that includes an area having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have an extent that is less than the extent of an underlying or overlying structure. Additionally, a layer may be an area of ​​a continuous structure, whether uniform or non-uniform, having a thickness that is less than the thickness of the continuous structure. For example, a layer may be positioned between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above, and / or below.

[0068] A monolithic three-dimensional memory array is a memory array in which multiple memory levels are formed above a single substrate, such as a semiconductor wafer, without an intervening substrate. The term "monolithic" means that the layers of each level of the array are deposited directly on the layers of each lower level of the array. In contrast, two-dimensional arrays can be formed separately and then packaged together to form a non-monolithic memory device. For example, as described in U.S. Patent 5,915,167, entitled "Three-dimensional Structure Memory," a non-monolithic stacked memory is constructed by forming memory levels on separate substrates and vertically stacking the memory levels. The substrate can be thinned or removed from the memory levels before bonding, but because the memory levels are initially formed above separate substrates, such memories are not true monolithic three-dimensional memory arrays.

[0069] Generally speaking, a semiconductor die or a semiconductor package may include a memory chip. Each semiconductor package contains one or more dies (e.g., one, two, or four dies). A die is the smallest unit that can independently execute commands or report status. Each die contains one or more planes (typically one or two faces). Although there are some limitations, the same concurrent operations can occur on each plane. Each plane contains multiple blocks, which are the smallest units that can be erased by a single erase operation. Each block contains multiple pages, which are the smallest units that can be programmed, that is, the smallest units on which a read operation can be performed.

[0070] See also Figure 1 , shows an exemplary structure according to an embodiment of the present disclosure, which can be used, for example, to manufacture a device structure containing a vertical NAND memory device. The exemplary structure includes a substrate 8, which can be a semiconductor substrate such as a single crystal silicon wafer. The substrate 8 can include a semiconductor material layer 10 at least at its upper portion. The semiconductor material layer 10 can include at least one elemental semiconductor material (e.g., a single crystal silicon wafer or layer), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. The semiconductor material layer 10 can have a major surface 7, which can be, for example, a front surface of the semiconductor material layer 10. In one embodiment, the semiconductor material layer 10 can be a single crystal semiconductor layer, such as a single crystal silicon layer deposited on a substrate (e.g., a single crystal silicon wafer) 8 or a doped well in an upper portion of the substrate (e.g., a single crystal silicon wafer) 8. In the case where the substrate 8 is composed of the semiconductor material layer 10, the thickness of the semiconductor material layer 10 can be in the range of 300 microns to 1 mm. Alternatively, if substrate 8 includes at least one additional layer (not shown), such as a combination of a handle substrate and a buried insulating layer in a silicon-on-insulator configuration, semiconductor material layer 10 can be a top silicon layer having a thickness in the range of 50 nm to 2,000 nm. Generally speaking, the thickness of semiconductor material layer 10 can be in the range of 50 nm to 1 mm, although lesser and greater thicknesses can also be employed. In one embodiment, main surface 7 can be a single crystal semiconductor surface, such as a single crystal silicon surface.

[0071] As used herein, "semiconductor material" refers to a material having a -6 S / cm to 1.0×10 5 S / cm. As used herein, "semiconductor material" refers to a material having an electrical conductivity in the range of 1.0×10 -6 S / cm to 1.0×10 5S / cm and can produce materials with electrical conductivity in the range of 1.0 S / cm to 1.0×10 5 S / cm. As used herein, "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the energy band structure, or an n-type dopant that adds electrons to the conduction band within the energy band structure. As used herein, "conductive material" refers to a material having an electrical conductivity greater than 1.0×10 5 As used herein, "insulator material" or "dielectric material" refers to a material having an electrical conductivity of less than 1.0×10 -6 As used herein, a "heavily doped semiconductor material" refers to a material that is doped with electrical dopants at a sufficiently high atomic concentration to become a conductive material when formed into a crystalline material or when converted to a crystalline material by an annealing process (e.g., starting from an initially amorphous state). 5 S / cm). "Doped semiconductor material" may be a heavily doped semiconductor material, or may include a semiconductor material that provides a conductivity of 1.0×10 -6 S / cm to 1.0×10 5 S / cm) in a concentration range of 1000 Å / s. "Intrinsic semiconductor material" refers to a semiconductor material that is not doped with electrical dopants. Thus, a semiconductor material can be semiconducting or conductive, and can be an intrinsic semiconductor material or a doped semiconductor material. Doped semiconductor materials can be semiconducting or conductive, depending on the atomic concentration of the electrical dopant therein. As used herein, "metallic material" refers to a conductive material that includes at least one metal element therein. All conductivity measurements are performed under standard conditions.

[0072] A stack of alternating multiple first material layers (which may be insulating layers 32) and second material layers (which may be sacrificial material layers 42) is formed over the top surface of substrate 8. As used herein, "material layer" refers to a layer comprising material throughout its entirety. As used herein, alternating multiple first elements and second elements refers to a structure in which instances of the first element and instances of the second element alternate. Each instance of a first element that is not an end element of the alternating multiple elements is adjacent to two instances of the second element on both sides, and each instance of a second element that is not an end element of the alternating multiple elements is adjacent to two instances of the first element on both ends. The first elements may have the same thickness therebetween, or may have different thicknesses. The second elements may have the same thickness therebetween, or may have different thicknesses. The alternating multiple first material layers and second material layers may start with an instance of the first material layer or an instance of the second material layer, and may end with an instance of the first material layer or an instance of the second material layer. In one embodiment, the instances of the first element and the second element may form a unit that repeats periodically within the alternating multiple elements.

[0073] Each first material layer includes a first material, and each second material layer includes a second material different from the first material. In one embodiment, each first material layer may be an insulating layer 32, and each second material layer may be a sacrificial material layer. In this case, the stack may include a plurality of alternating insulating layers 32 and sacrificial material layers 42, and constitute a prototype stack including alternating layers of insulating layers 32 and sacrificial material layers 42.

[0074] The alternating plurality of stacks is referred to herein as an alternating stack (32, 42). In one embodiment, the alternating stack (32, 42) may include an insulating layer 32 composed of a first material and a sacrificial material layer 42 composed of a second material, wherein the second material is different from the material of the insulating layer 32. The first material of the insulating layer 32 may be at least one insulating material. Thus, each insulating layer 32 may be a layer of insulating material. Insulating materials that can be used for the insulating layer 32 include, but are not limited to, silicon oxide (including doped silicate glass or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides commonly referred to as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and their silicates, dielectric metal oxynitrides and their silicates, and organic insulating materials. In one embodiment, the first material of the insulating layer 32 may be silicon oxide. The thickness of each insulating layer 32 may be in the range of 10 nm to 60 nm, but smaller and larger thicknesses may also be used.

[0075] The second material of sacrificial material layer 42 is a sacrificial material that is selectively removable relative to the first material of insulating layer 32. As used herein, removal of a first material is "selective" relative to a second material if the removal process removes the first material at a rate at least twice the rate at which the second material is removed. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material relative to the second material.

[0076] The sacrificial material layer 42 may comprise an insulating material, a semiconductor material, or a conductive material. The second material of the sacrificial material layer 42 may subsequently be replaced with a conductive electrode that may serve as, for example, a control gate electrode for a vertical NAND device. Non-limiting examples of the second material include silicon nitride, an amorphous semiconductor material (such as amorphous silicon), and a polycrystalline semiconductor material (such as polycrystalline silicon). In one embodiment, the sacrificial material layer 42 may be a spacer material layer comprising silicon nitride or a semiconductor material comprising at least one of silicon and germanium. The thickness of each sacrificial layer 42 may be in the range of 10 nm to 60 nm, although smaller and larger thicknesses may also be employed.

[0077] In one embodiment, insulating layer 32 may include silicon oxide, and the sacrificial material layer may include a silicon nitride sacrificial material layer. The first material of insulating layer 32 may be deposited, for example, by chemical vapor deposition (CVD). For example, if silicon oxide is used for insulating layer 32, tetraethyl orthosilicate (TEOS) may be used as a precursor material for the CVD process. The second material of sacrificial material layer 42 may be formed, for example, by CVD or atomic layer deposition (ALD).

[0078] The sacrificial material layer 42 can be appropriately patterned so that the conductive material portion subsequently formed by replacing the sacrificial material layer 42 can be used as a conductive electrode, such as a control gate electrode of a subsequently formed single three-dimensional NAND string memory device. The sacrificial material layer 42 can include a portion having a stripe shape extending substantially parallel to the main surface 7 of the substrate.

[0079] According to one aspect of the present disclosure, the alternating stacks of insulating layers 32 and spacer material layers (such as sacrificial material layers 42) include a first stack of a first insulating layer 32A and a first spacer material layer (such as first sacrificial material layer 42A), and a second stack of a second insulating layer 32B and a second spacer material layer (such as second sacrificial material layer 42B), the second stack being further from the substrate 8 than the first stack (32A, 42A). An intermediate insulating layer 32M (which is one of the insulating layers 32) may be disposed between the first stacks (32A, 42A). Generally, the first and second spacer material layers are formed as, or subsequently replaced by, the first and second conductive layers, respectively.

[0080] Although the present disclosure is described using an embodiment in which the spacer material layer is a sacrificial material layer 42 that is subsequently replaced by a conductive layer, embodiments in which the sacrificial material layer is formed as a conductive layer are expressly contemplated herein. In this case, the step of replacing the spacer material layer with the conductive layer can be omitted.

[0081] The total number of first insulating layer 32A and first spacer material layer pairs within the first layer stack (32A, 42A) can be in the range of 2 to 512, such as 4 to 128, but a smaller number or a larger number of first insulating layer 32A and first spacer material layer pairs can be employed within the first layer stack (32A, 42A). The total number of second insulating layer 32B and second spacer material layer pairs within the second layer stack (32B, 42B) can be in the range of 2 to 512, such as 4 to 128, but a smaller number or a larger number of second insulating layer 32B and second spacer material layer pairs can be employed within the second layer stack (32B, 42B). The semiconductor material layer 10 can have a front surface (i.e., a major surface 7) in contact with the proximal planar surface of the alternating stacks (32, 42) and a backside surface located on the opposite side of the front surface. In this application, the interface between the semiconductor material layer 10 and the alternating stack (32, 42) is used as a reference plane for determining the proximity or distance of an element, and therefore, the proximal surface of an element refers to the surface close to the main surface 7, while the distal surface of an element refers to the surface away from the main surface 7.

[0082] refer to Figure 2A and Figure 2B, a portion of the second layer stack (32B, 42B) located in the connection region 300 can be patterned to form a stepped surface, which is referred to herein as a distal stepped surface or a second stepped surface. The connection region 300 can be disposed between a pair of memory array regions 100, which can include a first memory array region 100A and a second memory array region 100B that are laterally spaced apart along a first horizontal direction hd1. The distal stepped surface can be formed within the corresponding region of the rectangular well by depositing a patterned hard mask layer (not shown) including a set of rectangular openings, applying a trimmable etch mask layer including a trimmable etch mask material (e.g., a trimmable photoresist material), and repeatedly performing a set of anisotropic etching processes and mask trimming processes. A stepped cavity having a stepped bottom surface can be formed within each patterned region of the second layer stack (32B, 42B). As used herein, a "stepped surface" refers to a stepped region comprising a set of surfaces including at least two horizontal surfaces and at least two vertical surfaces such that each horizontal surface is adjacent to a first vertical surface extending upward from a first edge of the horizontal surface and is adjacent to a second vertical surface extending downward from a second edge of the horizontal surface. A stepped cavity is formed within the volume, and a portion of the second layer stack (32B, 42B) is removed from the volume by forming the stepped surface. A "stepped cavity" refers to a cavity having a stepped surface located in a stepped region. The stepped region and the stepped cavity are laterally offset along a second horizontal direction hd2 (e.g., a bit line direction) that is perpendicular to the first horizontal direction hd1 (e.g., a word line direction). In one embodiment, adjacent stepped regions offset along the second horizontal direction hd2 may have stepped surfaces that step upward in opposite directions along the first horizontal direction hd1. For example, also in Figure 2B Shown in Figure 2A The stepped area in the lower portion may rise in a stepped manner from left to right along the first horizontal direction hd1, while Figure 2A The stepped region in the upper portion of the first horizontal direction hd1 may rise in steps from right to left (as described below). Figure 5C Adjacent steps and stepped cavities may or may not be laterally offset along the first horizontal direction hd1. Each stepped cavity may extend vertically to the top surface of the middle-level insulating layer 32M.

[0083] Each stepped cavity may have various stepped surfaces such that the horizontal cross-sectional shape of the stepped cavity changes stepwise depending on the vertical distance from the top surface of substrate 8. In one embodiment, the stepped cavity may be formed by repeatedly performing a set of processing steps. The set of processing steps may include, for example, a first type of etching process that vertically increases the cavity depth by one or more steps and a second type of etching process that laterally expands the area to be vertically etched in a subsequent etching process of the first type. As used herein, a "level" of a structure comprising an alternating plurality is defined as the relative positions of a pair of first and second material layers within the structure.

[0084] Each second sacrificial material layer 42B in the second layer stack (32B, 42B) except the topmost second sacrificial material layer 42B extends laterally further than any overlying second sacrificial material layer 42B in the second layer stack (32B, 42B). Each stepped cavity includes a stepped surface of the second layer stack (32B, 42B) that extends continuously from the bottommost layer in the second layer stack (32B, 42B) to the topmost layer in the second layer stack (32B, 42B). Each vertical step of the stepped surface can have the height of one or more pairs of second insulating layers 32B and second sacrificial material layers 42B. In one embodiment, the vertical steps in the distal stepped surface in each stepped cavity can be arranged along a first horizontal direction hd1. Each opening in the patterned hard mask layer defines the lateral extent of each distal stepped surface in a corresponding one of the stepped cavities. The trimmable etch mask layer and the patterned hard mask layer can be removed after the distal stepped surface and the stepped cavity are formed. The stepped surface formed in each stepped cavity includes a distal stepped surface, which is the stepped surface of the second layer stack (32B, 42B). When the distal stepped surface is formed, the lateral extent of the second spacer material layer (such as the second sacrificial material layer 42B) decreases with the vertical distance from the substrate 8. Each overlying second spacer material layer has an area smaller than any underlying second spacer material layer.

[0085] A backward stepped dielectric material portion 265 (i.e., an insulating fill material portion) may be formed in each stepped cavity by depositing a dielectric material therein. For example, a dielectric material such as silicon oxide may be deposited in the stepped cavity. Excess portions of the deposited dielectric material may be removed from above the top surface of the alternating stack (32, 42), for example, by chemical mechanical planarization (CMP). Each remaining portion of the deposited dielectric material filling the stepped cavity constitutes a backward stepped dielectric material portion 265. As used herein, a "backward stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that increases monotonically with respect to the vertical distance from the top surface of the substrate on which the element is located. If silicon oxide is used for the backward stepped dielectric material portion 265, the silicon oxide of the backward stepped dielectric material portion 265 may or may not be doped with a dopant, such as B, P, and / or F.

[0086] Generally speaking, a rearward stepped dielectric material portion 265 can be formed on each set of consecutive distal stepped surfaces. Each rearward stepped dielectric material portion 265 has a variable horizontal cross-sectional area that increases with the vertical distance from the substrate 8. Each rearward stepped dielectric material portion 265 contacts a distal stepped surface (also referred to as a second stepped surface) that has a variable horizontal cross-sectional area that increases with the vertical distance from the substrate 8.

[0087] refer to Figure 3A and Figure 3B A stack of photoresist materials (not shown) including at least a photoresist layer may be formed over the alternating stacks (32, 42) and the backward stepped dielectric material portion 265 and may be photolithographically patterned to form openings therein. The openings include a memory opening 49 formed over the memory array region 100 and optional support openings (not shown for simplicity) in portions of the memory array region 100 and the connection region 300, such that the area not filled by the memory opening 49 includes the support openings. In the case where the spacer material layer includes a sacrificial material layer 42 and a lateral recess is temporarily formed between a pair of vertically adjacent insulating layers 32 during subsequent processing steps, the support openings are employed to form support pillar structures that provide structural support.

[0088] The pattern stack in the photoresist material stack can be transferred through the alternating stacks (32, 42) and the backward stepped dielectric material portion 265 by at least one anisotropic etch using the patterned photoresist material stack as an etch mask. Portions of the alternating stacks (32, 42) below the openings in the patterned photoresist material stack are etched to form memory openings 49 and support openings (not shown). As used herein, "memory opening" refers to a structure in which a memory element, such as a memory stack structure, is subsequently formed. As used herein, "support opening" refers to a structure in which a support structure (such as a support post structure) that mechanically supports other elements is subsequently formed. Memory opening 49 is formed through the entirety of the alternating stacks (32, 42) and the alternating stacks (32, 42) in the memory array area 100. The support opening is formed in an area that does not include memory opening 49 or is laterally separated from the memory opening.

[0089] The memory opening 49 extends vertically through each layer in the alternating stack (32, 42). The support opening may extend vertically through each layer in the alternating stack (32, 42), or may extend through a subset of the layers in the alternating stack (32, 42) and the backward stepped dielectric material portion 265. The chemistry of the anisotropic etching process used to etch the material through the alternating stack (32, 42) may be alternating to optimize etching of the first material and the second material in the alternating stack (32, 42). The anisotropic etching may be, for example, a series of reactive ion etches. The sidewalls of the memory opening 49 and the support opening may be substantially vertical or may be tapered. The patterned photoresist material stack may then be removed, for example, by ashing.

[0090] The memory openings 49 and the support openings can extend from the top surface of the alternating stacks (32, 42) to at least a horizontal plane including the major surface 7 (i.e., the top surface) of the semiconductor material layer 10. In one embodiment, after the top surface of the semiconductor material layer 10 is physically exposed at the bottom of each memory opening 49 and each support opening, an overetch of the semiconductor material layer 10 can be optionally performed. The recess depth can be in the range of, for example, 1 nm to 50 nm, although smaller and larger depths can also be used. Overetching is optional and can be omitted. If overetching is not performed, the bottom surfaces of the memory openings 49 and the support openings can be coplanar with the topmost surface of the semiconductor material layer 10.

[0091] Each of the memory openings 49 and the support openings may include a sidewall (or multiple sidewalls) that extends substantially perpendicular to the topmost surface of the substrate 8 (i.e., the top surface of the semiconductor material layer 10). A two-dimensional array of memory openings 49 may be formed in each memory array region 100. A two-dimensional array of support openings (not shown) may be formed in the connection region 300.

[0092] Figures 4A to 4H shows the structural changes in the storage opening 49, which is Figure 3A and Figure 3B The same structural changes occur simultaneously in each of the other storage openings 49 and each support opening.

[0093] refer to Figure 4A , showing Figure 4A and Figure 4B Memory openings 49 in the exemplary device structure of FIG. Memory openings 49 extend through the alternating stacks (32, 42), the alternating stacks (32, 42), and optionally extend into an upper portion of the semiconductor material layer 10. The bottom surface of each memory opening may be recessed to a depth in the range of 0 nm to 30 nm relative to the top surface of the semiconductor material layer 10, although greater recess depths may also be employed. Optionally, the sacrificial material layer 42 may be partially laterally recessed, for example by isotropic etching, to form a lateral recess (not shown).

[0094] refer to Figure 4B An optional pedestal channel portion (e.g., epitaxial pedestal) 11 may be formed, for example, by selective epitaxy, at the bottom portion of each memory opening 49 and each support opening. Each pedestal channel portion 11 comprises a single crystalline semiconductor material epitaxially aligned with the single crystalline semiconductor material of semiconductor material layer 10. In one embodiment, pedestal channel portion 11 may be doped with an electrical dopant of the same conductivity type as semiconductor material layer 10. In one embodiment, the top surface of each pedestal channel portion 11 may be formed above a horizontal plane including the top surface of sacrificial material layer 42. In this case, at least one source select gate electrode may be subsequently formed by replacing each sacrificial material layer 42 positioned below the horizontal plane including the top surface of pedestal channel portion 11 with a corresponding conductive material layer. Pedestal channel portion 11 may be the portion of the transistor channel extending between a source region to be subsequently formed in substrate 8 and a drain region to be subsequently formed in the upper portion of memory opening 49. A memory cavity 49′ exists in the unfilled portion of memory opening 49 above pedestal channel portion 11. In one embodiment, pedestal channel portion 11 may comprise single crystal silicon. In one embodiment, pedestal channel portion 11 may have a doping of a first conductivity type that is the same conductivity type as the semiconductor material layer 10 that the pedestal channel portion contacts. If semiconductor material layer 10 is not present, pedestal channel portion 11 may be formed directly on semiconductor material layer 10 and may have a doping of the first conductivity type.

[0095] refer to Figure 4CThe layer stack including the blocking dielectric layer 52, the charge storage layer 54, the tunneling dielectric layer 56, and the optional first semiconductor channel layer 601 can be sequentially deposited in the memory opening 49.

[0096] The blocking dielectric layer 52 can include a single dielectric material layer or a stack of multiple dielectric material layers. In one embodiment, the blocking dielectric layer can include a dielectric metal oxide layer consisting essentially of a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material including at least one metallic element and at least oxygen. The dielectric metal oxide can consist essentially of at least one metallic element and oxygen, or can consist essentially of at least one metallic element, oxygen, and at least one non-metallic element such as nitrogen. In one embodiment, the blocking dielectric layer 52 can include a dielectric metal oxide having a dielectric constant greater than 7.9 (i.e., having a dielectric constant greater than that of silicon nitride).

[0097] Non-limiting examples of dielectric metal oxides include aluminum oxide (AI2O3), hafnium oxide (HfO2), lanthanum oxide (LaO2), yttrium oxide (Y2O3), tantalum oxide (Ta2O5), silicates thereof, nitrogen-doped compounds thereof, alloys thereof, and stacks thereof. The dielectric metal oxide layer can be deposited, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), liquid-source misted chemical deposition, or combinations thereof. The thickness of the dielectric metal oxide layer can be in a range from 1 nm to 20 nm, although lesser and greater thicknesses can also be employed. Subsequently, the dielectric metal oxide layer can serve as a dielectric material portion that blocks the stored charge from leaking to the control gate electrode. In one embodiment, the blocking dielectric layer 52 includes aluminum oxide. In one embodiment, the blocking dielectric layer 52 can include multiple dielectric metal oxide layers having different material compositions.

[0098] Alternatively or additionally, the blocking dielectric layer 52 can include a dielectric semiconductor compound such as silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof. In one embodiment, the blocking dielectric layer 52 can include silicon oxide. In this case, the dielectric semiconductor compound of the blocking dielectric layer 52 can be formed by a conformal deposition method such as low pressure chemical vapor deposition, atomic layer deposition, or combinations thereof. The thickness of the dielectric semiconductor compound can be in a range from 1 nm to 20 nm, although lesser and greater thicknesses can also be employed. Alternatively, the blocking dielectric layer 52 can be omitted, and a backside blocking dielectric layer can be formed after forming a lateral recess on the surface of the subsequently to be formed memory film.

[0099] Subsequently, a charge storage layer 54 may be formed. In one embodiment, the charge storage layer 54 may be a continuous layer or patterned discrete portions of a charge trapping material including a dielectric charge trapping material (e.g., which may be silicon nitride). Alternatively, the charge storage layer 54 may include a continuous layer or patterned discrete portions of a conductive material (such as doped polysilicon or a metallic material) that is patterned into a plurality of electrically isolated portions (e.g., floating gates), for example, by being formed as a sacrificial material layer 42 within a lateral recess. In one embodiment, the charge storage layer 54 includes a silicon nitride layer. In one embodiment, the sacrificial material layer 42 and the insulating layer 32 may have vertically coinciding sidewalls, and the charge storage layer 54 may be formed as a single continuous layer.

[0100] In another embodiment, the sacrificial material layer 42 can be laterally recessed relative to the sidewalls of the insulating layer 32, and a combination of a deposition process and an anisotropic etching process can be employed to form the charge storage layer 54 into a plurality of vertically spaced memory material portions. Although the present disclosure is described using an embodiment in which the charge storage layer 54 is a single continuous layer, embodiments are expressly contemplated herein in which the charge storage layer 54 is replaced by a plurality of vertically spaced memory material portions (which can be charge trapping material portions or electrically isolated conductive material portions).

[0101] The charge storage layer 54 can be formed as a single charge storage layer of uniform composition, or can include a stack of multiple charge storage layers. The multiple charge storage layers (if employed) can include multiple spaced-apart floating gate material layers comprising a conductive material (e.g., a metal such as tungsten, molybdenum, tantalum, titanium, platinum, ruthenium, and alloys thereof, or a metal silicide such as tungsten silicide, molybdenum silicide, tantalum silicide, titanium silicide, nickel silicide, cobalt silicide, or a combination thereof) and / or a semiconductor material (e.g., a polycrystalline or amorphous semiconductor material comprising at least one elemental semiconductor element or at least one compound semiconductor material). Alternatively or in addition, the charge storage layer 54 can include an insulating charge trapping material, such as one or more silicon nitride segments. Alternatively, the charge storage layer 54 can include conductive nanoparticles, such as metal nanoparticles, which can be, for example, ruthenium nanoparticles. The charge storage layer 54 can be formed, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or any suitable deposition technique for storing charge therein. The thickness of charge storage layer 54 may be in the range of 2 nm to 20 nm, although lesser and greater thicknesses may also be employed.

[0102] The tunneling dielectric layer 56 comprises a dielectric material through which charge tunneling can be performed under suitable electrical bias conditions. Charge tunneling can be performed by hot carrier injection or by Fowler-Nordheim tunneling induced charge transfer, depending on the operating mode of the single three-dimensional NAND string memory device to be formed. The tunneling dielectric layer 56 may include silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitrides, dielectric metal silicates, alloys thereof, and / or combinations thereof. In one embodiment, the tunneling dielectric layer 56 may include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, which stack is generally referred to as an ONO stack. In one embodiment, the tunneling dielectric layer 56 may include a substantially carbon-free silicon oxide layer or a substantially carbon-free silicon oxynitride layer. The thickness of the tunneling dielectric layer 56 may be in the range of 2 nm to 20 nm, but smaller and larger thicknesses may also be used.

[0103] The optional first semiconductor channel layer 601 comprises a semiconductor material, such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the first semiconductor channel layer 601 comprises amorphous silicon or polycrystalline silicon. The first semiconductor channel layer 601 can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the first semiconductor channel layer 601 can be in the range of 2nm to 10nm, but smaller and larger thicknesses can also be used. The memory cavity 49' is formed in the volume of each memory opening 49 that is not filled with the deposited material layer (52, 54, 56, 601).

[0104] See also Figure 4D , the optional first semiconductor channel layer 601, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52 are sequentially anisotropically etched using at least one anisotropic etching process. Portions of the first semiconductor channel layer 601, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52 positioned above the top surface of the alternating stack (32, 42) can be removed by at least one anisotropic etching process. In addition, horizontal portions of the first semiconductor channel layer 601, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52 at the bottom of each memory cavity 49' can be removed to form openings in the remaining portions thereof. Each of the first semiconductor channel layer 601, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52 can be etched by a corresponding anisotropic etching process using a corresponding etching chemistry, which can be the same or different for the various material layers.

[0105] Each remaining portion of the first semiconductor channel layer 601 may have a tubular configuration. The charge storage layer 54 may include a charge trapping material or a floating gate material. In one embodiment, each charge storage layer 54 may include a vertical stack of charge storage regions that store charge during programming. In one embodiment, the charge storage layer 54 may be a charge storage layer in which each portion adjacent to the sacrificial material layer 42 constitutes a charge storage region.

[0106] The surface of the pedestal channel portion 11 (or the surface of the semiconductor material layer 10 if the pedestal channel portion 11 is not employed) can be physically exposed below the opening through the first semiconductor channel layer 601, the tunneling dielectric layer 56, the charge storage layer 54, and the blocking dielectric layer 52. Optionally, the physically exposed semiconductor surface at the bottom of each memory cavity 49' can be vertically recessed, such that the recessed semiconductor surface below the memory cavity 49' is vertically offset from the topmost surface of the pedestal channel portion 11 (or the semiconductor material layer 10 if the pedestal channel portion 11 is not employed) by a recessed distance. The tunneling dielectric layer 56 is positioned above the charge storage layer 54. The set of blocking dielectric layers 52, charge storage layers 54, and tunneling dielectric layers 56 in the memory opening 49 constitutes a memory film 50, which includes multiple charge storage regions (such as those implemented as charge storage layers 54) insulated from surrounding materials by the blocking dielectric layer 52 and the tunneling dielectric layer 56. In one embodiment, the first semiconductor channel layer 601 , the tunneling dielectric layer 56 , the charge storage layer 54 , and the blocking dielectric layer 52 may have vertically overlapping sidewalls.

[0107] refer to Figure 4E , the second semiconductor channel layer 602 can be deposited directly on the semiconductor surface of the base channel portion 11 or on the semiconductor material layer 10 (if the base channel portion 11 is omitted), and directly on the first semiconductor channel layer 601. The second semiconductor channel layer 602 includes a semiconductor material, such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the second semiconductor channel layer 602 includes amorphous silicon or polycrystalline silicon. The second semiconductor channel layer 602 can be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the second semiconductor channel layer 602 can be in the range of 2nm to 10nm, but smaller and larger thicknesses can also be used. The second semiconductor channel layer 602 can partially fill the memory cavity 49' in each memory opening, or can completely fill the cavity in each memory opening.

[0108] The materials of the first semiconductor channel layer 601 and the second semiconductor channel layer 602 are collectively referred to as semiconductor channel materials. In other words, the semiconductor channel materials are a collection of all semiconductor materials in the first semiconductor channel layer 601 and the second semiconductor channel layer 602.

[0109] refer to Figure 4F In the event that the memory cavity 49' in each memory opening is not completely filled with the second semiconductor channel layer 602, a dielectric core layer 62L may be deposited in the memory cavity 49' to fill any remaining portion of the memory cavity 49' within each memory opening. The dielectric core layer 62L includes a dielectric material such as silicon oxide or organosilicate glass. The dielectric core layer 62L may be deposited by a conformal deposition method such as low-pressure chemical vapor deposition (LPCVD) or by a self-planarizing deposition process such as spin coating.

[0110] refer to Figure 4G , the horizontal portion of the dielectric core layer 62L can be removed, for example, by recess etching from above the top surface of the alternating stack (32, 42). Each remaining portion of the dielectric core layer 62L constitutes the dielectric core 62. In addition, the horizontal portion of the second semiconductor channel layer 602 located above the top surface of the alternating stack (32, 42) can be removed by a planarization process that can employ recess etching or chemical mechanical planarization (CMP). Each remaining portion of the second semiconductor channel layer 602 can be positioned entirely within the memory opening 49 or entirely within the support opening.

[0111] Each adjacent pair of the first semiconductor channel layer 601 and the second semiconductor channel layer 602 can together form a vertical semiconductor channel 60, through which current can flow when the vertical NAND device including the vertical semiconductor channel 60 is turned on. The tunneling dielectric layer 56 is surrounded by the charge storage layer 54 and laterally surrounds a portion of the vertical semiconductor channel 60. Each set of adjacent blocking dielectric layers 52, charge storage layers 54 and tunneling dielectric layers 56 together constitutes a memory film 50 that can store charge for a macroscopic retention time. In some embodiments, the blocking dielectric layer 52 may not be present in the memory film 50 at this step, and the blocking dielectric layer may be subsequently formed after the lateral recess is formed. As used herein, the macroscopic retention time refers to a retention time suitable for the operation of a memory device as a permanent memory device, such as a retention time exceeding 24 hours.

[0112] refer to Figure 4H, the top surface of each dielectric core 62 can be further recessed into each memory opening, for example by recess etching to a depth between the top surface of the alternating stack (32, 42) and the bottom surface of the alternating stack (32, 42). Drain regions 63 can be formed by depositing a doped semiconductor material in each recessed region above the dielectric core 62. The drain regions 63 can have a doping of a second conductivity type opposite to the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. The dopant concentration of the drain regions 63 can be between 5.0×10 19 / cm 3 to 2.0×10 21 / cm 3 The doped semiconductor material may be, for example, doped polysilicon. Excess portions of the deposited semiconductor material may be removed from above the top surface of the alternating stacks (32, 42) by, for example, chemical mechanical planarization (CMP) or recess etching to form drain regions 63.

[0113] Each combination of the memory film 50 and the vertical semiconductor channel 60 within the memory opening 49 constitutes a memory stack structure 55. The memory stack structure 55 is a combination of a semiconductor channel, a tunneling dielectric layer, a plurality of memory elements embodied as part of the charge storage layer 54, and an optional blocking dielectric layer 52. Each combination of the pedestal channel portion 11 (if present), the memory stack structure 55, the dielectric core 62, and the drain region 63 within the memory opening 49 is referred to herein as a memory opening fill structure 58. Each combination of the pedestal channel portion 11 (if present), the memory film 50, the vertical semiconductor channel 60, the dielectric core 62, and the drain region 63 within each support opening fills the corresponding support opening and constitutes a support pillar structure.

[0114] refer to Figures 5A to 5C , shows an exemplary structure after forming a memory opening filling structure 58 and a support pillar structure in the memory opening 49 and the support opening, respectively. Figure 3A and Figure 3B An instance of memory opening fill structure 58 is formed within each memory opening 49 of the structure. Figure 3A and Figure 3B An instance of a support column structure is formed within each support opening of the structure.

[0115] Each memory stack structure 55 includes a vertical semiconductor channel 60, which may include multiple semiconductor channel layers (601, 602) and a memory film 50. The memory film 50 may include a tunneling dielectric layer 56 laterally surrounding the vertical semiconductor channel 60 and a vertical stack of charge storage regions laterally surrounding the tunneling dielectric layer 56 (such as a portion of the charge storage layer 54 located at the level of the sacrificial material layer 42) and an optional blocking dielectric layer 52. Although the present disclosure is described using the configuration for the memory stack structure shown, the methods of the present disclosure can be applied to alternative memory stack structures including different layer stacks or structures for the memory film 50 and / or for the vertical semiconductor channel 60. Generally speaking, each memory opening fill structure 58 includes a memory stack structure 55. Each memory stack structure 55 includes a vertical stack of memory elements, such as a portion of the charge storage layer 54 located at the level of the sacrificial material layer 42.

[0116] refer to Figures 6A to 6C A contact-level dielectric layer 80 may be deposited on the distal planar surface of the alternating stacks (32, 42). The contact-level dielectric layer 80 comprises a dielectric material such as undoped silicate glass or doped silicate glass. The thickness of the contact-level dielectric layer 80 may be in the range of 100 nm to 1,000 nm, such as 200 nm to 500 nm, although lesser and greater thicknesses may also be employed.

[0117] The first carrier substrate 500 can be attached to the physically exposed surface (i.e., the distal surface) of the contact level dielectric layer 80. The first carrier substrate 500 can have a thickness in the range of 300 microns to 1 mm and include a material that can provide structural support for the alternating stack (32, 42) and the substrate 8 during subsequent thinning of the back side of the substrate 8. The first carrier substrate 500 can include a semiconductor (e.g., silicon) substrate, an insulating (e.g., glass or plastic) substrate, or a conductive substrate. In the case where the first carrier substrate 500 includes a silicon substrate, the bonding between the contact level dielectric layer 80 and the first carrier substrate 500 can include, for example, a silicon oxide-silicon bonding. In some embodiments, a temporary adhesive layer (not shown) can be employed to bond the contact level dielectric layer 80 and the first carrier substrate 500. In some embodiments, the first carrier substrate 500 may include a microchannel network having a width in the range of 100 nm to 1,000 nm and a depth in the range of 100 nm to 1,000 nm and an inter-channel spacing in the range of 300 nm to 3,000 nm, and a sacrificial high etch rate silicon oxide material, such as borosilicate glass, may be deposited on the bonding surface of the first carrier substrate 500 to facilitate bonding with the contact level dielectric layer 80 and subsequent separation of the first carrier substrate 500.

[0118] The substrate 8 can be thinned from the back side. The thinning of the back side of the substrate can be performed using various methods. For example, grinding, polishing, anisotropic etching processes, isotropic etching processes, or a combination thereof can be used to remove the back side portion of the substrate 8. In some embodiments, the bottom portion of the substrate 8 can be cut away. During the back side thinning of the semiconductor material layer 10, the first carrier substrate 500 provides structural support for the alternating stacks (32, 42) and the semiconductor material layer 10. After the thinning process, the thickness of the semiconductor material layer 10 can be in the range of 100 nm to 3,000 nm, such as 200 nm to 1,000 nm, but smaller and larger thicknesses can also be used.

[0119] refer to 7A to 7C A photoresist layer (not shown) may be applied to the backside surface of the semiconductor material layer 10 and may be photolithographically patterned to cover the memory array region 100 but not the connection region 300. An etching process, such as an anisotropic etching process, may be performed to remove unmasked portions of the semiconductor material layer 10 from the connection region 300. The etching process may be selective to the material of the insulating layer 32. Thus, the nearest insulating layer 32 is in contact with the semiconductor material layer 10. Generally speaking, an opening 302 may be formed through the semiconductor material layer 10 within each connection region 300, which may be disposed, for example, between a pair of memory array regions 100 laterally spaced apart along the first horizontal direction hd1. The opening 302 may be formed through the semiconductor material layer 10 after thinning the semiconductor material layer 10. A first portion of the proximal surface of the alternating stacks (32, 42) located within the area of ​​the opening 302 located in the connection area 300 can be physically exposed, and a second portion of the proximal surface of the alternating stacks (32, 42) located outside the area of ​​the opening 302 contacts the major surface of the semiconductor material layer 10, which is the front surface of the semiconductor material layer 10. The front surface (i.e., major surface) of the semiconductor material layer 10 contacts the proximal planar surface of the alternating stacks (32, 42). The physically exposed back side of the semiconductor material layer 10 can be located on the opposite side of the front side of the semiconductor material layer 10.

[0120] refer to Figures 8A to 8C, an optional patterned hard mask layer 271 can be formed over a first portion of the proximal surface of the alternating stacks (32, 42), the sidewalls of the semiconductor material layer 10, and the backside surface of the semiconductor material layer 10. The patterned hard mask layer 271 includes a stack or patterned film of an etch mask material such as a dielectric metal oxide (such as an amorphous aluminum oxide layer), an amorphous carbon or diamond-like carbon, a silicon oxide layer, and a polysilicon layer. The patterned hard mask layer 271 includes openings 304 within the connection region 300, i.e., an area of ​​the first portion of the proximal surface of the alternating stacks (32, 42) located within the region of the opening 302 in the semiconductor material layer 10. Each opening 304 through the patterned hard mask layer 271 is smaller than the area of ​​the connection region 300 or the opening 302. A plurality of openings 304 can be formed through the patterned hard mask layer 271 that are laterally spaced apart along the second horizontal direction hd2. Each opening 304 defines an area in which a set of proximal stepped surfaces are subsequently formed by patterning the first layer stack (32A, 42A). In one embodiment, each opening 304 through the patterned hard mask layer 271 can have a rectangular shape having a pair of longitudinal sidewalls extending laterally along a first horizontal direction hd1 and a pair of lateral sidewalls extending laterally along a second horizontal direction hd2.

[0121] refer to Figures 9A to 9C A trimmable etch mask layer 273 may be applied over the patterned hard mask layer 271 and photolithographically patterned to form openings 306 having edges extending laterally along a second horizontal direction hd2 over respective ones of the openings 304 in the patterned hard mask layer 271. The trimmable etch mask layer 273 comprises an etch mask material that can be controllably trimmed during subsequent processing steps. For example, the trimmable etch mask layer 273 may comprise a photoresist material that provides a slow ash rate. A first anisotropic etching process may be performed to transfer the composite pattern formed by the intersection of the openings 306 in the trimmable etch mask layer 273 and the openings 304 in the patterned hard mask layer 271. Each region where the pair of first insulating layer 32A and the first sacrificial material layer 42A closest to the semiconductor material layer 10 intersect with the openings 306 in the trimmable etch mask layer 273 and the openings 304 in the patterned hard mask layer 271 may be etched by the first anisotropic etching process.

[0122] refer to Figures 10A to 10C, an alternating series of etch mask trimming processes and anisotropic etching processes may be performed to form a set of proximal stepped surfaces (also referred to as first stepped surfaces) within each region of the opening through the patterned hard mask layer 271. Generally, a plurality of masked anisotropic etching processes may be performed. Each masked anisotropic etching process uses a combination of the trimmable etch mask layer 273 and the patterned hard mask layer 271 as an etching mask. In addition to the patterned hard mask layer 271, the trimmable etch mask layer 273 serves as an etching mask for each masked anisotropic etching process. The trimmable etch mask layer 273 is trimmed between each sequentially adjacent pair of masked anisotropic etching processes (i.e., a pair of masked anisotropic etching processes and another masked anisotropic etching process immediately following the masked anisotropic etching processes, without any intervening masked anisotropic etching processes). Multiple masked anisotropic etching processes etch unmasked areas of portions of the first layer stack (32A, 42A) below the opening in the semiconductor material layer 10 in a direction from the substrate (i.e., the semiconductor material layer 10) toward the alternating stack (32, 42), i.e., in a vertical direction from the semiconductor material layer toward the contact-level dielectric layer 80.

[0123] By patterning corresponding portions of the first layer stack (32A, 42A), a set of proximal stepped surfaces is formed within each region of the opening in the patterned hard mask layer 271. Each set of proximal stepped surfaces is located within the region of the opening through the semiconductor material layer 10. A stepped cavity 269 is formed above each set of proximal stepped surfaces. Each set of proximal stepped surfaces may include a proximal horizontal surface of the first insulating layer 32A and sidewalls of the first insulating layer 32A and the first sacrificial material layer 42A. Alternatively, each set of proximal stepped surfaces may include a proximal horizontal surface of the first sacrificial material layer 42A and sidewalls of the first insulating layer 32A and the first sacrificial material layer 42A. In one embodiment, the stepped cavity 269 may overlie the rear stepped dielectric material portion 265 and may have an area overlap with the rear stepped dielectric material portion.

[0124] refer to Figures 11A to 11C The remaining portion of the trimmable etch mask layer 273 can be etched, for example, by ashing or dissolving in an organic solvent. The patterned hard mask layer 271 can be removed by selectively etching the materials of the alternating stacks (32, 42) and the semiconductor material layer 10.

[0125] A dielectric fill material, such as undoped silicate glass or doped silicate glass, can be deposited in the stepped cavities 269 and within each opening 302 through the semiconductor material layer 10. Excess portions of the dielectric fill material located above a horizontal plane including the backside surface of the semiconductor material layer 10 can be removed by a planarization process, such as a chemical mechanical planarization process. The remaining portions of the dielectric fill material filling the openings 302 through the semiconductor material layer 10 and the set of stepped cavities 269 located below the openings constitute upright stepped dielectric material portions 165. Each upright stepped dielectric material portion 165 can have a flat surface located within a horizontal plane including the backside surface of the semiconductor material layer 10 (referred to herein as a substrate-side flat surface). The upright stepped dielectric material portion 165 can contact the proximal stepped surface of the first layer stack (32A, 42A) surrounding each stepped cavity.

[0126] Each upright stepped dielectric material portion 165 can have a uniform horizontal cross-sectional area that is uniform between a horizontal plane including the backside surface of the semiconductor material layer 10 and a horizontal plane including the front surface of the semiconductor material layer 10, and a variable horizontal cross-sectional area that decreases with vertical distance from the horizontal plane including the front surface of the semiconductor material layer 10 toward the distal planar surface of the alternating stack (32, 42) that contacts the contact-level dielectric layer 80. Thus, when viewed in a direction with the semiconductor material layer 10 at the bottom and the contact-level dielectric layer 80 at the top, each upright stepped dielectric material portion 165 can have a vertical cross-sectional profile, wherein the top portion has a smaller width than the bottom portion, and the vertical cross-sectional profile appears to be in an "upright" position to the observer to form a "upright stepped" dielectric material portion 165. In one embodiment, the backside surface of the semiconductor material layer 10 can be located within a horizontal plane including the substrate-side planar surface (also referred to as the backside planar surface) of the upright stepped dielectric material portion 165. Sidewalls of the upright stepped dielectric material portion 165 may contact the semiconductor material layer 10 .

[0127] refer to 12A to 12C A photoresist layer (not shown) may be applied over the backside surface of semiconductor material layer 10 and the substrate-side planar surface of upright stepped dielectric material portion 165 and may be photolithographically patterned to form an array of openings in areas within connection region 300 that do not overlap with backward stepped dielectric material portion 265 and upright stepped dielectric material portion 165. Each opening in the photoresist layer may be formed within an area of ​​each layer in which the alternating stacks (32, 42) are present.

[0128] An anisotropic etching process may be performed to form an array of via cavities extending through the upright stepped dielectric material portion 165, the alternating stacks (32, 42), and the contact level dielectric layer 80. A via cavity is formed that extends vertically to the first carrier substrate 500. The via cavity extends vertically through the alternating stacks (32, 42) and is subsequently used to form a conductive via structure that provides electrical connection between metal interconnect structures to be formed on the proximal side of the alternating stacks (32, 42) and the distal side of the alternating stacks (32, 42), and is therefore referred to herein as a through-stack connection via cavity 283.

[0129] refer to 13A to 13C A conformal dielectric material layer comprising a dielectric material such as silicon oxide can be deposited in the through-stack connecting via cavity 283 and deposited over the backside surface of the semiconductor material layer 10 and the substrate-side planar surface of the upright stepped dielectric material portion 165. An anisotropic etching process can be performed to remove the horizontal portion of the conformal dielectric material layer. Each remaining tubular portion of the conformal dielectric material layer constitutes a tubular dielectric spacer 82. Each tubular dielectric spacer 82 can extend vertically through the upright stepped dielectric material portion 165, the alternating stacks (32, 42) and the contact level dielectric layer 80, and can contact their sidewalls. Each tubular dielectric spacer 82 can have a thickness in the range of 5 nm to 100 nm between the inner cylindrical sidewall and the outer cylindrical sidewall, but smaller and larger thicknesses can also be used.

[0130] A sacrificial fill material, such as amorphous silicon or amorphous carbon, can be deposited in the remaining volume of the through-stack connection via cavity 283. Excess portions of the sacrificial fill material can be removed from the horizontal plane of the substrate-side planar surface including the upright stepped dielectric material portion 165 by a planarization process, which can employ a recess etching process and / or a chemical mechanical planarization process. Each remaining portion of the sacrificial fill material located within a corresponding one of the through-stack connection via cavities 283 comprises a sacrificial via structure 287. Each successive combination of the sacrificial via structure 287 and the tubular dielectric spacer 82 constitutes a laterally isolated through-stack connection via structure (287, 82) in the process, which is subsequently modified to form a laterally isolated through-stack connection via structure. Alternatively, a conductive material can be deposited in the remaining volume of the through-stack connection via cavity 283 instead of the sacrificial fill material. In this case, a laterally isolated through-stack connection via structure is formed at this step.

[0131] refer to Figures 14A to 14CA photoresist layer (not shown) may be applied over the backside surface of the semiconductor material layer 10 and the substrate-side planar surface of the upright stepped dielectric material portion 165 and may be photolithographically patterned to form linear openings extending laterally along a horizontal direction connecting the first memory array region 100A and the second memory array region 100B. For example, the linear openings may extend laterally along a first horizontal direction hd1 and have a uniform width along a second horizontal direction hd2. The width of each linear opening along the second horizontal direction hd2 may be greater than the thickness of each sacrificial material layer 42 and may be in the range of twice the thickness of the sacrificial material layer 42 to 60 times the thickness of each sacrificial material layer 42.

[0132] An anisotropic etching process may be performed to etch the semiconductor material layer 10, the upright stepped dielectric material portions 165, and the unmasked portions of the alternating stacks (32, 42). Line trenches 79 may be formed that extend laterally along a first horizontal direction hd1. Each line trench 79 may extend vertically at least to a proximal horizontal surface of the contact-level dielectric layer 80 and may extend partially into or through the contact-level dielectric layer 80. The semiconductor material layer 10 is divided into a plurality of semiconductor material layers 10 that are laterally spaced apart along a second horizontal direction hd2 within each memory array region 100. The alternating stacks (32, 42) are divided into a plurality of alternating stacks (32, 42) located between corresponding adjacent pairs of line trenches 79. The upright stepped dielectric material portions 165 may be divided into a plurality of upright stepped dielectric material portions 165. Each upstanding stepped dielectric material portion 165 may be located between an adjacent pair of linear trenches 79 and may include a corresponding set of stepped surfaces that contact a set of proximal stepped surfaces of the alternating stacks ( 32 , 42 ) separated by the linear trenches 79 .

[0133] Each alternating stack (32, 42) can extend laterally between the first memory array region 100A and the second memory array region 100B and can include a narrow connection region 200 adjacent to the upright stepped dielectric material portion 165. Each connection region 200 of the alternating stack (32, 42) has a width that is the distance between an adjacent pair of line trenches 79 minus the width of the upright stepped dielectric material portion 165. Each alternating stack (32, 42) can include a first insulating layer 32A (which is formed in the 13A to 13C The patterned portion of the first insulating layer 32A in the processing step of 13A to 13C The corresponding first layer stack of the first sacrificial material layer 42A in the processing step of 13A to 13C The patterned portion of the second insulating layer 32B in the processing step) and the second sacrificial material layer 42B (which are 13A to 13C The corresponding second layer stack of the second sacrificial material layer 42B in the processing step of the present invention and the corresponding middle level insulating layer 32M (which is the patterned portion of the second sacrificial material layer 42B in the processing step of the present invention) ... are formed. 13A to 13C (the patterned portion of the intermediate level insulating layer 32M in the processing step of ).

[0134] In one embodiment, each linear trench 79 can have a tapered vertical cross-sectional profile along the width direction, i.e., along a vertical plane perpendicular to the length direction (such as the first horizontal direction hd1). In this case, the width of each linear trench 79 at the nearest insulating layer 32 (i.e., the first insulating layer 32A in contact with the semiconductor material layer 10) can be greater than the width of each linear trench 79 at the farthest insulating layer 32 (i.e., the second insulating layer 32B in contact with the contact-level dielectric layer 80). In one embodiment, the linear trench 79 can have tapered longitudinal sidewalls. In a vertical cross-sectional view along a vertical plane perpendicular to the first horizontal direction hd1, the taper angle of the tapered longitudinal sidewalls (as measured relative to the vertical direction) can be in the range of 0.2 degrees to 10 degrees, such as 0.5 degrees to 3 degrees, although smaller and larger taper angles can also be employed. The photoresist layer can be removed after the anisotropic etching process.

[0135] refer to Figures 15A to 15C , an etching process may be employed, for example, to introduce an etchant into the line trench 79 that selectively etches the second material of the sacrificial material layer 42 relative to the first material of the insulating layer 32. A lateral recess 43 is formed in the volume from which the sacrificial material layer 42 is removed. The second material of the sacrificial material layer 42 may be removed selectively relative to the first material of the insulating layer 32, the material of the upright stepped dielectric material portion 165, the material of the backward stepped dielectric material portion 265, the semiconductor material of the semiconductor material layer 10, and the material of the outermost layer of the memory film 50. In one embodiment, the sacrificial material layer 42 may include silicon nitride, and the material of the insulating layer 32, the upright stepped dielectric material portion 165, and the backward stepped dielectric material portion 265 may include a silicon oxide material (such as undoped silicate glass or doped silicate glass).

[0136] The etching process that selectively removes the second material from the first material and the outermost layer of the memory film 50 can be a wet etching process using a wet etching solution, or can be a vapor phase (dry) etching process in which the etchant is introduced into the line trench 79 in the vapor phase. For example, if the sacrificial material layer 42 includes silicon nitride, the etching process can be a wet etching process in which the exemplary structure is immersed in a wet etching tank containing phosphoric acid, which selectively etches silicon nitride from silicon oxide, silicon, and various other materials used in the art. The support pillar structure (not shown), the upright stepped dielectric material portion 165, the backward stepped dielectric material portion 265, and the memory opening fill structure 58 provide structural support, while the lateral recess 43 exists within the volume previously occupied by the sacrificial material layer 42.

[0137] Each lateral recess 43 may be a laterally extending cavity having a lateral dimension greater than its vertical extent. In other words, the lateral dimension of each lateral recess 43 may be greater than the height of the lateral recess 43. Multiple lateral recesses 43 may be formed in the volume of the second material from which the sacrificial material layer 42 was removed. In one embodiment, the memory array area 100 may include a single three-dimensional NAND string array having multiple device levels disposed on the semiconductor material layer 10. In this case, each lateral recess 43 may define a space for receiving a corresponding word line of the single three-dimensional NAND string array.

[0138] Each backside recess in the plurality of lateral recesses 43 may extend substantially parallel to the top surface of the substrate 8. The lateral recesses 43 may be vertically bounded by the top surface of the underlying insulating layer 32 and the bottom surface of the overlying insulating layer 32. In one embodiment, each lateral recess 43 may have a uniform height throughout. The lateral recesses 43 include a first lateral recess 43A formed within a volume from which the first sacrificial material layer 42A was removed, and a second lateral recess 43B formed within a volume from which the second sacrificial material layer 42B was removed.

[0139] The optional base channel portion 11 and the physically exposed surface portion of the semiconductor material layer 10 can be converted into a dielectric material portion by thermally converting and / or plasma converting the semiconductor material into a dielectric material. For example, thermal conversion and / or plasma conversion can be used to convert a surface portion of each base channel portion 11 into a tubular dielectric spacer 216. A semiconductor oxide liner (not shown) can be formed on the physically exposed surface of the semiconductor material layer 10. In one embodiment, each tubular dielectric spacer 216 can be topologically homeomorphic to a torus, i.e., substantially annular. As used herein, an element is topologically homeomorphic to a torus if its shape can be continuously stretched without destroying pores or forming new pores into the shape of the torus. The tubular dielectric spacer 216 comprises a dielectric material that includes the same semiconductor element as the base channel portion 11 and additionally includes at least one non-metallic element such as oxygen and / or nitrogen, such that the material of the tubular dielectric spacer 216 is a dielectric material. In one embodiment, the tubular dielectric spacer 216 may include a dielectric oxide, a dielectric nitride, or a dielectric oxynitride of the semiconductor material of the base channel portion 11 .

[0140] refer to 16A to 16C , a backside blocking dielectric layer can optionally be formed by a conformal deposition process. The backside blocking dielectric layer, if present, comprises a dielectric material that serves as part of a control gate dielectric for a control gate subsequently formed in the lateral recess 43. In one embodiment, the backside blocking dielectric layer comprises a dielectric metal oxide layer, such as an aluminum oxide layer. The thickness of the backside blocking dielectric layer can be in the range of 1 nm to 15 nm, such as 2 nm to 6 nm, although smaller and larger thicknesses can also be used.

[0141] A metal barrier layer may be deposited in the lateral recess 43. The metal barrier layer comprises a conductive metal material that may serve as a diffusion barrier and / or adhesion promoting layer for a subsequently deposited metal fill material. The metal barrier layer may comprise a conductive metal nitride material such as TiN, TaN, WN, or a stack thereof, or may comprise a conductive metal carbide material such as TiC, TaC, WC, or a stack thereof. In one embodiment, the metal barrier layer may be deposited by a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the metal barrier layer may be in the range of 2 nm to 8 nm, such as 3 nm to 6 nm, although smaller and larger thicknesses may also be employed. In one embodiment, the metal barrier layer may consist essentially of a conductive metal nitride such as TiN.

[0142] A metal filler material is deposited in the plurality of lateral recesses 43, on the sidewalls of the at least one linear trench 79, and above the top surface of the contact-level dielectric layer 73 to form a metal filler material layer. The metal filler material can be deposited by a conformal deposition method, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. In one embodiment, the metal filler material layer can be substantially composed of at least one elemental metal. The at least one elemental metal of the metal filler material layer can be selected from, for example, tungsten, cobalt, ruthenium, titanium, and tantalum. In one embodiment, the metal filler material layer can be substantially composed of a single elemental metal. In one embodiment, the metal filler material layer can be deposited using a fluorine-containing precursor gas such as WF6. In one embodiment, the metal filler material layer can be a tungsten layer including residual hierarchical fluorine atoms as impurities. The metal filler material layer is separated from the insulating layer 32 and the memory opening filling structure 58 by a metal barrier layer, which is a metal barrier layer that prevents fluorine atoms from diffusing therethrough.

[0143] A plurality of conductive layers 46 may be formed in the plurality of lateral recesses 43, and a continuous metal material layer may be formed on the sidewalls of each linear trench 79 and over the contact-level dielectric layer 73. Each conductive layer 46 includes a portion of a metal barrier layer and a portion of a metal filler layer located between a pair of vertically adjacent dielectric material layers, such as a pair of insulating layers 32. The continuous metal material layer includes a continuous portion of the metal barrier layer and a continuous portion of the metal filler layer, which are located in the linear trench 79 or over the semiconductor material layer 10 or over the upright stepped dielectric material portion 165.

[0144] For example, the deposited metal material of the continuous conductive material layer is etched back from the sidewalls of each linear trench 79, from above the semiconductor material layer 10, and from above the upright stepped dielectric material portion 165 by isotropic wet etching, anisotropic dry etching, or a combination thereof. Each remaining portion of the deposited metal material in the lateral recess 43 comprises a conductive layer 46. Each conductive layer 46 can be a conductive line structure. Thus, the sacrificial material layer 42 is replaced by the conductive layer 46. The conductive layer 46 includes a first conductive layer 46A formed in the first backside recess 43A and a second conductive layer 46B formed in the second backside recess 43B.

[0145] Each conductive layer 46 can function as a combination of a plurality of control gate electrodes located at a same level and word lines electrically interconnected (i.e., electrically shorted) to the plurality of control gate electrodes located at the same level. The plurality of control gate electrodes within each conductive layer 46 are control gate electrodes for vertical memory devices including the memory stack structures 55. In other words, each conductive layer 46 can be a word line functioning as a common control gate electrode for a plurality of vertical memory devices. Further, one or more uppermost conductive layers 46 can function as source-side select gate electrodes, and one or more lowermost conductive layers 46 can function as drain-side select gate electrodes.

[0146] Referring to 17A to 17C , a dielectric fill material such as an undoped silicate glass or a doped silicate glass can be deposited in the line trenches 79 and over the semiconductor material layers 10 and the vertical stepped dielectric material portions 165. Excess portions of the dielectric fill material can be removed from above the horizontal plane including the backside surfaces of the semiconductor material layers 10. Each remaining portion of the dielectric fill material filling the line trenches 79 comprises a dielectric line trench fill structure 76. A top surface (i.e., a substrate side planar surface) of the dielectric line trench fill structure 76 can be located within the horizontal plane including the backside surfaces of the semiconductor material layers 10. The substrate side planar surface of each dielectric line trench fill structure 76 can have a greater width than the interconnect side planar surface of the dielectric line trench fill structure 76 contacting the first carrier substrate 500. Alternatively, a conductive source local interconnect surrounded by a dielectric spacer can be formed in each line trench 79 instead of a dielectric line trench fill structure 76.

[0147] Referring to 18A to 18C , a photoresist layer (not shown) can be applied over the backside surfaces of the semiconductor material layers 10 and the substrate side planar surfaces of the vertical stepped dielectric material portions 165 and can be lithographically patterned to form an array of openings in regions overlying the vertical stepped dielectric material portions 165. In particular, each opening in the photoresist layer can be formed within a region of a horizontal surface within a set of proximal stepped surfaces of a respective first layer stack of the first insulating layers 32A and the first conductive layers 46A. An anisotropic etch process can be performed to etch through unmasked portions of the vertical stepped dielectric material portions 165 and any first insulating layers 32A in contact with the vertical stepped dielectric material portions 165 to form substrate side contact via cavities, which are referred to herein as substrate side contact via cavities. A horizontal surface of the respective first conductive layer 46A can be physically exposed at a bottom of each substrate side contact via cavity.

[0148] A combination of at least one conductive material, such as a metal nitride liner material (e.g., TiN, TaN, and / or WN) and a metal fill material, can be deposited in the substrate-side contact via cavity. Excess portions of the at least one conductive material can be removed from above the horizontal plane of the substrate-side planar surface including the upright stepped dielectric material portion 165 by a planarization process. The planarization process can employ a recess etching process and / or a chemical mechanical planarization process. Each remaining portion of the at least one conductive material filling the substrate-side contact via cavity constitutes a contact via structure, which is referred to herein as a substrate-side contact via structure 286.

[0149] Generally speaking, substrate-side contact via structures 286 can be formed by upright stepped dielectric material portions 165 on the proximal surface of a corresponding one of first conductive layers 46A. In one embodiment, substrate-side end surfaces of substrate-side contact via structures 286 can be located within a horizontal plane including the substrate-side planar surface of upright stepped dielectric material portions 165.

[0150] refer to 19A to 19C , a first backside insulating layer 290 can be deposited over the semiconductor material layer 10 and the upright stepped dielectric material portion 165. The first backside insulating layer 290 includes a dielectric material such as undoped silicate glass or doped silicate glass. A cavity (which may include a line cavity) can be formed through the first backside insulating layer 290 by a combination of a photolithographic patterning step and an anisotropic etching step. Metal interconnect structures such as metal lines can be formed within the cavities in the first backside insulating layer 290. The metal interconnect structures embedded within the first backside insulating layer 290 are referred to herein as substrate-side metal interconnect structures 296. The metal lines within the substrate-side metal interconnect structures 296 are referred to herein as source-side metal lines.

[0151] The pattern of the substrate-side metal interconnect structures 296 can be selected so that the substrate-side metal interconnect structures 296 provide a lateral conductive path between each substrate-side end surface of the substrate-side contact via structures 286 and the substrate-side end surface of a corresponding one of the sacrificial via structures 287. Although the present disclosure describes an embodiment in which the substrate-side metal interconnect structures 296 are formed as source-side metal lines that contact the substrate-side planar surface of the upright stepped dielectric material portion 165, embodiments are expressly contemplated herein in which multiple backside insulating layers (not shown) are formed and the substrate-side metal interconnect structures 296 are formed as a multilayer structure including metal lines and metal via structures embedded within the multiple backside insulating layers. Generally speaking, a subset of the substrate-side metal interconnect structures 296 can provide a conductive path between the substrate-side end surface of the substrate-side contact via structures 286 and the substrate-side end surface of a corresponding one of the sacrificial via structures 287. In one embodiment, each substrate-side metal interconnect structure 296 can electrically connect a corresponding substrate-side contact via structure 286 to its corresponding sacrificial via structure 287, which is located on a side of the corresponding wire trench 79 opposite the corresponding substrate-side contact via structure 286. Thus, the substrate-side metal interconnect structure 296 can extend over the corresponding wire trench 79 filled with the corresponding dielectric wire trench filling structure 76.

[0152] refer to Figure 20, additional backside insulating layers, such as a second backside insulating layer 292, may be deposited on the first backside insulating layer 290. The collection of all backside insulating layers is referred to herein as at least one backside insulating layer (290, 292), or when viewed together, as backside insulating layers (290, 292). Subsequently, a second carrier substrate 600 may be attached to the physically exposed flat surface of the at least one backside insulating layer (290, 292). The second carrier substrate 600 may have a thickness in the range of 300 microns to 1 mm and include a material that can provide structural support for the alternating stacks (32, 46) during subsequent processing steps. The second carrier substrate 600 may include a semiconductor (e.g., silicon) substrate, an insulating (e.g., glass or plastic) substrate, or a conductive substrate. In the case where the second carrier substrate 600 includes a silicon substrate, the bond between the at least one backside insulating layer (290, 292) and the second carrier substrate 600 may include, for example, a silicon oxide-silicon bond. In some embodiments, a temporary adhesive layer (not shown) can be employed to bond the at least one backside insulating layer (290, 292) and the second carrier substrate 600. In some embodiments, the second carrier substrate 600 can include a microchannel network having a width in the range of 100 nm to 1,000 nm and a depth in the range of 100 nm to 1,000 nm and an inter-channel spacing in the range of 300 nm to 3,000 nm, and a sacrificial high etch rate silicon oxide material, such as borosilicate glass, can be deposited on the bonding surface of the second carrier substrate 600 to facilitate bonding to the at least one backside insulating layer (290, 292) and subsequent separation of the second carrier substrate 600. The first carrier substrate 500 can then be separated from the contact level dielectric layer 80 by performing an appropriate separation process, which can include mechanical separation, an isotropic etching process, thermal annealing, and / or by irradiation with appropriate light (such as ultraviolet irradiation).

[0153] refer to Figure 21 , the exemplary structure can be flipped so that the contact level dielectric layer 80 faces upward, that is, in an inverted orientation. A selective etching process that etches the material of the sacrificial via structure (if present) 287 can be performed to remove the sacrificial via structure 287. The selective etching process etches the material of the sacrificial via structure 287, which is selective to the material of the contact level dielectric layer 80, the tubular dielectric spacer 82, and the substrate-side metal interconnect structure 296. For example, a wet etching process can be used. A through-stack via cavity 285 can be formed in the volume from which the sacrificial via structure 287 was removed. Alternatively, if a conductive layer of a laterally isolated through-stack connection via structure is formed in an earlier step instead of the sacrificial via structure 287, the removal step can be omitted.

[0154] A photoresist layer (not shown) can be applied over the contact-level dielectric layer 80 and can be photolithographically patterned to form an array of openings in the area overlying the back-stepped dielectric material portion 265. Specifically, each opening in the photoresist layer can be formed within an area of ​​a horizontal surface within a set of distal stepped surfaces of the corresponding second layer stack of the second insulating layer 32B and the second first conductive layer 46B. An anisotropic etching process can be performed to etch through the unmasked portions of the back-stepped dielectric material portion 265 and any second insulating layer 32B in contact with the back-stepped dielectric material portion 265 to form contact via cavities, which are referred to herein as interconnect-side contact via cavities. The horizontal surface of the corresponding second conductive layer 46B can be physically exposed at the bottom of each interconnect-side contact via cavity 85.

[0155] Another photoresist layer (not shown) can be applied over contact-level dielectric layer 80 and can be photolithographically patterned to form openings in areas overlying drain regions 63. An anisotropic etch process can be performed to form drain contact via cavities 87 over each drain region 63 of memory opening fill structure 58. Alternatively, two or more, or all, cavities (285, 85, 87) can be formed during the same patterning and etching step.

[0156] refer to Figure 22 At least one conductive material, such as a combination of a metal nitride liner material (e.g., TiN, TaN, and / or WN) and a metal fill material, may be deposited in the through-stack via cavity (if present) 285, the interconnect-side contact via cavity 285, and the drain contact via cavity 87. Excess portions of the at least one conductive material may be removed from a horizontal plane above the distal planar surface of the contact-level dielectric layer 80 by a planarization process. The planarization process may employ a recess etching process and / or a chemical mechanical planarization process. Each remaining portion of the at least one conductive material filling the interconnect-side contact via cavity 85 constitutes a contact via structure, referred to herein as an interconnect-side contact via structure 86. Each remaining portion of the at least one conductive material filling the through-stack via cavity 285 constitutes a contact via structure, referred to herein as a connection via structure 288. Each consecutive combination of a connection via structure 288 and a tubular dielectric spacer 82 constitutes a laterally isolated through-stack connection via structure (288, 82). Each remaining portion of the at least one conductive material filling the drain contact via cavity 87 constitutes a contact via structure, which is referred to herein as a drain contact via structure 88 .

[0157] Generally speaking, the interconnect-side contact via structure 86 can be formed by the rear-stepped dielectric material portion 265 on the distal surface of a corresponding one of the second conductive layers 46B. In one embodiment, the interconnect-side end surface (i.e., distal surface) of the interconnect-side contact via structure 86 can be located in a horizontal plane including the distal surface of the contact-level dielectric layer 80.

[0158] Each laterally isolated through-stack connecting via structure (288, 82) extends vertically through each layer within the alternating stacks (32, 46), the upright stepped dielectric material portion 165, and the contact-level dielectric layer 80. The substrate-side end surfaces of the connecting via structures 288 can contact the substrate-side metal interconnect structure 296, which electrically connects the substrate-side contact via structures 286 (and thus the first electrical connection layer 46A) to the corresponding pair of connecting via structures 288. The source-side end surfaces of the laterally isolated through-stack connecting via structures (288, 82) can lie in a horizontal plane that includes the substrate-side end surfaces of the substrate-side contact via structures 286. The interconnect-side end surfaces of the laterally isolated through-stack connecting via structures (288, 82) can lie in a horizontal plane that includes the interconnect-side end surfaces of the interconnect-side contact via structures 86.

[0159] A first line-level dielectric layer 90 may be formed on the contact-level dielectric layer 80, and first line-level metal lines 96 may be formed in the first line-level dielectric layer 90. The first line-level metal lines 96 may include bit lines 96B contacting a corresponding set of drain contact via structures 88, first word line connection metal lines contacting the interconnect-side contact via structures 86, second word line connection metal lines contacting the connection via structures 288, and additional metal lines.

[0160] A first via-level dielectric layer 110 may be deposited over the first line-level dielectric layer 90, and a first via-level metal via structure 118 may be formed therein. A second line-level dielectric layer 120 may be deposited over the first line-level dielectric layer 110, and a second line-level metal line 128 may be formed therein. A second via-level dielectric layer 130 may be deposited over the second line-level dielectric layer 120, and a second via-level metal via structure 138 may be formed therein. A pad-level dielectric layer 140 may be formed over the second via-level dielectric layer 130, and a memory-side metal bonding pad 148 may be formed therein. The first line-level dielectric layer 90, the first via-level dielectric layer 110, the second line-level dielectric layer 120, the second via-level dielectric layer 130, and the pad-level dielectric layer 140 are collectively referred to herein as the interconnect-level dielectric layers (90, 110, 120, 130, 140). The first line-level metal line 96, the first via-level metal via structure 118, the second line-level metal line 128, and the second via-level metal via structure 138 are collectively referred to herein as the memory-side metal interconnect structure (96, 118, 128, 138). Although the present disclosure describes embodiments employing two layers of metal line structures and two layers of metal via structures embedded within the interconnect-level dielectric layer (90, 110, 120, 130, 140), embodiments employing fewer or greater numbers of metal line levels and metal via levels are expressly contemplated herein.

[0161] Generally, the memory-side metal interconnect structures (96, 118, 128, 138) are electrically connected to the drain region and the conductive layer 46 located within the memory opening fill structure 58. A substrate including a semiconductor material layer 10 is located proximal to the alternating stack of insulating layers 32 and conductive layers 46. Interconnect-level dielectric layers (90, 110, 120, 130, 140) are embedded in the memory-side metal interconnect structures (96, 118, 128, 138) and are located on the opposite side of the substrate relative to the alternating stacks (32, 46). Memory-side metal bonding pads 148 are embedded in the interconnect-level dielectric layer 140 and are electrically connected to the memory-side metal interconnect structures (96, 118, 128, 138). An assembly of a memory die 900 and a second carrier substrate 600 is provided.

[0162] refer to Figure 23, shows a logic die 700 according to an embodiment of the present disclosure. The logic die 700 may include a logic die substrate 708 and a semiconductor device 710 formed thereon. The logic die substrate 708 includes a logic die substrate semiconductor layer 709 at least at an upper portion thereof. A shallow trench isolation structure 720 may be formed in an upper portion of the logic die substrate semiconductor layer 709 to provide electrical isolation from other semiconductor devices. The semiconductor device 710 may include, for example, field effect transistors, which include corresponding transistor active regions 742 (i.e., source and drain regions), channel regions 746, and gate structures 750. The field effect transistors may be arranged in a CMOS configuration. Generally speaking, the semiconductor device 710 may include logic circuitry configured to control the operation of memory elements within the memory stack structure 55 in the memory die 900. Each gate structure 750 may include, for example, a gate dielectric 752, a gate electrode 754, a dielectric gate spacer 756, and a gate cap dielectric 758.

[0163] A dielectric material layer is formed over the semiconductor device, which is referred to herein as a logic-side dielectric material layer 760. The logic-side dielectric material layer 760 may include, for example, a dielectric liner 762 (such as a silicon nitride liner that blocks the diffusion of mobile ions and / or applies appropriate stress to underlying structures), a logic-side interconnect dielectric layer 764 overlying the dielectric liner 762, a silicon nitride layer (e.g., a hydrogen diffusion barrier) 766 overlying the logic-side interconnect dielectric layer 764, and a logic-side bonding pad-level dielectric layer 768.

[0164] The logic side dielectric material layer 760 serves as the substrate for the logic side metal interconnect structure 780, which provides electrical connections between the semiconductor device 710 and the logic side metal bonding pads 792. The logic side metal bonding pads 792 are embedded in the logic side bonding pad level dielectric layer 768. Each dielectric material layer within the logic side interconnect dielectric layer 764 may include any one of doped silicate glass, undoped silicate glass, organosilicate glass, silicon nitride, silicon oxynitride, and a dielectric metal oxide (such as aluminum oxide). In one embodiment, the logic side interconnect dielectric layer 764 may include or be substantially composed of a dielectric material layer having a dielectric constant not exceeding the dielectric constant of undoped silicate glass (silicon oxide) of 3.9. The logic side metal interconnect structure 780 is formed within the dielectric layer stack of the logic side dielectric material layer 760. The logic side metal interconnect structure 780 may include various metal via structures 786 and various metal line structures 788.

[0165] Generally, logic die 700 includes support (ie, driver / peripheral) circuitry configured to control the operation of the three-dimensional memory devices within memory die 900. Logic side metal bond pads 792 may have a mirror image pattern of memory side metal bond pads 148.

[0166] refer to Figure 24 , the logic die 700 can be bonded to the memory die 900. For example, the logic-side metal bond pad 792 can be bonded to a corresponding one of the memory-side metal bond pads 148 by metal-to-metal bonding. In the case where the logic-side bonding pad-level dielectric layer 768 and the pad-level dielectric layer 140 include silicon oxide, oxide-to-oxide bonding can be used in addition to or in place of the metal-to-metal bonding. The second carrier substrate 600 can be separated from the assembly of the memory die 900 and the logic die 700.

[0167] Generally speaking, the logic-side metal bond pad 792 can be bonded to a corresponding one of the memory-side metal bond pads 148. The logic die 700 includes support circuitry configured to control the operation of the three-dimensional memory device within the memory die 900. The support circuitry can include bit line drivers, word line drivers, sense amplifiers, bit line address decoders, word line address decoders, input / output control circuitry, and various other circuits that can be used to control the operation of the three-dimensional memory array in the memory die 900.

[0168] refer to Figure 24 , a backside contact structure can optionally be formed through the backside insulating layer (290, 292). The backside contact structure can include, for example, a source contact metal pad 298, which is formed by electrically contacting the source electrode and / or local interconnect (not shown for clarity) through the backside insulating layer (290, 292). In one embodiment, the source contact metal pad 298 can be formed as a bonding pad, which can be used for C4 bonding or wire bonding.

[0169] Referring to all of the drawings and in accordance with various embodiments of the present disclosure, a semiconductor structure including a memory die 900 is provided. The memory die 900 includes: an alternating stack of insulating layers 32 and electrically conductive layers 46 located above a substrate (e.g., a remaining portion of a substrate 8 including a semiconductor material layer 10); and a memory stack structure 55 extending vertically through the alternating stack (32, 46), wherein: the alternating stack (32, 46) includes a first stack of layers including first insulating layers 32A and first electrically conductive layers 46A and a second stack of layers including second insulating layers 32B and second electrically conductive layers 46B and vertically spaced apart from the substrate by the first alternating stack; the first stack of layers (32A, 46A) includes a first stepped region in which the first electrically conductive layers 46A have respective lateral extents that increase with vertical distance from the substrate to provide a first stepped surface; and the second stack of layers (32B, 46B) includes a second stepped region in which the second electrically conductive layers 46B have respective lateral extents that decrease with vertical distance from the substrate to provide a second stepped surface.

[0170] In one embodiment, the memory die 900 further includes: an upstanding stepped dielectric material portion 165 contacting the first stepped surface and having a first variable horizontal cross-sectional area that decreases with vertical distance from the substrate (such as the semiconductor material layer 10); and a backstepped dielectric material portion 265 contacting the second stepped surface and having a second variable horizontal cross-sectional area that increases with vertical distance from the substrate.

[0171] In one embodiment, the memory die 900 further includes: a substrate-side contact via structure 286 extending vertically through the upstanding stepped dielectric material portion 165 and contacting a proximal surface of a respective one of the first electrically conductive layers 46A; and an interconnect-side contact via structure 86 extending vertically through the backstepped dielectric material portion 265 and contacting a distal surface of a respective one of the second electrically conductive layers 46B.

[0172] In one embodiment, the substrate includes a semiconductor material layer 10 having a front surface in contact with a proximal planar surface of the alternating stack (32, 46) and a backside surface located on an opposite side of the front surface; and the memory die 900 includes a contact-level dielectric layer 80 located on a distal planar surface of the alternating stack (32, 46).

[0173] In one embodiment, the substrate-side end surface of substrate-side contact via structure 286 lies within a horizontal plane that includes the planar surface of upright stepped dielectric material portion 165. In one embodiment, the backside surface of semiconductor material layer 10 lies within a horizontal plane that includes the planar surface of upright stepped dielectric material portion 165; and the sidewalls of upright stepped dielectric material portion 165 contact semiconductor material layer 10. In one embodiment, the interconnect-side end surface of interconnect-side contact via structure 86 lies within a horizontal plane that includes the distal surface of contact-level dielectric layer 80.

[0174] In one embodiment, the memory die 900 further includes: laterally isolated through-stack connecting via structures (82, 288) comprising respective combinations of connecting via structures 288 and tubular dielectric spacers 82 and extending vertically through each layer within the alternating stacks (32, 46); and substrate-side metal interconnect structures 296 electrically connecting respective pairs of one of the substrate-side contact via structures 286 and one of the connecting via structures 288. In one embodiment, each of the substrate-side metal interconnect structures 296 comprises a source-side metal line contacting a planar surface of the upright stepped dielectric material portion 165. In one embodiment, the memory die 900 further includes a backside insulating layer (290, 292) contacting a backside surface of the semiconductor material layer 10 and a planar surface of the upright stepped dielectric material portion 165 and embedding the substrate-side metal interconnect structures 196.

[0175] In one embodiment, the laterally isolated through-stack connecting via structure (82, 288) extends vertically through the contact level dielectric layer 80 and the upright stepped dielectric material portion 165; the source side end surface of the laterally isolated through-stack connecting via structure (82, 288) is located in a horizontal plane including the substrate side end surface of the substrate side contact via structure 286; and the interconnect side end surface of the laterally isolated through-stack connecting via structure (82, 288) is located in a horizontal plane including the interconnect side end surface of the interconnect side contact via structure 86.

[0176] In one embodiment, the memory die 900 further includes an interconnect level dielectric layer (90, 110, 120, 130, 140) embedded with a metal interconnect structure (96, 118, 128, 138) and located on an opposite side of the substrate relative to the alternating stack (32, 46), wherein the metal interconnect structure (96, 118, 128, 138) is electrically connected to the conductive layer 46.

[0177] In one embodiment, the semiconductor structure also includes a logic die 700, which includes logic circuits configured to control the operation of memory elements within the memory stack structure 55 and includes a logic side dielectric material layer 760 embedded in a logic side metal interconnect structure 780 and a logic side metal bonding pad 792, wherein: the memory die 900 includes a memory side metal bonding pad 148 embedded in the interconnect level dielectric layer (90, 110, 120, 130, 140) and electrically connected to the metal interconnect structure (96, 118, 128, 138); and the logic die 700 is bonded to the memory die 900 by a metal-metal bond between the logic side metal bonding pad 792 and the memory side metal bonding pad 148.

[0178] Various embodiments of the present disclosure can be used to provide a three-dimensional memory array including a double-sided stepped surface. The number of conductive layers that can be used for the three-dimensional memory array can be increased and doubled by using a double-sided stepped surface. The increased number of conductive layers can be advantageously used to increase the device density in the three-dimensional memory array. In addition, the area of ​​each stepped region can be reduced by half compared to when the stepped regions are located on the same side of the memory die. Finally, the chip length can also be reduced to improve the fit of the die in the package. Logic circuits for operating the three-dimensional memory array can be provided in the logic die 700, which can be bonded to the memory die 900 by metal-metal bonding or by other suitable bonding methods.

[0179] Although specific preferred embodiments have been mentioned above, it will be understood that the present disclosure is not limited thereto. It will be appreciated by those skilled in the art that various modifications may be made to the disclosed embodiments, and such modifications are intended to fall within the scope of the present disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless expressly stated otherwise, the words "comprising" or "including" contemplate all embodiments in which the words "consisting essentially of" or the words "consisting of" replace the words "comprising" or "including." Where embodiments are shown in the present disclosure that employ specific structures and / or configurations, it will be understood that the present disclosure may be practiced with any other compatible structures and / or configurations that are functionally equivalent, provided that such substitution is not expressly prohibited or otherwise deemed impossible by those skilled in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A semiconductor structure comprising a memory die, the memory die comprising: an alternating stack of insulating and conductive layers, the alternating stack positioned above the substrate; as well as a memory stack structure extending vertically through the alternating stacks, in: The alternating stacks include a first layer stack including a first insulating layer and a first conductive layer, and a second layer stack including a second insulating layer and a second conductive layer and vertically spaced apart from the substrate by the first layer stack; the first layer stack comprising a first stepped region, wherein the first conductive layer has a respective lateral extent that increases with vertical distance from the substrate to provide a first stepped surface; the second layer stack comprising a second stepped region, wherein the second conductive layer has a respective lateral extent that decreases with the vertical distance from the substrate to provide a second stepped surface; an upstanding stepped dielectric material portion contacting the first stepped surface and having a first variable horizontal cross-sectional area that decreases with the vertical distance from the substrate; a rearwardly stepped dielectric material portion, the rearwardly stepped dielectric material portion contacting the second stepped surface, having a second variable horizontal cross-sectional area that increases with the vertical distance from the substrate; a substrate-side contact via structure extending vertically through the upstanding stepped dielectric material portion and contacting a proximal surface of a respective one of the first conductive layers; and an interconnect side contact via structure extending vertically through the rear stepped dielectric material portion and contacting a distal surface of a corresponding one of the second conductive layers; in: The substrate includes a layer of semiconductor material having a front surface in contact with the proximal planar surfaces of the alternating stacks and a backside surface on an opposite side of the front surface; The memory die includes a contact level dielectric layer on a distal planar surface of the alternating stack; The substrate-side end surface of the substrate-side contact via structure is located in a horizontal plane including the flat surface of the upright stepped dielectric material portion; a backside surface of the semiconductor material layer lying within the horizontal plane including the planar surface of the upstanding stepped dielectric material portion; and A sidewall of the upright stepped dielectric material portion contacts the semiconductor material layer. 2 . The semiconductor structure according to claim 1 , wherein an interconnect-side end surface of the interconnect-side contact via structure is located in a horizontal plane including a distal surface of the contact-level dielectric layer.

3. The semiconductor structure of claim 1 , wherein the memory die further comprises: laterally isolated through-stack connecting via structures comprising respective combinations of connecting via structures and tubular dielectric spacers and extending vertically through each layer within the alternating stack; as well as A substrate-side metal interconnect structure electrically connects corresponding pairs of one of the substrate-side contact via structures and one of the connection via structures.

4. The semiconductor structure of claim 3 , wherein each of the substrate-side metal interconnect structures comprises a source-side metal line contacting a planar surface of the upright stepped dielectric material portion, and wherein each memory stack structure comprises a vertical semiconductor channel and a memory film.

5. The semiconductor structure of claim 4, wherein the memory die further comprises a backside insulating layer contacting a backside surface of the semiconductor material layer and the planar surface of the upright stepped dielectric material portion and embedding the substrate-side metal interconnect structure.

6. The semiconductor structure of claim 3, wherein: the laterally isolated through-stack connection via structure extending vertically through the contact level dielectric layer and the upright stepped dielectric material portion; The source-side end surface of the laterally isolated through-stack connection via structure is located in a horizontal plane including the substrate-side end surface of the substrate-side contact via structure; and The interconnect-side end surface of the laterally isolated through-stack connection via structure is located in a horizontal plane including the interconnect-side end surface of the interconnect-side contact via structure.

7. The semiconductor structure of claim 1 , wherein the memory die further comprises an interconnect-level dielectric layer embedded in a metal interconnect structure and located on an opposite side of the substrate relative to the alternating stack, wherein the metal interconnect structure is electrically connected to the conductive layer.

8. The semiconductor structure of claim 7 , further comprising a logic die including logic circuits configured to control operations of memory elements within the memory stack structure and including a logic-side dielectric material layer embedding a logic-side metal interconnect structure and a logic-side metal bonding pad, wherein: The memory die includes a memory-side metal bond pad embedded in the interconnect level dielectric layer and electrically connected to the metal interconnect structure; and The logic die is bonded to the memory die through metal-to-metal bonding between the logic-side metal bond pads and the memory-side metal bond pads.

9. A method of forming a semiconductor structure, comprising: forming an alternating stack of insulating layers and spacer material layers over a substrate including a semiconductor material layer, the alternating stack including a first layer stack of a first insulating layer and a first spacer material layer and a second layer stack of a second insulating layer and a second spacer material layer, the second layer stack being further from the substrate than the first layer stack, and the first spacer material layer and the second spacer material layer being formed as a first conductive layer and a second conductive layer, respectively, or subsequently replaced by the first conductive layer and the second conductive layer, respectively; forming a distal stepped surface by patterning the second layer stack, wherein a lateral extent of the second spacer material layer decreases with vertical distance from the substrate when forming the distal stepped surface; forming a memory stack structure across the alternating stacks, wherein each of the memory stack structures includes a vertical semiconductor channel and a memory film; forming an opening through the layer of semiconductor material; forming a proximal stepped surface by patterning a portion of the first layer stack within the region of the opening through the layer of semiconductor material using a plurality of masked anisotropic etching processes that etches unmasked areas of the portion of the first layer stack in a direction directed from the substrate toward the alternating stack; forming an upstanding stepped dielectric material portion on the proximal stepped surface of the first layer stack; forming a substrate-side contact via structure on a proximal surface of a corresponding one of the first conductive layers through the upright stepped dielectric material portion; forming a rearwardly stepped dielectric material portion on the distal stepped surface, wherein the rearwardly stepped dielectric material portion has a variable horizontal cross-sectional area that increases with vertical distance from the substrate; and After forming the substrate-side contact via structure, forming an interconnect-side contact via structure on a distal surface of a corresponding one of the second conductive layers, the interconnect-side contact via structure passing through the backward stepped dielectric material portion; and wherein the semiconductor structure comprises a memory die; and in: The substrate includes the semiconductor material layer having a front surface in contact with the proximal planar surfaces of the alternating stacks and a backside surface on an opposite side of the front surface; The memory die includes a contact level dielectric layer on a distal planar surface of the alternating stack; The substrate-side end surface of the substrate-side contact via structure is located in a horizontal plane including the flat surface of the upright stepped dielectric material portion; a backside surface of the semiconductor material layer lying within the horizontal plane including the planar surface of the upstanding stepped dielectric material portion; and A sidewall of the upright stepped dielectric material portion contacts the semiconductor material layer.

10. The method according to claim 9, further comprising: forming a contact-level dielectric layer over the alternating stacks after forming the memory stack structure; attaching a carrier substrate to the contact-level dielectric layer; as well as thinning the semiconductor material layer from the back side, wherein the opening through the semiconductor material layer is formed after thinning the semiconductor material layer, wherein a first portion of the proximal surface of the alternating stack located within the area of ​​the opening is physically exposed, and a second portion of the proximal surface of the alternating stack located outside the area of ​​the opening contacts the semiconductor material layer.

11. The method according to claim 10, further comprising: forming a patterned hard mask layer over the first portion of the proximal surface of the alternating stack, the sidewalls of the semiconductor material layer, and the backside surface of the semiconductor layer, wherein the patterned hard mask layer has an opening in the region of the first portion of the proximal surface of the alternating stack; forming a trimmable etch mask layer comprising an edge extending across the opening in the patterned hard mask layer; as well as The plurality of masked anisotropic etching processes are performed, wherein the trimmable etch mask layer is used as an etch mask for each of the masked anisotropic etching processes, and the trimmable etch mask layer is trimmed between each sequentially adjacent pair of masked anisotropic etching processes.

12. The method according to claim 9, further comprising: forming a laterally isolated through-stack connecting via structure comprising a respective combination of a connecting via structure and a tubular dielectric spacer through a portion of the alternating stack in which each layer of the alternating stack is present; as well as A substrate-side metal interconnect structure is formed on the substrate-side contact via structure, wherein each of the connection via structures contacts a corresponding substrate-side metal interconnect structure of the substrate-side metal interconnect structures.

13. The method according to claim 9, further comprising: forming an interconnect-level dielectric layer over the alternating stacks embedded with a metal interconnect structure, wherein the metal interconnect structure is electrically connected to the conductive layer; forming a memory-side metal bond pad embedded in the interconnect level dielectric layer and electrically connected to the metal interconnect structure; providing a logic die including logic circuitry configured to control operation of memory elements within the memory stack structure and including a logic-side dielectric material layer embedding a logic-side metal interconnect structure and a logic-side metal bond pad; as well as The logic die is bonded to the memory die through metal-to-metal bonding between the logic-side metal bond pads and the memory-side metal bond pads.

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