Unique chip identifier leveraging the unclonable characteristics of a resistive memory array on a chip

Abstract

A semiconductor device is disclosed, which includes a plurality of two-terminal resistive switching devices (420), wherein an electrode (322) in contact with a resistive switching layer (324) has a root mean square surface roughness (425, 427) greater than 2 nm, and a correlation coefficient of the intrinsic characteristics of two resistive switching devices is in the range of -0.1 to 0.1. The random physical characteristics of the resistive switching devices on the semiconductor chip can be used to generate unique data for electronic identification of the semiconductor chip, to verify communication with the semiconductor chip or to generate encryption keys.

Description

[0001] Cross - reference to related applications

[0002] This patent application claims the priority benefit of U.S. Provisional Application No. 63 / 005,879, filed on April 6, 2020, entitled "Resistive Random Access Devices, Systems, and Fabrication Techniques", the entire content of which is incorporated herein by reference for all purposes. Technical Field

[0003] The present disclosure generally relates to two - terminal resistive switching memories, and as an exemplary example, uses the stochastic properties of resistive switching devices to uniquely identify chips. Background Art

[0004] Resistive switching memories represent a recent innovation within the field of integrated circuit technology. While various resistive switching memory technologies are in the development stage, the various technical concepts of resistive switching memories have been demonstrated and are in one or more validation stages to prove or disprove related theories or techniques. In the near future, resistive switching memory technologies are expected to show strong evidence of significant advantages over competing technologies in the semiconductor electronics industry.

[0005] Proposals have been made to practically apply resistive switching technology to memory applications of electronic devices. For example, resistive switching elements are generally at least partially theoretically viable alternatives to metal - oxide - semiconductor (MOS) type memory transistors for the electronic storage of digital information. For example, the model of resistive switching memory devices offers some potential technical advantages over non - volatile flash MOS type transistors.

[0006] In view of the above, the assignee of the present disclosure has continued to develop and is committed to the practical application of resistive switching technology. Summary of the Invention

[0007] A simplified summary of the present specification is presented below to provide a basic understanding of certain aspects of the present specification. This summary of the invention is not a broad overview of the present specification. It is not intended to identify the key or main elements of the present specification, nor to describe the scope of any particular embodiment of the present specification or the scope of any claims. Its purpose is to present some concepts of the present specification in a simplified form as a prelude to the specific embodiments presented in the present disclosure.

[0008] Embodiments of the present disclosure provide for generating unique data of resistive switching devices by utilizing the physical properties of the resistive switching devices. This unique data can be used for various purposes related to electronic identification. As an example, data generated by the physical properties of resistive switching devices on a semiconductor chip can be used to form a unique identifier sequence for the semiconductor chip.

[0009] In a further embodiment, the present disclosure provides physical characteristics of resistive switching devices that can have or can be fabricated to have random or substantially random characteristics. Additionally, these physical characteristics can result in different measurable unique characteristics between adjacent resistive switching devices (or other suitable groupings) on an array, between different resistive switching devices on a semiconductor die, between different resistive switching devices on a wafer or multiple wafers, etc., or combinations of the foregoing groupings. Further, physical characteristics are provided that result in consistent measurements of a given resistive switching device or set of devices through multiple measurements at different temperatures or different operating conditions, etc. Thus, the unique data generated through these measurements can be reliably reproduced over multiple measurement cycles under various operating conditions. As disclosed herein, this in turn enables a very low error rate in reproducing a sequence of unique identifiers derived from the resistive switching devices.

[0010] Another embodiment discloses various measurable unique characteristics of resistive switching devices that can be used to generate unique identifier data. Examples include the raw leakage current of a device or set of devices, the raw resistance of the device, the raw switching speed of the device, the raw programming voltage of the device, the differential programming speed of multiple sets of devices, the differential programming voltage of multiple sets of devices, and other examples disclosed herein, or known in the art, or reasonably conveyed to one of ordinary skill in the art through the context provided herein.

[0011] In a still further embodiment, the measurement process used to generate identifier data from resistive switching devices can be made permanent to minimize or avoid errors in regenerating the identifier data. For example, the measurement process that is partially or wholly based on program events of the resistive switching device can include a process to make the program events permanent for the resistive switching device. As an example, after a measurement process that associates identifier data with the program events of the resistive switching device, a programming process applicable to form a one-time programmable resistive switching device can be utilized. Making the resistive switching device one-time programmable is helpful for a longer service life in recalling the identifier data associated with the measurement process under a large temperature range and other conditions (e.g., electromagnetic radiation at x-ray or gamma frequencies) that may interfere with the program events of the resistive switching device, even over multiple read cycles.

[0012] In another embodiment, an electronic device is disclosed that facilitates generating unique (e.g., unique) identifier data for a semiconductor chip after manufacturing. The unique identifier data can be derived through a measurable process associated with the random or substantially random physical characteristics of a resistive switching device fabricated within the semiconductor chip. In some embodiments, the electronic device can facilitate selecting among multiple measurable processes of the resistive switching device to generate the identifier data for the semiconductor chip. In other embodiments, the electronic device can facilitate selecting a subset of the resistive switching devices on the semiconductor chip for the measurable process. In yet another embodiment, for different purposes (including rewritable non-volatile memory, one-time programmable (non-rewritable) memory, or an identifier device for generating the identifier data for the semiconductor chip), the electronic device can facilitate specifying different subsets of an array of resistive switching devices. In still further embodiments, the electronic device can provide a combination of the foregoing processes. By allowing post-manufacturing selection of a portion of the array to generate the identifier data, the identifier data can be opaque even to the manufacturer of the semiconductor chip, thereby providing a high degree of reliability regarding the security of the identifier data for subsequent users (e.g., purchasers, licensees, sublicensees, etc.) and precluding unauthorized access, intrusion, cloning, etc.

[0013] The following description and the drawings set forth certain exemplary aspects of the present specification. However, these aspects merely indicate some of the various ways in which the principles of the present specification can be used. Other advantages and novel features of the present specification will become apparent from the following detailed description of the present specification when considered in conjunction with the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Aspects or features of the present disclosure are described with reference to the accompanying drawings, in which like reference numerals are always used to refer to like elements. In this specification, numerous specific details are set forth to provide a thorough understanding of the present disclosure. However, it should be understood that certain aspects of the present disclosure can be practiced without these specific details or using other methods, components, materials, etc. In other instances, known structures and devices are shown in block diagram form to facilitate describing the present disclosure.

[0015] Figure 1 A block diagram showing an example electronic device in one embodiment that provides control over a process for generating resistive switching (RS) device identifier data;

[0016] Figure 2 Shows an example subset view of an array of RS devices that can be externally controlled by an electronic device in one embodiment; Figure 1 of the electronic device from the external control of the RS device array;

[0017] Figure 3A block diagram showing an exemplary RS device stack structure in a further disclosed embodiment and the surface roughness of the layers in the stack structure;

[0018] Figure 4 A block diagram showing exemplary adjacent RS devices of an array and changes in the surface roughness of the layers in another embodiment;

[0019] Figure 4A A close-up showing exemplary surface roughness between layers of an RS device in a still further embodiment;

[0020] Figure 4B and Figure 4C A block diagram showing an exemplary RS device and filament formation and deformation according to one or more disclosed embodiments;

[0021] Figure 5 A block diagram showing a group of RS devices within a die in an embodiment and an exemplary Hamming distance distribution between multiple dies;

[0022] Figure 6 An exemplary graph showing the cross-correlation of a 256-bit identifier sequence formed by an RS device according to a further disclosed embodiment;

[0023] Figure 7 An exemplary graph showing the bit error rate for multiple read operations at different temperatures according to another embodiment disclosed herein;

[0024] Figure 8 An exemplary graph comparing the entropy metric of identifier data generated by an RS device with an existing benchmark;

[0025] Figure 9 An exemplary schematic diagram showing a group of RS devices for a differential process that helps generate unique identifier bit data in an embodiment;

[0026] Figure 10 An exemplary schematic diagram showing multiple groups of RS devices for a differential process for generating identifier bit data in a further embodiment;

[0027] Figure 11 An exemplary schematic diagram showing multiple groups of RS devices for a differential process for generating identifier bit data in yet another embodiment;

[0028] Figure 12 An exemplary schematic diagram showing multiple groups of RS devices for a differential process for generating identifier bit data according to yet a further embodiment;

[0029] Figure 13 A flowchart showing an exemplary method for generating identifier data through the intrinsic current leakage of an RS device in one or more embodiments;

[0030] Figure 14 and Figure 14A shows a flowchart of an example method for generating identifier data from the physical characteristics of an RS device according to a further embodiment;

[0031] Figure 15 shows a flowchart of an example method for generating an identifier sequence from the intrinsic programming voltage of an RS device in another embodiment;

[0032] Figure 16 and Figure 16A shows a flowchart of an example method for generating identifier data from the programming voltage of an RS device in an alternative or additional embodiment;

[0033] Figure 17 shows a flowchart of an example method for forming identifier data from the intrinsic programming speed of an RS device in a still further embodiment;

[0034] Figure 18 and Figure 18A shows a flowchart of an example method for forming identifier data from the intrinsic RS programming speed in an alternative or additional embodiment;

[0035] Figure 19 shows a flowchart of an example method for generating identifier data from differential program events of multiple sets of RS devices in an embodiment;

[0036] Figure 20 and Figure 20A shows a flowchart of an example method for generating identifier data from differential program events of multiple sets of RS devices in an embodiment;

[0037] Figure 21 and Figure 21A shows a flowchart of an example method for increasing the service life of RS device identifier data using one-time programmable programming;

[0038] Figure 22 shows a block diagram of an example electronic operating environment according to certain embodiments presented herein;

[0039] Figure 23 shows a block diagram of an example computing environment for implementing one or more of the disclosed embodiments of the present disclosure. Detailed Description

[0040] Introduction

[0041] One or more embodiments of the present disclosure utilize the random or substantially random physical characteristics of nanoscale resistive switching devices to generate data. The random characteristics of the resistive switching devices are typically random, and thus this randomness can be utilized to generate data that has little correlation between multiple such devices (e.g., see below Figure 6 ). Thus, this data can be applicable to applications that require unique or distinct identification, such as identification and authorization applications related to a device (e.g., a semiconductor die, also referred to herein as a semiconductor chip, or a semiconductor wafer, one or more groups of dies, one or more groups of wafers, an electronic device including a semiconductor die, etc.). Additionally, highly uncorrelated data can also be used in security applications, such as random number generation, cryptographic key generation applications, etc.

[0042] Furthermore, various embodiments disclose resistive switching device processes for generating high-entropy data sequences that meet or exceed the scientific criteria for randomness (e.g., see below Figure 5 and Figure 8 ) and are comparable to high-quality cryptographic random number sources. Additionally, the switching device processes for generating the data sequences can be selected from the intrinsic resistive switching devices that most closely utilize the nanoscale unclonable physical characteristics of the resistive switching devices (e.g., devices that have not been previously programmed and are the original or initial devices after fabrication). This achieves a high degree of non-correlation between the devices on a die (intra-die), between the dies on a wafer (inter-die), and between the wafers in a manufacturing facility, thereby minimizing the likelihood that the data sequences generated from the resistive switching devices on a single die will repeat with other devices on the same die or with other resistive switching devices on a given wafer or different wafers.

[0043] Even further, the disclosed resistive switching devices can be constructed between the electromagnetic-impermeable metal lines of a semiconductor die (e.g., between back-end wiring structures that are opaque to a significant portion of the electromagnetic imaging spectrum, visible light, ultraviolet light, infrared light, etc.), which exacerbates the difficulties associated with illegal side-channel access techniques such as unauthorized device layer microscopy. In one or more additional embodiments, some of the disclosed sequence generation processes can be made permanent through a one-time programmable process, thereby allowing the sequences to be reliably reread over a very large number of read cycles to reliably and accurately reproduce the previously generated data sequences, thereby achieving a very low bit error rate (e.g., see below Figure 7)。In a further embodiment, the disclosed process for generating uncorrelated data sequences can involve processes compatible with the operation of resistive switching devices, thereby allowing a set of resistive switching devices to be selected from any suitable subset of resistive switching devices on the chip after fabrication. Systems and methods are also provided to output control of the selection of resistive switching devices, the selection of data sequence processes, and the process configuration related to the generation of physically unclonable data sequences disclosed herein to the user of the chip after fabrication. Based on the disclosure herein and the related drawings, various other embodiments will be apparent.

[0044] As used herein, the terms "substantially" and other related terms or terms of degree (e.g., nearly, approximately, essentially, etc.) are intended to have the meaning expressly set forth in connection with their use herein, or the meaning that can be reasonably inferred by one of ordinary skill in the art, or the reasonable variation of a particular quality or quantity that can be understood by one of ordinary skill in the art by reference to the entire specification (including the knowledge of one of ordinary skill in the art and the materials incorporated herein by reference). For example, the term of degree can refer to the reasonable manufacturing tolerances that a manufacturing device can achieve for a particular quality or quantity. Thus, as a specific example without limitation, for an element of a resistive switching device that is explicitly identified as having a dimension of about 50 angstroms (A), the relative term "about" can refer to the reasonable variation of about 50 A that one of ordinary skill in the art would expect the particular dimension of the element to be achievable with commercial manufacturing equipment, industrial manufacturing equipment, laboratory manufacturing equipment, etc., and is not limited to a mathematically precise quantity (or quality). In other examples, the term of degree can refer to a variation of + / -0 - 3%, + / -0 - 5%, or + / -0 - 10% of the explicitly stated value, which is applicable to one of ordinary skill in the art to achieve the stated function or feature of the element disclosed herein. In other examples, the term of degree can refer to any suitable variation in quality or quantity that will be applicable to achieve one or more of the explicitly disclosed functions or features of the disclosed element. Thus, this specification is in no way limited to the specific qualities and quantities disclosed herein, but rather includes all variations of a particular quality or quantity that are reasonably conveyed to one of ordinary skill in the art by the context disclosed herein.

[0045] As the name implies, a two-terminal resistive switching device has two terminals or electrodes. In this document, the terms "electrode" and "terminal" are used interchangeably; furthermore, the two-terminal resistive switching device includes a non-volatile two-terminal memory device and a volatile two-terminal switching device. Generally, the first electrode of the two-terminal resistive switching device is referred to as the "top electrode" (TE), and the second electrode of the two-terminal resistive switching device is referred to as the "bottom electrode" (BE), however, it is understood that the electrodes of the two-terminal resistive switching device can be arranged in any suitable configuration, including a horizontal arrangement where the components of the memory cell are (substantially) side by side rather than overlapping each other. There is generally an intermediate layer, a resistive switching medium (RSM) or a resistive switching layer (RSL), sometimes referred to as a switching layer, between the TE and BE of the two-terminal resistive switching device; however, such a device is not limited to these layers, for example, as disclosed herein, as disclosed in publications incorporated herein by reference, as generally understood and used in the art, or as reasonably conveyed to those skilled in the art by the context provided herein and the publications supplementing or incorporated into the general understanding of the art, one or more barrier layers, adhesion layers, ion-conducting layers, seed layers, particle source layers, etc. can be included between or adjacent to one or more of the TE, BE or intermediate layers consistent with the proper operation of such a device.

[0046] Generally, the composition of the memory cells of each device may vary, with different components, materials or deposition processes being selected to achieve the desired characteristics (e.g., stoichiometric / non-stoichiometric, volatile / non-volatile, on / off current ratio, switching time, read time, memory endurance, program / erase cycles, etc.). An example of a filament-based device can include: a conductive layer, e.g., a metal, metal alloy, metal nitride (e.g., including TiN, TaN, TiW or other suitable metal compounds); an optional interface layer (e.g., a doped p-type (or n-type) silicon (Si)-containing layer (e.g., a p-type or n-type Si-containing layer, p-type or n-type polysilicon, p-type or n-type polycrystalline SiGe, etc.)); a resistive switching layer (RSL); and an active metal-containing layer capable of being ionized. Under appropriate conditions, the active metal-containing layer can provide filament-forming ions to the RSL. In such an embodiment, a conductive filament (e.g., formed by ions) can pass through at least a subset of the RSL to facilitate conductivity, and as an example, the resistance of the filament-based device can be determined by the tunneling resistance between the filament and the conductive layer. A memory cell having such characteristics can be described as a filament-based device.

[0047] For example, the RSL (which can also be referred to as a resistive switching medium (RSM) in the art) can include an undoped amorphous silicon-containing layer, a semiconductor layer with intrinsic properties, stoichiometric or non-stoichiometric silicon nitride (e.g., SiN, Si3N4, SiN x etc.), silicon suboxide (e.g., SiO x, where the value of x is between 0.1 and 2), silicon sub-nitride, metal oxide, metal nitride, non-stoichiometric silicon compound, etc. Other examples of materials suitable for RSL may include Si x Ge y O z (where x, y, and z are positive numbers appropriate respectively), silicon oxide (e.g., SiO N , where N is a positive number appropriate), silicon oxynitride, undoped amorphous Si (a-Si), amorphous SiGe (a-SiGe), TaO B (where B is a positive number appropriate), HfO C (where C is a positive number appropriate), TiO D (where D is a number appropriate), Al2O E (where E is a positive number appropriate), etc., nitride (e.g., AlN, SiN) or their appropriate combinations.

[0048] In some embodiments, the RSL (non-volatile RSL) used as part of a non-volatile memory device may include a relatively large amount (e.g., compared to a volatile selector device) of material holes or defects to trap neutral metal particles (e.g., at low voltages) within the RSL. A large number of holes or defects can facilitate the formation of a thick and stable structure of neutral metal particles. In such a structure, these trapped particles can hold the non-volatile memory device in a low-resistance state without external stimulation (e.g., electric power), thereby enabling non-volatile operation. In other embodiments, the RSL (volatile RSL) for a volatile selector device may have few material holes or defects to trap particles. Due to the presence of a small number of particle-trapping holes / defects, the conductive filaments formed in such an RSL can be very thin (e.g., one to several particles wide, depending on the field strength, particle material, or RSL material, or their appropriate combinations), and are unstable without an appropriate high external stimulation (e.g., electric field, voltage, current, Joule heating, or their appropriate combinations). Additionally, particles with high surface energy and good diffusivity within the RSL can be selected. This results in conductive filaments that can form rapidly in response to appropriate stimulation and are also easily deformable, e.g., in response to an external stimulation reduced to a deformation amount (which may be lower than the formation amount of the external stimulation associated with the formation of volatile conductive filaments, e.g., in response to the current flowing through the selector device; see U.S. Patent No. 9,633,724 B2, the entire content of which is incorporated herein by reference and used for all purposes) below. It should be noted that the volatile RSL and conductive filaments for a selector device may have different electrical characteristics from the conductive filaments and non-volatile RSL of a non-volatile memory device. For example, the selector device RSL may particularly have a higher material resistance and may have a higher on / off current ratio, etc.

[0049] The active metal layer for a filament-based memory cell may particularly include silver (Ag), gold (Au), titanium (Ti), titanium nitride (TiN), or other suitable compounds of titanium, nickel (Ni), copper (Cu), aluminum (Al), chromium (Cr), tantalum (Ta), iron (Fe), manganese (Mn), tungsten (W), vanadium (V), cobalt (Co), platinum (Pt), hafnium (Hf), and palladium (Pd), etc. In some aspects of the present disclosure, other suitable conductive materials and stoichiometric or non-stoichiometric compounds, nitrides, oxides, alloys, mixtures, or combinations thereof or similar materials may be used for the active metal layer. Additionally, in at least one embodiment, non-stoichiometric compounds, for example, non-stoichiometric metal oxides / metal-oxygen or metal nitrides / metal-nitrogen (e.g., AlO x , AlN x , CuO x , CuN x , AgO x , AgN x , etc., where x is a suitable positive number or a numerical range such as 0 < x < 2, 0 < x < 3, 0 < x < 4 or other numerical values / numerical ranges that may have different values for different non-stoichiometric compounds, or other suitable metal compounds may be used for the active metal layer.

[0050] In one or more embodiments, the disclosed filament resistive switching device may include an active metal layer that includes a metal-nitrogen selected from the group consisting of TiN x , TaN x , AlN x , CuN x , WN x , and AgN x , where x is a positive number (or range of numbers) that may vary depending on the metal-nitrogen material. In a further embodiment, the active metal layer may include a metal-oxygen selected from the group consisting of TiO x , TaO x , AlO x , CuO x , WO x , and AgO x , where x is also a positive number (or range of numbers) that may vary depending on the metal-oxygen material. In other embodiments, the active metal layer may include a metal-nitrogen-oxygen selected from the group consisting of TiO a N b , AlO a N b , CuO a N b , WO a N b , and AgOa N b Metal oxynitrogen in a group consisting of, where a and b are appropriate positive numbers / number ranges. The disclosed filament resistive switching device may further include a switching layer, the switching layer comprising a material selected from the group consisting of SiO y , AlN y , TiO y , TaO y , AlO y , CuO y , TiN x , TiN y , TaN x , TaN y , SiO x , SiN y , AlN x , CuN x , CuN y , AgN x , AgN y , TiO x , TaO x , AlO x , CuO x , AgO x and AgO y where x and y are positive numbers (or ranges), and y is greater than x. Various combinations as described above are contemplated and envisioned within the scope of the embodiments of the present invention.

[0051] In one example, the disclosed filament resistive switching device includes: a particle donor layer (e.g., an active metal-containing layer) comprising a stoichiometric or non-stoichiometric metal compound (or mixture); and a resistive switching layer. In an alternative embodiment of this example, the particle donor layer comprises metal-nitrogen: MN x (e.g., AgN x , TiN x , AlN x etc.), the resistive switching layer comprises metal-nitrogen: MN y (e.g., AgO y , TiO y , AlO y etc.), where y and x are positive numbers (or ranges), and in some cases y is greater than x. In an alternative embodiment of this example, the particle donor layer comprises metal-oxygen: MO x , AgO x , TiO x , AlO x etc.), the resistive switching layer comprises metal-oxygen: MO y (e.g., AgO y , TiO y, AlO y etc.), where y and x are positive numbers (or ranges), and in some cases y is greater than x. In another alternative, the metal compound of the particle donor layer is MN x (such as AgN x , TiN x , AlN x etc.), and the resistive switching layer is selected from the group consisting of MO y (for example, AgO y , TiO y , AlO y etc.) and SiO y , where x and y are generally non-stoichiometric values, or vice versa in further embodiments.

[0052] As used herein, variables x, y, a, b, etc., representing values in a compound or mixture or the ratio of one element to another (or others), can have different values (or ranges) applicable to each compound / mixture and are not intended to represent the same or similar values or ratios between compounds. The mixture can refer to non-stoichiometric materials containing free elements (e.g., metal-rich nitrides or oxides (metal oxides / nitrides containing free metal atoms), metal-poor nitrides or oxides (metal oxides / nitrides containing free oxygen / nitrogen atoms)), and other combinations of elements that do not form traditional stoichiometric compounds as understood in the art. Some details related to the embodiments of the present disclosure can be found in the following U.S. patent applications assigned to the assignee of this patent application: U.S. patent application Ser. No. 11 / 875,541 filed on Oct. 19, 2007, and U.S. patent application Ser. No. 12 / 575,921 filed on Oct. 8, 2009; the entire content of each of the above patent applications is incorporated herein by reference for all purposes in addition to patent applications incorporated herein by reference elsewhere.

[0053] It should be understood that the various embodiments herein can utilize various memory cell technologies having different physical characteristics. Such physical characteristics can be associated with one or more manufacturing processes and can have random or substantially random characteristics that reduce or avoid replication or duplication between manufactured memory cells (even if the memory cells are manufactured by the same process). As an example, in one embodiment, one or more layers of the disclosed resistive switching device can have a root mean square (RMS) surface roughness greater than 0.2 nm (e.g., see below Figure 4A), a surface roughness of up to about 10.0 nm. This results in random or near-random variations in layer thickness, including unpredictable variations in the physical characteristics of such devices. In some theoretical models, the RMS surface roughness affects the geometric structure of the resistive switching material layer, resulting in random or substantially random variations in the characteristics of the resistive switching device (e.g., the intrinsic or original (e.g., as manufactured) current conductance, programming voltage, differential programming voltage, programming speed, differential programming speed, and other characteristics disclosed in this specification). As a further example, different resistive switching memory cells and cell technologies can have different discrete programmable resistances, different associated program / erase voltages, and other different characteristics. In one embodiment, a resistive switching memory device produced by a 28 nm lithography process (device size between about 50 nanometers (nm) width and about 130 nm width (e.g., about 100 nm width, about 56 nm width, about 75 nm width, about 128 nm width, etc.)) can be suitable for implementing the random physical characteristics disclosed herein. In other embodiments, a 22 nm lithography process producing device sizes between 40 nm and 100 nm width (e.g., about 44 nm width, about 60 nm width, about 66 nm width, about 88 nm width, etc.) can implement random physical characteristics.

[0054] At the time of manufacture, the disclosed resistive switching devices can have intrinsic physical characteristics resulting from the manufacturing process used to produce the resistive switching devices. These intrinsic physical characteristics can have an inherent random or substantially random nature that varies between resistive switching devices in a group of such devices (e.g., see below Figure 4 , Figure 4A , Figure 4B and Figure 4C ), and can vary between devices on a die and between devices on a wafer or multiple wafers. Thus, a minimal correlation of the intrinsic physical characteristics between devices, dies, wafers, etc. can result in a minimal correlation between the operating processes and the data derived from such processes between devices, dies, wafers, etc. For example, the intrinsic resistance of the resistive switching layer (RSL) can depend at least in part on these uncorrelated physical characteristics and can vary between devices, even for adjacent devices in a single array on a single die (additionally, as previously mentioned, between multiple dies, wafers, etc.). Further, the current flowing through the RSL in the intrinsic unprogrammed state, the programming voltage in the intrinsic unprogrammed state, the programming speed in the intrinsic unprogrammed state, the differential programming voltage / current / speed, etc. in the intrinsic unprogrammed state can vary between resistive switching devices. The processes disclosed herein for forming resistive switching devices and leveraging the random or substantially random physically unclonable characteristics of resistive switching devices can provide excellent uncorrelated data sequences.

[0055] As used herein, terms such as "intrinsic", "as fabricated", "initial", etc. refer to the operation of a resistive switching device on a semiconductor die after fabrication but prior to commercialization. Intrinsic (and similar terms) do not necessarily exclude some or all post-fabrication operations such as quality tests or other verification procedures performed by the manufacturer, or even some pre-commercialization operations not performed by the manufacturer such as tests to ensure the chip meets the manufacturer's quality specifications, chip setup procedures, or configuration procedures (e.g., defining one-time programmable memory or identifier memory in a resistive switching memory array; see below Figure 1 and Figure 2 ). Generally, as used herein, a resistive switching device is in an intrinsic state if it has not received a stimulus (e.g., electrical, thermal, magnetic, or similar stimuli known in the art and suitable combinations thereof, etc.) as described herein or known in the art that is suitable for forming a conductive filament within the resistive switching device and changing the resistive switching device from a resistive state to a conductive state.

[0056] Some embodiments of the present disclosure may employ a bipolar switching device that exhibits a first switching response (e.g., programming to one of a set of programmed states) to an electrical signal of a first polarity and a second switching response (e.g., erasing to an erased state) to an electrical signal of a second polarity. For example, a bipolar switching device is contrasted with a unipolar device that exhibits a first switching response (e.g., programming) and a second switching response (e.g., erasing) in response to electrical signals having the same polarity and different amplitudes.

[0057] In various embodiments, a filament-based resistive switching device may operate in a bipolar manner, exhibiting different responses to external stimuli of different polarities (or directions, energy flow, energy source orientation, etc.). For a volatile filament-based selector device, as an exemplary example, in response to a first polarity stimulus exceeding a first threshold voltage (or a set of voltages), the filament selector device may change from a first resistive state to a second resistive state. Additionally, in response to a second polarity stimulus exceeding a second threshold voltage, the filament selector device may change from the first state to a third state. In some embodiments, the third state may be substantially the same as the first state, having the same or similar measurable unique characteristics (e.g., conductivity, etc.), having the same or similar threshold stimulus magnitudes (although opposite in polarity or direction), etc. In other embodiments, the third state may be different from the second state according to a measurable characteristic (e.g., different conductivity values in response to reverse polarity compared to forward polarity) or according to the threshold stimulus associated with the transition from the first state (e.g., different positive voltage magnitudes required to transition to the second state compared to the negative voltage magnitude required to transition to the third state).

[0058] For the bipolar operation of a non-volatile filament-based memory cell, in response to an appropriate programming voltage applied to the memory cell, a conductive path or filament is formed through the non-volatile RSL. In particular, upon application of the programming voltage, metal ions are generated from the active metal-containing layer and migrate into the non-volatile RSL layer. The metal ions can occupy hole or defect positions within the non-volatile RSL layer. In some embodiments, after removal of the bias voltage, the metal ions become neutral metal particles and are trapped in the holes or defects of the non-volatile RSL layer. When enough particles are trapped, a filament is formed and the memory cell switches from a relatively high-resistance state to a relatively low-resistance state.

[0059] In some disclosed embodiments, the completion of the conductive filament can involve only a small number of particles (e.g., atoms, ions, conductive compounds, etc.) or fewer of the conductive material. As a specific example, in some embodiments, an electrically continuous conductive filament can be established at the boundary of the switching layer by the positions of 1 to 3 atoms, and repositioning of one or more of these atoms may disrupt the electrical continuity. Since the ratio between the completed filaments and the uncompleted filaments is very small, it is very difficult (if not impossible) for an illegal side-channel attempt to read the bits of the memory (e.g., by high-intensity microscopy), because it is very difficult to image such small particles and determine whether their positions are sufficient to establish electrical continuity. Additionally, the disclosed resistive switching device can be formed between the metal lines of a semiconductor chip (e.g., between the back-end wiring layers). The density of the metal wiring layers further hinders the visibility of the resistive switching device, rendering common side-channel techniques ineffective.

[0060] Once the conductive filament is formed, the trapped conductive particles provide a conductive path or filament through the non-volatile RSL layer, and the resistance is typically determined by the tunneling resistance between one or more such particles and the conductive material adjacent to the non-volatile RSL layer. In some resistive switching devices, an erase process can be implemented to at least partially deform the conductive filament, thereby returning the memory cell from the low-resistance state to the high-resistance state. More specifically, upon application of the erase bias voltage, the metal particles trapped in the holes or defects of the non-volatile RSL become mobile ions and migrate back to the active metal layer, or separate within the RSL (or a combination of the foregoing), to disrupt the conductivity of the conductive filament through the RSL layer. In the context of a memory, this state change can be associated with the respective states of binary bits. For an array of multiple memory cells, words, bytes, pages, blocks, etc. of the memory cells can be programmed or erased to represent 0 or 1 of binary information and effectively store the binary information by maintaining these states over time. In various embodiments, multi-level information (e.g., multiple bits) can be stored in such memory cells.

[0061] In the absence of specifying a particular memory cell technology or program / erase voltage for the various aspects and embodiments herein, and as known to those skilled in the art or as made known to those skilled in the art through the context provided herein, these aspects and embodiments are intended to include any suitable memory cell technology and operate with a program / erase voltage appropriate for that technology. It should also be understood that embodiments including alternative memory cell technologies or signal level changes are considered within the scope of the present disclosure where substituting different memory cell technologies requires circuit modifications known to those skilled in the art or requires a change in the operating signal levels known to those skilled in the art.

[0062] As described above, applying a programming voltage (also referred to as a "programming pulse") to one of the electrodes of a two-terminal memory can result in the formation of a conductive filament in an intermediate layer (e.g., RSL). By convention, and as generally described herein, the TE receives the programming pulse and the BE is grounded (or held at a lower voltage or opposite polarity compared to the programming pulse), but this is not intended to limit all embodiments. Instead, applying an "erase pulse" to one of the electrodes (usually a pulse of opposite polarity to the programming pulse or a pulse applied to the opposite electrode as the programming pulse) may disrupt the continuity of the filament, e.g., by driving the metal particles or other materials forming the filament back to the active metal source. The characteristics of the conductive filament and its presence or absence affect the electrical characteristics of the two-terminal memory cell, e.g., when the conductive filament is present, as opposed to when it is absent, the resistance between the two terminals is reduced and / or the conductance between the two terminals is increased.

[0063] After a programming pulse or an erase pulse, a read pulse can be asserted. The amplitude of the read pulse is typically lower than that of the programming pulse or the erase pulse and is generally not sufficient to affect the conductive filament and / or change the state of the two-terminal memory cell. By applying a read pulse to one of the electrodes of the two-terminal memory, when compared to a predetermined threshold current, the measured current (e.g., I on ) can indicate the conductive state of the two-terminal memory cell. The threshold current can be preset based on the expected current values in the different states (e.g., high resistance state current; currents for one or more low resistance states, etc.) of the two-terminal memory device applicable to a given two-terminal memory technology. For example, when a conductive filament has been formed (e.g., in response to applying a programming pulse), the conductance of the cell is greater than otherwise, and the measured current (e.g., I on ) reading in response to the read pulse will be greater. On the other hand, when the conductive filament is removed (e.g., in response to applying an erase pulse), the resistance of the cell is higher because the intermediate layer has a relatively high resistance, and thus the conductance of the cell is lower, and the measured current (e.g., I off) will be lower. Conventionally, when a conductive filament is formed, the memory cell is said to be in the "on state" with high conductivity. When the conductive filament is absent, the memory cell is said to be in the "off state". Memory cells in the on state or off state can be logically mapped to binary values, e.g., "1" and "0". It should be understood that the convention associated with the state of the cell or the associated logical binary mapping used herein is not intended to be restrictive, as other conventions including the opposite convention can be used in conjunction with the disclosed subject matter. The techniques described in detail herein are described and illustrated in connection with single-level cell (SLC) memories, but it should be understood that the disclosed techniques can also be used in multi-level cell (MLC) memories, where a single memory cell can retain a set of measurable distinct states representing multiple bits of information.

[0064] By mapping digital information to the non-volatile resistance states of two-terminal memory cells, digital information can be stored on such devices. An electronic device containing many of these two-terminal memory cells can likewise store a large amount of data. A high-density array is configured to contain as many memory cells as possible within a given chip space area, thereby maximizing the data storage capacity of the memory chip or system-on-chip device.

[0065] Two general conventions are used to form two-terminal memories (e.g., crossbar switch arrays) at the intersections of metal lines within a wafer. The first convention is a 1T1R memory array, where each memory cell is isolated from the electrical effects (e.g., current, including leakage path current) of the surrounding circuitry by an associated transistor. The second convention is a 1TnR memory array (n is a positive number greater than 1), where a group of multiple memory cells is isolated from the electrical effects of the surrounding circuitry by one (or more) transistors. In the 1T1R context, individual memory cells can be configured to have high current suppression between the memory cells, thereby significantly reducing the leakage path current of the 1T1R memory array. In the 1TnR context, many individual memory cells with a high device density in a given amount of silicon space can be connected to a single transistor with a much lower density. Thus, the 1TnR context facilitates a higher bit density of resistive memory cells on a semiconductor chip.

[0066] Overview

[0067] Figure 1A block diagram of an example integrated circuit device 100 of an electronic device in accordance with one or more embodiments of the present disclosure is shown. The integrated circuit device 100 includes an array of RS devices 105. The array of RS devices 105 may include resistive switching devices 110, identifier devices 120, and one-time programmable (OTP) devices 130. In various embodiments, the resistive switching device 110 may include a non-volatile two-terminal resistive switching memory device, a volatile two-terminal resistive switching device, or a combination of a non-volatile two-terminal resistive switching memory device and a volatile two-terminal resistive switching device (e.g., used as a selector device for a non-volatile memory, or independently used as a volatile latch, switch, etc.). In some embodiments, the array of RS devices 105 may include other memory cell technologies, such as phase change memory, oxygen vacancy memory cells, magnetic memory, conductive bridge memory, etc.

[0068] The identifier device 120 may also be referred to herein as a fingerprint memory, a non-clonable memory, a random sequence memory, etc. The identifier device 120 and the OTP device 130 may be memory structures separate from the array of RS devices 105 (e.g., external to the array of RS devices 105 located on a semiconductor chip), or may be at least partially included in the array of RS devices 105 (e.g., one of a set of arrays including the array of RS devices 105, a block of memory in such an array, one or more blocks or a set of pages in the array, or other suitable arrangements). In one or more embodiments, the identifier device 120 and the OTP device 130 may have a fixed size / number of storage cells and may be pre-allocated within the integrated circuit device 100. In other embodiments, the identifier device 120 and the OTP device 130 may have a variable size or a controllable position after manufacturing. For example, the number of storage cells allocated to the identifier device 120 or the OTP device 130 may be dynamically increased or decreased by the controller 160. As an exemplary example, without limitation, the array of RS devices 105 may have a fixed amount of memory (e.g., 65 megabytes, or other suitable value), and a first subset of the fixed amount of memory (e.g., 4 megabytes, or any other suitable value from zero to the fixed amount) may be allocated to the identifier device 120, and a second subset of the fixed amount of memory (e.g., 8 megabytes, or any other suitable value from zero to the fixed amount) may be allocated to the OPT device 130. In this example, if the identifier device 620 is not fully used to generate identifier data sequence data, a portion of the first subset (e.g., 2 megabytes, etc.) may be allocated back to the resistive switch device 110, and if more OTP is needed, a third subset of the resistive switch device 110 (e.g., 4 megabytes or other suitable value) may be allocated from the resistive switch device 110 to the OTP device 130. Any other suitable reallocation that is obvious to those skilled in the art based on their experience in the art or based on the context provided herein is considered to be within the scope of the present disclosure and may also be provided by the controller 160. However, in some embodiments, if the memory has been used for fingerprint recognition (identifier sequence data) or programmed as OTP data, such memory may be prevented from being reallocated back to general memory (or another form of memory).

[0069] Inputs 140 and outputs 150 are also shown in integrated circuit device 100. In some embodiments, input 140 may include data to be stored in resistive switching device 110, identifier device 120, or OTP device 130 (or provide a path for such data). Output 150 may output data stored in resistive switching device 110, identifier device 120, or OTP device 130. In some embodiments, output 150 may output data generated by calculations using data stored in identifier device 120, or, in further embodiments, may output data stored in resistive switching device 110 or OTP device 130 that is generated by such calculations.

[0070] Figure 1 A novel mechanism is provided to output control for generating physically unclonable identifier sequences after fabrication. Using static random access memory (SRAM) to generate identifier sequence data has encountered a rather high bit error rate (BER), ranging from 3% to 15% depending on the implementation. To reduce the BER associated with generating SRAM identifier sequences, complex circuitry is incorporated into the SRAM bits during fabrication. This permanently fixes the SRAM bits that can be used to generate the identifier sequence and further adds significant hardware overhead to the semiconductor die. The disclosed resistive switching device can generate identifier sequence data with an extremely low BER (e.g., see below Figure 7 ). Thus, the embodiments disclosed herein provide circuits and processes for memory operations (e.g., for storing data, reading data, rewriting data, etc.) for resistive switching devices and extend them to generating identifier sequence data. In such embodiments, the resistive switching devices for memory operations, identifier data, or OTP storage do not need to be fixed during fabrication but can be dynamically exposed for selection and reconfiguration after fabrication (e.g., by controller 160).

[0071] In addition to the foregoing, the disclosed resistive switching device has excellent characteristics for generating identifier data sequences. Such characteristics include high entropy, as shown below Figure 6 and Figure 8 to generate random or substantially random numbers, low BER, inherent difficulty in reverse engineering or illegal side-channel data access, and fast sensing times. For example, a bit sequence of 128 or 256 identifier bits (also referred to herein as physically unclonable feature (or PUF) bits) can be formed by 128 or 256 resistive switching devices (as described herein) or 128 or 256 groups of multiple such resistive switching devices (as described herein for generating differential identifier bits). The high randomness in generating the identifier bits minimizes non-random patterns between the sequence bits (multiple resistive switching devices / groups of such devices), thereby reducing or avoiding the false rejection rate. In addition, the high randomness minimizes the non-random patterns within a single die (internal HD; Figure 5Hamming distance values of multiple read operations of the identifier sequence on [identifier], and provide an ideal Gaussian distribution of Hamming distance values between multiple dies of the resistive switching device to increase the safety margin. This can increase the total number of semiconductor chips that can obtain unique identifier sequences of a given number of bits, even with a high safety margin (e.g., defined by the number of unique bits between individual sequences used to identify a single die).

[0072] In one or more embodiments, the operable controller 160 is operable to perform memory operations on the array of RS devices 105. For example, in one embodiment, the operable controller 160 is operable to perform sensing operations related to generating identifier data bits from one (or a group) of the resistive switching devices assigned to the identifier device 120. Examples of sensing operations related to generating identifier bits can include the intrinsic current described in this specification (the intrinsic current of an unprogrammed resistive switching device, also referred to as leakage current), the intrinsic resistance of the resistive switching device, detection of a program event, detection of the speed or timing of a program event, programming voltage, program current, on-state (programmed) resistance, erase voltage or current, delay frequency, parasitic resistance or capacitance, program or erase minimum pulse width, etc. or a suitable combination of the foregoing. In other embodiments, in further embodiments, the operable controller 160 is operable to perform program operations related to generating identifier data bits from one or more of the resistive switching devices assigned to the identifier device 120. Examples of such program operations include intrinsic programming voltage, intrinsic programming speed, intrinsic program current, etc. In other embodiments, the controller 160 can be configured to implement differential operations related to generating identifier bits from multiple resistive switching devices. Differential operations that can be used to generate identifier bits according to aspects of the present disclosure can include differential programming speed, differential intrinsic programming voltage, differential intrinsic (leakage) current, differential intrinsic resistance, differential on-state resistance, differential erase voltage or current, differential delay frequency, differential parasitic resistance or capacitance, differential program or erase minimum pulse width, etc. or a suitable combination of the foregoing (e.g., see below Figures 9 to 12 ).

[0073] In other embodiments, the controller 160 is operable to selectively perform a one-time programmable operation on the selected identifier device 120 to present a permanent identifier bit sequence generated using program events (e.g., intrinsic programming voltage, intrinsic programming speed, differential programming speed, differential programming voltage, etc.). In additional embodiments, as described herein, the controller 160 is operable to establish one or more threshold metrics (e.g., current metric, resistance metric, programming voltage metric, programming speed metric, etc.) to define identifier bit values (e.g., logic levels; "0" bits and "1" bits in a binary context) through sensing operations or program operations performed on the identifier device 120. As an exemplary example, if the operation selected for generating identifier bit data is characterized by an intrinsic leakage current, a current value threshold (or a small range of values) (e.g., 500 nA or any other appropriate value or range) can be selected, and a resistive switching device with a resistance above the current value threshold can be assigned a "1" identifier bit value, and a device below the current value threshold can be assigned a "0" identifier bit value. In other embodiments, a threshold range with a smaller threshold and a larger threshold can be utilized (e.g., a smaller threshold of 400 nA and a larger threshold of 600 nA, or any other appropriate threshold or range of values). In one embodiment, a device with an intrinsic current below 400 nA can be assigned a "0" identifier bit value; a device with an intrinsic current above 600 nA can be assigned a "1" identifier bit value, and devices between 400 nA and 600 nA can be discarded. In one embodiment, a further read operation can use a 500 nA threshold to regenerate the "0" bit value and the "1" bit value. According to embodiments of the present disclosure, using lower and higher initial thresholds can increase the sensing margin and reduce the bit error rate.

[0074] It should be understood that appropriate thresholds or a set of thresholds can be established for other resistive switching device operation characteristics selected for generating identifier bit information. As another (non-limiting) exemplary example, a logic level "0" can be associated with a programming voltage above 2 volts, and a logic level "1" can be associated with a programming voltage below 1.8 volts. As previously mentioned, other appropriate thresholds can be used to define the logic level values of the identifier bits disclosed herein. In some embodiments, when a large number of resistive switching devices are sensed as part of generating identifier bits, threshold voltages, currents, pulse widths, etc. can be selected such that approximately half of the devices are associated with a logic level "0" and the other half are associated with a logic level "1". In some embodiments, the threshold settings can be manually performed by the controller 160; in other embodiments, default threshold settings can be set during the initialization of the semiconductor chip.

[0075] In a further embodiment, the operating characteristics or program events used to generate the identifier bit sequence can be selected to have the same or substantially the same measured values over time, multiple read cycles, and the temperature range common to semiconductor chips. This results in a very low bit error rate for the disclosed identifier bit sequence (e.g., see below Figure 7 ). As an exemplary example, the intrinsic leakage current (or other physically unclonable characteristic) of a resistive switching device measured for the first time at room temperature on day 1 can be measured as the same or substantially the same (e.g., relative to a constant intrinsic leakage current threshold) at 100 degrees Celsius after 1 million read operations five years later. The value of the resistive switching device can be determined according to the requirements of the controller 160. As another exemplary example, to determine the resistance of a resistive switching device, a current source can be applied to the resistive switching device, the voltage drop measured, and the resistance calculated. Other techniques known in the art or reasonably conveyed to those skilled in the art for measuring or determining the physical characteristics of resistive switching devices are considered to be within the scope of the present disclosure.

[0076] In addition to the foregoing, the controller 160 can be configured to define the arrangement or order of resistive switching devices (or multiple sets of resistive switching devices) to create a multi-bit sequence of identifier bits. As an exemplary example, resistive switching devices 0:7 can be read and assigned to bits 0:7 of the bit sequence. In other embodiments, the bit sequence need not be derived from resistive switching devices arranged in a specific order. As an example, devices 15, 90, 7, 21, 50, 2, 37, 19 can be read from sequential rows of resistive switching devices and assigned to bits 0:7 of the output bit string, respectively. The larger bit string can be of any arbitrarily selected length. For example, bit strings of 64 bits, 256 bits, 1024 bits, 64 kilobits, or any other suitable subset of the identifier devices 120 up to all of the identifier devices 120 (which can include all arrays of the RS devices 105 in at least some embodiments) can be used for the bit string. As another non-limiting example, for a 256-bit identifier sequence, the controller 160 can define the order of the identifier devices 120 / multiple sets of identifier devices 120 to correspond to a 256-bit sequence. Then, the controller 160 can sort the identifier bit values (e.g., logic levels, …) generated from the identifier devices 120 / multiple sets of identifier devices 120 in the device order, thereby creating a 256-bit identifier sequence. As a specific example, in the case of selecting a row of 256 resistive switching devices in an array to generate an identifier sequence, the identifier bit values of the 256 resistive switching devices can be arranged in the order of the physical positions of the resistive switching devices in that row; however, this is only an exemplary example, and any other suitable arrangement or order can be implemented by the controller 160 as an alternative or supplement.

[0077] It is apparent from the entire disclosure that any suitable number of bits can be allocated to the identifier bits, and thus the operable controller 160 can be configured to determine which of the identifier bits from the identifier device 120 contribute to the identifier data: 64 bits, 1 kilobit, 64 kilobits, or any other suitable subset of the arrays of the RS devices 105 up to and including all of the arrays of the RS devices 105. In one or more embodiments, the controller 160 can be implemented on the arrays of the RS devices 105 Figures 13 to 21A of methods 1300 to 2100.

[0078] In one or more additional embodiments, the operable controller 160 can be configured to store data in the resistive switching device 110 or the OTP device 130. For example, the controller 160 can receive an input data word to be stored from the input 140. In some embodiments, the controller 160 can combine the input data word with an identifier data sequence stored at / produced by the identifier device 120 to produce an output data word. The output data word can be stored in the resistive switching device 110. Optionally, the input word can be deleted. Subsequently, to recreate the input data, the output data word stored in the resistive switching device 110 can be combined with the identifier data sequence (optionally computed on the fly by the controller 160), and the recreated input data word can be output via the output 150. In various embodiments, such input data words can be passwords, documents, encryption keys, or any other suitable data to be securely stored. Initial randomness tests of the various embodiments for generating identifier data disclosed herein have been successful. In one randomness test, NIST SP800-22, embodiments based on applying a voltage or current drive signal to the identifier device 120 passed all 15 subtests. Similarly, in another randomness test, NIST SP800-90B, similar embodiments based on applying a voltage or current drive signal passed all subtests. In the randomness test, 100 bitstreams were tested using NIST SP 800-90B with a 1 Mb / bitstream and a total of 300 Mb and passed all randomness subtests.

[0079] Figure 2 A block diagram of an example array of resistive switching (RS) devices 205 in accordance with an alternative or additional embodiment of the present disclosure is shown. In one embodiment, the array of RS devices 205 can be substantially similar to the array of RS devices 105 described above. However, the array of RS devices 205 is not limited to the description given above, and in some embodiments, can include other features or functions in addition to or in place of the features or functions described above.

[0080] The array of RS devices 205 can be partitioned into subsets as shown by the optional block 210. Although in Figure 2An example array of the RS device 205 shows various sizes and positions of the optional block 210, but it should be understood that these sizes and positions are merely exemplary. Additionally, the term "block" is not intended to limit the number, position, layout, or spatial orientation of the groups of resistive switching devices that can be assigned to the optional block 210. Instead, the term "block" is only intended to represent an optional grouping of any suitable subset of resistive switching devices within the array of the RS device 205, which depends only on the physical limitations of the circuit layout (if any) that can be created when manufacturing the semiconductor die containing the array of the RS device 205 and the operational access to a group of resistive switching devices. However, in the case of using bit-addressable two-terminal resistive switching devices within the array of the RS device 205, such a limitation does not need to be applied, and in such an embodiment, any suitable selection, grouping, association, etc. of the resistive switching devices can be defined as the optional block 210 by the controller 160. For example, in at least one embodiment, a non-consecutive group of resistive switching devices can be defined as the optional block 210 (e.g., the optional block 210A and the optional block 210B can be defined as a single optional block 210AB), and in another example, a group of resistive switching devices defining a non-rectangular or even irregular-shaped region (e.g., a shapeless region) can be defined as the optional block 210 in other embodiments. A suitable combination of the foregoing can be implemented in other embodiments.

[0081] The controller 160 can receive an input of the selected resistive switching devices (e.g., via the input 140 described above Figure 1 or via another command path not described) to be assigned as a group. The selection can include any suitable number of resistive switching devices, including regular or irregular-shaped groupings, shapeless groupings, consecutive and non-consecutive resistive switching devices, etc., or a suitable combination of the foregoing groupings. Thus, although Figure 2 a rectangular block of the identifier device 120 within the array of the RS device 205 is shown, it should be understood that alternatively, different subsets of the array of the RS device 205 can be defined as being selected as the identifier device 120. Similarly, the controller 160 can receive an input of the selected one-time programmable (OTP) devices 130. Although the grouping of the TOP devices 130 is shown within a rectangular space, similar to the identifier device 120, non-regular, shapeless, non-consecutive groupings of the OTP devices 130 can also be selected and defined as the OTP devices 130 by the controller 160. The controller 160 can also receive a grouping selection for the resistive switching storage devices (e.g., the resistive switching devices 110 described above Figure 1 for one or more optional blocks 210), or include a grouping selection for volatile resistive switching devices for one or more optional blocks 210 during manufacturing.

[0082] In various embodiments, the controller 160 may facilitate defining the optional blocks 210 during a setup procedure prior to post-manufacture operation. In some embodiments, the controller 160 may facilitate defining or redefining the optional blocks after operation of the array of RS devices 205. For example, in one or more embodiments, during the lifespan of a chip or electronic device that includes an array of RS devices 205, and subject to the physical constraints of the resistive switching devices for the array of RS devices 205, the pre-operation grouping of devices that serve as identifier devices 120, OTP devices 130, or resistive switching devices 110 may be modified. Generally, a device programmed for OTP operation to store data as OTP data typically cannot be erased and thus cannot be reused for non-OTP operations. However, this depends on the technical capabilities of the resistive switching devices for the array of RS devices 205; for example, in at least one embodiment, the controller 160 may effect such re-designation in the case where the OTP device can be re-purposed after OTP programming. As disclosed herein, and known in the art or reasonably conveyed to those skilled in the art by the context provided herein, subject to physical limitations, selection commands at the controller 160 may be used to redefine devices as identifier devices 120, OTP devices 130, and resistive switching devices 110 to redefine a subset of the array of RS devices 205 for switching, memory, identifier, or OTP operations.

[0083] Controller 160 helps to define a subset of an array of user-selected RS devices 205 for the identifier device 120. An embodiment further improves the security of the identifier sequence generated by the identifier device 120, making it more difficult to illegally access such an identifier sequence. This is because a fixed set of bits within the array of RS devices 205 used to generate the identifier data does not add additional ambiguity to the physical location containing (or generating) the identifier data. Thus, a hacker attempting to illegally obtain the identifier data can perform an illegal side-channel reading operation on an exact portion of the array of RS devices 205. For example, a high-intensity microscope (e.g., using high-magnification electromagnetic technology, whether visible, infrared, or ultraviolet, to image the physical properties of the identifier bits to see if they are in a programmed or unprogrammed state). Compromising the security of the chip does not even require the chip itself to be successful; some illegal intrusion operations only require the identifier data to impersonate an illegal chip as a chip associated with the identifier data. In this case, the hacker does not even care if a portion of the array of RS devices 205 is physically damaged during the side-channel access process (or even if most of the chip is damaged); as long as the identifier data is accurately extracted, the illegal intrusion is successful. In contrast, when the portion of the resistive-switching device assigned to the identifier device 120 is unknown, the illegal intrusion technique cannot target an exact subset of the bits containing the identifier data. Thus, even the manufacturer layout of the array of fabricated RS devices 205 is not sufficient to determine which bits contain the identifier data; even the chip manufacturer itself does not know this information. Additionally, if some bits of the array of RS devices 205 contain a portion of the identifier data, destroying these bits can effectively destroy the identifier data, thus effectively thwarting an illegal intrusion attempt. Thus, providing the controller 160 with the ability to output selected identifier bits after fabrication, particularly allowing selection of identifier bits of different sizes and different positions within the array of RS devices 205, non-contiguous multiple sets of identifier bits, and even irregularly shaped or shapeless multiple sets of identifier bits significantly increases the difficulty associated with illegally accessing the identifier data generated by the array of RS devices 205 as described herein.

[0084] Figure 3 A block diagram of an exemplary resistive-switching device stack structure 300 in accordance with a further embodiment of the present disclosure is shown. Note that the device stack structure 300 and the elements shown therein (as well as other integrated circuit device diagrams included herein) are not drawn to scale but are only representative examples. The device stack structure 300 includes a substrate 302. The substrate 302 can provide a basis on which an integrated circuit manufacturing process can be implemented to form the physical components of the devices included within the device stack structure 300. In one embodiment, the substrate 302 can be silicon (Si) or a silicon-oxide material (e.g., SiO2,...), but is not limited thereto, and can include any suitable substrate material in other embodiments.

[0085] Each embodiment of the present disclosure may optionally provide Figure 3 One or more layers fabricated on or above the substrate 302 not shown in. Such layers may include layers of integrated circuit devices such as electronic devices, mechanical devices, electromechanical devices, etc. In one or more embodiments, such devices may be formed as part of a front-end manufacturing technology, which may include manufacturing technologies for forming devices within or at least partially within the substrate 302, and the present disclosure is not limited to such embodiments. Additionally, in further embodiments, one or more layers covering the substrate 302 may be formed by back-end manufacturing technologies. Such layers may include metal layers (e.g., metal x-1 layer, x-2 layer... x-n layer, where n is a suitable integer) located below the insulator / dielectric layer 304, dielectric layers, etc. or a suitable combination of the foregoing layers. In one embodiment, according to multi-die bonding techniques known in the art, one or more additional substrates similar to the substrate 302 and optionally including integrated circuit devices or layers formed on an additional substrate may be bonded to the substrate 302 and located under the insulator / dielectric layer 304.

[0086] As Figure 3 shown, the insulator / dielectric layer 304 is located on the substrate 302 and on any optional layers formed between the substrate 302 and the insulator / dielectric layer 304. A metal layer such as the metal "x" layer 306 is disposed on the insulator / dielectric layer 304. x may be a suitable integer greater than zero. In one embodiment, the metal "x" layer 306 may be a back-end metal layer, but the present disclosure is not limited to this embodiment.

[0087] An insulator 308 is formed on the metal "x" layer 306, and the metal "x" layer 306 includes conductive electrodes 310 (or conductive plugs) formed at spatial intervals. Separated devices 320, such as, for example, resistive switching devices (e.g., resistive switching memory devices, volatile resistive switching devices, or a combination of resistive switching memory devices and volatile resistive switching devices), are respectively disposed on the conductive electrodes 310. The conductive layer 322 of the separated devices 320 is in electrical contact (physical contact in some embodiments) with the respective upper surfaces of the conductive electrodes 310 and with respective portions of the upper surface of the insulator 308. In some embodiments, one or more additional layers (e.g., adhesion layers, diffusion barrier layers, seed layers, ion conductor layers, etc., or a suitable combination of the foregoing layers) may be located between the insulator 308 and the conductive layer 322.

[0088] The resistive switching layer 324 is formed on the conductive layer 322 (and optionally in physical contact with the conductive layer 322). The resistive switching layer 324 is shown to have an intrinsic surface roughness 325 that forms as the lower surface of the resistive switching layer 324 at the boundary of the conductive electrode 310. The intrinsic surface roughness 325 can be defined by grain boundaries of atomic / molecular particles that form the (upper) surface of the conductive electrode 310, the (lower) surface of the resistive switching layer 324, or a combination of the foregoing surfaces. Atomic / molecular particles or multiple sets of such particles (also referred to as atomic / molecular “grains”) can form an irregular surface structure in the surface of the resistive switching layer 324. In one embodiment, the distribution of the fabricated particles can result in the surface of the resistive switching layer 324 having an RMS surface roughness greater than 0.2 nm (e.g., see below Figure 4A ). Although Figure 3 not shown (however see below Figure 4B and Figure 4C ), the upper surface of the resistive switching layer 324 can also have an RMS surface roughness greater than 0.2 nm. In one embodiment, the upper and lower surfaces can have a maximum RMS surface roughness not greater than 10 nm. In a further embodiment, the RMS surface roughness of the upper and lower surfaces of the resistive switching layer 324 can be in the range between 0.2 nm and 10 nm or any suitable value therebetween or in any suitable range therebetween (e.g., 0.2 nm to 5 nm; 0.5 nm to 5 nm; 0.75 nm to 3 nm, etc.). This can result in a thickness variation of the resistive switching layer 324 throughout its volume (measured from the upper surface to the lower surface). Additionally, the position, orientation, size, and distribution of the grain boundaries within the resistive switching layer 324 are typically a random or substantially random process, resulting in uncorrelated surface roughnesses of the switching layer surfaces of the individual discrete devices 320 (e.g., see below Figure 4 ).

[0089] The metal layer 326 is disposed on the resistive switching layer 324. The metal layer 326 may include conductive particles diffused within the resistive switching layer 324 and may also be referred to in the present disclosure as a metal layer, an active metal layer, etc. As disclosed herein, or as known in the art, or as reasonably conveyed to a person skilled in the art through the context provided herein, the metal layer 326 may include suitable materials for an active metal layer or a particle donor layer. Additionally, a conductive layer 328 may be disposed on the metal layer 326. In one embodiment, the conductive layer 328 may be a metal “x+1” layer that is part of the back-end metal wiring in combination with a metal “x” layer 306. However, the conductive layer 328 is not limited thereto and may be a doped silicon layer, a doped silicon-germanium layer, a metal-containing layer (e.g., a conductive metal compound, alloy, mixture, etc.), or other suitable conductive layer disposed between the back-end metal wirings of an integrated circuit device. In at least one embodiment, one or more layers such as a conductive capping layer (e.g., providing electrical continuity between the metal layer 326 and the conductive layer 328), an adhesion layer, a diffusion barrier layer, an etch stop layer, an ion conductor layer, etc. may be disposed between the metal layer 326 and the conductive layer 328. An insulator / dielectric material 330 covers and surrounds the discrete device 320, providing electrical isolation between the discrete device 320 and the layer (not shown) covering the discrete device.

[0090] Figure 4 A block diagram of an inter-device switch surface variation 400 in accordance with an embodiment of the present disclosure is shown. A pair of discrete devices 420 formed as part of an integrated circuit device are shown. In one or more embodiments, the discrete devices 420 may be substantially similar to Figure 3 the discrete devices 320, but the present disclosure is not limited to this embodiment. For example, the discrete devices 420 may be formed between adjacent back-end metal wirings metal “x” 306 and metal “x+1” 428 of an integrated circuit device. In one embodiment, the metal wirings 306, 428 may be formed (or lined, not shown) with a lining of a dense metal-containing material that is opaque to the visible, infrared, or ultraviolet electromagnetic spectra. Examples include Ti, Ta, W, Cu, Al, Fe, suitable alloys or mixtures of the foregoing metals, suitable nitrides or oxides of the foregoing metals, etc. or suitable combinations thereof. Such an arrangement helps to block the observation of the discrete devices 420 by illegal microscopy techniques to erroneously read the bit states of the discrete devices 420 (e.g., see below Figure 4B and Figure 4C ).

[0091] The discrete devices 420 include respective switching layers 324 having respective fabricated surface roughnesses (including surface roughness device 1 425 and surface roughness device 2 427). A cut-away portion 425A shows a close-up view of the fabricated surface roughness device 1 425 (see also Figure 4A, showing a separate surface roughness variation 405A in the boundary between the conductive layer 322 and the switching layer 324, and an example range of the RMS surface roughness 410). As described herein, in one or more embodiments, the RMS value of the surface roughness can be greater than 0.2 nm. In a further embodiment, the maximum RMS value of the surface roughness does not exceed 10.0 nm. However, since the surface roughness is formed by a random or substantially random process, the inherent variations in the surface roughness and the associated thickness of the switching layer 324 between devices can result in random variations in the operating characteristics between separate devices, the operating characteristics including: each programming voltage, each intrinsic resistance, each programming resistance (resistance in the programmed state), each programming current, each erase current (current in the unprogrammed state, or leakage current), each erase voltage, current, field strength, field polarity, etc. or a suitable combination of the above. In some embodiments, one or more of these characteristics will have little cross-correlation between separate devices 420 and little cross-correlation with the spatial location on the die or wafer. Intentional variations during manufacturing can result in a very small cross-correlation: in the range of about -0.2 to about 0.2, in the range of about -0.1 to about 0.1, in the range of about -0.02 to about 0.02, in the range of about -0.01 to about 0.01, and in some embodiments in the range of about -0.003 to about 0.003 (e.g., see below Figure 9 ).

[0092] In one or more embodiments, the thickness of the switching layer 324 varies spatially with the RMS surface roughness of the lower and upper surfaces of the switching layer 324 (e.g., greater than 0.2 nm). In one embodiment, by design, the process for depositing the switching layer 324 can be based entirely on a manufacturing parameter range that is wider than the conventional manufacturing parameter range specified for depositing the switching layer. In one or more embodiments, the nominal thickness of the switching layer 324 can be in to to to range, or any suitable value therebetween or in any suitable range therebetween. In various embodiments, greater variations in surface roughness can be achieved by adjusting the deposition temperature, deposition time, reagent chemical purity, reagent chemical flow rate, deposition power, etc. or a suitable combination of the above. In one or more embodiments, the spatial thickness variation of the switching layer 324 can be in the range of: 2% to 10%, 5% to 20%, 2% to 20%, or any suitable value therebetween or in any suitable range therebetween.

[0093] The thickness of the switching layer 324 is a parameter that can affect the various operating characteristics of the separation device 420. Examples of such operating characteristics can include: volatile / non-volatile, on / off current ratio, switching time, read time, memory durability, program / erase cycle, etc. Based on the range of manufacturing tolerances, at least some of these characteristics of the resistive switching device can have very low cross-correlation between resistive switching devices in an array, or between switching devices on a die (intra-die), between dies in a wafer, or between wafers (inter-die). In some embodiments, for two resistive switching devices on a die, the cross-correlation of the intrinsic (unprogrammed) resistance, intrinsic (unprogrammed) current, intrinsic programming voltage, programmed resistance, erase voltage, etc. can be between -0.1 and 0.1 in some embodiments, or between -0.01 and 0.01 in further embodiments. As an example, the intrinsic resistance can be in the range of 100 kiloohms (kΩ) to 50 megohms (MΩ), 100 kΩ to 100 MΩ, or any suitable value or range therebetween.

[0094] Figure 4B and Figure 4C FIG. shows an example switching layer 324 of two resistive switching devices 320B and 320C. However, the switching layer 324 is merely representative, as for the sake of illustration only, the surface roughness of each device 320B, 320C is the same; as discussed above, this is not the case for real devices. Instead, Figure 4B and Figure 4C FIG. shows filaments of conductive particles (hereinafter referred to as conductive filaments 402B, 402C) formed within the switching layer 324 of devices 320B and 320C. Since the conductivity through the switching layer 324 can be mainly defined by the electrical continuity (or at least the continuity based on electron tunneling) between the conductive filament 402B and the conductive layer 322, the resistance states of the devices 320B, 320C can also be mainly defined by the electrical continuity of the conductive filaments. The conductive filament 402B represents an electrically continuous path between the metal layer 326 and the conductive layer 322 passing through the switching layer 324 of the device 320B, such that the device 320B is in a low resistance (or programmed) resistance state. In contrast, the conductive filament 402C represents an electrically discontinuous path between the metal layer 326 and the conductive layer 322 of the device 320C, resulting in the device 320C being in a high resistance (or erased or unprogrammed) resistance state. In Figure 4B and Figure 4CIn the examples shown, these respective continuity states are determined by only a pair of conductive particles 404B and 404C. For the conductive filament 402B, the particle 404B is completely continuous between the conductive filament 402B and the conductive layer 322, while for the conductive filament 402C, the particle 404C is not completely continuous between the conductive filament 402C and the conductive layer 322. Thus, in these examples, the positions of these two particles 404B, 404C determine the resistance states of the devices 320B and 320C. These figures illustrate the difficulty of side-channel reading of filament-based resistive switching devices. Since only a few atomic / molecular particles may be needed to complete or disrupt continuity, leading to one state or the other, illicit techniques for determining the resistance state (e.g., high-intensity microscopy) can be very difficult. When the devices 320B and 320C are formed between metal wiring layers (e.g., as shown above Figure 3 and Figure 4 ), this difficulty can be further exacerbated due to the density of the metal materials typically used for back-end wiring structures. Thus, the resistive switching devices disclosed herein can provide a relatively high intrinsic security for identifier data against illicit side-channel access techniques to which other pseudo-random state devices (e.g., SRAM) are vulnerable.

[0095] Figure 5 FIG. shows an example graph of the Hamming distance (HD) distribution 500 of a 100 megabit (Mb) resistive switching device according to one embodiment. The graph plots the normalized Hamming distance on the x-axis against the overall resistive switching devices (again normalized) on the y-axis. The Hamming distance represents the minimum deviation between uniquely identifiable bit sequences (e.g., two sequences where at least one bit of each sequence is different). The blue graph lists the Hamming distances of the identifier sequence data generated by the resistive switching device techniques disclosed herein between different semiconductor dies. Figure 5 The Gaussian or near-Gaussian distribution centered at a Hamming distance of 0.5 as shown provides an excellent distribution with no significant overlap, indicating unique sequences for each semiconductor die. The red line represents the Hamming device within a single die for multiple reads of the identifier sequence. The ideal HD within a single die is 0.0, i.e., the case where the bit error rate (BER) is zero when the same data sequence is read each time. Existing structures for generating identifier data such as SRAM have a very high intrinsic BER, resulting in values within the HD significantly greater than 0.0. This reduces the security margin for distinguishing within-HD and between-HD, increases the likelihood of read errors overlapping with the identifier sequences of another semiconductor die, and undermines the uniqueness of the identifier. For the resistive switching device, the HD within effectively is 0.0, providing an excellent security margin, minimizing the BER, and maximizing the uniqueness of the identifier sequence over multiple read cycles.

[0096] Figure 6Shows an example view of the spatial randomness 600 of the identifier data generated from the disclosed resistive switching device according to a further embodiment of the present disclosure. The spatial randomness is defined by the correlation function 620 as where N is a number equal to 256 bits, x i is the i-th bit, and x i+j is the (i + j)-th bit. As shown in the view of the correlation 600, the correlation between adjacent bits is between -0.003 and 0.003, and largely between -0.002 and 0.002, indicating excellent decorrelation of the disclosed resistive switching device.

[0097] Figure 7 Shows an example view of the service life 700 of the resistive switching device identifier data within a temperature range according to one or more embodiments of the present disclosure. This view plots the number of read operations on the x-axis and the bit error rate on the y-axis at temperatures of -40 degrees Celsius, 25 degrees Celsius, and 125 degrees Celsius. Even when reading more than 10 8 times at all temperatures, the BER is essentially zero. In one embodiment, as Figure 7 shown, a very high service life can be partially achieved by determining the identifier bit values from program-related events (such as, median programming voltage, differential programming speed, etc.) that distinguish between programmed and non-programmed resistive switching device bits. After the initial distinction, the bits defined as programmed can be programmed once (e.g., using high-voltage programming pulses, long program cycle times, multi-pulse program cycles with high program peaks and long pulse lengths, etc.) to present programmed bits that are permanently programmed, non-erasable, one-time programmable, etc. The one-time programming process can significantly reduce bit loss in the programmed device, achieving a very low bit error rate, as Figure 7 shown.

[0098] Figure 8 Shows an example view of the randomness 800 of the disclosed resistive switching device compared to a reference cryptographic quality random number generator according to a further embodiment. This view plots the entropy of the binary numbers: 2 on the x-axis -x where x of 1.0 equals perfect entropy (the probability of 0 or 1 in any bit of the binary sequence is 50%). The y-axis plots the bit count. The light shaded bar 806 represents the identifier data derived from the physically unclonable characteristics of the resistive switching device for 100 megabits of identifier data, the dark shaded bar 802 represents the first reference random source, and the medium shaded bar represents the second reference random source. As Figure 8 shown, the data generated by the resistive switching device has entropy comparable to that of two cryptographic quality random number generators.

[0099] Now refer to Figure 9, showing an example schematic diagram of an array of resistive switching devices and an example differential grouping 900 of identifier bits 902, 902A, 902B (collectively referred to as identifier bits 902) in accordance with one or more of the disclosed embodiments. In Figure 9 the differential grouping 900, pairs of resistive switching devices are assigned to a single identifier bit (e.g., by a controller such as Figure 1 controller 160). Also as shown in the differential grouping 900, each pair of resistive switching devices grouped into a single identifier bit 902, 902A, 902B are adjacent resistive switching devices on a common word line (e.g., word line 0 910 to word line N 912, where N is a suitable integer greater than 0). Thus, for example, the lower right identifier bit 902 includes resistive switching device 1 904 and adjacent resistive switching device 2 906 on word line N 912. Each resistive switching device 904, 906 can be connected to bit lines 936, 938 at one terminal and to source lines 926, 928 at a second terminal through respective transistors 908. In Figure 9 the schematic diagram, word line N 912 activates or deactivates transistors 908 connected to resistive switching devices 904, 906, thereby connecting or disconnecting resistive switching devices 904, 906 to source lines 926, 928, respectively. In other words, when word line N 912 has a high voltage and activates transistor 908, resistive switching devices 904, 906 are connected to source lines 926, 928, respectively. Conversely, when word line N 912 has a low voltage and deactivates transistor 908, resistive switching devices 904, 906 are disconnected from source lines 926, 928, respectively.

[0100] The bit value of each identifier bit 902, 902A, 902B can be determined by the selected differential characteristics of the resistive switching devices defined for each identifier bit 902, 902A, 902B. If the first resistive switching device in a pair of resistive switching devices 904, 906 (e.g., defined by the controller 160) has a first threshold characteristic, the identifier bit 902 can have a first binary value (e.g., a "0" value). Conversely, if the second resistive switching device in a pair of resistive switching devices 904, 906 (e.g., defined by the controller 160) has a first threshold characteristic, the identifier bit 902 can have a second binary value (e.g., a "1" value). Example differential characteristics can include: programming speed (e.g., which device is the first device programmed in response to a programming voltage determines whether the identifier bit 902 is "0" or "1"), programming voltage (e.g., device 1 904 with a programming voltage higher than device 2 906 determines "0", and vice versa determines "1"), intrinsic current (e.g., device 1 904 with an intrinsic current higher than device 2 906 determines "0", and vice versa determines "1"), intrinsic resistance (e.g., device 1 904 with an intrinsic resistance higher than device 2 906 determines "0", and vice versa determines "1"), etc., or a suitable combination of the foregoing. In one embodiment, once a differential program-related event has established the value of the identifier bit 902, the first device programmed (or the device with a higher or lower programming voltage determined at the controller 160) can be set to one-time programmable programming so that the identifier bit can be reread multiple times with an almost zero error rate.

[0101] In at least one embodiment, the differential characteristics of the resistive switching devices defined for each identifier bit 902, 902A, 902B can be used to generate multi-bit binary data for the identifier bits. In one embodiment, more groups of resistive switching devices can be grouped into each identifier bit 902 to achieve a multi-bit binary value. For example, four resistive switching devices can be grouped into the identifier bit 902 to achieve a two-bit identifier data (e.g., see below Figure 11 and Figure 12)。However, in another embodiment, the controller (e.g., controller 160) may alternatively establish multiple states for the pair of resistive switching devices 904, 906 to implement multi-bit binary information. For example, a threshold intrinsic current (or a range of intrinsic currents) may be established, and the intrinsic current values of the pair of resistive switching devices 904, 906 may be utilized to define four (or more) differential states, which may be associated with two-bit (or more) binary data. As an example, four differential states may be defined to include: a zero state, where both devices 904, 906 are less than the threshold intrinsic current (e.g., 500 nA); a first state, where device 904 is less than the threshold intrinsic current and device 906 is greater than the threshold intrinsic current; a second state, where device 906 is less than the threshold current and device 904 is greater than the threshold current; and a third state, where both devices 904, 906 are greater than the threshold current. Thus, measuring the intrinsic currents of the pair of devices 904, 906 can be used to generate a two-bit binary value for the identifier bit 902. As yet another example, multiple threshold current values may be defined relative to the intrinsic current values of the pair of devices 904, 906 to implement a greater number of multi-bits. For example, two intrinsic current thresholds (500 nA, 550 nA) may define three intrinsic current states for each pair of devices 904, 906 (one current state less than 500 nA; one current state between 500 nA and 550 nA; and one current state greater than 550 nA). Three intrinsic current states measured relative to the two resistive switching devices 904, 906 can generate 2 3 differential states, enabling the definition of three-bit binary data for the identifier bit 902, etc. In various embodiments, a combination of a larger number of resistive switching devices 904, 906 and multiple measurement thresholds may be utilized to implement a larger number of differential states, where 2 # differential states define the number of binary bits that may be associated with a single identifier bit 902, 902A, 902B.

[0102] Figure 10A schematic diagram showing an example array of resistive switching devices according to an alternative or additional embodiment of the present disclosure provides an alternative definition of the differential group 1000 of identifier bits 902, 1002, 1010. The differential group 1000 can define multiple non-adjacent resistive switching devices on a word line as a single identifier group. For example, the identifier bit 1002 includes device 1 1004 on word line 0910 and bit line 930 and device 2 1006 on word line 0 910 and bit line 934 (which is not directly adjacent to bit line 930). Similarly, the identifier group 1010 includes device 1 1014 on word line N 912 and bit line 930 and device 2 1016 on word line N 912 and bit line 935 (which is also not directly adjacent to bit line 930). The identifier bits 1002 and 1010 and other suitable combinations can be defined by the controller 160 Figure 1 described below. In addition to the foregoing, in the embodiment described by the differential group 1000, the identifier bit 902 of the devices on the common word line and the adjacent bit lines can also be grouped. Therefore, in some disclosed embodiments, the differential group 1000 can mix the grouping of devices on adjacent bit lines with the grouping of devices on non-adjacent bit lines.

[0103] Figure 11 A schematic diagram showing an example array of resistive switching devices according to a further embodiment of the present disclosure provides another alternative definition of the differential group 1100 of identifier bits 1102, 1110. As shown, the differential group 1100 defines multiple resistive switching devices on bit lines 930, 932... as identifier bits 1102, 1110 respectively. Although Figure 11 the example array accommodates one or more word lines between word line 0 910 and word line N 912, in one embodiment, the identifier bits 1102 and 1110 can group the resistive switching devices on adjacent word lines. The present disclosure is not limited thereto, and the identifier bits can also include multiple groups of resistive switching devices on non-adjacent word lines. As described herein (for example, see Figure 9 ), the differential operating characteristics of each resistive switching device of each identifier bit 1102, 1110 can be used to generate identifier data for each identifier bit 1102, 1110. However, the present disclosure is not limited thereto, and the definitions of the differential operating characteristics explicitly disclosed using the identifier bit data, as well as the definitions reasonably conveyed to those skilled in the art through the context provided herein, are considered to be within the scope of the present disclosure.

[0104] Figure 12A schematic diagram showing an example array of resistive switching devices according to another embodiment of the present disclosure provides another definition of the differential group 1200 of identifier bits 1202, 1210, 1220. In particular, the differential group 1200 allows resistive switching devices on different bit lines and different word lines to be grouped into identifier groups. For example, the identifier bit 1202 includes resistive switching devices on bit lines 930, 932 and word lines 910, 912. In addition, the identifier bits 1210 and 1220 group resistive switching devices on non-adjacent bit lines with other resistive switching devices on different word lines. It should be understood that according to various embodiments of the present disclosure, any regular or irregular grouping of resistive switching devices into identifier bits can also be implemented, and the scope of the present disclosure is not limited to what is explicitly described. In addition, the identifier bits 1202, 1210, 1220 each include four resistive switching devices. Even for a single-threshold qualitative criterion (e.g., the first device programmed within the identifier bit in response to a programming voltage applied to all devices), this allows two-bit binary data for each of the identifier bits 1202, 1210, 1220. For example, if device 11204 is the first to be programmed, the identifier bit is equal to 00; if device 2 1206 is the first to be programmed, it is equal to 01; if device 3 1208 is the first to be programmed, it is equal to 10; if device N 1209 is the first to be programmed, it is equal to 11, or a similar definition. In some embodiments, the number N of resistive switching devices in each identifier bit may be equal to 2 x , where x is the number of bits of the multi-bit binary number. In other embodiments, a differential quantitative threshold metric can be used to increase the multi-bit capacity of each identifier bit having four resistive switching devices, similar to the description above regarding Figure 9 . Other variations and combinations known in the art or reasonably suggested to those skilled in the art by the context provided herein are considered to be within the scope of the present disclosure.

[0105] The accompanying drawings included herein describe several components, layers, and materials of resistive switching devices or dies or wafers containing multiple resistive switching devices. It should be understood that such drawings may include these components, layers, and materials explicitly indicated therein, parts of the explicitly indicated components / layers / materials, or additional components / layers / materials not explicitly depicted but known in the art or reasonably conveyed to those skilled in the art by the context provided herein. Sub-layers can also be implemented as adjacent other sub-layers within the depicted layer. In addition, where appropriate, the embodiments in a particular drawing of this specification can be applied in part or in whole to other embodiments depicted in other drawings, and vice versa. As an exemplary example, Figure 3 's switching device stack structure 300 can be used to form a resistive switching device array as shown in Figures 9 to 12 , which in turn can be associated with Figure 1an array of RS devices 105, or Figure 22 a memory array 2202, or Figure 23 a volatile memory 2310A or a non-volatile memory 2310B, etc. may be included together. In addition, it should be noted that one or more of the disclosed processes may be combined into a single process that provides an aggregated function. For example, a deposition process may include an etching process (and vice versa) to facilitate depositing and etching components of an integrated circuit device through a single process. Components of the disclosed architecture may also interact with one or more other components not specifically described herein but known to those skilled in the art.

[0106] In view of the exemplary views described above, referring to Figures 13 to 21A the flowchart, the processing methods that can be implemented according to the disclosed subject matter will be better understood. Although, for simplicity of explanation, Figures 13 to 21A the methods are shown and described as a series of blocks, it should be understood and appreciated that the claimed subject matter is not limited by the order of the blocks, as some blocks may occur in a different order and / or simultaneously with other blocks depicted and described herein. In addition, not all of the shown blocks are required to implement the methods described herein, and in some embodiments, additional steps known in the art or reasonably conveyed to those skilled in the art through the context provided herein are also considered to be within the scope of this disclosure. Further, in appropriate cases, some steps shown as part of one process may be implemented for another process; other steps of one or more processes may be added or replaced in other processes disclosed herein within the scope of this disclosure. In addition, it should be further understood that the methods disclosed in this specification can be stored on a manufacture's article to facilitate the transmission and transfer of such methods to an electronic device. The term manufacture's article is intended to include a computer program that can be accessed from any computer-readable device, a device incorporating a carrier, or a storage medium.

[0107] Figure 13 A flowchart of an example method 1300 for generating identifier data for an electronic device using a resistive switching device according to various disclosed embodiments is shown. At 1302, method 1300 may include selecting a subset of resistive switching devices on a die to generate bits for an identifier sequence. The selection may be in response to a command received at a memory control device (e.g., the controller 160 described above Figure 1 , the command interface 2216 and the state machine 2220 described below Figure 22 , the system memory 2310 and the processing unit 2304 described below Figure 23 , or other suitable memory control, management, or operating device). In other embodiments, in at least some embodiments, the selection may be established when the semiconductor device is initialized by the manufacturer, or may be established when the user initializes it, or during normal operation.

[0108] At 1304, method 1300 may include applying a low voltage less than the programming voltage of the resistive switching devices to a subset of the resistive switching devices. In one embodiment, the low voltage may be in the range of about 0.1 volts to about 1 volt; or in some embodiments, in the range of about 0.3 volts to about 0.5 volts or about 0.6 volts. The programming voltage magnitude is selected to avoid program events in any subset of the resistive switching devices.

[0109] At 1306, method 1300 may include reading an original current value of each resistive switching device in response to the low voltage. The original current (also referred to herein as the intrinsic current or initial current) may be the current associated with a resistive switching device that has not been previously programmed (e.g., since manufacture). At 1308, method 1300 may include comparing the current value of each device to one or more thresholds of a high current and a low current. In one embodiment, a single current threshold may be used to distinguish a measured original current value as being above or below the single current threshold. In other embodiments, multiple current thresholds may be utilized to distinguish a measured current value as being above a higher current threshold or below a lower current threshold. Other current thresholds known in the art or reasonably conveyed to one of ordinary skill in the art through the context provided herein and relationships to the original current values described herein are considered to be within the scope of the present disclosure.

[0110] At 1310, method 1300 may include digitizing the original current value relative to the high current and low current thresholds. In one embodiment, digitizing the original current value may include assigning a "0" bit value to a resistive switching device having an original current value below (smaller) the threshold, and assigning a "1" bit value to a resistive switching device having an original current value above (larger) the threshold, or vice versa in other embodiments. At 1312, method 1300 may include forming a bit sequence from the digitized current values and equating the digital bit sequence to an identifier sequence. In various embodiments, the identifier sequence may be output as part of an identification application in response to an ID request of a device (e.g., a semiconductor chip, an electronic device including resistive switching devices, etc.), to authenticate the device as part of an authentication application, to generate or verify a key as part of an encryption application, or a suitable combination of the foregoing.

[0111] Now refer to Figure 14 and Figure 14A, which shows a flowchart of an example method 1400 for generating identifier data using a nanoscale resistive switching device according to a further embodiment of the present disclosure. At 1402, method 1400 may include initiating an identifier acquisition process for a semiconductor chip. According to various disclosed embodiments, the identifier acquisition process may be configured to derive random or substantially random data from the physically unclonable characteristics of the resistive switching device. In other applications using uncorrelated data sequences, random data may be used to generate random numbers for various applications, identify electronic devices, authenticate electronic devices, or generate / verify encryption keys in encryption applications.

[0112] At 1404, method 1400 may optionally include receiving a selection of a subset of the resistive switching devices of the semiconductor chip. According to various embodiments, the selection may be received as an input from a controller (e.g., Figure 1 controller 160), a memory controller (e.g., Figure 22 state machine 2220 or command interface 2216 of Figure 23 ), or other suitable processing or logic execution device (e.g.,

[0113] system memory 2310 or processing unit 2304 of

[0114] ), or a suitable combination of the foregoing. In other embodiments, the selection may be a parameter stored in a memory (e.g., OTP device 130) during semiconductor chip initialization.

[0115] At 1406, method 1400 may include activating a voltage and current control circuit for the subset of resistive switching devices. At 1408, method 1400 may include applying a sub-programming voltage to each resistive switching device in the subset of resistive switching devices. At 1410, method 1400 may include measuring the raw unprogrammed current of each resistive switching device in the subset. Figure 14Aof 1424; otherwise, if the identifier bit sequence is determined to be the unit sequence, method 1400 may proceed to 1416.

[0116] At 1416, method 1400 may include assigning the digit "0" to a resistive switching device having a current below a small (or smaller) threshold current value. At 1418, method 1400 may include assigning the digit "1" to a resistive switching device having a current above a large (or larger) threshold current value. At 1420, method 1400 may include mapping the digit values of the resistive switching devices to an identifier bit sequence, and at 1422, method 1400 may include outputting the identifier bit sequence as an output of the identifier acquisition process.

[0117] Figure 14A Continue with method 1400. At 1424, method 1400 may include assigning the digit "0" to a resistive switching device having a current below a minimum threshold. At 1426, method 1400 may include assigning the digit "1" to a resistive switching device having a current above the minimum threshold and below a second minimum threshold. At 1428, method 1400 may include assigning digit values to resistive switching devices having currents between subsequent thresholds up to the Xth digit value, where 2 N defines the number of X digit values for an N-bit binary number. At 1430, method 1400 may include mapping the digit values of the resistive switching devices to a multi-digit identifier sequence, and at 1432, method 1400 may include outputting the multi-digit identifier sequence as an output of the identifier acquisition process.

[0118] Figure 15 A flowchart of an example method 1500 for generating identifier data using resistive switching devices in accordance with one or more additional embodiments of the present disclosure is shown. At 1502, method 1500 may include selecting a subset of resistive switching devices in an array to generate bits for an identifier sequence. In one embodiment, the resistive switching devices may be included on a semiconductor die, and the identifier sequence may be used for the semiconductor die.

[0119] At 1504, method 1500 may include applying a median program loop to the subset of resistive switching devices. The median program loop may have the property of being selected such that approximately half of the resistive switching devices are programmed and approximately half of the resistive switching devices remain unprogrammed. In one or more embodiments, such properties may include programming voltage magnitude, program current magnitude, cycle time, number, amplitude, or duration of cycle pulses, etc., or a suitable combination of the foregoing.

[0120] At 1506, method 1500 may include stopping the median program loop upon completion of a stop criterion. In one embodiment, the stop criterion may be completion of the median program loop. In other embodiments, the stop criterion may be determining that half (or approximately half) of the resistive switching devices have been programmed.

[0121] At 1508, method 1500 may include performing a read operation on the resistive switching devices and identifying the resistive switching devices in a programmed state and a non-programmed state. At 1510, method 1500 may include assigning a first binary value to the resistive switching devices in the programmed state and a second binary value to the resistive switching devices in the non-programmed state.

[0122] At 1512, method 1500 may include forming a bit sequence from the binary values and equating the binary bit sequence to an identifier sequence. At 1514, method 1500 may optionally include applying a permanent programming voltage to the resistive switching devices in the programmed state to permanently program the resistive switching devices in the programmed state.

[0123] Figure 16 and Figure 16A FIG. shows a flowchart of an example method 1600 for generating identifier sequence data in accordance with a further embodiment of the present disclosure. In one or more embodiments, according to at least some embodiments of the present disclosure, method 1600 may generate identifier sequence data through physically unclonable characteristics formed during the fabrication of dual-terminal resistive switching devices on a die substrate using a nanoscale manufacturing process.

[0124] At 1602, method 1600 may include initiating an identifier acquisition process for a semiconductor chip. At 1604, method 1600 may optionally include receiving a selection of a subset of the resistive switching devices of the semiconductor chip. Method 1600 may also include organizing multiple subsets of resistive switching devices into identifier bits. In one or more embodiments, a single resistive switching device may be assigned to each identifier bit. In other embodiments, multiple groups of resistive switching devices may be assigned to each identifier bit. The multiple resistive switching devices may include X resistive switching devices, where X = 2 N , N is the number of bits in the multi-bit binary number assigned to each identifier bit. As an exemplary example, in the case where each identifier bit generated for the identifier sequence data is a two-bit binary number, the number of resistive switching devices assigned to each identifier bit may be X = 2 2 or 4. In other embodiments, X may be defined by a combination of a smaller number of resistive switching devices and multiple threshold metrics for defining the identifier bit values (or bit states) of the multi-bit binary number (see, for example, above Figures 9 - 12)。Where appropriate, the numbering and organization of the resistive switching devices for each of the above identifier bits can be used in other embodiments of this specification (e.g., Figures 13 - 15 and the methods of 17 - 21A; Figure 1 , 2 , 9 - 12, 22, 23, etc.), and vice versa (e.g., other numberings and organizations described elsewhere herein can be used for method 1600). Other numberings and organizations of the logical states and threshold metrics of single - or multi - bit binary numbers known in the art or reasonably conveyed to those skilled in the art through the context provided herein are considered to be within the scope of this disclosure.

[0125] At 1606, method 1600 can include activating a voltage and current control circuit for a subset of resistive switching devices. At 1608, a median program loop is applied to each resistive switching device in the subset of resistive switching devices. In one embodiment, the median program loop can employ a programming voltage of approximately 2 volts; in other embodiments, the median program loop can employ a programming voltage in the range of approximately 1.8 volts to approximately 2.2 volts. Other voltages can be implemented in combination with appropriate current, pulse time, number of pulses, relative amplitude of pulses, or timing, etc. In one embodiment, the median program loop is selected such that after the median program loop is completed, approximately half of the resistive switching devices in the subset are programmed and approximately half of the resistive switching devices in the subset remain unprogrammed. In one embodiment, the median program loop can be selected such that after the median program loop, half + / - 5% are programmed; in other embodiments, after the median program loop, half + / - 10% are programmed; in further embodiments, after the median program loop, half + / - 15% are programmed; in other embodiments, after the median program loop, half + / - 20% are programmed. Where appropriate, these embodiments can be used in other aspects of this disclosure.

[0126] At 1610, method 1600 can include monitoring the median program loop relative to a stop criterion. In one embodiment, the stop criterion can be detecting a program event for approximately half of the resistive switching devices (or, e.g., half + / - 5%, + / - 10%, + / - 15%, + / - 20% of the resistive switching devices). At 1612, the method can include terminating the median program loop when the stop criterion is determined.

[0127] At 1614, it can optionally be determined whether the identifier bit sequence is a single - or multi - bit binary number. If it is a single - bit, then method 1600 can proceed to reference numeral 1616; otherwise, method 1600 can proceed to Figure 16Aat 1626. In other embodiments, determination 1614 may not exist, method 1600 may be pre-configured only for single or multiple bits, and method 1600 may then go to reference numeral 1616 or reference numeral 1626 respectively only.

[0128] At 1616, method 1600 may include reading the programmed state of each selected resistive switching device in a subset of resistive switching devices. At 1618, method 1600 may include assigning the digit "0" to a resistive switching device in a programmed state. At 1620, method 1600 may include assigning the digit "1" to a resistive switching device in a non-programmed state. At 1622, method 1600 may include mapping the digital value of the resistive switching device to an identifier bit sequence. At 1624, method 1600 may optionally include outputting the identifier bit sequence as an output of the identifier acquisition process. In at least one embodiment, method 1600 may further include applying a permanent one-time programmable (OTP) programming operation to each resistive switching device in a programmed state to facilitate very low bit error rates for subsequent reads of the identifier bit sequence over time, multiple read cycles, and a substantial temperature range.

[0129] Reference Figure 16A , method 1600 may continue at 1626. At 1626, method 1600 may include measuring the programmed state of each selected resistive switching device in a subset of resistive switching devices. At 1628, method 1600 may include assigning the digit "0" to a resistive switching device measured in an unprogrammed state. At 1630, method 1600 may include assigning the digit "1" to a resistive switching device measured in a first programmed state (although in at least some embodiments, this relative digit assignment may be reversed). At 1632, method 1600 may include assigning digital values to resistive switching devices measured in second and higher programmed states up to the Xth digital value (e.g., where 2 N defines the number of X digital values for an N-bit binary number, and N is an integer greater than 1).

[0130] At 1634, method 1600 may include mapping the digital value of the resistive switching device to a multi-digit identifier sequence (each digit of the identifier sequence includes N-bit binary data). At 1636, method 1600 may optionally include outputting the multi-digit identifier sequence as an output of the identifier acquisition process.

[0131] Figure 17A flowchart of an example method 1700 for generating identifier data in accordance with a further embodiment of the present disclosure is shown. At 1702, method 1700 may include selecting a subset of resistive switching devices on a die to generate bits for an identifier sequence for the die. At 1704, method 1700 may include applying a programming voltage to the subset of resistive switching devices at the start. In one embodiment, the resistive switching devices may be virgin resistive switching devices that have never been programmed before. At 1706, method 1700 may include measuring the time from the start time to the time when each resistive switching device is programmed, optionally up to a predetermined stop time. At 1708, method 1700 may include comparing the respective programming speed values of each resistive switching device with one or more thresholds of high and low programming speeds. In one embodiment, a single programming speed threshold may be utilized and the respective programming speed values may be compared with the single programming speed threshold to determine their relationship (e.g., above or below) with the single programming speed threshold. In other embodiments, multiple programming speed thresholds may be utilized and the respective programming speed values may be compared to determine programming speeds below a smaller threshold and programming speeds above a larger threshold.

[0132] At 1710, method 1700 may include assigning a first binary value to resistive switching devices with a below-threshold speed (or below a smaller threshold speed). At 1712, method 1700 may include assigning a second binary value to resistive switching devices with an above-threshold speed (or above a larger threshold speed). At 1714, method 1700 may include forming a bit sequence from the binary values and equating the bit sequence to the identifier sequence. At 1716, method 1700 may optionally include applying a one-time programmable programming cycle to resistive switching devices having the first binary value or the second binary value.

[0133] Figure 18 and Figure 18A A flowchart of an example method 1800 for generating an identifier bit sequence from a two-terminal resistive switching device in accordance with a further disclosed embodiment is shown. At 1802, method 1800 may include initiating an identifier acquisition process for a semiconductor chip. At 1804, method 1800 may include optionally receiving a selection of a subset of resistive switching devices of the semiconductor chip. In one embodiment, the selection may be received as an input of a control device included on (or operatively connected to) the semiconductor chip, while in other embodiments, the selection may be a default selection stored on the semiconductor chip.

[0134] At 1806, method 1800 may include activating a voltage and current control circuit for a subset of resistive switching devices. At 1808, method 1800 may include applying a program loop to each resistive switching device at a start time. At 1810, method 1800 may include monitoring the electrical response of each resistive switching device in response to the program loop. At 1812, method 1800 may optionally include determining and saving the program time for each resistive switching device in the subset of resistive switching devices starting from the start time.

[0135] At 1814, it may optionally be determined whether the identifier bit sequence is a single or multi-bit binary number. If it is single, method 1800 may proceed to reference numeral 1816; otherwise, method 1800 may proceed to Figure 18A 1826. In other embodiments, determination 1814 may not exist, method 1800 may be pre-configured only for single or multi-bit, and method 1800 may then proceed only to reference numeral 1816 or reference numeral 1826 respectively.

[0136] At 1816, method 1800 may include assigning the digit "0" to a resistive switching device whose program time is below a threshold speed (or below a smaller threshold speed in some embodiments). At 1818, method 1800 may include assigning the digit "1" to a resistive switching device whose program time is above the threshold speed (or above a larger threshold speed in one or more embodiments). At 1820, method 1800 may include mapping the digital value of the resistive switching device to the identifier bit sequence. At 1822, method 1800 may optionally include outputting the identifier bit sequence as the output of an identifier acquisition process. At 1824, method 1800 may optionally include applying a one-time programmable program loop to the devices assigned the digit "0" or the digit "1".

[0137] Referring to Figure 18A , at 1826, method 1800 may include comparing the measured program time to a minimum threshold in a set of program time thresholds. At 1828, method 1800 may include assigning the digit "0" to a resistive switching device that is measured to program faster than the minimum threshold. At 1830, method 1800 may include comparing the measured program time to a second threshold in the set of program time thresholds. At 1832, method 1800 may include assigning the digit "1" to a resistive switching device whose measured program time is between the minimum threshold and the second threshold in the set of program time thresholds. At 1834, method 1800 may include assigning digital values to resistive switching devices whose measured program times are between subsequent thresholds in the set of program time thresholds up to the Xth digital value, where 2 N is defined as the number of X digital values provided by an N-bit binary number.

[0138] At 1836, method 1800 may include mapping a digital value of a resistive switching device to a multi-digit identifier sequence. At 1838, method 1800 may include outputting the identifier sequence as an output of an identifier acquisition process.

[0139] Figure 19 A flowchart of an example method 1900 in accordance with alternative or additional embodiments of the present disclosure is shown. At 1902, method 1900 may include selecting a subset of resistive switching devices on a die to generate bits of an identifier sequence for the die. At 1904, method 1900 may include grouping subsets of multiple resistive switching devices into bits of the identifier sequence. In one embodiment, the multiple resistive switching devices grouped into one identifier bit may be devices on a word line and an adjacent bit line in an array, devices on a bit line and an adjacent word line in an array, devices on a word line and a non-adjacent bit line in an array, devices on a bit line and a non-adjacent word line in an array, or devices on non-adjacent word lines and non-adjacent bit lines in an array or a suitable combination of the foregoing.

[0140] At 1906, method 1900 may include applying a program loop to each resistive switching device in the subsets of multiple resistive switching devices. At 1908, method 1900 may monitor the subsets of multiple resistive switching devices for a program event for one resistive switching device in the subsets of multiple resistive switching devices. At 1910, method 1900 may include terminating the program loop of the multiple resistive switching devices in response to detecting a program event of any resistive switching device in the multiple resistive switching devices. At 1912, method 1900 may include assigning a digital value to a bit of the identifier sequence based on which resistive switching device in the associated multiple resistive switching devices first exhibits the program event. For example, in the case of grouping a pair of resistive switching devices into one identifier bit, if the first resistive switching device (e.g., a device connected to the first bit line of a pair of bit lines, a device connected to the first word line of a pair of word lines, a device connected to the first bit line and the first word line of a pair of bit lines and word lines, or other suitable definitions and arrangements) first exhibits the program event, the identifier bit may be assigned a first digital value (e.g., “0” or “1”), and if the second resistive switching device first exhibits the program event, the identifier bit may be assigned a second digital value (e.g., “1” or “0”).

[0141] At 1914, method 1900 may include forming a bit sequence from the digital values and equating the bit sequence to the identifier sequence. At 1916, method 1900 may optionally include applying a one-time programmable program loop to the first programmed resistive switching device in the subsets of multiple resistive switching devices.

[0142] Figure 20and [[ID= FIG. 2 shows a flowchart of an example method 2000 according to a further embodiment of the present disclosure. At 2002, method 2000 may include initiating an identifier acquisition process for a semiconductor chip. At 2004, method 2000 may optionally include receiving a selection of a subset of resistive switching devices of the semiconductor chip. At 2006, method 2000 may include grouping a plurality of resistive switching devices into respective identifier digits of an identifier digit sequence. In various embodiments, each identifier digit may be a single digit, while in other embodiments, each identifier digit may be a multi-digit number.

[0143] At 2008, method 2000 may include activating a voltage and current control circuit for the resistive switching devices. At 2010, method 2000 may include applying a program loop to the plurality of resistive switching devices in each identifier digit of the identifier digit sequence. At 2012, method 2000 may include monitoring program events of the resistive switching devices in each group of the plurality of resistive switching devices. At 2014, method 2000 may include detecting a program event of one of the plurality of resistive switching devices grouped to an identifier digit. At 2016, method 2000 may include terminating the program loop of the plurality of resistive switching devices grouped to the identifier digit in response to detecting the program event of the resistive switching device. At 2018, it is determined whether any other plurality of resistive switching devices grouped to an identifier digit are still being programmed. If so, method 2000 may return to reference numeral 2014; otherwise, when the program loops of all the plurality of resistive switching devices are terminated, method 2000 may proceed to 2020.

[0144] At 2020, method 2000 may include assigning a first numerical value to the first identifier digit of the first resistive switching device programmed among the plurality of resistive switching devices. At 2022, method 2000 may include assigning a second numerical value to the first identifier digit of the second resistive switching device programmed among the plurality of resistive switching devices.

[0145] Now referring to ​ , method 2000 continues at 2024. At 2024, method 2000 may optionally include assigning an X-th numerical value to the first identifier digit of the X-th resistive switching device programmed among the plurality of resistive switching devices. In various embodiments, the number X of numerical values = 2 N, where N is the integer number of bits of the N-bit binary number associated with each identifier digit of the identifier digit sequence. At 2026, method 2000 may include mapping the digit value of the identifier digit to the identifier digit sequence. At 2028, method 2000 may optionally include outputting the identifier digit sequence as the output of the identifier acquisition process. At 2030, method 2000 may optionally include applying a one-time programmable program cycle to each first programmed resistive switching device grouped to each identifier digit.

[0146] ​ and ​ FIG. shows a flowchart of an example method 2100 according to a further embodiment of the present disclosure. At 2102, method 2100 may include selecting a subset of resistive switching devices on the die to generate an identifier sequence for the die. At 2104, method 2100 may include measuring one or more device characteristics of the resistive switching devices affected by random physical characteristics of the resistive switching devices. At 2106, method 2100 may include generating a characteristic threshold for differentiating the resistive switching devices based on the measurement differences.

[0147] At 2108, method 2100 may include assigning the digit "0" to a first group of resistive switching devices having a first relationship with the characteristic threshold. At 2110, method 2100 may include assigning "1" to a second group of resistive switching devices having a second relationship with the characteristic threshold. At 2112, method 2100 may include grouping the resistive switching devices in a sequence of bits having bit values defined by the assigned "0" and "1" values. At 2114, method 2100 may optionally include outputting the bit sequence as the identifier of the die. At 2116, method 2100 may include permanently programming (or erasing) one of the first group of resistive switching devices or the second group of resistive switching devices.

[0148] ​ Continuing with method 2100, at 2218, method 2100 may include maintaining the second group of the first group of resistive switching devices or the second group of resistive switching devices in an opposite state. At 2120, method 2100 may include receiving a request for the identifier sequence of the die. At 2122, method 2100 may include reading the states of the first group of resistive switching devices and the second group of resistive switching devices. At 2124, method 2100 may include regenerating the bit sequence by reading the states. At 2126, method 2100 may include outputting the regenerated bit sequence in response to the request for the identifier sequence.

[0149] According to various embodiments, an electronic device is disclosed, including: a plurality of resistive switching devices disposed on a substrate of a semiconductor die, wherein each of the plurality of resistive switching devices includes a resistive switching material layer disposed between a first electrode and a second electrode, wherein one of the first electrode or the second electrode includes metal particles that diffuse into the material of the resistive switching material layer in response to an external stimulus applied between the first electrode and the second electrode, and further wherein the plurality of resistive switching devices are associated with an operating characteristic having a correlation coefficient within a range of -0.1 to 0.1 between resistive switching devices among the plurality of resistive switching devices; a first plurality of wires providing electrical connection to the upper electrodes of the plurality of resistive switching devices; a second plurality of wires providing electrical connection to the lower electrodes of the plurality of resistive switching devices; a control circuit configured to partition a subset of the plurality of resistive switching devices, thereby defining a first subset of resistive switching devices for generating a data sequence based on the operating characteristic having the correlation coefficient; and a sensing circuit at least partially disposed on the semiconductor substrate and electrically connected to the plurality of resistive switching devices through the first plurality of wires and the second plurality of wires, wherein the sensing circuit is configured to selectively apply a sensing signal to a first wire of the first plurality of wires and a second wire of the second plurality of wires to apply the sensing signal to a first resistive switching device in the first subset of resistive switching devices, wherein the sensing circuit is configured to determine a first response signal from the first resistive switching device in response to the sensing signal, and wherein the sensing circuit is configured to selectively apply the sensing signal to the first wire of the first plurality of wires and a third wire of the second plurality of wires to apply the sensing signal to a second resistive switching device in the first subset of resistive switching devices, wherein the sensing circuit is configured to determine a second response signal from the second resistive switching device in response to the sensing signal.

[0150] The electronic device may include a control circuit configured to receive an input command identifying a subset of the resistive switching devices, wherein in response to receiving the input command, the subset of the plurality of resistive switching devices is partitioned and a first subset of resistive switching devices is defined.

[0151] In one embodiment, the control circuit is further configured to partition an additional subset of the plurality of resistive switching devices (different from the above subset of the plurality of resistive switching devices for one-time programmable (OTP) operation), thereby defining a second subset of OTP resistive switching devices. In a further embodiment, the control circuit is further configured to define resistive switching devices among the plurality of resistive switching devices that are not included in the first subset of resistive switching devices and not included in the second subset of OTP resistive switching devices as rewritable non-volatile resistive storage devices, thereby defining a third subset of rewritable non-volatile resistive storage devices.

[0152] In another embodiment, the correlation coefficient between the first response signal and the second response signal is in the range of -0.1 to 0.1. In a further embodiment, the correlation coefficient between the first response signal and the second response signal is in a second range of -0.01 to 0.01. In other embodiments, the correlation coefficient between the first response signal and the second response signal is in a third range of -0.003 to 0.003.

[0153] In other embodiments, in response to the first response signal and the sense signal, a first characteristic associated with the first resistive switching device is determined; in response to the second response signal and the sense signal, a second characteristic associated with the second resistive switching device is determined. In one embodiment, the first characteristic and the second characteristic are selected from the group consisting of an intrinsic unprogrammed current, an intrinsic programming voltage, an intrinsic programming speed, a maximum program current, a program resistance, an erase voltage, a minimum erase current, and an erase state current after at least one program and erase.

[0154] In one or more embodiments, the control circuit further includes a processing circuit communicatively coupled to the sensing circuit and configured to compare the first response signal and the second response signal with one or more qualitative or quantitative benchmarks. In one embodiment, the processing circuit is configured to assign a binary value to the first response signal based on a comparison of the first response signal with a benchmark among the one or more qualitative or quantitative benchmarks. In another embodiment, the processing circuit is further configured to assign a second binary value to the second response signal based on a comparison of the second response signal with the benchmark, wherein the processing circuit is configured to generate a data sequence at least in part through the binary value and the second binary value.

[0155] In a still further embodiment, the processing circuit is configured to assign a first logical value to the first response signal or the second response signal if the value of the first response signal or the second response signal is respectively lower than a lower benchmark among the one or more qualitative or quantitative benchmarks; and the processing circuit is configured to assign a second logical value to the first response signal or the second response signal if the value of the first response signal or the second response signal is respectively higher than a higher benchmark among the one or more qualitative or quantitative benchmarks. In a still further embodiment, the processing circuit is configured to discard the first response signal or the second response signal if the value of the first response signal or the second response signal is higher than the lower benchmark and lower than the higher benchmark.

[0156] In one embodiment, the processing circuit is configured to generate a data sequence at least in part by a first digital value or a second digital value. In other embodiments, the processing circuit is configured to receive an input value and is configured to determine an output value in response to the input value, a first logic value, and a second logic value. In other embodiments, the processing circuit is configured to: receive a first input value and a second input value; determine a first output value in response to the first input value and the first logic value; and determine a second output value in response to the second input value and the second logic value. In other embodiments, the control circuit is configured to store the order of a first subset of resistive switching devices and generate a data sequence by bit values derived from the operating characteristics of the first subset of resistive switching devices, wherein the bit values are sorted according to the first subset of resistive switching devices to generate the data sequence. In a further embodiment, the control circuit is configured to define groups of two or more resistive switching devices from the first subset of resistive switching devices and assign each group of two or more resistive switching devices to respective bits of the data sequence. In other embodiments, the control circuit assigns a first logic value to a bit of the data sequence in response to a first resistive switching device among two or more resistive switching devices in a group assigned to the bit that meets a criterion, wherein the criterion is selected from the group consisting of first occurrence of a program event, first occurrence of an erase event, lowest intrinsic current magnitude, lowest intrinsic programming voltage, and lowest erase voltage. In at least one embodiment, the control circuit assigns a second logic value to a bit of the data sequence in response to a second resistive switching device among two or more resistive switching devices in a group assigned to the bit that meets the criterion.

[0157] A further embodiment discloses a method for operating a circuit, comprising: applying a first programming signal to a first resistive switching device in an unprogrammed state and a second resistive switching device in an unprogrammed state; in response to applying the first programming signal, determining whether the first resistive switching device and the second resistive switching device remain in the unprogrammed state; in response to determining that both the first resistive switching device and the second resistive switching device remain in the unprogrammed state, applying a second programming signal to the first resistive switching device and the second resistive switching device; at least one of the following:

[0158] characterizing the circuit as being in a first programming state in response to the first resistive switching device entering a programmed state in response to the second programming signal while the second resistive switching device remains in the unprogrammed state in response to the second programming signal; or characterizing the circuit as being in a second programming state in response to the second resistive switching device entering a programmed state in response to the second programming signal while the first resistive switching device remains in the unprogrammed state in response to the second programming signal; receiving an input stimulus; and at least one of the following: outputting a first output in response to the input stimulus and the circuit being characterized by the first programming state; or outputting a second output in response to the input stimulus and the circuit being characterized by the second programming state.

[0159] In an embodiment, the method further includes applying a third programming signal to the first resistive switching device in response to the first resistive switching device entering a programming state. In another embodiment, the third programming signal includes a one-time programming signal that causes the first resistive switching device to enter a one-time programmable programming state from the programming state. In another embodiment, the first programming signal is selected from the group consisting of a controlled current signal and a controlled voltage signal.

[0160] In a further embodiment, the method further includes: applying a first programming signal to a third resistive switching device in an unprogrammed state; determining, in response to the first programming signal, whether the third resistive switching device remains in the unprogrammed state; applying a second programming signal to the third resistive switching device in the unprogrammed state in response to determining that the third resistive switching device remains in the unprogrammed state; wherein, in response to the first resistive switching device and the third resistive switching device entering a programming state in response to the application of the second programming signal while the second resistive switching device remains in the unprogrammed state in response to the application of the second programming signal, it is characterized that the circuit is in a first programming state.

[0161] In a further embodiment, the method includes: applying a first programming signal to a fourth resistive switching device in an unprogrammed state; determining, in response to the application of the first programming signal, whether the fourth resistive switching device remains in the unprogrammed state; applying a second programming signal to the fourth resistive switching device in the unprogrammed state in response to determining that the fourth resistive switching device remains in the unprogrammed state; wherein, in response to the second resistive switching device and the fourth resistive switching device entering a programming state in response to the application of the second programming signal while the first resistive switching device and the third resistive switching device remain in the unprogrammed state in response to the application of the second programming signal, it is characterized that the circuit is in a second programming state. In a further embodiment, compared with the first programming signal, the parameters of the second programming signal increase, where the parameters are selected from the group consisting of current or voltage magnitude, signal duration, pulse count, and duty cycle.

[0162] In other embodiments, determining whether the first resistive switching device and the second resistive switching device remain in the unprogrammed state further includes: applying a read signal to the first resistive switching device; determining, in response to the read signal, whether the first resistive switching device is in the unprogrammed state; applying a read signal to the second resistive switching device; and determining, in response to the read signal, whether the second resistive switching device is in the unprogrammed state.

[0163] In some embodiments, the data word includes a plurality of resistive switching devices, the plurality of resistive switching devices including a first resistive switching device and a second resistive switching device; and the first resistive switching device is disposed at a predetermined position within the data word. In a further embodiment, the predetermined position is selected from the group consisting of the most significant bit (MSB) and the least significant bit (LSB).

[0164] Disclosed is a method of operating a circuit including an array of resistive switching devices, comprising: selecting a subset of the resistive switching devices to generate bits for an identifier sequence; defining a group of more than two resistive switching devices in the subset of resistive switching devices and assigning the group to a bit of the identifier sequence; applying a program cycle to the group of more than two resistive switching devices; monitoring the program cycle of the group of more than two resistive switching devices; terminating the program cycle in response to detecting a program for even one of the more than two resistive switching devices; and at least one of the following: assigning a first logical value to the bit of the identifier sequence in response to a first resistive switching device of the more than two resistive switching devices exhibiting a program event; or assigning a second logical value to the bit of the identifier sequence in response to a second resistive switching device of the more than two resistive switching devices exhibiting a program event.

[0165] In one embodiment, the method further comprises receiving a command input identifying the subset of resistive switching devices and selecting the subset of resistive switching devices in response to the command input. In other embodiments, the method further comprises defining multiple groups of more than two resistive switching devices in the subset of resistive switching devices and assigning each group to a respective bit of the identifier sequence. In additional embodiments, the method comprises applying a program cycle to each of the multiple groups of more than two resistive switching devices and monitoring each group for a program event associated with any of the resistive switching devices in the group. In another embodiment, the method further comprises terminating the program cycle for one of the multiple groups of more than two resistive switching devices in response to detecting a second program event for any one of the more than two resistive switching devices. In additional embodiments, the method further comprises determining whether the second program event is exhibited by a first resistive switching device of the more than two resistive switching devices or by a second resistive switching device of the more than two resistive switching devices.

[0166] In one or more other embodiments, the method further comprises one of the following: assigning a first logical value to a second identifier bit of the identifier sequence in response to a first resistive switching device of the more than two resistive switching devices exhibiting a second program event, and assigning a second logical value to the second identifier bit of the identifier sequence in response to a second resistive switching device of the more than two resistive switching devices exhibiting a second program event.

[0167] Other embodiments of the method further comprise: detecting each program event for each of the multiple groups of more than two resistive switching devices; assigning a first logical value or a second logical value to each identifier bit of the identifier sequence; and compiling the identifier sequence from each respective logical value assigned to each identifier bit.

[0168] In one embodiment, the method may include applying a one-time programmable programming signal to a first resistive switching device in response to detecting a programming event of the first resistive switching device. In yet another embodiment, the method may include applying a one-time programmable programming signal to a second resistive switching device in response to detecting a programming event of the second resistive switching device.

[0169] A method of operating a circuit is disclosed in a further embodiment, including: selecting a subset of unprogrammed resistive switching devices on a semiconductor die to generate bit values of a data sequence; applying a sub-programming voltage to the subset of unprogrammed resistive switching devices; reading an original current of each resistive switching device in the subset of unprogrammed resistive switching devices; comparing the original current of a resistive switching device with one or more thresholds of high and low original currents; and defining a logic value for a bit of the data sequence based on the comparison of the original current with one or more thresholds of high and low original currents.

[0170] Further embodiments of the method include comparing the original current value of each resistive switching device with one or more thresholds of high and low original currents and defining the logic value of each bit of the data sequence by comparing the respective original current values with one or more thresholds. In another embodiment, comparing the original current with one or more thresholds further includes: comparing the original current with a threshold current value and determining whether the original current is less than or greater than the threshold current value. In other embodiments, the method further includes: defining a first logic level for a bit of the data sequence in response to the original current being below the threshold current value; or defining a second logic level for a bit of the data sequence in response to the original current being above the threshold current value. In one embodiment, the method further includes setting the threshold current value to a current magnitude of about 500 nA. In alternative or additional embodiments, the method further includes setting the threshold current value to a current magnitude selected from a range between 400 nA and 600 nA.

[0171] In another embodiment, comparing the original current with one or more thresholds further includes: comparing the original current with a smaller threshold current and a larger threshold current and determining whether the original current is below the smaller threshold current or above the larger threshold current. In one embodiment, the method further includes: defining a first logic level for a bit of the data sequence in response to the original current being below the smaller threshold current; or defining a second logic level for a bit of the data sequence in response to the original current being above the larger threshold current. In a further embodiment, the method further includes removing the bit from the data sequence in response to the original current being above the smaller threshold current and below the larger threshold current. In other embodiments, the method further includes receiving an input defining the subset of unprogrammed resistive switching devices and selecting the subset in response to the input.

[0172] According to an alternative or additional embodiment, a method of operating a semiconductor device including a resistive switching device is disclosed, comprising: initiating an identifier acquisition sequence of a semiconductor chip; identifying a subset of resistive switching devices on the semiconductor chip for the identifier acquisition sequence; applying a sub-programming voltage to each resistive switching device in the subset of resistive switching devices; measuring an original unprogrammed current of each resistive switching device in the subset; comparing the measured current values with one or more thresholds of the unprogrammed current; defining a digital value of the measured current values according to respective comparison results with the one or more thresholds of the unprogrammed current; and aggregating the defined digital values into a data sequence.

[0173] In an embodiment, the method further includes comparing the measured current values with a single unprogrammed current threshold. In other embodiments, the method further includes assigning the digit "0" to a resistive switching device having a current lower than the single unprogrammed current threshold, and assigning the digit "1" to a resistive switching device having a current higher than the single unprogrammed current threshold. In other embodiments, the method further includes comparing the measured current values with a smaller unprogrammed current threshold and a larger unprogrammed current threshold. In an additional embodiment, the method further includes assigning the digit "0" to a resistive switching device having a measured current lower than the smaller unprogrammed current threshold, and assigning the digit "1" to a resistive switching device having a measured current higher than the larger unprogrammed current threshold.

[0174] In one or more additional embodiments, the method may include outputting the data sequence as a unique identifier of the semiconductor chip. Further embodiments provide that the method further includes generating or verifying an encryption key associated with the semiconductor device using the data sequence. Additional embodiments of the method further include: comparing the measured current values with a set of discrete current value thresholds; assigning the digit "0" to a resistive switching device having a measured current value lower than the smallest current threshold among the discrete current value thresholds; assigning the digit "1" to a resistive switching device having a measured current value between the smallest current threshold and the second smallest current threshold among the discrete current value thresholds; assigning digital values to resistive switching devices having currents between subsequent pairs of discrete current value thresholds up to the Xth digital value of an N-bit binary number, where the number of X digital values is defined by 2 N and N is greater than 1. In one embodiment, the method further includes aggregating N-bit binary numbers for each bit of the data sequence. In other embodiments, the method further includes outputting the data sequence in response to the identifier acquisition sequence.

[0175] Disclosed is a method of operating a circuit, comprising: selecting a subset of unprogrammed resistive switching devices on a semiconductor die to generate bit values of a data sequence; applying a median programming voltage to the subset of unprogrammed resistive switching devices; monitoring the subset of unprogrammed resistive switching devices for a stop criterion; stopping the median programming voltage in response to detecting a threshold number of unprogrammed resistive switching devices triggering the stop criterion; performing a read operation and identifying resistive switching devices in the subset of unprogrammed resistive switching devices that are in a programmed state and a non-programmed state; and defining a logical value of a bit of the data sequence based on a result of the read operation for each resistive switching device. In one embodiment, the method further comprises receiving an input command identifying the subset of unprogrammed resistive switching devices and selecting the subset in response to the input command. In another embodiment, the method may comprise selecting the median programming voltage such that a voltage magnitude is configured to cause approximately half of the unprogrammed resistive switching devices to be programmed in response to the median programming voltage. In another embodiment, approximately half of the unprogrammed resistive switching devices are selected from the group consisting of half of the unprogrammed resistive switching devices of + / -5%, half of the unprogrammed resistive switching devices of + / -10%, half of the unprogrammed resistive switching devices of + / -15%, and half of the unprogrammed resistive switching devices of + / -20%.

[0176] In a further embodiment, the threshold number of unprogrammed resistive switching devices is approximately half of the unprogrammed resistive switching devices. In other embodiments, the stop criterion is an initial program event in which one of the subset of unprogrammed resistive switching devices is first programmed. In yet another embodiment, defining a logical value of a bit of the data sequence further comprises, in response to the read operation, assigning a logic level "0" to the bit of the data sequence associated with a resistive switching device in a non-programmed state and assigning a logic level "1" to the bit of the data sequence associated with a resistive switching device in a programmed state.

[0177] In one embodiment, the method further comprises aggregating the defined logical values into the data sequence according to an order of unprogrammed resistive switching devices in an array on the semiconductor die. In other embodiments, the method further comprises, in response to the read operation, applying a one-time programmable signal to the resistive switching devices identified as being in a programmed state. In other embodiments, the median programming voltage is selected from a range of 1.8 volts to 2.2 volts.

[0178] According to one or more additional embodiments, a method of operating a semiconductor device including a resistive switching device is disclosed, including: initiating an identifier acquisition sequence of a semiconductor chip; identifying a subset of unprogrammed resistive switching devices on the semiconductor chip for the identifier acquisition process; applying a median program cycle to each unprogrammed resistive switching device in the subset of unprogrammed resistive switching devices; monitoring the median program cycle with respect to a stop criterion; terminating the median program cycle after determining the stop criterion; in response to terminating the median program cycle, reading the subset of unprogrammed resistive switching devices and identifying resistive switching devices in a programmed state and resistive switching devices remaining in an unprogrammed state; and in response to identifying resistive switching devices in a programmed state and resistive switching devices in an unprogrammed state, defining bits of a bit sequence.

[0179] In one or more embodiments, the method may include applying a median program cycle, further including: applying a programming signal to the subset of unprogrammed resistive switching devices; in response to the programming signal, determining a second subset of resistive switching devices from the subset in the programmed state and determining a third subset of resistive switching devices from the subset in the unprogrammed state; determining whether the second subset of resistive switching devices is equal to half of the unprogrammed resistive switching devices within a threshold range. In a further embodiment, the method further includes increasing the programming signal in response to determining that the second subset of resistive switching devices is less than half of the unprogrammed resistive switching devices within the threshold range until the second subset of resistive switching devices is equal to half of the unprogrammed resistive switching devices within the threshold range. In one embodiment, the threshold range is selected from the group consisting of 5%, 10%, 15%, and 20% of half of the unprogrammed resistive switching devices. In other embodiments, defining bits of the bit sequence further includes, in response to the median program cycle, assigning a logic level "0" to the bits associated with the resistive switching devices in the unprogrammed state, and in response to the median program cycle, assigning a logic level "1" to the bits associated with the resistive switching devices in the programmed state.

[0180] In one embodiment, defining bits of the bit sequence further includes measuring the programming state of each unprogrammed resistive switching device, assigning a digit "0" to the bits associated with the measured resistive switching devices in the unprogrammed state, and assigning a digit "1" to the bits associated with the measured resistive switching devices in a first programmed state. In such an embodiment, the method further includes assigning a numerical value to the bits of the bit sequence associated with the measured resistive switching devices in a second and higher programmed state up to the X numerical value, where 2 NDefine the number of X digital values of an N-bit binary number. In yet another embodiment, the method may further include aggregating a bit sequence by an N-bit binary number associated with a bit of the bit sequence in an order defined by the positions of unprogrammed resistive switching devices in an array on a semiconductor chip. In at least one embodiment, the method further includes applying a one-time programmable signal to a resistive switching device identified as being in a programmed state.

[0181] Example operating environment

[0182] ​ FIG. 2200 is a block diagram of an example operating and control environment 2200 for a memory array 2202 of a storage cell array in accordance with aspects of the present disclosure. In some embodiments, the control environment 2200 and the memory array 2202 may be formed within a single semiconductor die, although the present disclosure is not limited thereto, and in other embodiments, some components of the control environment 2200 may be formed on separate semiconductor dies. In at least one aspect of the present disclosure, the memory array 2202 may include memories selected from a variety of storage cell technologies. In at least one embodiment, the memory array 2202 may include a two-terminal memory technology arranged in a compact two-dimensional or three-dimensional architecture. Suitable two-terminal memory technologies may include resistive switching memory, conductive bridge memory, phase change memory, organic memory, magnetoresistive memory, etc., or a suitable combination of the foregoing. In a further embodiment, the two-terminal memory technology may be a two-terminal resistive switching technology.

[0183] The column controller 2206 and the sense amplifier 2208 may be formed adjacent to the memory array 2202. Additionally, the column controller 2206 may be configured to activate (or identify for activation) a subset of the bit lines of the memory array 2202. The column controller 2206 may utilize control signals provided by the reference and control signal generator 2218 to activate and operate the corresponding bit lines in the bit line subset, applying appropriate program, erase, or read voltages to these bit lines. The non-activated bit lines may be held at an inhibit voltage (also applied by the reference and control signal generator 2218) to mitigate or avoid bit interference effects on these non-activated bit lines.

[0184] Furthermore, the operating and control environment 2200 may include a row controller 2204. The row controller 2204 may be formed adjacent to and electrically connected to the word lines of the memory array 2202. Also utilizing the control signals of the reference and control signal generator 2218, the row controller 2204 may select a particular row of storage cells with an appropriate select voltage. Additionally, the row controller 2204 may facilitate programming, erase, or read operations by applying an appropriate voltage at the selected word line.

[0185] The sense amplifier 2208 can read data from or write data to the activated memory cells of the memory array 2202 selected by the column control 2206 and the row control 2204. The data read from the memory array 2202 can be provided to the input / output buffer 2212. Similarly, the data to be written to the memory array 2202 can be received from the input / output buffer 2212 and written to the activated memory cells of the memory array 2202.

[0186] The clock source 2210 can provide corresponding clock pulses to facilitate the timing of read, write, and programming operations of the row controller 2204 and the column controller 2206. The clock source 2210 can further facilitate the selection of word lines or bit lines in response to external or internal commands received by the operation and control environment 2200. The input / output buffer 2212 can include command and address inputs, as well as bidirectional data inputs and outputs. Instructions are provided through the command and address inputs, and the data to be written to the memory array 2202 and the data read from the memory array 2202 are transferred on the bidirectional data inputs and outputs, thereby facilitating connection to an external host device (not shown, but see the computer 2302 below ​ of the computer 2302).

[0187] The input / output buffer 2212 can be configured to receive write data, receive erase instructions, receive status or maintenance instructions, output read data, output status information, receive address data and command data, and address data corresponding to the respective instructions. The address data can be transferred to the row controller 2204 and the column controller 2206 through the address register 2214. In addition, the input data is transferred to the memory array 2202 through the signal input line between the sense amplifier 2208 and the input / output buffer 2212, and the output data is received from the memory array 2202 through the signal output line from the sense amplifier 2208 to the input / output buffer 2212. The input data can be received from the host device, and the output data can be transferred to the host device through the I / O bus.

[0188] The commands received from the host device can be provided to the command interface 2216. The command interface 2216 can be configured to receive external control signals from the host device and determine whether the data input to the input / output buffer 2212 is write data, a command, or an address. The input commands can be transferred to the state machine 2220.

[0189] The state machine 2220 can be configured to manage the programming and reprogramming of the memory array 2202 (and other memory banks in the multiple sets of memory arrays). The instructions provided to the state machine 2220 are implemented according to the control logic configuration, enabling the state machine 2220 to manage read, write, erase, data input, data output, and other functions associated with the memory cell array 2202. In some aspects, the state machine 2220 can send and receive acknowledgments and denials regarding the successful reception or execution of various commands. In further embodiments, the state machine 2220 can decode and implement state-related commands, decode and implement configuration commands, and so on.

[0190] To implement functions such as read, write, erase, input, output, etc., the state machine 2220 can control the clock source 2210 or the reference and control signal generator 2218. The control of the clock source 2210 can generate output pulses configured to facilitate the row controller 2204 and the column controller 2206 in implementing specific functions. For example, the output pulses can be transmitted to the selected bit lines through the column controller 2206, or for example, the output pulses can be transmitted to the selected word lines through the row controller 2204.

[0191] Combined ​ with

[0192] Reference ​ to

[0193] System bus 2308 can be any one of several types of bus structures, where the bus structure includes a memory bus or memory controller, a peripheral bus or external bus, and / or a local bus using any of a variety of available bus architectures, and the available bus architectures include, but are not limited to, Industry Standard Architecture (ISA), Micro Channel Architecture (MSA), Extended ISA (EISA), Intelligent Drive Electronics (IDE), VESA Local Bus (VLB), Peripheral Component Interconnect (PCI), Card Bus, Universal Serial Bus (USB), Advanced Graphics Port (AGP), Personal Computer Memory Card International Association Bus (PCMCIA), FireWire (IEEE1394), and Small Computer System Interface (SCSI).

[0194] System memory 2310 includes volatile memory 2310A and non-volatile memory 2310B. The Basic Input / Output System (BIOS) is stored in non-volatile memory 2310B, and the Basic Input / Output System (BIOS) contains basic routines for transferring information between elements within computer 2302 (e.g., during startup). Additionally, according to the present invention, codec 2314 can include at least one of an encoder or a decoder, where at least one of the encoder or the decoder can be constituted by hardware, software, or a combination of hardware and software. Although codec 2314 is shown as a separate component, codec 2314 can be included in non-volatile memory 2310B. By way of example and not limitation, non-volatile memory 2310B can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, dual-port memory, etc. Volatile memory 2310A includes random access memory (RAM), and in some embodiments can include a cache memory. By way of example and not limitation, RAM has various forms such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), and enhanced SDRAM (ESDRAM).

[0195] Computer 2302 can further include removable / non-removable, volatile / non-volatile computer storage media. For example, ​Disk storage device 2306 is shown. Disk memory 1306 includes, but is not limited to, devices such as disk drives, solid state disks (SSDs), floppy disk drives, tape drives, Jaz drives, Zip drives, LS-100 drives, flash memory cards, or memory sticks. In addition, disk storage device 2306 may include storage media, either alone or in combination with other storage media, including, but not limited to, optical disk drives such as compact disk read-only memory devices (CD-ROMs), CD recordable drives (CD-R drives), CD rewritable drives (CD-RW drives), or digital versatile disk read-only memory drives (DVD-ROMs). To facilitate connection of disk storage device 2306 to system bus 2308, a removable or non-removable interface, such as storage interface 2312, is typically used. It should be understood that disk storage device 2306 may store user-related information. Such information may be stored on or provided to a server or an application running on a user device. In one embodiment, the type of information stored to disk storage device 2306 or transmitted to a server or application may be notified to the user (e.g., via output device 2332). The user may be provided with the opportunity to opt in or out of collecting and / or sharing such information with a server or application (e.g., via input from input device 2342).

[0196] It should be understood that ​ Software acting as an intermediary between a user and the basic computer resources described in the appropriate operating environment 2300 is described. Such software includes operating system 2306A. Operating system 2306A, which may be stored on disk storage device 2306, is used to control and allocate the resources of computer system 2302. Application 2306C utilizes the management of resources by operating system 2306A through program modules 2306D and program data 2306D such as a startup / shutdown transaction table, where program data 2306D is stored in system memory 2310 or disk storage device 2306. It should be understood that the claimed subject matter may be implemented in various operating systems or combinations of operating systems.

[0197] The user inputs commands or information to the computer 2302 through the input device 2342. The input device 2342 includes, but is not limited to, pointing devices such as a mouse, trackball, stylus, touchpad, keyboard, microphone, joystick, gamepad, satellite antenna, scanner, TV tuner card, digital camera, digital video camera, web camera, etc. These and other input devices are connected to the processing unit 2304 via the input port 2340 through the system bus 2308. For example, the input port 2340 includes serial ports, parallel ports, game ports, and universal serial bus (USB). The output device 2332 uses some of the same types of ports as the input device 2342. Thus, for example, a USB port can be used to provide input to the computer 2302 and output information from the computer 2302 to the output device 2332. The output adapter 2330 is provided to illustrate some of the output devices 2332 such as monitors, speakers, and printers among other output devices 2332 that require special adapters. By way of example and not limitation, the output adapter 2330 includes video and sound cards that provide a means of connection between the output device 2332 and the system bus 2308. It should be noted that other devices and / or systems of devices provide both input and output functions simultaneously, for example, the remote computer 2338.

[0198] The computer 2302 can operate in a network environment using a logical connection to one or more remote computers, such as the remote computer 2324. The remote computer 2324 can be a personal computer, server, router, network PC, workstation, microprocessor-based device, peer device, smartphone, tablet, or other network node, and generally includes many of the elements described with respect to the computer 2302. For the sake of brevity, only the memory storage device 2326 is shown for the remote computer 2324. The remote computer 2324 is logically connected to the computer 2302 through the network 2322 and then through the communication interface 2320. The network 2322 includes wired or wireless communication networks, such as local area networks (LANs) and wide area networks (WANs) as well as cellular networks. LAN technologies include Fiber Distributed Data Interface (FDDI), Copper Distributed Data Interface (CDDI), Ethernet, Token Ring, etc. WAN technologies include, but are not limited to, point-to-point links, circuit-switched networks (such as Integrated Services Digital Network (ISDN) and its variants), packet-switched networks, and Digital Subscriber Line (DSL).

[0199] The communication interface 2320 refers to the hardware / software used to connect the network 2322 to the bus 2308. Although shown inside the computer 2302 for clarity, it can also be external to the computer 2302. For illustrative purposes only, the hardware / software required to connect to the network 2322 includes internal and external technologies such as modems (including conventional telephone-grade modems, cable modems, and DSL modems), ISDN adapters, wired and wireless Ethernet cards, hubs, and routers.

[0200] The aspects shown in this disclosure can also be implemented in a distributed computing environment where certain tasks are performed by remote processing devices linked through a communication network. In a distributed computing environment, program modules or stored information, instructions, etc. can be located in local or remote memory storage devices.

[0201] In addition, it should be understood that the various components described herein can include circuits, which can include components and circuit elements with appropriate values to implement the embodiments of this disclosure. In addition, it should be understood that many different components can be implemented on one or more IC chips. For example, in one embodiment, a set of components can be implemented in a single IC chip. In other embodiments, one or more corresponding components are fabricated or implemented on separate IC chips.

[0202] Regarding the various functions performed by the above components, architectures, circuits, processes, etc., unless otherwise specified, the terms used to describe such components (including references to "methods") are intended to correspond to any component (e.g., functionally equivalent) that performs the specific function of the described component, even if not structurally equivalent to the disclosed structure (the structure that performs the functions in the exemplary aspects of the embodiments shown herein). In this regard, it will also be recognized that the embodiments include systems having computer-executable instructions for performing the actions and / or events of various processes and computer-readable media.

[0203] In addition, although a particular feature may be disclosed only for one of several embodiments, such a feature can be combined with one or more other features of other embodiments, which can be expected and advantageous for any given or particular application. In addition, where the terms "comprising" and "including" and their variants are used in the detailed description or claims, these terms are intended to be inclusive in a manner similar to the term "including".

[0204] As used in this application, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless otherwise stated or made clear by context, "X uses A or B" is intended to mean any reasonable inclusive arrangement. That is, if X uses A; X uses B; or X uses both A and B, then "X uses A or B" holds in any of the foregoing instances. Further, unless otherwise stated or made clear by context to be in the singular form, the article "a" as used in this application and the appended claims is generally to be construed to mean "one or more".

[0205] After reading this disclosure, those skilled in the art can envision further embodiments. For example, in various embodiments, an erase operation can be initiated simultaneously on multiple ReRAM devices (e.g., 16, 32, etc.).

[0206] In other embodiments, combinations or sub - combinations of the embodiments disclosed above can be advantageously made. For ease of understanding, the architecture block diagrams and flowcharts are grouped. However, it should be understood that combinations of blocks, addition of new blocks, rearrangement of blocks, etc. are contemplated in alternative embodiments of this disclosure.

[0207] It should also be understood that the examples and embodiments described herein are for illustrative purposes only, and various modifications or changes made in accordance therewith will be conveyed to those skilled in the art and will be included within the spirit and scope of this application and the scope of the appended claims.

Claims

1. A semiconductor device, comprising: a substrate; and a plurality of two-terminal resistive switching devices disposed on the substrate of the semiconductor, the plurality of two-terminal resistive switching devices each comprising: a first electrode, a switching layer, a particle donor layer, and a second electrode, wherein the first electrode includes a surface in contact with the switching layer having a root mean square surface roughness greater than 2 nm, the switching layer has a nominal thickness, and the variation in the thickness of the switching layer is in the range of 2% to 20%, wherein the switching layer has a lateral width, and the variation in the lateral width of the switching layer is in the range of 5% to 20%, the particle donor layer is disposed on and in contact with the switching layer, and wherein the correlation coefficient of the intrinsic characteristics of a first two-terminal resistive switching device among the plurality of two-terminal resistive switching devices and a second two-terminal resistive switching device among the plurality of two-terminal resistive switching devices is in the range of -0.1 to 0.1, wherein the intrinsic characteristics are intrinsic unprogrammed resistance, intrinsic unprogrammed current, intrinsic programming voltage, intrinsic programming speed, program resistance, erase voltage.

2. The semiconductor device according to claim 1, wherein, The correlation coefficient of each of the plurality of two-terminal resistive switching devices is in the range of -0.1 to 0.

1.

3. The semiconductor device according to claim 2, wherein, The correlation coefficient of each of the plurality of two-terminal resistive switching devices is in a second range of -0.01 to 0.

01.

4. The semiconductor device according to claim 3, wherein, The correlation coefficient of each of the plurality of two-terminal resistive switching devices is in a third range of -0.003 to 0.

003.

5. The semiconductor device according to claim 1, wherein, The intrinsic characteristic is the intrinsic unprogrammed resistance of the first two-terminal resistive switching device and the second two-terminal resistive switching device.

6. The semiconductor device according to claim 1, wherein, The intrinsic characteristic is the intrinsic unprogrammed current of the first two-terminal resistive switching device and the second two-terminal resistive switching device.

7. The semiconductor device according to claim 1, wherein, The intrinsic characteristic is the intrinsic programming speed of the first two-terminal resistive switching device and the second two-terminal resistive switching device.

8. The semiconductor device according to claim 1, wherein, The intrinsic characteristic is the intrinsic programming voltage of the first two-terminal resistive switching device and the second two-terminal resistive switching device.

9. The semiconductor device according to claim 1, wherein, The switching layer is selected from the group consisting of amorphous metal oxides, amorphous metal nitrides, non-stoichiometric metal oxides, and non-stoichiometric metal nitrides, and the resistance value of each of the plurality of two-terminal resistive switching devices is partially related to the amount of metal in the switching layer.

10. The semiconductor device according to claim 9, wherein, The particle donor layer is selected from a second group consisting of amorphous metal oxides, amorphous metal nitrides, non-stoichiometric metal oxides, and non-stoichiometric metal nitrides, and metal particles from the particle donor layer are configured to migrate into the switching layer in response to a bias voltage between the first electrode and the second electrode.

11. The semiconductor device according to claim 10, wherein, When the bias voltage is applied, metal particles from the particle donor layer of the first two-terminal resistive switching device among the plurality of two-terminal resistive switching devices are configured to migrate into the switching layer of the first two-terminal resistive switching device among the plurality of two-terminal resistive switching devices, and reduce the intrinsic resistance of the switching layer of the first two-terminal resistive switching device among the plurality of two-terminal resistive switching devices.

12. The semiconductor device according to claim 1, wherein, The thickness of the particle donor layer of the first two-terminal resistive switching device among the multiple two-terminal resistive switching devices is in the range of 50 angstroms to 5000 angstroms.

13. The semiconductor device according to claim 1, wherein, The thickness of the switching layer of the first two-terminal resistive switching device among the multiple two-terminal resistive switching devices is in the range of 5 angstroms to 100 angstroms.

14. The semiconductor device according to claim 1, wherein, The first electrode of the first two-terminal resistive switching device among the multiple two-terminal resistive switching devices comprises a material selected from the group consisting of W, TiN, TaN, and TiW.

15. The semiconductor device according to claim 1, wherein The first electrode is connected to a plurality of first wires disposed along a first direction below the multiple two-terminal resistive switching devices.

16. The semiconductor device according to claim 15, wherein, The second electrode is connected to a plurality of second wires disposed along a second direction above the multiple two-terminal resistive switching devices.

17. The semiconductor device according to claim 16, wherein, The multiple two-terminal resistive switching devices are respectively disposed at cross regions between the plurality of first wires and the plurality of second wires.

18. The semiconductor device according to claim 1, wherein, The multiple two-terminal resistive switching devices include device technologies selected from the group consisting of resistive switching memories, magnetic switching memories, and phase change memories.

19. The semiconductor device according to claim 1, wherein, The intrinsic resistance of the switching layer is in the range of 100 kiloohms to 100 megaohms.

20. The semiconductor device according to claim 1, further comprising a multiplexer and a control circuit, the multiplexer and the control circuit being configured to selectively activate a subset of the dual-terminal resistive switching devices for an operation process and measure a result of the operation process, wherein, The correlation coefficient of the results of the operation process of any plurality of two-terminal resistive switching devices in the subset of the two-terminal resistive switching devices is in the range of -0.1 to 0.1.

Images