Display panel and display device

Abstract

A display panel and a display device, comprising: a substrate (10), a transistor array layer, a first planarization layer, a first electrode layer, and a plurality of sub-pixels including a first-color sub-pixel (spx1) and a second-color sub-pixel (spx2) adjacent to each other along a first direction (F1); for the first-color sub-pixel (spx1) and the second-color sub-pixel (spx2) adjacent to each other along the first direction (F1), one side of the anode (YG2) in the second-color sub-pixel (spx2) has a first recess (AX1) facing the side of the projection of the anode (YG1) in the first-color sub-pixel (spx1) on the substrate (10); and the first recess (AX1) is arranged towards the center of the main body of the second-color sub-pixel (spx2); each repeating unit (PX) includes at least one first-color sub-pixel (spx1) and at least one second-color sub-pixel (spx2); two adjacent repeating units (PX) have two first recesses (AX1) and two first vias (GK1); and, in the first direction (F1), the two first recesses (AX1) and the two first vias (GK1) of at least two adjacent repeating units (PX) are arranged in a straight line.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the continuous development of display technology, organic light emitting diode (OLED) display panels have been increasingly used in various electronic devices due to their advantages such as self-luminescence, wide viewing angle, high contrast, low power consumption, and high response speed. With the increasing requirements for OLED display panels, in order to achieve high-resolution design in display panels, OLED display panels usually adopt SPR pixel arrangement, that is, pixel borrowing method. Summary of the invention

[0003] The display panel provided by the embodiment of the present disclosure includes:

[0004] A substrate, comprising a plurality of sub-pixels:

[0005] A transistor array layer, located on the base substrate, and the transistor array layer includes an anode transfer portion located in each of the sub-pixels;

[0006] A first planar layer, located on a side of the transistor array layer away from the substrate;

[0007] A first electrode layer is located on a side of the first flat layer away from the base substrate, the first electrode layer includes an anode located in each of the sub-pixels; wherein the anode includes a main body portion and a via portion electrically connected to each other; and the via portion in each of the sub-pixels is electrically connected to the anode transfer portion through a first via hole; and the first via hole penetrates the first flat layer;

[0008] The plurality of sub-pixels include a first color sub-pixel and a second color sub-pixel adjacent to each other along a first direction; an orthographic projection of a first via hole in the first color sub-pixel on the base substrate is located between an orthographic projection of a main body portion in the first color sub-pixel and a main body portion in the second color sub-pixel on the base substrate;

[0009] For a first color sub-pixel and a second color sub-pixel adjacent to each other along the first direction, one side of the anode in the second color sub-pixel has a first recess on the side of the orthogonal projection of the substrate substrate facing the anode in the first color sub-pixel on the orthogonal projection of the substrate substrate; and the first recess is arranged toward the center of the main body of the second color sub-pixel;

[0010] The display panel comprises a plurality of repeating units, each of the repeating units comprises at least one first color sub-pixel and at least one second color sub-pixel;

[0011] Two adjacent ones of the repeating units each have at least two of the first recesses and two of the first vias; and, in the first direction, at least two adjacent ones of the repeating units have the two first recesses and the first vias arranged on the same straight line.

[0012] In some examples, in the same repeating unit, a positive projection of the first recess of the anode in the second color sub-pixel in the second direction covers a positive projection of the first via in the first color sub-pixel in the second direction.

[0013] In some examples, in the same sub-pixel, a positive projection of the via portion on the substrate covers a positive projection of the first via on the substrate;

[0014] The first recess is provided in a main body portion of the second color sub-pixel, and a positive projection of the first recess in the second direction covers a positive projection of the via portion in the first color sub-pixel in the second direction.

[0015] In some examples, an edge of a positive projection of the first recess on the substrate is substantially parallel to an edge of a positive projection of the via portion in the first color sub-pixel on the substrate.

[0016] In some examples, a first distance between an edge of a positive projection of the first recess on the substrate and an edge of a positive projection of the via portion in the first color sub-pixel on the substrate is 2.5 to 20 μm.

[0017] In some examples, the first color sub-pixel is a red sub-pixel, and the second color sub-pixel is a green sub-pixel;

[0018] The transistor array layer includes driving transistors located in respective ones of the sub-pixels; a positive projection of the anode in the green sub-pixel on the substrate and a positive projection of a channel region of the driving transistor in the red sub-pixel on the substrate have an overlapping region.

[0019] In some examples, a positive projection of the anode in the red sub-pixel on the substrate and positive projections of channel regions of the respective driving transistors on the substrate do not overlap.

[0020] In some examples, the transistor array layer includes: a plurality of scan lines, a plurality of reset lines, and a plurality of light emission control lines that are spaced apart from each other; wherein, one repeating unit corresponds to at least one of the scan lines, at least one of the reset lines, and at least one of the light emission control lines;

[0021] In one of the repeating units, the orthographic projection of the reset line on the substrate does not overlap with the orthographic projection of the anode in the red sub-pixel controlled by the reset line on the substrate, the orthographic projection of the emission control line on the substrate has an overlapping area with the orthographic projection of the anode in the green sub-pixel controlled by the emission control line on the substrate, and the orthographic projection of the scan line on the substrate does not overlap with the orthographic projections of the anodes controlled by the scan line on the substrate.

[0022] In some examples, the transistor array layer further includes an active layer of a conduction control transistor located in each of the sub-pixels; and in the same sub-pixel, the anode transfer portion is electrically connected to the conductive region of the active layer of the conduction control transistor through a second via hole.

[0023] The orthographic projections of the first via hole and the second via hole in the red sub-pixel on the substrate have a first overlapping area.

[0024] The orthographic projections of the first via hole and the second via hole in the green sub-pixel on the substrate have a second overlapping area.

[0025] The area of the first overlapping area is not greater than the area of the second overlapping area.

[0026] In some examples, the area of the first overlapping area is 0 - 0.9 μm; the area of the second overlapping area is 0 - 0.9 μm.

[0027] In some examples, the first color sub-pixel is a green sub-pixel, and the second color sub-pixel is a blue sub-pixel.

[0028] The orthographic projection of the anode in the blue sub-pixel on the substrate has an overlapping area with the orthographic projection of the channel region of the driving transistor in the green sub-pixel on the substrate.

[0029] In some examples, in the same blue sub-pixel, the orthographic projection of the anode on the substrate has an overlapping area with the orthographic projection of the channel region of the driving transistor on the substrate.

[0030] In some examples, for one of the repeating units, the orthographic projection of the emission control line controlling the repeating unit on the substrate has overlapping areas with the orthographic projections of the anodes in the blue sub-pixel and the green sub-pixel on the substrate respectively, and the orthographic projections of the reset line and the scan line controlling the repeating unit on the substrate do not overlap with the orthographic projections of the anodes on the substrate.

[0031] In some examples, the positive projection of the first via and the second via in the green sub-pixel on the substrate has a second overlapping area, and the positive projection of the first via and the second via in the blue sub-pixel on the substrate has a third overlapping area, and the area of the third overlapping area is 0 - 9 μm².

[0032] In some examples, the area of the third overlapping area is less than or equal to the area of the second overlapping area.

[0033] In some examples, the repeating unit further includes at least one third color sub-pixel;

[0034] The connection lines between the anodes in the adjacent first color sub-pixel, the second color sub-pixel, and the third color sub-pixel form a triangle.

[0035] In some examples, in the same repeating unit, the positive projection of the first via in the second color sub-pixel on the substrate is located between the positive projections of the via portion in the first color sub-pixel and the main body portion in the third color sub-pixel on the substrate, and the positive projections of the first via in the second color sub-pixel, the via portion in the first color sub-pixel, and the main body portion in the third color sub-pixel on the substrate are located on the same straight line, and the straight line is substantially parallel to the first direction.

[0036] In some examples, in the same repeating unit, the main body portion of the third color sub-pixel has a second recess on the side facing the positive projection of the first via in the second color sub-pixel in the positive projection on the substrate.

[0037] In some examples, in the same repeating unit, the positive projection of the second recess of the main body portion of the third color sub-pixel in the first direction and the positive projection of the first via in the second color sub-pixel in the first direction have at least an overlapping area.

[0038] In some examples, in the same repeating unit, the positive projection of the second recess of the main body portion of the third color sub-pixel in the first direction covers the positive projection of the first via in the second color sub-pixel in the first direction.

[0039] In some examples, in the same repeating unit, the positive projection of the second recess of the main body portion of the third color sub-pixel in the first direction covers the positive projection of the via portion in the second color sub-pixel in the first direction.

[0040] In some examples, the edge of the positive projection of the second recess on the substrate is substantially parallel to the edge of the main body portion of the second color sub-pixel in the positive projection on the substrate.

[0041] In some examples, a second distance between an edge of a positive projection of the second recess on the substrate substrate and an edge of a main body portion of the second color sub-pixel in the positive projection on the substrate substrate is 2.5 to 20 μm.

[0042] In some examples, a positive projection of a first via hole in the third color sub-pixel on the substrate substrate is located on a side of the positive projection of the second recess on the substrate substrate away from a positive projection of a via hole portion in the second color sub-pixel on the substrate substrate.

[0043] In some examples, the anode in the first color sub-pixel further includes a first connection portion electrically connected between the main body portion and the via hole portion;

[0044] The first connection portion extends along the first direction.

[0045] In some examples, the anode in the second color sub-pixel further includes a second connection portion electrically connected between the main body portion and the via hole portion;

[0046] The second connection portion extends along a third direction;

[0047] The third direction is different from both the first direction and the second direction.

[0048] In some examples, in the same repeating unit, positive projections of the anode in the third color sub-pixel on the substrate substrate respectively have overlapping regions with positive projections of a reset line and a light emission control line for controlling a pixel circuit in the repeating unit on the substrate substrate.

[0049] In some examples, the first via holes in the repeating units adjacent along the second direction are arranged in sequence substantially along the second direction.

[0050] In some examples, positive projections of the first via holes in the repeating units adjacent along the second direction overlap in the first direction.

[0051] The display panel provided by an embodiment of the present disclosure includes:

[0052] A substrate substrate, including a plurality of sub-pixels:

[0053] A transistor array layer, located on the substrate substrate, and the transistor array layer includes anode transfer portions located in each of the sub-pixels;

[0054] A first planar layer, located on a side of the transistor array layer away from the substrate substrate;

[0055] A first electrode layer, located on a side of the first flat layer away from the base substrate, the first electrode layer includes an anode located in each of the sub-pixels, and the anode in each of the sub-pixels is electrically connected to the anode transfer portion through a first via hole; the first via hole penetrates the first flat layer; each of the anodes includes a main body portion and a via hole portion;

[0056] A pixel defining layer is located on a side of the first electrode layer away from the base substrate; the pixel defining layer includes an opening located in each of the sub-pixels, and in the same sub-pixel, the orthographic projection of the opening on the base substrate is located within the orthographic projection of the anode on the base substrate;

[0057] The plurality of sub-pixels include a third color sub-pixel; in the third color sub-pixel, the opening is facing the orthographic projection of the base substrate, and the first via hole in the third color sub-pixel has an opening recess on one side of the orthographic projection of the base substrate;

[0058] In the third color sub-pixel, the main body of the anode has a third recess on one side of the orthographic projection of the substrate substrate facing the first via hole of the anode of the third color sub-pixel, and the third recess is substantially parallel to the opening recess.

[0059] In some examples, in the third color sub-pixel, an orthographic projection of the opening recess in the first direction covers an orthographic projection of the first via hole in the first direction.

[0060] In some examples, in the third color sub-pixel, an edge of the orthographic projection of the opening recess on the base substrate is substantially parallel to an edge of the orthographic projection of the first via hole on the base substrate.

[0061] In some examples, in the third color sub-pixel, a third distance between an edge of an orthographic projection of the opening recess on the base substrate and an edge of an orthographic projection of the first via hole on the base substrate is 2.25-20 μm.

[0062] In some examples, in the third color sub-pixel, an edge of an orthographic projection of the third recess on the base substrate overlaps an edge of an orthographic projection of the opening recess on the base substrate.

[0063] In some examples, the plurality of sub-pixels further include: a first color sub-pixel and a second color sub-pixel;

[0064] In at least one of the first color sub-pixel and the second color sub-pixel, the orthographic projection of the opening on the base substrate is a rectangle.

[0065] In some examples, the area of the opening in the third color sub-pixel is larger than the area of the opening in the second color sub-pixel;

[0066] The area of the opening in the second color sub-pixel is larger than the area of the opening in the first color sub-pixel.

[0067] The display device provided by an embodiment of the present disclosure further includes the above display panel. Description of the Drawings

[0068] Figure 1 It is a schematic structural diagram of the display panel provided by an embodiment of the present disclosure;

[0069] Figure 2a It is a schematic structural diagram of the pixel circuit provided by an embodiment of the present disclosure;

[0070] Figure 2b It is a signal timing diagram provided by an embodiment of the present disclosure;

[0071] Figure 3 It is a schematic layout structure diagram of the display panel provided by an embodiment of the present disclosure;

[0072] Figure 4a It is a schematic diagram of some active semiconductor layers provided by an embodiment of the present disclosure;

[0073] Figure 4b It is a schematic diagram of some gate conductive layers provided by an embodiment of the present disclosure;

[0074] Figure 4c It is a schematic diagram of some reference conductive layers provided by an embodiment of the present disclosure;

[0075] Figure 4d It is a schematic diagram of some source-drain metal layers provided by an embodiment of the present disclosure;

[0076] Figure 4e It is a schematic diagram of some first electrode layers provided by an embodiment of the present disclosure;

[0077] Figure 4f It is a schematic diagram of some first electrode layers and spacer layers provided by an embodiment of the present disclosure;

[0078] Figure 5a It is a schematic diagram of some stacked structures of an active semiconductor layer and a gate conductive layer provided by an embodiment of the present disclosure;

[0079] Figure 5b It is a schematic diagram of some stacked structures of an active semiconductor layer, a gate conductive layer, and a reference conductive layer provided by an embodiment of the present disclosure;

[0080] Figure 5cSome schematic diagrams of the active semiconductor layer, gate conductive layer, reference conductive layer, and source-drain metal layer provided by the embodiments of the present disclosure;

[0081] Figure 5d Some schematic diagrams of the active semiconductor layer, gate conductive layer, reference conductive layer, source-drain metal layer, and spacer layer provided by the embodiments of the present disclosure;

[0082] Figure 6 Some schematic diagrams of other first electrode layers provided by the embodiments of the present disclosure. Detailed implementation manners

[0083] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. And, without conflict, the embodiments and features in the embodiments of the present disclosure may be combined with each other. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0084] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the ordinary meanings understood by those of ordinary skill in the art to which the present disclosure pertains. The "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. The terms such as "include" or "comprise" mean that the elements or items appearing before the term cover the elements or items listed after the term and their equivalents, without excluding other elements or items. The terms such as "connect" or "couple" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0085] It should be noted that the sizes and shapes of the various figures in the drawings do not reflect the true proportions, and the purpose is only to schematically illustrate the content of the present invention. And, the same or similar reference numerals represent the same or similar elements or elements having the same or similar functions throughout.

[0086] As Figure 1 shown, the display panel provided by the embodiments of the present disclosure may include: a substrate substrate 10. A plurality of sub-pixels spx located on the substrate substrate 10. Exemplarily, the plurality of sub-pixels may include red sub-pixels, green sub-pixels, and blue sub-pixels. In this way, the display panel can mix light using the red sub-pixels, green sub-pixels, and blue sub-pixels to achieve color display. Of course, the embodiments of the present disclosure include but are not limited to this.

[0087] Exemplarily, in combination withFigure 1 As shown in Figure 2a , at least one sub-pixel spx (e.g., each sub-pixel) among multiple sub-pixels spx may include: a pixel circuit 0121 and a light-emitting element 0120. Among them, the pixel circuit 0121 has transistors and capacitors, and generates an electrical signal through the interaction of the transistors and capacitors. The generated electrical signal is input into the anode of the light-emitting element 0120. And by applying a corresponding voltage to the cathode of the light-emitting element 0120, the light-emitting element 0120 can be driven to emit light.

[0088] As shown in Figure 2a , the pixel circuit 0121 may include: a driving control circuit 0122, a first light-emitting control circuit 0123, a second light-emitting control circuit 0124, a data writing circuit 0126, a storage circuit 0127, a threshold compensation circuit 0128, and a reset circuit 0129.

[0089] The driving control circuit 0122 may include a control terminal, a first terminal, and a second terminal. And the driving control circuit 0122 is configured to provide a driving current for driving the light-emitting element 0120 to emit light. For example, the first light-emitting control circuit 0123 is connected to the first terminal of the driving control circuit 0122 and the first voltage terminal VDD. And the first light-emitting control circuit 0123 is configured to realize the connection conduction or disconnection between the driving control circuit 0122 and the first voltage terminal VDD.

[0090] The second light-emitting control circuit 0124 is electrically connected to the second terminal of the driving control circuit 0122 and the anode of the light-emitting element 0120. And the second light-emitting control circuit 0124 is configured to realize the connection conduction or disconnection between the driving control circuit 0122 and the light-emitting element 0120.

[0091] The data writing circuit 0126 is electrically connected to the first terminal of the driving control circuit 0122. And the data writing circuit 0126 is configured to write the signal on the data line VD into the storage circuit 0127.

[0092] The storage circuit 0127 is electrically connected to the control terminal of the driving control circuit 0122 and the first voltage terminal VDD. And the storage circuit 0127 is configured to store data signals and information of the driving control circuit 0122.

[0093] The threshold compensation circuit 0128 is respectively electrically connected to the control terminal and the second terminal of the driving control circuit 0122. And the threshold compensation circuit 0128 is configured to perform threshold compensation on the driving control circuit 0122.

[0094] ​​​​The reset circuit 0129 is also electrically connected to the control terminal of the drive control circuit 0122 and the anode of the light-emitting element 0120 respectively. And the reset circuit 0129 is configured to reset the anode of the light-emitting element 0120 and the control terminal of the drive control circuit 0122.

[0095] Among them, the light-emitting element 0120 can be set as an electroluminescent diode, such as at least one of OLED, QLED, micro LED, and mini OLED. Among them, the light-emitting element 0120 can include an anode, a light-emitting layer, and a cathode arranged in a stacked manner. Further, the light-emitting layer can also include film layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. Of course, in practical applications, the light-emitting element 0120 can be designed and determined according to the requirements of the actual application environment, which is not limited here.

[0096] Exemplarily, in combination with Figure 2a As shown, the drive control circuit 0122 includes: a drive transistor T1. The control terminal of the drive control circuit 0122 includes the gate of the drive transistor T1. The first terminal of the drive control circuit 0122 includes the first pole of the drive transistor T1. The second terminal of the drive control circuit 0122 includes the second pole of the drive transistor T1.

[0097] Exemplarily, in combination with Figure 2a As shown, the data writing circuit 0126 includes a data writing transistor T2. The storage circuit 0127 includes a storage capacitor CST. The threshold compensation circuit 0128 includes a threshold compensation transistor T3. The first light emission control circuit 0123 includes a light emission control transistor T4. The second light emission control circuit 0124 includes a conduction control transistor T5. The reset circuit 0129 includes an initialization transistor T6 and a reset transistor T7.

[0098] Specifically, the first pole of the data writing transistor T2 is electrically connected to the first pole of the drive transistor T1. The second pole of the data writing transistor T2 is configured to be electrically connected to the data line VD to receive a data signal. The gate of the data writing transistor T2 is configured to be electrically connected to the scan line GA to receive a signal.

[0099] The first pole of the storage capacitor CST is electrically connected to the first power supply terminal VDD. The second pole of the storage capacitor CST is electrically connected to the gate of the drive transistor T1.

[0100] The first pole of the threshold compensation transistor T3 is electrically connected to the second pole of the drive transistor T1. The second pole of the threshold compensation transistor T3 is electrically connected to the gate of the drive transistor T1. The gate of the threshold compensation transistor T3 is configured to be electrically connected to the scan line GA to receive a signal.

[0101] The first pole of the initialization transistor T6 is configured to be electrically connected to the initialization line VINIT to receive a reset signal. The second pole of the initialization transistor T6 is electrically connected to the gate of the driving transistor T1. The gate of the initialization transistor T6 is configured to be electrically connected to the reset line RST to receive a signal.

[0102] The first pole of the reset transistor T7 is configured to be electrically connected to the initialization line VINIT to receive a reset signal. The second pole of the reset transistor T7 is electrically connected to the anode of the light-emitting element 0120. The gate of the reset transistor T7 is configured to be electrically connected to the reset line RST to receive a signal.

[0103] The first pole of the light-emitting control transistor T4 is electrically connected to the first power supply terminal VDD. The second pole of the light-emitting control transistor T4 is electrically connected to the first pole of the driving transistor T1. The gate of the light-emitting control transistor T4 is configured to be electrically connected to the light-emitting control line EM to receive a light-emitting control signal.

[0104] The first pole of the conduction control transistor T5 is electrically connected to the second pole of the driving transistor T1. The second pole of the conduction control transistor T5 is electrically connected to the anode of the light-emitting element 0120. The gate of the conduction control transistor T5 is configured to be electrically connected to the light-emitting control line EM to receive a light-emitting control signal.

[0105] The cathode of the light-emitting element 0120 is electrically connected to the second power supply terminal VSS. Herein, the first pole and the second pole of the above transistors can be determined as the source or the drain according to the actual application, and are not limited herein.

[0106] Exemplarily, one of the first power supply terminal VDD and the second power supply terminal VSS is a high voltage terminal, and the other is a low voltage terminal. For example, in the embodiment shown as Figure 2a In the shown embodiment, the first power supply terminal VDD is a voltage source to output a constant first voltage. For example, the first voltage is a positive voltage; and the second power supply terminal VSS can be a voltage source to output a constant second voltage. For example, the second voltage is 0 or a negative voltage, etc. For example, in some examples, the second power supply terminal VSS can be grounded.

[0107] Figure 2a The signal timing diagram corresponding to the pixel circuit shown as Figure 2b is shown as follows. During one frame display time, the working process of the pixel circuit has three stages: the T10 stage, the T20 stage, and the T30 stage. Herein, rst represents the signal transmitted on the reset line RST, ga represents the signal transmitted on the scan line GA, and em represents the signal transmitted on the light-emitting control line EM.

[0108] In the T10 stage, the signal rst controls the initialization transistor T6 to conduct, so that the signal transmitted on the initialization line VINIT can be provided to the gate of the driving transistor T1 to reset the gate of the driving transistor T1. The signal rst controls the reset transistor T7 to conduct, so that the signal transmitted on the initialization line VINIT can be provided to the anode of the light-emitting element 0120 to reset the anode of the light-emitting element 0120. Also, in this stage, the signal ga controls both the data writing transistor T2 and the threshold compensation transistor T3 to be cut off. The signal em controls both the light-emitting control transistor T4 and the conduction control transistor T5 to be cut off.

[0109] In the T20 stage, the signal ga controls the data writing transistor T2 and the threshold compensation transistor T3 to conduct. The conducting data writing transistor T2 charges the gate of the driving transistor T1 with the data signal transmitted on the data line VD, so that the voltage of the gate of the driving transistor T1 becomes: Vdata + Vth. Here, Vth represents the threshold voltage of the driving transistor T1, and Vdata represents the voltage of the data signal. Also, in this stage, the signal rst controls both the initialization transistor T6 and the reset transistor T7 to be cut off. The signal em controls both the light-emitting control transistor T4 and the conduction control transistor T5 to be cut off.

[0110] In the T30 stage, the signal em controls both the light-emitting control transistor T4 and the conduction control transistor T5 to conduct. The conducting light-emitting control transistor T4 provides the voltage Vdd of the first power supply terminal VDD to the first pole of the driving transistor T1, so that the voltage of the first pole of the driving transistor T1 is Vdd. The driving transistor T1 generates a driving current according to its gate voltage Vdata + |Vth| and the voltage Vdd of the first pole. This driving current is provided to the light-emitting element 0120 through the conducting conduction control transistor T5 to drive the light-emitting element 0120 to emit light. Also, in this stage, the signal rst controls the initialization transistor T6 and the reset transistor T7 to be cut off. The signal ga controls the data writing transistor T2 and the threshold compensation transistor T3 to be cut off.

[0111] It should be noted that in the embodiments of the present disclosure, the first pole of the above transistor can be its source electrode, and the second pole can be its drain electrode; or the first pole can be its drain electrode and the second pole can be its source electrode, which can be designed and determined according to the requirements of actual applications. Also, the pixel circuit in the sub-pixel can be Figure 2a and Figure 2b In addition to the structures shown, it can also be a structure including other numbers of transistors, and the embodiments of the present disclosure do not limit this. The following takes Figure 2a the structure shown as an example for illustration.

[0112] Exemplarily, the display panel includes a substrate substrate 10, a transistor array layer disposed on the substrate substrate 10, a first planar layer on a side of the transistor array layer away from the substrate substrate 10, a first electrode layer on a side of the first planar layer away from the substrate substrate 10, a pixel defining layer on a side of the first electrode layer away from the substrate substrate 10, a light-emitting layer on a side of the pixel defining layer away from the substrate substrate 10, and a cathode on a side of the light-emitting layer away from the substrate substrate 10. Among them, the transistor array layer can be used to form transistors and capacitors in the pixel circuit, as well as to form scan lines, reset lines, light emission control lines EM, initialization lines VINIT, a first power signal line VDD electrically connected to the first power supply terminal VDD, and the like. Exemplarily, the transistor array layer may include an active semiconductor layer 0310, a gate conductive layer 0320, a reference conductive layer 0330, and a source-drain metal layer 0340.

[0113] Exemplarily, as Figure 3 shown in Figure 4a FIG. shows the active semiconductor layer 0310 of the pixel circuit 0121. The active semiconductor layer 0310 can be formed by patterning using a semiconductor material. The active semiconductor layer 0310 can be used to fabricate the driving active layer T1-A of the driving transistor T1, the active layer T2-A of the data writing transistor T2, the active layer T3-A of the threshold compensation transistor T3, the active layer T4-A of the light emission control transistor T4, the active layer T5-A of the conduction control transistor T5, the active layer T6-A of the initialization transistor T6, and the active layer T7-A of the reset transistor T7. Each active layer may include a source region, a drain region, and a channel region between the source region and the drain region. For example, the active layers of the respective transistors are integrally provided.

[0114] Exemplarily, the active semiconductor layer 0310 can be fabricated using amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the above-mentioned source region and drain region can be regions doped with n-type impurities or p-type impurities.

[0115] Exemplarily, a gate insulating layer is formed on the above-mentioned active semiconductor layer 0310 to protect the above-mentioned active semiconductor layer 0310. As Figure 3 shown in Figure 4b FIG. Figure 5aAs shown, the gate conductive layer 0320 of the pixel circuit 0121 is shown. The gate conductive layer 0320 is disposed on the side of the gate insulating layer away from the substrate 10, so as to be insulated from the active semiconductor layer 0310. The gate conductive layer 0320 may include the second pole cc2 of the storage capacitor CST, the scan line GA, the reset line RST, the emission control line EM, the protrusion TB, and the gates T2-G of the data writing transistor T2, the gate T3-G of the threshold compensation transistor T3, the gate T4-G of the emission control transistor T4, the gate T5-G of the conduction control transistor T5, the gate T6-G of the initialization transistor T6, and the gate T7-G of the reset transistor T7. Among them, the protruding part of the scan line GA forms the protrusion TB. Among them, one repeating unit corresponds to at least one scan line GA, at least one reset line RST, and at least one emission control line EM. For example, one repeating unit may correspond to one scan line GA, one reset line RST, and one emission control line EM.

[0116] For example, as Figure 4b shown, the gate T2-G of the data writing transistor T2 may be the overlapping part of the scan line GA and the active semiconductor layer 0310, the gate T4-G of the emission control transistor T4 may be the first overlapping part of the emission control line EM and the active semiconductor layer 0310, the gate T5-G of the conduction control transistor T5 may be the second overlapping part of the emission control line EM and the active semiconductor layer 0310, the gate T6-G of the initialization transistor T6 is the first overlapping part of the reset line RST and the active semiconductor layer 0310, the gate T7-G of the reset transistor T7 is the second overlapping part of the reset line RST and the active semiconductor layer 0310, the threshold compensation transistor T3 may be a thin film transistor with a double gate structure, the first gate of the threshold compensation transistor T3 may be the overlapping part of the scan line GA and the active semiconductor layer 0310, and the second gate of the threshold compensation transistor T3 may be the overlapping part of the protrusion TB protruding from the scan line GA and the active semiconductor layer 0310. As Figure 3 With Figure 4b shown, the second pole cc2 of the storage capacitor CST is multiplexed as the gate of the driving transistor T1.

[0117] It should be noted that Figure 5a the dotted lines in

[0118] Exemplarily, as Figure 3 With Figure 4bAs shown, the scan line GA, the reset line RST, and the emission control line EM are arranged along the first direction F1. And the scan line GA, the reset line RST, and the emission control line EM extend substantially along the second direction F2. Exemplarily, the orthographic projection of the scan line GA on the substrate 10 is located between the orthographic projection of the reset line RST on the substrate 10 and the orthographic projection of the emission control line EM on the substrate 10. Exemplarily, Figure 3 Only taking the first direction F1 as the column direction and the second direction F2 as the row direction as an example for illustration. In specific implementation, the first direction F1 can also be the row direction, and the second direction F2 can also be the column direction, which is not limited herein.

[0119] Exemplarily, in the first direction F1, the second pole cc2 of the storage capacitor CST is located between the scan line GA and the emission control line EM. And, the protruding portion TB protruding from the scan line GA is located on the side of the scan line GA away from the emission control line EM. The protruding portion TB protrudes from the scan line GA in the direction opposite to the arrow of the first direction F1.

[0120] Exemplarily, an interlayer dielectric layer is formed on the above-mentioned gate conductive layer 0320 to protect the above-mentioned gate conductive layer 0320. As Figure 3 、 Figure 4c And Figure 5b As shown, the reference conductive layer 0330 of the pixel circuit 120a is shown. The reference conductive layer 0330 includes the first pole cc1 of the storage capacitor CST, the initialization line VINIT, and the light shielding layer ZG. Among them, the first pole cc1 of the storage capacitor CST and the second pole cc2 of the storage capacitor CST overlap at least partially to form the storage capacitor CST. Exemplarily, the first pole cc1 of the storage capacitor CST has a hollowed-out area LQ, and the orthographic projection of the hollowed-out area LQ on the substrate 10 may have an overlapping area with the orthographic projection of the second pole cc2 of the storage capacitor CST on the substrate 10.

[0121] Exemplarily, as Figure 3 、 Figure 4c And Figure 5b As shown, the orthographic projection of the light shielding layer ZG on the substrate 10 overlaps with the drain region of the initialization transistor T6 in the active semiconductor layer 0310 (that is, the side where the drain region of the initialization transistor T6 is electrically connected to the gate of the driving transistor T1) in the orthographic projection on the substrate 10. This can reduce the influence of light on the initialization transistor T6 and improve the reset accuracy.

[0122] Exemplarily, as Figure 3 、 Figure 4c And Figure 5bAs shown, the threshold compensation transistor T3 is a double-gate transistor. For example, the light-shielding layer ZG shields the active layer portion between the two gates of the threshold compensation transistor T3. Since the threshold compensation transistor T3 is directly connected to the driving transistor T1, it can play a role in stabilizing the operating state of the driving transistor T1.

[0123] Exemplarily, an interlayer insulating layer is formed on the above-mentioned reference conductive layer 0330 to protect the above-mentioned reference conductive layer 0330. As Figure 3 、 Figure 4d and Figure 5c shown, the source-drain metal layer 0340 of the pixel circuit 0121 is shown. The source-drain metal layer 0340 is located on the side of the interlayer insulating layer away from the substrate 10. Among them, the source-drain metal layer 0340 may include a first power supply signal line VDD, a data line VD, a first transfer portion ZB1, a second transfer portion ZB2, and an anode transfer portion YZ. Exemplarily, each sub-pixel spx includes a first transfer portion ZB1, a second transfer portion ZB2, and an anode transfer portion YZ.

[0124] Exemplarily, as Figure 3 、 Figure 4d and Figure 5c shown, in the same sub-pixel, the anode transfer portion YZ is electrically connected to the conductive region of the active layer of the conduction control transistor through a second via GK2. Among them, the second via GK2 penetrates the interlayer insulating layer, the interlayer dielectric layer, and the gate insulating layer.

[0125] Exemplarily, as Figure 3 、 Figure 4d and Figure 5c shown, the first end of the first transfer portion ZB1 is electrically connected to the initialization line VINIT through a via TK01, and the second end of the first transfer portion ZB1 is electrically connected to the source region of the initialization transistor T6 in the active semiconductor layer 0310 (such as the source region of the initialization transistor T6 and the source region of the reset transistor T7 in the active semiconductor layer 0310 being an integrated structure) through a via TK02. Among them, the via TK01 penetrates the interlayer insulating layer. The via TK02 penetrates the interlayer insulating layer, the interlayer dielectric layer, and the gate insulating layer.

[0126] Exemplarily, as Figure 3 、 Figure 4d and Figure 5cAs shown, the first end of the second transfer portion ZB2 is electrically connected through the through-hole TK03 to the drain region of the initialization transistor T6 in the active semiconductor layer 0310 (the drain region of the initialization transistor T6 is electrically connected to the gate of the driving transistor), and the second end of the second transfer portion ZB2 is electrically connected through the through-hole TK04 to the second pole cc2 of the storage capacitor CST (i.e., the gate of the driving transistor). Among them, the through-hole TK03 penetrates the interlayer insulating layer, the interlayer dielectric layer, and the gate insulating layer. The through-hole TK04 penetrates the interlayer insulating layer and the interlayer dielectric layer.

[0127] Exemplarily, as Figure 3 , Figure 4d and Figure 5c shown, the anode transfer portion YZ is electrically connected through the second via GK2 to the drain region of the second light-emitting control circuit 0124 in the active semiconductor layer 0310. Among them, the second via GK2 penetrates the interlayer insulating layer, the interlayer dielectric layer, and the gate insulating layer.

[0128] Exemplarily, as Figure 3 , Figure 4d and Figure 5c shown, the data line VD is electrically connected through the through-hole TK05 to the source region of the data writing transistor T2 in the active semiconductor layer 0310. Among them, the through-hole TK05 penetrates the interlayer insulating layer, the interlayer dielectric layer, and the gate insulating layer.

[0129] Exemplarily, as Figure 3 , Figure 4d and Figure 5c shown, the first power supply signal line VDD is electrically connected through the through-hole TK06 to the source region of the light-emitting control transistor T4 in the active semiconductor layer 0310. Among them, the through-hole TK06 penetrates the interlayer insulating layer, the interlayer dielectric layer, and the gate insulating layer.

[0130] Exemplarily, as Figure 3 , Figure 4d and Figure 5c shown, the first power supply signal line VDD and the data line VD are arranged along the second direction F2, and the first power supply signal line VDD and the data line VD extend substantially along the first direction F1. It should be noted that in the actual process, due to process conditions or other factors such as wiring or via setting, as long as the extension directions of the first power supply signal line VDD and the data line VD generally meet the above conditions, they all fall within the protection scope of the present invention.

[0131] Exemplarily, an auxiliary insulating layer may also be formed on the above source-drain metal layer 0340 for protecting the above source-drain metal layer 0340. An auxiliary conductive layer may also be formed on the side of the auxiliary insulating layer away from the substrate 10, so that the auxiliary conductive layer can be electrically connected to the first power supply signal line VDD to reduce the resistance of the first power supply signal line VDD.

[0132] Exemplarily, a first planar layer is formed on the source-drain metal layer 0340 to protect the source-drain metal layer 0340. Exemplarily, as Figure 3 and Figure 4e as well as Figure 5d As shown, a first electrode layer is formed on the first flat layer. The first electrode layer includes an anode located in each sub-pixel. The anode in each sub-pixel is electrically connected to the anode transition part YZ through a first via hole GK1. Moreover, the first via hole GK1 penetrates the first flat layer.

[0133] For example, Figure 1 and Figure 4e As shown, the plurality of sub-pixels include a first color sub-pixel spx1 and a second color sub-pixel spx2 adjacent along a first direction F1; wherein the first color sub-pixel spx1 includes an anode YG1, and the second color sub-pixel spx2 includes an anode YG2. The orthographic projection of the first via hole GK1 in the first color sub-pixel spx1 on the substrate 1000 is located between the main body ZT1 in the first color sub-pixel spx1 and the main body ZT2 in the second color sub-pixel on the substrate 1000. Exemplarily, for the first color sub-pixel spx1 and the second color sub-pixel spx2 adjacent along the first direction F1, one side of the anode in the second color sub-pixel spx2 has a first recess AX1 on the orthographic projection side of the substrate 10 facing the anode in the first color sub-pixel spx1 on the substrate 10. And the first recess AX1 is arranged toward the center of the main body of the second color sub-pixel spx2. Further, the display panel includes a plurality of repeating units PX; each repeating unit PX includes at least one first color sub-pixel spx1 and at least one second color sub-pixel spx2. For example, each repeating unit PX includes a first color sub-pixel spx1 and a second color sub-pixel spx2 adjacent to each other along a first direction F1, and two adjacent repeating units have two first recesses AX1 and two first via holes GK1; and, in the first direction F1, at least two adjacent repeating units have two first recesses AX1 and two first via holes GK1 arranged on the same straight line. For example, the first color sub-pixel spx1 is a red sub-pixel, and the second color sub-pixel spx2 is a green sub-pixel, then the red sub-pixel and the green sub-pixel are adjacent to each other along the first direction F1. And, for the red sub-pixel and the green sub-pixel adjacent to each other along the first direction F1, the anode in the green sub-pixel has a first recess AX1 on the side of the orthogonal projection of the substrate substrate 10 facing the anode in the red sub-pixel on the side of the orthogonal projection of the substrate substrate 10.

[0134] For example, Figure 1 and Figure 4eAs shown, the schematic layout structure diagrams of the pixel circuits included in each sub-pixel are arranged in an array in the first direction and the second direction. That is to say, the layout structures of the pixel circuits included in each sub-pixel are periodically arranged in the row direction and the column direction. Further, a plurality of repeating units PX are arranged in the second direction F2 to form a repeating unit group PXZ, and the repeating unit group PXZ is arranged in the first direction F1. And, the repeating unit includes a first color sub-pixel spx1 and a second color sub-pixel spx2 arranged in sequence in the first direction F1. The anode in the second color sub-pixel spx2 has a first recess AX1 on the side of the positive projection of the anode in the first color sub-pixel spx1 on the substrate 10. That is to say, the first recess AX1 is provided in the main body portion ZT2 of the second color sub-pixel spx2. For example, the first color sub-pixel spx1 is a red sub-pixel, and the second color sub-pixel spx2 is a green sub-pixel. In the same repeating unit, the anode in the green sub-pixel has a first recess AX1 on the side of the positive projection of the anode in the red sub-pixel on the substrate 10. For example, one repeating unit group PXZ can correspond to a scan line GA, a reset line RST, and an emission control line EM.

[0135] Exemplarily, as Figure 1 With Figure 4e shown, the repeating unit further includes at least one third color sub-pixel spx3. For example, the repeating unit may include one third color sub-pixel spx3. Among them, the connection lines between the anodes of the adjacent first color sub-pixel spx1, second color sub-pixel spx2, and third color sub-pixel form a triangle. For example, the first color sub-pixel spx1 is a red sub-pixel, the second color sub-pixel spx2 is a green sub-pixel, and the third color sub-pixel spx3 is a blue sub-pixel. In the same repeating unit, the connection lines between the anodes of the red sub-pixel, green sub-pixel, and blue sub-pixel form a triangle.

[0136] Exemplarily, as Figure 3 With Figure 4eAs shown, the anode may include a main body and a via portion electrically connected to each other; wherein the orthographic projection of the via portion on the substrate 10 covers the orthographic projection of the first via GK1 on the substrate 10, and in each sub-pixel, the via portion is electrically connected to the anode transition portion YZ through the first via GK1. Exemplarily, the anode YG1 in the first color sub-pixel spx1 may also include a first connection portion LB1 electrically connected between the main body ZT1 and the via portion GB1, that is, the main body ZT1 in the first color sub-pixel spx1 is electrically connected to the via portion GB1 through the first connection portion LB1. The anode YZ2 in the second color sub-pixel spx2 also includes a second connection portion LB2 electrically connected between the main body ZT2 and the via portion GB2, that is, the main body ZT2 in the second color sub-pixel spx2 is electrically connected to the via portion GB2 through the second connection portion LB2. The main body ZT3 in the third color sub-pixel spx3 is directly electrically connected to the via portion GB3. For example, if the first color sub-pixel spx1 is a red sub-pixel, the main body of the red sub-pixel is electrically connected to the via portion through the first connection portion. If the second color sub-pixel spx2 is a green sub-pixel, the main body of the green sub-pixel is electrically connected to the via portion through the second connection portion. If the third color sub-pixel spx3 is a blue sub-pixel, the main body of the blue sub-pixel is directly electrically connected to the via portion.

[0137] For example, Figure 3 and Figure 4e As shown, the first connection portion extends along the first direction F1. The second connection portion extends along the third direction F3. The third direction F3 is different from the first direction F1 and the second direction F2. For example, the third direction F3 has an angle with the first direction F1 and the second direction F2, respectively, so that the second connection portion can extend obliquely upward.

[0138] For example, Figure 3 and Figure 4e As shown, in the same repeating unit, the main body of the third color sub-pixel spx3 has a second recess AX2 on the side of the orthogonal projection of the substrate substrate 10 facing the first via GK1 in the second color sub-pixel spx2 on the side of the orthogonal projection of the substrate substrate 10. For example, the first color sub-pixel spx1 is a red sub-pixel, the second color sub-pixel spx2 is a green sub-pixel, and the third color sub-pixel spx3 is a blue sub-pixel. In the same repeating unit, the main body of the blue sub-pixel has a second recess AX2 on the side of the orthogonal projection of the substrate substrate 10 facing the first via GK1 in the green sub-pixel on the side of the orthogonal projection of the substrate substrate 10.

[0139] For example, Figure 3 and Figure 4eAs shown, in the same repeating unit, the orthographic projection of the first via GK1 in the first color sub-pixel spx1 on the substrate 10 is located between the orthographic projection of the anode YZ1 in the first color sub-pixel spx1 and the orthographic projection of the anode YZ2 in the second color sub-pixel spx2 on the substrate 10.

[0140] Exemplarily, as Figure 3 With Figure 4e shown, in the same repeating unit, the orthographic projection of the first via GK1 in the second color sub-pixel spx2 on the substrate 10 is located between the orthographic projection of the via portion GB1 in the first color sub-pixel spx1 and the orthographic projection of the main body portion ZT3 in the third color sub-pixel spx3 on the substrate 10. And the orthographic projections of the first via GK1 in the second color sub-pixel spx2, the via portion GB1 in the first color sub-pixel spx1, and the main body portion ZT3 in the third color sub-pixel spx3 on the substrate 1000 are located on the same straight line, and this straight line can be substantially parallel to the first direction F1.

[0141] Exemplarily, as Figure 3 With Figure 4e shown, in the same repeating unit, the orthographic projection of the first via GK1 in the third color sub-pixel spx3 on the substrate 10 is located on the side of the orthographic projection of the second recess AX2 on the substrate 10 away from the orthographic projection of the via portion GB2 in the second color sub-pixel spx2 on the substrate 10. For example, the second color sub-pixel spx2 is a green sub-pixel, the first color sub-pixel spx1 is a red sub-pixel, and the third color sub-pixel spx3 is a blue sub-pixel. In the same repeating unit, the orthographic projection of the first via GK1 in the red sub-pixel on the substrate 10 is located between the orthographic projection of the anode in the red sub-pixel and the orthographic projection of the anode in the green sub-pixel on the substrate 10. The orthographic projection of the first via GK1 in the green sub-pixel on the substrate 10 is located between the orthographic projection of the via portion in the red sub-pixel and the orthographic projection of the main body portion in the blue sub-pixel on the substrate 10. The orthographic projection of the first via GK1 in the blue sub-pixel on the substrate 10 is located on the side of the orthographic projection of the second recess AX2 on the substrate 10 away from the orthographic projection of the via portion in the green sub-pixel on the substrate 10.

[0142] Exemplarily, as Figure 3 With Figure 4eAs shown, in the same repeating unit, the positive projection of the first recess AX1 of the anode in the second color sub-pixel spx2 in the second direction F2 and the positive projection of the first via GK1 in the first color sub-pixel spx1 in the second direction F2 have at least an overlapping area; wherein, the first direction F1 is different from the second direction F2. For example, the first color sub-pixel spx1 is a red sub-pixel, the second color sub-pixel spx2 is a green sub-pixel, and the third color sub-pixel spx3 is a blue sub-pixel. In the same repeating unit, the positive projection of the first recess AX1 of the anode in the green sub-pixel in the second direction F2 and the positive projection of the first via GK1 in the red sub-pixel in the second direction F2 have at least an overlapping area. It should be noted that the positive projection in the second direction F2 refers to the line projection of the first recess AX1 of the anode of the green sub-pixel and the first via GK1 in the red sub-pixel on the straight line in the second direction F2, and the line projection lengths of the two overlap. In this application, the positive projection in the first or second direction refers to the line projection on the straight line in the first direction or the second direction.

[0143] Exemplarily, as Figure 3 with Figure 4e As shown, in the same repeating unit, the positive projection of the second recess AX2 of the main body in the third color sub-pixel spx3 in the first direction F1 and the positive projection of the first via GK1 in the second color sub-pixel spx2 in the first direction F1 have at least an overlapping area. For example, the first color sub-pixel spx1 is a red sub-pixel, the second color sub-pixel spx2 is a green sub-pixel, and the third color sub-pixel spx3 is a blue sub-pixel. In the same repeating unit, the positive projection of the second recess AX2 of the main body in the blue sub-pixel in the first direction F1 and the positive projection of the first via GK1 in the green sub-pixel in the first direction F1 have at least an overlapping area.

[0144] Exemplarily, as Figure 3 with Figure 4e As shown, in the same repeating unit, the positive projection of the first recess AX1 of the anode in the second color sub-pixel spx2 in the second direction F2 covers the positive projection of the first via GK1 in the first color sub-pixel spx1 in the second direction F2. The positive projection of the first recess AX1 of the anode in the second color sub-pixel spx2 in the second direction F2 covers the positive projection of the via portion GB1 in the first color sub-pixel spx1 in the second direction F2. For example, the first color sub-pixel spx1 is a red sub-pixel, the second color sub-pixel spx2 is a green sub-pixel, and the third color sub-pixel spx3 is a blue sub-pixel. In the same repeating unit, the positive projection of the first recess AX1 of the anode in the green sub-pixel in the second direction F2 covers the positive projection of the first via GK1 in the red sub-pixel in the second direction F2.

[0145] Exemplarily, as Figure 3 shown in Figure 4e , in the same repeating unit, the positive projection of the second recess AX2 of the main body ZT3 in the third color sub-pixel spx3 in the first direction F1 covers the positive projection of the first via hole GK1 in the second color sub-pixel spx2 in the first direction F1. The first color sub-pixel spx1 is a red sub-pixel, the second color sub-pixel spx2 is a green sub-pixel, and the third color sub-pixel spx3 is a blue sub-pixel. In the same repeating unit, the positive projection of the second recess AX2 of the main body in the blue sub-pixel in the first direction F1 covers the positive projection of the first via hole GK1 in the green sub-pixel in the first direction F1.

[0146] Exemplarily, as Figure 3 shown in Figure 4e , in the same repeating unit, the positive projection of the second recess AX2 of the main body ZT3 in the third color sub-pixel spx3 in the first direction F1 covers the positive projection of the via hole portion GB2 in the second color sub-pixel spx2 in the first direction F1. The first color sub-pixel spx1 is a red sub-pixel, the second color sub-pixel spx2 is a green sub-pixel, and the third color sub-pixel spx3 is a blue sub-pixel. In the same repeating unit, the positive projection of the second recess AX2 of the main body in the blue sub-pixel in the first direction F1 covers the positive projection of the via hole portion GB2 in the green sub-pixel in the first direction F1.

[0147] Exemplarily, as Figure 3 shown in Figure 4e , the main body ZT2 in the second color sub-pixel spx2 has a first recess AX1, and in the same repeating unit, the positive projection of the first recess AX1 in the second direction F2 covers the positive projection of the via hole portion in the first color sub-pixel spx1 in the second direction F2. For example, if the second color sub-pixel spx2 is a green sub-pixel, the first color sub-pixel spx1 is a red sub-pixel, and the third color sub-pixel spx3 is a blue sub-pixel, then the main body in the green sub-pixel has a first recess AX1, and in the same repeating unit, the positive projection of the first recess AX1 in the second direction F2 covers the positive projection of the via hole portion in the red sub-pixel in the second direction F2.

[0148] Exemplarily, as Figure 3 shown in Figure 4eAs shown, in the same repeating unit, the orthographic projection of the second recess AX2 of the main body ZT3 in the third color sub-pixel spx3 in the first direction F1 covers the orthographic projection of the via ZT2 in the second color sub-pixel spx2 in the first direction F1. For example, the second color sub-pixel spx2 is a green sub-pixel, the first color sub-pixel spx1 is a red sub-pixel, and the third color sub-pixel spx3 is a blue sub-pixel, then in the same repeating unit, the orthographic projection of the second recess AX2 of the main body in the blue sub-pixel in the first direction F1 covers the orthographic projection of the via in the green sub-pixel in the first direction F1.

[0149] For example, Figure 3 and Figure 4e As shown, the edge of the orthographic projection of the first recess AX1 on the substrate 10 is roughly parallel to the edge of the orthographic projection of the via portion GB1 in the first color sub-pixel spx1 on the substrate 10. For example, the second color sub-pixel spx2 is a green sub-pixel, the first color sub-pixel spx1 is a red sub-pixel, and the third color sub-pixel spx3 is a blue sub-pixel. In the same repeating unit, the edge of the orthographic projection of the first recess AX1 on the substrate 10 is roughly parallel to the edge of the orthographic projection of the via portion in the red sub-pixel on the substrate 10. It should be noted that in actual processes, due to limitations of process conditions or other factors such as the setting of wiring or vias, the above-mentioned parallel relationship only needs to roughly meet the above conditions and is within the protection scope of the present invention.

[0150] For example, Figure 3 and Figure 4e As shown, the edge of the orthographic projection of the second recess AX2 on the substrate 10 is roughly parallel to the edge of the orthographic projection of the main part ZT2 in the second color sub-pixel spx2 on the substrate 10. For example, the second color sub-pixel spx2 is a green sub-pixel, the first color sub-pixel spx1 is a red sub-pixel, and the third color sub-pixel spx3 is a blue sub-pixel. In the same repeating unit, the edge of the orthographic projection of the second recess AX2 on the substrate 10 is roughly parallel to the edge of the orthographic projection of the main part in the green sub-pixel on the substrate 10. It should be noted that in actual processes, due to the limitations of process conditions or other factors such as the setting of wiring or vias, the above-mentioned parallel relationship only needs to roughly meet the above conditions and is within the protection scope of the present invention.

[0151] For example, Figure 3 and Figure 4eAs shown, the first distance between the edge of the orthographic projection of the first recess AX1 on the substrate 10 and the edge of the orthographic projection of the via portion ZT1 in the first color sub-pixel spx1 on the substrate 10 is not less than 2.5 μm. For example, the second color sub-pixel spx2 is a green sub-pixel, the first color sub-pixel spx1 is a red sub-pixel, the third color sub-pixel spx3 is a blue sub-pixel, and the first distance between the edge of the orthographic projection of the first recess AX1 on the substrate 10 and the edge of the orthographic projection of the via portion in the red sub-pixel on the substrate 10 is not less than 2.5 μm. For example, the first distance between the edge of the orthographic projection of the first recess AX1 on the substrate 10 and the edge of the orthographic projection of the via portion in the red sub-pixel on the substrate 10 is 2.5 to 20 μm. For example, the first distance can be set to 2.5 μm. Alternatively, the first distance can be set to 3.5 μm, or the first distance can be set to 5.5 μm, or the first distance can be set to 10 μm, or the first distance can be set to 20 μm. In practical applications, in combination with the preparation process and the accuracy of the equipment, when mass-producing a display panel, the first distance can be set to 3.5 μm. Of course, in practical applications, the value of the first distance can be set according to actual application requirements, which is not limited herein.

[0152] Exemplarily, as Figure 3 with Figure 4e shown, the second distance between the edge of the orthographic projection of the second recess AX2 on the substrate 10 and the edge of the orthographic projection of the main body portion ZT2 in the second color sub-pixel spx2 on the substrate 10 is not less than 2.5 μm. For example, the second distance between the edge of the orthographic projection of the second recess AX2 on the substrate 10 and the edge of the orthographic projection of the main body portion ZT2 in the second color sub-pixel spx2 on the substrate 10 is 2.5 to 20 μm. For example, for example, the second color sub-pixel spx2 is a green sub-pixel, the first color sub-pixel spx1 is a red sub-pixel, the third color sub-pixel spx3 is a blue sub-pixel, and the second distance between the edge of the orthographic projection of the second recess AX2 on the substrate 10 and the edge of the orthographic projection of the via portion in the green sub-pixel on the substrate 10 is not less than 2.5 μm. Further, the second distance is 2.5 to 20 μm, and the second distance can be set to 2.5 μm. Alternatively, the second distance can be set to 3.5 μm, or the second distance can be set to 5.5 μm, or the second distance can be set to 10 μm, or the second distance can be set to 20 μm. In practical applications, in combination with the preparation process and the accuracy of the equipment, when mass-producing a display panel, the second distance can be set to 3.5 μm. Of course, in practical applications, the value of the second distance can be set according to actual application requirements, which is not limited herein.

[0153] Exemplarily, as Figure 3 shown in Figure 4e , the transistor array layer includes driving transistors located in each sub-pixel. The first color sub-pixel spx1 is a red sub-pixel, the second color sub-pixel spx2 is a green sub-pixel, and the third color sub-pixel spx3 is a blue sub-pixel. The positive projection of the anode in the green sub-pixel on the substrate 10 overlaps with the positive projection of the channel region of the driving transistor in the red sub-pixel on the substrate 10. The positive projection of the anode in the red sub-pixel on the substrate 10 does not overlap with the positive projection of the channel region of each driving transistor on the substrate 10. Exemplarily, the positive projection of the anode in the red sub-pixel on the substrate 10 overlaps with the positive projection of the pixel circuit in the red sub-pixel on the substrate 10.

[0154] Exemplarily, as Figure 1 shown in Figure 3 and Figure 4e , one repeating unit corresponds to one scan line GA, one reset line RST, and one emission control line EM. Further, one repeating unit group PXZ corresponds to one scan line GA, one reset line RST, and one emission control line EM, that is, the pixel circuits in one repeating unit group PXZ are electrically connected to the same scan line GA, the same reset line RST, and the same emission control line EM. Among them, for the scan line GA, reset line RST, and emission control line EM corresponding to the same repeating unit, the positive projection of the scan line GA on the substrate 10 is located between the positive projections of the reset line RST and the emission control line EM on the substrate 10. For example, for the scan line GA, reset line RST, and emission control line EM corresponding to the same repeating unit group, the positive projection of the scan line GA on the substrate 10 is located between the positive projections of the reset line RST and the emission control line EM on the substrate 10.

[0155] Exemplarily, as Figure 1 shown in Figure 3 and Figure 4eAs shown, in a repeating unit, the orthographic projection of the reset line RST on the substrate 1000 does not overlap with the orthographic projection of the anode in the red sub-pixel controlled by the reset line RST on the substrate 1000. The orthographic projection of the emission control line EM on the substrate 1000 has an overlapping area with the orthographic projection of the anode in the green sub-pixel controlled by the emission control line EM on the substrate 1000. The orthographic projection of the scan line GA on the substrate 1000 does not overlap with the orthographic projections of the respective anodes controlled by the scan line GA on the substrate 1000. Further, in a repeating unit group PXZ, the orthographic projection of the reset line RST on the substrate 1000 does not overlap with the orthographic projection of the anode in the red sub-pixel controlled by the reset line RST on the substrate 1000. The orthographic projection of the emission control line EM on the substrate 1000 has an overlapping area with the orthographic projection of the anode in the green sub-pixel controlled by the emission control line EM on the substrate 1000. The orthographic projection of the scan line GA on the substrate 1000 does not overlap with the orthographic projections of the respective anodes controlled by the scan line GA on the substrate 1000. Further, for a repeating unit, the orthographic projection of the emission control line EM controlling the repeating unit on the substrate 1000 has overlapping areas with the orthographic projections of the anodes in the blue sub-pixel and the green sub-pixel on the substrate 1000 respectively. The orthographic projections of the reset line RST and the scan line GA controlling the repeating unit on the substrate 1000 do not overlap with the orthographic projections of the respective anodes on the substrate 1000. It should be noted that the reset line RST is the signal line for controlling the initialization transistor T6 and the reset transistor T7 in a repeating unit. The emission control line EM is the signal line for controlling the emission control transistor T4 and the conduction control transistor T5 in a repeating unit. The scan line GA is the signal line for controlling the data writing transistor T2 and the threshold compensation transistor T3 in a repeating unit. For example, for a repeating unit group PXZ, the orthographic projection of the emission control line EM controlling the repeating unit group PXZ on the substrate 1000 has overlapping areas with the orthographic projections of the anodes in the blue sub-pixel and the green sub-pixel on the substrate 1000 respectively. The orthographic projections of the reset line RST and the scan line GA controlling the repeating unit group PXZ on the substrate 1000 do not overlap with the orthographic projections of the respective anodes on the substrate 1000. It should be noted that the reset line RST is the signal line for controlling the initialization transistor T6 and the reset transistor T7 in a repeating unit group. The emission control line EM is the signal line for controlling the emission control transistor T4 and the conduction control transistor T5 in a repeating unit group. The scan line GA is the signal line for controlling the data writing transistor T2 and the threshold compensation transistor T3 in a repeating unit group.

[0156] Exemplarily, as Figure 1 、 Figure 3 and Figure 4eAs shown, the orthographic projection of the reset line on the substrate 10 and the orthographic projection of the anode in the red sub-pixel on the substrate 10 have an overlapping area. The orthographic projection of the light-emitting control line on the substrate 10 and the orthographic projection of the anode in the green sub-pixel on the substrate 10 have an overlapping area. The orthographic projection of the scanning line on the substrate 10 and the orthographic projections of the respective anodes on the substrate 10 do not overlap.

[0157] Exemplarily, as Figure 3 with Figure 4e shown, in the same repeating unit, the orthographic projection of the anode in the third-color sub-pixel spx3 on the substrate 10 and the orthographic projections of the reset line and the light-emitting control line that control the pixel circuit in the third-color sub-pixel spx3 on the substrate 10 have overlapping areas. For example, the first-color sub-pixel spx1 is a red sub-pixel, the second-color sub-pixel spx2 is a green sub-pixel, and the third-color sub-pixel spx3 is a blue sub-pixel. In the same repeating unit, the orthographic projection of the anode in the blue sub-pixel on the substrate 10 and the orthographic projections of the reset line and the light-emitting control line on the substrate 10 have overlapping areas.

[0158] Exemplarily, as Figure 3 with Figure 4e shown, the orthographic projections of the first via GK1 and the second via GK2 in the red sub-pixel on the substrate 10 have a first overlapping area. The orthographic projections of the first via GK1 and the second via GK2 in the green sub-pixel on the substrate 10 have a second overlapping area. The orthographic projections of the first via GK1 and the second via GK2 in the blue sub-pixel on the substrate 10 have a third overlapping area. Among them, the area of the first overlapping area is not greater than the area of the second overlapping area. The area of the first overlapping area is not greater than the area of the third overlapping area. Further, the area of the third overlapping area can be made to be approximately equal to the area of the second overlapping area and less than it. It should be noted that in actual processes, due to process condition limitations or other factors such as wiring or via settings, as long as the above equal relationship generally meets the above conditions, it falls within the protection scope of the present invention.

[0159] Exemplarily, the area of the first overlapping area is 0 to 0.9 μm. For example, the area of the first overlapping area can also be 0.5 μm, or the area of the first overlapping area can also be 0.9 μm. Or, the area of the first overlapping area can be 0, so that the orthographic projections of the first via GK1 and the second via GK2 in the red sub-pixel on the substrate 10 do not overlap.

[0160] Exemplarily, the area of ​​the second overlapping region is 0 to 0.9 μm. For example, the area of ​​the second overlapping region may also be 0.5 μm, or the area of ​​the second overlapping region may also be 0.9 μm. Alternatively, the area of ​​the second overlapping region may be 0, so that the orthographic projections of the first via hole GK1 and the second via hole GK2 in the green sub-pixel on the base substrate 10 do not overlap.

[0161] Exemplarily, the area of ​​the third overlapping region is 0-0.9 μm. For example, the area of ​​the third overlapping region may also be 0.5 μm, or the area of ​​the third overlapping region may also be 0.9 μm. Alternatively, the area of ​​the third overlapping region may be 0, so that the orthographic projections of the first via hole GK1 and the second via hole GK2 in the blue sub-pixel on the base substrate 10 do not overlap.

[0162] Exemplarily, when the first color sub-pixel spx1 is a red sub-pixel, the second color sub-pixel spx2 is a green sub-pixel, and the third color sub-pixel spx3 is a blue sub-pixel, the second overlapping area can be set larger to ensure the distance between the anodes in the blue sub-pixel and the green sub-pixel to avoid color mixing.

[0163] For example, Figure 3 and Figure 4e As shown, the first vias GK1 in the repeating units adjacent along the second direction F2 are arranged in sequence approximately along the second direction F2. For example, the first vias GK1 in the repeating unit group are arranged in sequence approximately along the second direction F2. Exemplarily, the orthographic projections of the first vias GK1 in the repeating units adjacent along the second direction F2 in the first direction F1 overlap. For example, the orthographic projections of the first vias GK1 in the repeating unit group in the first direction F1 overlap. It should be noted that in actual processes, due to limitations of process conditions or other factors such as wiring or via setting, the arrangement relationship of the first vias GK1 only needs to roughly meet the above conditions and all belong to the protection scope of the present invention.

[0164] For example, Figure 3 , Figure 4e and Figure 4f As shown, a pixel defining layer is formed on the side of the first electrode layer away from the base substrate 10, and the pixel defining layer includes an opening located in each sub-pixel, and in the same sub-pixel, the orthographic projection of the opening on the base substrate 10 is located within the orthographic projection of the anode on the base substrate 10. For example, the first color sub-pixel spx1 is a red sub-pixel, the second color sub-pixel spx2 is a green sub-pixel, and the third color sub-pixel spx3 is a blue sub-pixel. The red sub-pixel has an opening KK1, the green sub-pixel has an opening KK2, and the blue sub-pixel has an opening KK3. It should be noted that the area where the opening in each sub-pixel is located is equivalent to the light-emitting area.

[0165] Exemplarily, as Figure 3 , Figure 4e and Figure 4f show, in at least one of the first color sub-pixel spx1 and the second color sub-pixel spx2, the orthographic projection of the opening on the substrate 10 is a rectangle. For example, the orthographic projections of the openings in the first color sub-pixel spx1 and the second color sub-pixel spx2 on the substrate 10 are both rectangles. For example, the first color sub-pixel spx1 is a red sub-pixel, the second color sub-pixel spx2 is a green sub-pixel, and the third color sub-pixel spx3 is a blue sub-pixel. The orthographic projections of the openings KK1 in the red sub-pixel and the openings KK2 in the green sub-pixel on the substrate 10 are both rectangles.

[0166] Exemplarily, as Figure 3 , Figure 4e and Figure 4f show, the area of the opening in the third color sub-pixel spx3 is larger than the area of the opening in the second color sub-pixel spx2, and the area of the opening in the second color sub-pixel spx2 is larger than the area of the opening in the first color sub-pixel spx1. For example, the first color sub-pixel spx1 is a red sub-pixel, the second color sub-pixel spx2 is a green sub-pixel, and the third color sub-pixel spx3 is a blue sub-pixel. The area of the opening KK3 in the blue sub-pixel is larger than the area of the opening KK2 in the green sub-pixel, and the area of the opening KK2 in the green sub-pixel is larger than the area of the opening KK1 in the red sub-pixel. In practical applications, the opening area in each sub-pixel can be inversely proportional to the luminous lifetime of the sub-pixel. For example, if the luminous lifetime of the red sub-pixel is greater than the luminous lifetime of the green sub-pixel and the luminous lifetime of the green sub-pixel is greater than the luminous lifetime of the blue sub-pixel, then the area of the opening in the blue sub-pixel can be larger than the area of the opening in the green sub-pixel, and the area of the opening in the green sub-pixel can be larger than the area of the opening in the red sub-pixel.

[0167] Exemplarily, as Figure 3 , Figure 4e and Figure 4f show, in the third color sub-pixel spx3, the orthographic projection of the opening on the substrate 10 has an opening depression AX0 on one side of the orthographic projection of the first via GK1 in the third color sub-pixel spx3 on the substrate 10. For example, the first color sub-pixel spx1 is a red sub-pixel, the second color sub-pixel spx2 is a green sub-pixel, and the third color sub-pixel spx3 is a blue sub-pixel. In the blue sub-pixel, the orthographic projection of the opening KK3 on the substrate 10 has an opening depression AX0 on one side of the orthographic projection of the first via GK1 on the substrate 10. By setting the opening depression AX0, the area required for the fan-out of the first via GK1 can be provided, so that the flatness of the anode in the opening KK3 can be ensured to be relatively high, improving the display effect.

[0168] Exemplarily, as Figure 3 、 Figure 4e and Figure 4f shown, in the third color sub-pixel spx3, the positive projection of the opening depression AX0 in the first direction F1 covers the positive projection of the first via GK1 in the first direction F1. For example, the first color sub-pixel spx1 is a red sub-pixel, the second color sub-pixel spx2 is a green sub-pixel, and the third color sub-pixel spx3 is a blue sub-pixel. In the blue sub-pixel, the positive projection of the opening depression AX0 in the first direction F1 covers the positive projection of the first via GK1 in the first direction F1.

[0169] Exemplarily, as Figure 3 、 Figure 4e and Figure 4f shown, in the third color sub-pixel spx3, the edge of the positive projection of the opening depression AX0 on the substrate 10 is substantially parallel to the edge of the positive projection of the first via GK1 on the substrate 10. For example, the first color sub-pixel spx1 is a red sub-pixel, the second color sub-pixel spx2 is a green sub-pixel, and the third color sub-pixel spx3 is a blue sub-pixel. In the blue sub-pixel, the edge of the positive projection of the opening depression AX0 on the substrate 10 is substantially parallel to the edge of the positive projection of the first via GK1 on the substrate 10. It should be noted that in the actual process, due to process conditions or other factors such as wiring or via settings, as long as the above parallel relationship generally meets the above conditions, it falls within the protection scope of the present invention.

[0170] Exemplarily, as Figure 3 、 Figure 4e and Figure 4f shown, in the third color sub-pixel spx3, the third distance between the edge of the positive projection of the opening depression AX0 on the substrate 10 and the edge of the positive projection of the first via GK1 on the substrate 10 is not less than 2.25 μm. Further, the third distance is 2.25 - 20 μm. For example, the first color sub-pixel spx1 is a red sub-pixel, the second color sub-pixel spx2 is a green sub-pixel, and the third color sub-pixel spx3 is a blue sub-pixel. In the blue sub-pixel, the third distance between the edge of the positive projection of the opening depression AX0 on the substrate 10 and the edge of the positive projection of the first via GK1 on the substrate 10 is not less than 2.25 μm. Exemplarily, the third distance can be set to 2.25 μm. Or, the third distance can also be set to 2.5 μm. Or, the third distance can also be set to 20 μm. In actual applications, in combination with the preparation process and the accuracy of the equipment, when mass-producing the display panel, the third distance can be set to 2.5 μm. Of course, in actual applications, the value of the third distance can be set according to actual application requirements, which is not limited herein.

[0171] Exemplarily, as Figure 3 , Figure 4e and Figure 4f show, in the third color sub-pixel spx3, the main body ZT3 of the anode YG3 has a third recess AX3 on one side of the orthographic projection of the first via GK1 of the anode YG3 of the third color sub-pixel spx3 on the substrate 1000, and the third recess AX3 is substantially parallel to the opening recess AX0. For example, the first color sub-pixel spx1 is a red sub-pixel, the second color sub-pixel spx2 is a green sub-pixel, and the third color sub-pixel spx3 is a blue sub-pixel. In the blue sub-pixel, the main body ZT3 of the anode YG3 has a third recess AX3 on one side of the orthographic projection of the first via GK1 of the anode YG3 of the third color sub-pixel spx3 on the substrate 1000, and the third recess AX3 is substantially parallel to the opening recess AX0.

[0172] Exemplarily, as Figure 3 , Figure 4e and Figure 4f show, in the third color sub-pixel spx3, the edge of the orthographic projection of the third recess AX3 on the substrate 1000 overlaps with the edge of the orthographic projection of the opening recess AX0 on the substrate 1000. For example, the first color sub-pixel spx1 is a red sub-pixel, the second color sub-pixel spx2 is a green sub-pixel, and the third color sub-pixel spx3 is a blue sub-pixel. In the blue sub-pixel, the edge of the orthographic projection of the third recess AX3 on the substrate 1000 overlaps with the edge of the orthographic projection of the opening recess AX0 on the substrate 1000.

[0173] Exemplarily, as Figure 3 , Figure 4e and Figure 4f show, a spacer layer is formed on the side of the pixel defining layer away from the substrate 1000, and the spacer layer includes a plurality of spacers PS arranged at intervals. One spacer PS is arranged between the anodes in the third sub-pixels adjacent along the first direction F1.

[0174] It should be noted that the formation of the above-mentioned vias and through-holes can be circular, square, octagonal, etc., which can be designed according to the actual application requirements and are not limited herein.

[0175] In some examples, as Figure 6As shown, the first color sub-pixel spx1 can also be a green sub-pixel, and the second color sub-pixel spx2 can be a blue sub-pixel. At this time, the first direction F1 can be the row direction of the sub-pixels, and the second direction F2 can be the column direction of the sub-pixels. The repeating unit includes a green sub-pixel and a blue sub-pixel arranged in sequence along the first direction F1. And the repeating unit can also include a red sub-pixel; wherein, the red sub-pixel and the green sub-pixel are arranged along the second direction F2. Among them, the positive projection of the anode in the blue sub-pixel on the substrate 10 has a first recess AX1 on one side of the positive projection of the anode in the green sub-pixel on the substrate 10.

[0176] In some examples, when the first color sub-pixel spx1 is a green sub-pixel and the second color sub-pixel spx2 is a blue sub-pixel, as Figure 6 shown, in the same repeating unit, the positive projection of the first via GK1 in the green sub-pixel on the substrate 10 is located between the positive projections of the anodes in the green sub-pixel and the blue sub-pixel on the substrate 10.

[0177] In some examples, when the first color sub-pixel spx1 is a green sub-pixel and the second color sub-pixel spx2 is a blue sub-pixel, as Figure 6 shown, in the same repeating unit, the positive projection of the first recess AX1 of the anode in the blue sub-pixel in the second direction F2 and the positive projection of the first via GK1 in the green sub-pixel in the second direction F2 have at least an overlapping area.

[0178] In some examples, when the first color sub-pixel spx1 is a green sub-pixel and the second color sub-pixel spx2 is a blue sub-pixel, as Figure 6 shown, in the same repeating unit, the positive projection of the first recess AX1 of the anode in the blue sub-pixel in the second direction F2 covers the positive projection of the first via GK1 in the green sub-pixel in the second direction F2.

[0179] In some examples, when the first color sub-pixel spx1 is a green sub-pixel and the second color sub-pixel spx2 is a blue sub-pixel, as Figure 6 shown, the main body of the blue sub-pixel has a first recess AX1, and in the same repeating unit, the positive projection of the first recess AX1 in the second direction F2 covers the positive projection of the via portion in the green sub-pixel in the second direction F2.

[0180] In some examples, when the first color sub-pixel spx1 is a green sub-pixel and the second color sub-pixel spx2 is a blue sub-pixel, as Figure 6As shown, the edge of the orthographic projection of the first recess AX1 on the substrate 10 is substantially parallel to the edge of the via portion in the green sub-pixel in the orthographic projection on the substrate 10. It should be noted that in the actual process, due to process condition limitations or other factors such as wiring or via settings, as long as the above parallel relationship generally meets the above conditions, it falls within the protection scope of the present invention.

[0181] In some examples, when the first color sub-pixel spx1 is a green sub-pixel and the second color sub-pixel spx2 is a blue sub-pixel, as Figure 6 shown, the first distance between the edge of the orthographic projection of the first recess AX1 on the substrate 10 and the edge of the via portion in the green sub-pixel in the orthographic projection on the substrate 10 is not less than 2.5 μm. Further, the first distance can be 2.5 - 20 μm. For example, the first distance can be 2.5 μm. Or, the first distance can also be 3.5 μm. Or, the first distance can also be 20 μm, which is not limited herein.

[0182] It should be noted that when the first color sub-pixel spx1 is a green sub-pixel and the second color sub-pixel spx2 is a blue sub-pixel, the setting method of the red sub-pixel in the repeating unit can refer to the above setting method of the red sub-pixel, which will not be elaborated herein.

[0183] Based on the same inventive concept, the embodiments of the present disclosure also provide a display device, including the above display panel provided by the embodiments of the present disclosure. The display device can be: a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any product or component with a display function. Other essential components of the display device are understood by those of ordinary skill in the art and will not be elaborated herein, nor should it be regarded as a limitation to the present disclosure. The implementation of the display device can refer to the embodiments of the above display panel, and the repeated parts will not be elaborated.

[0184] Although the preferred embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications once they learn the basic creative concept. Therefore, the appended claims are intended to be construed as including the preferred embodiments and all changes and modifications falling within the scope of the present invention.

[0185] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations of the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these changes and modifications.

Claims

1. A display panel, wherein, comprising: a substrate substrate including a plurality of sub-pixels; a transistor array layer located on the substrate substrate, and the transistor array layer includes an anode transfer portion in each of the sub-pixels; a first planar layer located on a side of the transistor array layer away from the substrate substrate; a first electrode layer located on a side of the first planar layer away from the substrate substrate, the first electrode layer includes an anode in each of the sub-pixels; wherein, the anode includes a main body portion and a via portion that are electrically connected to each other; and the via portion in each of the sub-pixels is electrically connected to the anode transfer portion through a first via; the first via penetrates the first planar layer; wherein, the plurality of sub-pixels include a first color sub-pixel and a second color sub-pixel adjacent to each other in a first direction; a positive projection of the first via in the first color sub-pixel on the substrate substrate is located between positive projections of the main body portion in the first color sub-pixel and the main body portion in the second color sub-pixel on the substrate substrate; For the first color sub-pixel and the second color sub-pixel adjacent to each other in the first direction, one side of the anode in the second color sub-pixel has a first recess in a positive projection on the substrate substrate facing a side of the positive projection of the anode in the first color sub-pixel on the substrate substrate; and the first recess is arranged towards the center of the main body portion of the second color sub-pixel; The display panel includes a plurality of repeating units, and each repeating unit includes at least one first color sub-pixel and at least one second color sub-pixel; At least two of the first recesses and two of the first vias are included in two adjacent repeating units; and, in the first direction, at least two adjacent repeating units have two first recesses and first vias arranged in a straight line.

2. The display panel according to claim 1, wherein, In the same repeating unit, a positive projection of the first recess of the anode in the second color sub-pixel in a second direction covers a positive projection of the first via in the first color sub-pixel in the second direction.

3. The display panel according to claim 2, wherein, In the same sub-pixel, a positive projection of the via portion on the substrate substrate covers a positive projection of the first via on the substrate substrate; The first recess is arranged in the main body portion of the second color sub-pixel, and a positive projection of the first recess in the second direction covers a positive projection of the via portion in the first color sub-pixel in the second direction.

4. The display panel according to claim 3, wherein, An edge of the positive projection of the first recess on the substrate substrate is substantially parallel to an edge of the positive projection of the first via in the first color sub-pixel on the substrate substrate.

5. The display panel according to claim 4, wherein, A first distance between an edge of the positive projection of the first recess on the substrate substrate and an edge of the positive projection of the first via in the first color sub-pixel on the substrate substrate is 2.5 - 20 μm.

6. The display panel according to any one of claims 1 - 5, wherein, The first color sub-pixel is a red sub-pixel, and the second color sub-pixel is a green sub-pixel; The transistor array layer includes driving transistors located in each of the sub-pixels; the positive projection of the anode in the green sub-pixel on the substrate has an overlapping area with the positive projection of the channel region of the driving transistor in the red sub-pixel on the substrate.

7. The display panel according to claim 6, wherein, The positive projection of the anode in the red sub-pixel on the substrate does not overlap with the positive projection of the channel region of each of the driving transistors on the substrate.

8. The display panel according to claim 7, wherein, The transistor array layer includes: a plurality of scan lines, a plurality of reset lines, and a plurality of light-emitting control lines that are spaced apart from each other; wherein, one of the repeating units corresponds to at least one of the scan lines, at least one of the reset lines, and at least one of the light-emitting control lines; In one of the repeating units, the positive projection of the reset line on the substrate does not overlap with the positive projection of the anode in the red sub-pixel controlled by the reset line on the substrate, the positive projection of the light-emitting control line on the substrate has an overlapping area with the positive projection of the anode in the green sub-pixel controlled by the light-emitting control line on the substrate, and the positive projection of the scan line on the substrate does not overlap with the positive projection of each of the anodes controlled by the scan line on the substrate.

9. The display panel according to claim 6, wherein, The transistor array layer further includes an active layer of a conduction control transistor located in each of the sub-pixels; and in the same sub-pixel, the anode transfer portion is electrically connected to the conductive region of the active layer of the conduction control transistor through a second via; The positive projection of the first via and the second via in the red sub-pixel on the substrate has a first overlapping area; The positive projection of the first via and the second via in the green sub-pixel on the substrate has a second overlapping area; The area of the first overlapping area is not greater than the area of the second overlapping area.

10. The display panel according to claim 7, wherein, The transistor array layer further includes an active layer of a conduction control transistor located in each of the sub-pixels; and in the same sub-pixel, the anode transfer portion is electrically connected to the conductive region of the active layer of the conduction control transistor through a second via; The positive projection of the first via and the second via in the red sub-pixel on the substrate has a first overlapping area; The positive projection of the first via and the second via in the green sub-pixel on the substrate has a second overlapping area; The area of the first overlapping area is not greater than the area of the second overlapping area.

11. The display panel according to claim 8, wherein, The transistor array layer further includes an active layer of a conduction control transistor located in each of the sub-pixels; and in the same sub-pixel, the anode transfer portion is electrically connected to the conductive region of the active layer of the conduction control transistor through a second via; The positive projection of the first via and the second via in the red sub-pixel on the substrate has a first overlapping area; The positive projections of the first via hole and the second via hole in the green sub-pixel on the substrate have a second overlapping area; The area of the first overlapping area is not greater than the area of the second overlapping area.

12. The display panel according to claim 9, wherein, The area of the first overlapping area is 0 - 0.9 μm; the area of the second overlapping area is 0 - 0.9 μm.

13. The display panel according to any one of claims 1 - 5, wherein, The first color sub-pixel is a green sub-pixel, and the second color sub-pixel is a blue sub-pixel; The positive projection of the anode in the blue sub-pixel on the substrate overlaps with the positive projection of the channel region of the driving transistor in the green sub-pixel on the substrate.

14. The display panel according to claim 13, wherein, In the same blue sub-pixel, the positive projection of the anode on the substrate overlaps with the positive projection of the channel region of the driving transistor on the substrate.

15. The display panel according to claim 14, wherein, For one repeating unit, control the positive projection of the light-emitting control line of the repeating unit on the substrate to respectively overlap with the positive projections of the anodes in the blue sub-pixel and the green sub-pixel on the substrate, and control the positive projections of the reset line and the scan line of the repeating unit on the substrate not to overlap with the positive projections of the respective anodes on the substrate.

16. The display panel according to claim 13, wherein, The orthographic projections of the first via hole and the second via hole in the green sub-pixel on the substrate have a second overlapping region, and the orthographic projections of the first via hole and the second via hole in the blue sub-pixel on the substrate have a third overlapping region, and the area of the third overlapping region is 0-9 μm 2 .

17. The display panel according to claim 14, wherein, The orthographic projections of the first via hole and the second via hole in the green subpixel on the substrate have a second overlapping region, and the orthographic projections of the first via hole and the second via hole in the blue subpixel on the substrate have a third overlapping region, and the area of the third overlapping region is 0-9 μm 2 .

18. The display panel according to claim 15, wherein, The orthographic projections of the first via hole and the second via hole in the green sub-pixel on the substrate have a second overlapping region, and the orthographic projections of the first via hole and the second via hole in the blue sub-pixel on the substrate have a third overlapping region, and the area of the third overlapping region is 0-9 μm 2 .

19. The display panel according to claim 16, wherein, The area of the third overlapping area is less than or equal to the area of the second overlapping area.

20. The display panel according to any one of claims 2 - 5, wherein, The repeating unit further includes at least one third color sub-pixel; The connection lines between the anodes in the adjacent first color sub-pixel, the second color sub-pixel, and the third color sub-pixel form a triangle.

21. The display panel according to claim 6, wherein, The repeating unit further includes at least one third color sub-pixel; The connection lines between the anodes in the adjacent first color sub-pixel, the second color sub-pixel, and the third color sub-pixel form a triangle.

22. The display panel according to claim 7, wherein, The repeating unit further includes at least one third color sub-pixel; The connection lines between the anodes in the adjacent first color sub-pixel, the second color sub-pixel, and the third color sub-pixel form a triangle.

23. The display panel according to claim 8, wherein, The repeating unit further includes at least one third color sub-pixel; The connection lines between the anodes in the adjacent first color sub-pixel, the second color sub-pixel, and the third color sub-pixel form a triangle.

24. The display panel according to claim 20, wherein, In the same repeating unit, the positive projection of the first via hole in the second color sub-pixel on the substrate is located between the positive projection of the via hole part in the first color sub-pixel and the positive projection of the main body part in the third color sub-pixel on the substrate, and the positive projections of the first via hole in the second color sub-pixel, the via hole part in the first color sub-pixel, and the main body part in the third color sub-pixel on the substrate are located on the same straight line, and the straight line is substantially parallel to the first direction.

25. The display panel according to claim 24, wherein, In the same repeating unit, the positive projection of the main body part in the third color sub-pixel on the substrate has a second recess on one side facing the positive projection of the first via hole in the second color sub-pixel.

26. The display panel according to claim 25, wherein, In the same repeating unit, the positive projection of the second recess of the main body part in the third color sub-pixel in the first direction and the positive projection of the first via hole in the second color sub-pixel in the first direction have at least an overlapping area.

27. The display panel according to claim 26, wherein, In the same repeating unit, the positive projection of the second recess of the main body part in the third color sub-pixel in the first direction covers the positive projection of the first via hole in the second color sub-pixel in the first direction.

28. The display panel according to claim 27, wherein, In the same repeating unit, the positive projection of the second recess of the main body part in the third color sub-pixel in the first direction covers the positive projection of the via hole part in the second color sub-pixel in the first direction.

29. The display panel according to claim 28, wherein, The edge of the positive projection of the second recess on the substrate is substantially parallel to the edge of the positive projection of the main body part in the second color sub-pixel on the substrate.

30. The display panel according to claim 29, wherein, The second distance between the edge of the positive projection of the second recess on the substrate and the edge of the positive projection of the main body part in the second color sub-pixel on the substrate is 2.5 - 20 μm.

31. The display panel according to claim 25, wherein, The positive projection of the first via hole in the third color sub-pixel on the substrate is located on one side of the positive projection of the second recess on the substrate away from the positive projection of the via hole part in the second color sub-pixel on the substrate.

32. The display panel according to any one of claims 3 - 5, wherein, The anode in the first color sub-pixel further includes a first connection part electrically connected between the main body part and the via hole part; The first connection part extends along the first direction.

33. The display panel according to any one of claims 3 - 5, wherein, The anode in the second color sub-pixel further includes a second connection part electrically connected between the main body part and the via hole part; The second connection part extends along a third direction; The third direction is different from both the first direction and the second direction.

34. The display panel according to claim 20, wherein, In the same repeating unit, the positive projection of the anode in the third color sub-pixel on the substrate has overlapping regions with the positive projections of the reset line and the light-emitting control line for controlling the pixel circuit in the repeating unit on the substrate, respectively.

35. The display panel according to any one of claims 20, wherein, The first vias in the repeating units adjacent to each other along the second direction are arranged substantially in sequence along the second direction.

36. The display panel according to claim 35, wherein, The positive projections of the first vias in the repeating units adjacent to each other along the second direction overlap in the first direction.

37. The display panel according to claim 1, wherein, further comprising: a pixel defining layer located on a side of the first electrode layer away from the substrate; The pixel defining layer includes openings in each of the sub-pixels, and in the same sub-pixel, the positive projection of the opening on the substrate is located within the positive projection of the anode on the substrate; wherein the plurality of sub-pixels include third color sub-pixels; in the third color sub-pixel, the positive projection of the opening on the substrate has an opening depression on a side facing the positive projection of the first via in the third color sub-pixel on the substrate; In the third color sub-pixel, the main body portion of the anode has a third depression on a side facing the positive projection of the first via of the anode of the third color sub-pixel on the substrate, and the third depression is substantially parallel to the opening depression.

38. The display panel according to claim 37, wherein, In the third color sub-pixel, the positive projection of the opening depression in the first direction covers the positive projection of the first via in the first direction.

39. The display panel according to claim 38, wherein, In the third color sub-pixel, the edge of the positive projection of the opening depression on the substrate is substantially parallel to the edge of the positive projection of the first via on the substrate.

40. The display panel according to claim 39, wherein, In the third color sub-pixel, the third distance between the edge of the positive projection of the opening depression on the substrate and the edge of the positive projection of the first via on the substrate is 2.25 to 20 μm.

41. The display panel according to any one of claims 37 - 40, wherein, In the third color sub-pixel, the edge of the positive projection of the third depression on the substrate overlaps with the edge of the positive projection of the opening depression on the substrate.

42. The display panel according to any one of claims 37 - 40, wherein, The plurality of sub-pixels further include: a first color sub-pixel and a second color sub-pixel; In at least one of the first color sub-pixel and the second color sub-pixel, the positive projection of the opening on the substrate is rectangular.

43. The display panel according to claim 41, wherein, The plurality of sub-pixels further include: a first color sub-pixel and a second color sub-pixel; In at least one of the first color sub-pixel and the second color sub-pixel, a positive projection of the opening on the substrate substrate is a rectangle.

44. The display panel according to claim 42, wherein, an area of the opening in the third color sub-pixel is larger than an area of the opening in the second color sub-pixel; the area of the opening in the second color sub-pixel is larger than the area of the opening in the first color sub-pixel.

45. The display panel according to claim 43, wherein, the area of the opening in the third color sub-pixel is larger than the area of the opening in the second color sub-pixel; the area of the opening in the second color sub-pixel is larger than the area of the opening in the first color sub-pixel.

46. A display device, wherein, comprising the display panel according to any one of claims 1-45.

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