Silicon Carbide Semiconductor Device, Power Conversion Device, and Method of Manufacturing Silicon Carbide Semiconductor Device

Abstract

Provided is a silicon carbide semiconductor device having a high withstand voltage and capable of reducing on-resistance. A silicon carbide semiconductor device (100) comprises: a substrate (1) of a first conductivity type; a drift layer (2) of a first conductivity type, arranged on the substrate (1) and composed of silicon carbide; a body region (3) of a second conductivity type, arranged on the drift layer (2); a source region (5) of a first conductivity type, arranged on the body region (3); a source electrode (12) connected to the source region (5); a gate insulating film (10) arranged on the inner surface of a trench (6); a gate electrode (11) arranged in the trench (6) via the gate insulating film (10); a protective layer (7) of a second conductivity type, arranged below the gate insulating film (10); a connecting layer (8) of a second conductivity type, connected to the protective layer (7) and the body region (3); and an electric field relaxation layer (9) of a second conductivity type, connected to the bottom surface of the connecting layer (8) and arranged below the connecting layer (8), wherein the impurity concentration of the second conductivity type is lower than that of the connecting layer (8).

Description

Technical Field

[0001] The present disclosure relates to a trench gate type silicon carbide semiconductor device, a power conversion device using the silicon carbide semiconductor device, and a method for manufacturing the silicon carbide semiconductor device. Background Art

[0002] As a power switching element, an insulated gate type semiconductor device such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor) is widely used. Among insulated gate type semiconductor devices, a semiconductor device using silicon carbide (SiC) (hereinafter referred to as "silicon carbide semiconductor device") has attracted attention, and development of a trench gate type silicon carbide semiconductor device is also being promoted.

[0003] In a trench gate type semiconductor device, when a high voltage is applied in the off state of the semiconductor device, electric field concentration occurs at the bottom of the trench, which is a problem. In particular, in a trench gate type silicon carbide semiconductor device, since silicon carbide has a high dielectric breakdown strength, gate insulating film breakdown due to electric field concentration at the bottom of the trench is more likely to occur before avalanche breakdown in the drift layer, and thus electric field concentration at the bottom of the trench is likely to be a problem.

[0004] As a countermeasure, the following structure is known: in order to alleviate the electric field concentration at the bottom of the trench, a protective layer having a conductivity type different from that of the drift layer is provided below the trench, and a connection layer for connecting the protective layer to the source electrode is further provided on the side of the trench. However, in such a structure, there is the following problem: the electric field concentrates on the lower part of the protective layer and the lower part of the connection layer, and the breakdown voltage of the semiconductor device deteriorates. Therefore, there is the following technique: by covering a high-concentration connection layer with a low-concentration connection layer, the electric field at the junction of the connection layer and the drift layer is alleviated (for example, refer to Patent Document 1).

[0005] Patent Document 1: WO2018 / 225600 Summary of the Invention

[0006] However, in the trench gate type MOSFET structure described in Patent Document 1, since two connection layers are provided along the side surface of the trench, the width of the connection layer becomes large, and thus the current path becomes narrow. Therefore, there is a problem that the JFET resistance increases when the device is turned on, and as a result, the on-resistance becomes large.

[0007] The present disclosure has been made to solve the above-mentioned problems, and an object of the present disclosure is to obtain a silicon carbide semiconductor device capable of reducing JFET resistance when the device is turned on and lowering on-resistance.

[0008] The silicon carbide semiconductor device involved in the present disclosure comprises: a substrate of the first conductivity type; a drift layer of the first conductivity type, which is arranged on the substrate and is composed of silicon carbide; a body region of the second conductivity type, which is arranged on the drift layer; a source region of the first conductivity type, which is arranged on the body region; a source electrode, which is connected to the source region; a gate insulating film, which is arranged on the inner surface of a groove, the groove passes through the body region and the source region, and the bottom surface is located in the drift layer; the gate electrode is arranged in the groove through the gate insulating film; a protective layer of the second conductivity type, which is arranged below the gate insulating film; a connection layer of the second conductivity type, which is arranged in the drift layer and is connected to the protective layer and the body region; and an electric field relaxation layer of the second conductivity type, which is in contact with the bottom surface of the connection layer and is arranged below the connection layer, and the second conductivity type impurity concentration of the electric field relaxation layer of the second conductivity type is lower than that of the connection layer.

[0009] The semiconductor device according to the present disclosure has a high withstand voltage and can reduce the JFET resistance when the device is turned on by providing a wide current path, thereby having an effect of reducing the on-resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 This is a cross-sectional view of the silicon carbide semiconductor device according to the first embodiment.

[0011] Figure 2 This is a plan view showing an example in which trenches are formed in stripes in the silicon carbide semiconductor device according to the first embodiment.

[0012] Figure 3 This is a plan view showing an example in which trenches are formed in a grid pattern in the silicon carbide semiconductor device according to the first embodiment.

[0013] Figure 4 This is a cross-sectional view showing a first step in the process of manufacturing the silicon carbide semiconductor device according to the first embodiment.

[0014] Figure 5 It is a cross-sectional view showing a second step in the process of manufacturing the silicon carbide semiconductor device according to the first embodiment.

[0015] Figure 6 This is a cross-sectional view showing a third step in the process of manufacturing the silicon carbide semiconductor device according to the first embodiment.

[0016] Figure 7 This is a cross-sectional view showing a fourth step in the process of manufacturing the silicon carbide semiconductor device according to the first embodiment.

[0017] Figure 8It is a cross-sectional view for explaining a method of forming an electric field relaxation layer in a manufacturing process of a silicon carbide semiconductor device according to Embodiment 1.

[0018] Figure 9 It is a cross-sectional view for explaining a method of forming a connection layer in a manufacturing process of a silicon carbide semiconductor device according to Embodiment 1.

[0019] Figure 10 It is a cross-sectional view of a main part of a silicon carbide semiconductor device according to Embodiment 1.

[0020] Figure 11 It is respectively along Figure 10 An example of impurity concentration curves along lines A-A' and B-B'.

[0021] Figure 12 It is a cross-sectional view showing a silicon carbide semiconductor device of the first comparative example.

[0022] Figure 13 It is a cross-sectional view showing a silicon carbide semiconductor device of the second comparative example.

[0023] Figure 14 It is a simulation result of the electric field distribution at cutoff for a silicon carbide semiconductor device according to Embodiment 1.

[0024] Figure 15 It is a simulation result of the electric field distribution at cutoff for a silicon carbide semiconductor device of the first comparative example.

[0025] Figure 16 It is a simulation result of the electric field distribution at cutoff for a silicon carbide semiconductor device of the second comparative example.

[0026] Figure 17 It is a cross-sectional view of a first modified example of a silicon carbide semiconductor device according to Embodiment 1.

[0027] Figure 18 It is a cross-sectional view showing a manufacturing process of a first modified example of a silicon carbide semiconductor device according to Embodiment 1.

[0028] Figure 19 It is a cross-sectional view of a second modified example of a silicon carbide semiconductor device according to Embodiment 1.

[0029] Figure 20 It is a cross-sectional view showing a first process in a manufacturing process of a second modified example of a silicon carbide semiconductor device according to Embodiment 1.

[0030] Figure 21 It is a cross-sectional view showing a second process in a manufacturing process of a second modified example of a silicon carbide semiconductor device according to Embodiment 1.

[0031] Figure 22It is a cross-sectional view of the third process in the manufacturing process of the second modification of the silicon carbide semiconductor device according to Embodiment 1.

[0032] Figure 23 It is a cross-sectional view of the fourth process in the manufacturing process of the second modification of the silicon carbide semiconductor device according to Embodiment 1.

[0033] Figure 24 It is a cross-sectional view of the fifth process in the manufacturing process of the second modification of the silicon carbide semiconductor device according to Embodiment 1.

[0034] Figure 25 It is a cross-sectional view of the sixth process in the manufacturing process of the second modification of the silicon carbide semiconductor device according to Embodiment 1.

[0035] Figure 26 It is a cross-sectional view of the silicon carbide semiconductor device according to Embodiment 2.

[0036] Figure 27 It is a cross-sectional view of the silicon carbide semiconductor device according to Embodiment 3.

[0037] Figure 28 It is a cross-sectional view of the silicon carbide semiconductor device according to Embodiment 4.

[0038] Figure 29 It is a cross-sectional view of a modification of the silicon carbide semiconductor device according to Embodiment 4.

[0039] Figure 30 It is a block diagram of a power conversion system to which the power conversion device according to Embodiment 5 is applied.

[0040] Explanation of reference numerals

[0041] 1: Substrate; 2: Drift layer; 3: Body region; 4: Body contact region; 5: Source region; 6: Trench; 7: Protective layer; 8: Connection layer; 9: Electric field relaxation layer; 10: Gate insulating film; 11: Gate electrode; 12: Source electrode; 13: Drain electrode; 14: Interlayer insulating film; 15: Semiconductor layer; 17: Tail region; 18: Current diffusion layer; 21: First drift layer; 22: Second drift layer; 23: Low-resistance layer; 100, 101, 102, 200, 300, 400: Silicon carbide semiconductor device; 500: Power conversion device; 501: Main conversion circuit; 502: Drive circuit; 503: Control circuit; 510: Power supply; 520: Load. Detailed implementation manners

[0042] Hereinafter, embodiments of the present invention will be described based on the drawings. In addition, in the following drawings, the same or corresponding parts are denoted by the same reference numerals, and their descriptions will not be repeated.

[0043] In addition, in the following description, terms indicating specific positions and directions, such as "upper", "lower", "side", "bottom", "front", and "back", are sometimes used. However, these terms are used for the convenience of understanding the content of the embodiments and are not related to the directions in actual implementation.

[0044] Embodiment 1.

[0045] Use Figures 1 to 16 to describe the silicon carbide semiconductor device of Embodiment 1.

[0046] First, use Figure 1 to describe the structure of the silicon carbide semiconductor device 100. Figure 1 is a cross-sectional view showing the silicon carbide semiconductor device 100 of this embodiment.

[0047] In addition, in the present disclosure, with reference to Figure 1 , the source electrode 12 side of the silicon carbide semiconductor device 100 with respect to the substrate 1 is defined as "upper", and the drain electrode 13 side with respect to the substrate 1 is defined as "lower".

[0048] As Figure 1 shown, the silicon carbide semiconductor device 100 includes a substrate 1, a gate electrode 11, a source electrode 12, a drain electrode 13, an interlayer insulating film 14, and a semiconductor layer 15. A semiconductor layer 15 is provided on the upper side of the substrate 1, and a drain electrode 13 is provided on the lower side of the substrate 1. In addition, a trench 6 is formed on the surface side of the semiconductor layer 15, and a gate insulating film 10 and a gate electrode 11 are provided in the trench 6. And, on the upper side of the semiconductor layer 15, an interlayer insulating film 14 is provided in a region above the trench 6 so as to cover the gate electrode 11, and a source electrode 12 is provided in a region where the interlayer insulating film 14 is not provided.

[0049] The substrate 1 is a silicon carbide semiconductor substrate of the first conductivity type. In addition, the semiconductor layer 15 is a semiconductor layer provided by epitaxial crystal growth of silicon carbide on the substrate 1. The semiconductor layer 15 has a drift layer 2, a body region 3, a body contact region 4, and a source region 5.

[0050] The drift layer 2 is a semiconductor layer of the first conductivity type provided on the substrate 1. The impurity concentration of the first conductivity type in the drift layer 2 is lower than the impurity concentration of the first conductivity type in the substrate 1. In addition, in the drift layer 2, a second conductivity type protection layer 7 is provided below the trench 6, a connection layer 8 is provided on the side of the trench 6, and an electric field relaxation layer 9 is provided on the side of the protection layer 7 and below the connection layer 8.

[0051] The body region 3 is a semiconductor region of the second conductivity type provided on the drift layer 2. A body contact region 4 and a source region 5 are provided on the body region 3.

[0052] The body contact region 4 is a semiconductor region of a second conductivity type provided on the body region 3. The impurity concentration of the second conductivity type in the body contact region 4 is higher than that in the body region 3 of the second conductivity type.

[0053] The source region 5 is a semiconductor region of a first conductivity type provided adjacent to the body contact region 4 on the body region 3.

[0054] On the surface of the semiconductor layer 15, a source electrode 12 is provided in contact with the body contact region 4 and the source region 5. The source electrode 12 is composed of a silicide which is a compound of a metal such as Ni (nickel) and Ti (titanium) and the semiconductor layer 15, and forms an ohmic contact with the body contact region 4 and the source region 5.

[0055] A drain electrode 13 is provided on the back surface of the substrate 1. The drain electrode 13 is a metal electrode made of Ni or the like.

[0056] The trench 6 is formed in the semiconductor layer 15 so as to penetrate the source region 5 and the body region 3 from the surface of the source region 5, and its bottom surface is located in the drift layer 2. A gate insulating film 10 is formed on the inner surface of the trench 6, that is, the bottom surface and the side surface, and a gate electrode 11 is buried so as to be covered by the gate insulating film 10 in the trench 6.

[0057] A protective layer 7 of the second conductivity type for protecting the bottom surface of the trench 6 is formed below the trench 6. The protective layer 7 is provided in contact with the bottom of the trench 6 and covers the entire bottom of the trench 6. The bottom of the trench 6 is typically a plane, but may also be a tapered shape with a thin and pointed tip.

[0058] A connection layer 8 of the second conductivity type is provided on the side of the trench 6. The connection layer 8 is provided in contact with one side surface of the trench 6 and is in contact with the body region 3 and the protective layer 7. The bottom surface of the connection layer 8 is provided to have a depth deeper than the bottom of the trench 6 and shallower than the bottom surface of the protective layer 7 starting from the outermost surface of the drift layer 2. In addition, a part of the side surface of the connection layer 8 may be in contact with the body region 3, and its upper surface may be in contact with the source region 5 or the source electrode 12. The side surfaces of the trench 6 are typically substantially parallel, but may also be a tapered shape inclined to each other.

[0059] The protective layer 7 is electrically connected to the source electrode 12 via the connection layer 8, the body region 3, and the source region 5, and thus its potential is grounded. This electrical connection is provided, for example, by adjacent cells or the like. Since the potential of the protective layer 7 is grounded, when the silicon carbide semiconductor device 100 is turned off, the depletion layer easily extends from the protective layer 7 to the drift layer 2.

[0060] Below the connection layer 8, an electric field relaxation layer 9 of a second conductivity type is provided. The electric field relaxation layer 9 is provided to be in contact with the bottom surface of the connection layer 8 and with one side surface of the protective layer 7. The bottom surface of the electric field relaxation layer 9 is provided to have a depth from the outermost surface of the drift layer 2 that is substantially the same as the depth of the bottom surface of the protective layer 7. In addition, the impurity concentration of the second conductivity type of the electric field relaxation layer 9 is lower than the impurity concentration of the second conductivity type of the connection layer 8.

[0061] In addition, the protective layer 7 is not limited to being provided in contact with the bottom of the trench 6, and may also be provided to be separated downward from the bottom of the trench 6 within the drift layer 2. In addition, the protective layer 7 is not limited to covering the entire bottom of the trench 6, and may be provided as long as it covers at least a part of the bottom of the trench 6. For example, the protective layer 7 may be periodically arranged at intervals along the extending direction of the trench 6 (the long side direction in plan view in the case of a strip shape, and the direction defined for each trench 6 in the case of a lattice shape), or may be provided to cover about half of the bottom of the trench 6 in a cross section orthogonal to the extending direction. Alternatively, the protective layer 7 may be configured such that the width of the protective layer 7 is larger than the width of the trench 6 by covering the entire bottom in a manner that extends beyond the width direction of the trench 6.

[0062] The protective layer 7 is not limited to being provided along the extending direction of the trench 6, and may also be provided to partially and periodically cover the bottom of the trench 6 in the extending direction by arranging a plurality of them to extend in a direction orthogonal to the extending direction of the trench 6.

[0063] The connection layer 8 is not limited to being provided in contact with the entire one side surface of the trench 6, and may also be provided in contact with at least a part of at least one side surface of the trench 6. The connection layer 8 may also be provided at a position separated from the side surface of the trench 6 within the drift layer 2. In addition, the bottom surface of the connection layer 8 is not limited to having a depth from the outermost surface of the drift layer 2 that is deeper than the bottom of the trench 6 and shallower than the bottom surface of the protective layer 7, and may be provided as long as it is in contact with the body region 3 and the protective layer 7 to electrically connect them. For example, the connection layer 8 may also be provided to a depth from the outermost surface of the drift layer 2 that is the same as the depth of the bottom surface of the protective layer 7, and may also be provided up to the vicinity of the upper surface of the protective layer 7.

[0064] The connection layer 8 may also be provided in the drift layer 2 in parallel with the extending direction of the trench 6 between adjacent trenches 6. In this case, the connection layer 8 is not limited to being linearly and continuously provided, and may also be periodically provided at intervals in the extending direction of the trench 6.

[0065] In addition, in Figure 1In the silicon carbide semiconductor device 100 shown, connection layers 8 are provided on both the first side surface 6a of the trench 6 and the second side surface 6b facing the first side surface 6a across the trench 6, but it is not limited thereto. That is, when viewed from above parallel to the device surface, the connection layer 8 and the electric field relaxation layer 9 may be formed on either the first side surface 6a or the second side surface of the trench 6, or may be formed on both the first side surface 6a and the second side surface 6b.

[0066] When the connection layer 8 and the electric field relaxation layer 9 are formed on both the first side surface 6a and the second side surface 6b, the connection layer 8 and the electric field relaxation layer 9 formed on the first side surface 6a side and the connection layer 8 and the electric field relaxation layer 9 formed on the second side surface 6b side may be formed to face each other across the trench 6, or may be alternately formed in a manner that does not face each other across the trench 6.

[0067] Here, use Figure 2 and Figure 3 , and a specific example will be described for the case where the connection layer 8 and the electric field relaxation layer 9 are formed on either the first side surface 6a or the second side surface of the trench 6. Figure 2 and Figure 3 are plan views of positions where the trench 6 and the connection layer 8 are formed below the body region 3 in the silicon carbide semiconductor device.

[0068] In Figure 2 the structure shown, the trench 6 is configured in a strip shape, and the connection layer 8 is formed on one side of the two side surfaces of the trench 6 and is formed separately along the extending direction of the trench 6.

[0069] When the trench 6 is configured in a strip shape, in the case where the substrate 1 made of silicon carbide has an off-angle, it is desirable to set the extending direction of the strip to the same direction as the off-angle of the substrate 1. For example, when the <0001> crystal axis of the substrate 1 is inclined at a certain off-angle toward the <11-20> crystal axis, it is desirable that the strip of the trench 6 be parallel to the <11-20> crystal axis, that is, the side surface of the trench 6 becomes a surface substantially close to the (1-100) plane and the (-1100) plane. Thereby, the anisotropy of the electrical characteristics caused by the off-angle is not affected between the first side surface of the trench 6 and the second side surface facing it, and the deviation of the characteristics of the channels formed on each side surface can be reduced.

[0070] In addition, in Figure 3 the structure shown, the trench 6 is configured in a lattice shape, and the connection layer 8 is provided to be in contact with one of the four sides constituting each lattice. In addition, the length of the connection layer 8 in contact with one side of the lattice is Figure 3 the same as the length of one side of the lattice formed by the trench 6, but it may also be shorter than one side.

[0071] When the trench 6 is arranged in a lattice pattern, in the case where the substrate 1 has an offset angle, it is desirable that the connection layer 8 be provided on the side surface of the trench 6 orthogonal to the direction in which the offset angle is provided. Among the four side surfaces of the trench 6 parallel to the four sides forming each lattice, the deviation of the characteristics of the channels formed on the two side surfaces parallel to the direction in which the offset angle is provided is small. However, on the side surface orthogonal to the direction in which the offset angle is provided, the channel characteristics deteriorate. Therefore, by providing the connection layer 8 on this side surface to invalidate the channels in this region, stable channel characteristics can be obtained during device operation.

[0072] In addition, the structure of the trench 6 is not limited to the above-mentioned strip shape and lattice shape, and can also be set to a substantially circular shape, a substantially polygonal unit, a configuration divided in the strip extension direction, etc.

[0073] Next, the impurity concentrations of each layer and each region constituting the silicon carbide semiconductor device 100 will be described.

[0074] The impurity concentration of the first conductivity type of the drift layer 2 is 1.0×10 14 ~1.0×10 17 cm -3 , and is appropriately set based on specifications such as the breakdown voltage of the silicon carbide semiconductor device 100. It is set that the impurity concentration of the first conductivity type of the drift layer 2 is lower than the impurity concentration of the first conductivity type of the substrate 1.

[0075] The impurity concentration of the second conductivity type of the body region 3 is 1.0×10 14 ~1.0×10 18 cm -3 .

[0076] The impurity concentration of the second conductivity type of the body contact region 4 is 1.0×10 18 ~1.0×10 21 cm -3 , and in order to reduce the contact resistance with the source electrode 12, it is set that the impurity concentration of the second conductivity type is higher than that of the body region 3.

[0077] The impurity concentration of the first conductivity type of the source region 5 is 1.0×10 18 ~1.0×10 21 cm -3 , which is higher than the impurity concentration of the first conductivity type of the drift layer 2.

[0078] The impurity concentration of the second conductivity type of the protective layer 7 is preferably 1.0×10 14 ~1.0×10 20 cm -3 , and the concentration curve can also be non-uniform.

[0079] The impurity concentration of the second conductivity type of the connection layer 8 is 1.0×10 14~1.0×10 20 cm -3 。

[0080] The impurity concentration of the second conductivity type in the electric field relaxation layer 9 is lower than the impurity concentration of the second conductivity type in the connection layer 8. Additionally, it is desirable that the impurity concentration of the second conductivity type in the electric field relaxation layer 9 is lower than the impurity concentration of the second conductivity type in the protective layer 7.

[0081] At the boundary between the connection layer 8 and the electric field relaxation layer 9, there may be a sharp impurity concentration difference, or the impurity concentration may change smoothly. In the case where there is a position where the impurity concentration changes sharply from the connection layer 8 to the electric field relaxation layer 9, or in the case where the concentration gradient with respect to the distance is gradually changing when plotting the impurity concentration against the distance from the bottom surface of the body region 3 and the gradient at a certain distance is greater than the gradient in the vicinity, the position where this large concentration difference occurs is set as the boundary between the connection layer 8 and the electric field relaxation layer 9. Additionally, in the case where the impurity concentration gradually decreases smoothly from near the lower part of the connection layer 8 to the electric field relaxation layer 9, the position where the impurity concentration becomes half of the maximum value of the impurity concentration of the connection layer 8 is set as the boundary between the connection layer 8 and the electric field relaxation layer 9.

[0082] Next, the operation of the silicon carbide semiconductor device 100 will be briefly described.

[0083] In Figure 1 , when a voltage equal to or higher than the threshold voltage is applied to the gate electrode 11, in the body region 3, a channel of the first conductivity type, which is a conductivity type inversion, is formed along the side surface of the trench 6. Then, since a current path of the same conductivity type is formed between the source electrode 12 and the drain electrode 13, current flows. Such a state where a voltage equal to or higher than the threshold voltage is applied to the gate electrode 11 is the on state of the silicon carbide semiconductor device 100.

[0084] On the other hand, when a voltage lower than the threshold voltage is applied to the gate electrode 11, no channel is formed in the body region 3, so no current path is formed as in the on state. Therefore, even if a voltage is applied between the drain electrode 13 and the source electrode 12, almost no current flows from the drain electrode 13 to the source electrode 12. Such a state where the voltage of the gate electrode 11 is lower than the threshold voltage is the off state of the silicon carbide semiconductor device 100. Moreover, the silicon carbide semiconductor device 100 operates by switching between the on state and the off state by controlling the voltage applied to the gate electrode 11.

[0085] Next, Figures 4 to 9 will be used to explain the manufacturing method of the silicon carbide semiconductor device 100. Figures 4 to 9 is a cross-sectional view showing each process of the manufacturing method of the silicon carbide semiconductor device 100.

[0086] As Figure 4 shown, a semiconductor layer 15 of a first conductivity type made of silicon carbide is formed on a substrate 1. Specifically, the semiconductor layer 15 of the first conductivity type may be formed on the substrate 1, which is a silicon carbide substrate of the first conductivity type, by epitaxial crystal growth. In addition, the impurity concentration of the first conductivity type in the semiconductor layer 15 is formed corresponding to the impurity concentration of the first conductivity type in the drift layer 2 described above.

[0087] As Figure 5 shown, a body region 3, a body contact region 4, and a source region 5 are respectively formed by ion implantation in the upper part of the semiconductor layer 15. In the case of forming an n-type region as the first conductivity type region, for example, N (nitrogen), P (phosphorus) ions are implanted as donor ions. In addition, in the case of forming a p-type region as the second conductivity type region, for example, Al (aluminum), B (boron) ions are implanted as acceptor ions. Each region is formed such that the impurity concentration is included within the above values. In addition, the order of forming each region may be reversed. In addition, for at least a part of the regions, they can also be formed by epitaxial crystal growth instead of ion implantation.

[0088] As Figure 6 shown, a mask 16 having an opening is formed on the semiconductor layer 15. Then, by reactive ion etching (RIE) using the mask 16, a trench 6 is formed that penetrates the source region 5 and the body region 3 from the surface of the source region 5 and reaches within the drift layer 2.

[0089] As Figure 7 shown, a protective layer 7 is formed by implanting acceptor ions of the second conductivity type into the bottom surface of the trench 6. For the formation of the protective layer 7, it can be carried out as Figure 7 shown using a mask 16 having an opening, or a mask can be formed separately. In addition, the protective layer 7 can also be formed by epitaxial crystal growth within the trench 6 after forming the trench 6 to be deep enough corresponding to the thickness of the protective layer 7.

[0090] As Figure 8 shown, acceptor ions with a dose N2 are implanted toward the side surface of the trench 6 with an inclination angle θ2 with respect to the direction perpendicular to the surface of the semiconductor layer 15 by injecting energy E2, thereby forming an electric field relaxation layer 9 of the second conductivity type.

[0091] As Figure 9 shown, acceptor ions with a dose N1 higher than the acceptor ion dose N2 are implanted toward the side surface of the trench 6 with an inclination angle θ1 greater than the angle θ2 with respect to the direction perpendicular to the surface of the semiconductor layer 15 by injecting ion implantation energy E1, thereby forming a connection layer 8 of the second conductivity type with an impurity concentration higher than that of the electric field relaxation layer 9.

[0092] In this way, in the processes shown in Figure 8 and Figure 9 by making the implantation angle θ1 greater than θ2, an electric field relaxation layer 9 can be formed below the connection layer 8. Further, by setting the ion implantation energy E1 to be equal to or greater than E2, the electric field relaxation layer 9 can be locally formed in a region below the bottom surface without contacting the side surfaces of the connection layer 8 in such a manner that the width of the electric field relaxation layer 9 is equal to or less than the width of the connection layer 8. Here, the width of the electric field relaxation layer 9 and the width of the connection layer 8 respectively mean the width of the electric field relaxation layer 9 and the width of the connection layer 8 in the width direction of the trench 6.

[0093] In addition, when performing inclined implantation, either the mask 16 can be used or the mask 16 can be removed. In either case, the implantation angle of the inclined implantation is preferably equal to or smaller than the angle formed by the diagonal line from the upper end of one side surface of the mask 16 or the trench 6 to the lower end of the opposite trench 6 side surface and the side surface. By doing so, the connection layer 8 and the electric field relaxation layer 9 can be formed around the trench 6 and the protective layer 7.

[0094] Further, the connection layer 8 and the electric field relaxation layer 9 can also be formed by epitaxial crystal growth, vertical ion implantation, or a combination thereof. In this case, the semiconductor layer between the lower part of the bulk region 3 and the lower part of the trench 6 or the lower part of the protective layer 7 may also be formed by individual epitaxial crystal growth. Additionally, an electric field relaxation layer 9 may be formed below the protective layer 7.

[0095] Here, Figure 10 and Figure 11 are used to detail the connection layer 8 and the electric field relaxation layer 9. Figure 10 is an enlarged view of the region from the bulk region 3 to the drift layer 2 below the protective layer 7 having the same structure as Figure 9 in the case where the connection layer 8 and the electric field relaxation layer 9 are formed by ion implantation. Additionally, Figure 11 are examples of impurity concentration curves of the second conductivity type along the A - A' line and the B - B' line of Figure 10 respectively.

[0096] When the connection layer 8 is formed by inclined implantation, as shown in Figure 10 , a tail region 17 where the impurity concentration gradually decreases toward the implantation direction of the ions is formed on the bottom surface of the electric field relaxation layer 9 and the side surfaces on the drift layer 2 side of the connection layer 8 and the electric field relaxation layer 9. Regarding the attenuation of the impurity concentration in the tail region 17, it can be as shown in Figure 11It is approximated by a Gaussian distribution as shown. The width Wt of the tail region 17 formed on the side surface of the drift layer 2 side of the connection layer 8 and the electric field relaxation layer 9 is smaller than the device longitudinal length L2 of the electric field relaxation layer 9 including the tail region 17. Therefore, it is possible to distinguish the tail region 17 generated by ion implantation from the electric field relaxation layer 9 having an impurity concentration lower than that of the connection layer 8.

[0097] Return to the description of the manufacturing method. After that, a gate insulating film 10 is formed on the bottom surface and side surface in the trench 6, and a gate electrode 11 is formed so as to be buried in the trench 6 with the gate insulating film 10 interposed therebetween. Then, after forming an interlayer insulating film 14 so as to cover the gate electrode 11, a source electrode 12 is formed so as to be in contact with the surface of the source region 5 and the surface of the body contact region 4, and a drain electrode 13 is formed on the back surface of the substrate 1.

[0098] Through the above processes, Figure 1 the silicon carbide semiconductor device 100 shown is completed.

[0099] Describe the effects of the silicon carbide semiconductor device 100 configured as described above.

[0100] In the silicon carbide semiconductor device 100, a connection layer 8 that connects the protective layer 7 and the body region 3 is formed, so that the protective layer 7 can be electrically connected to the source electrode 12 that is connected to the body region 3 via the body contact region 4. As a result, the charge to the source electrode 12 is extracted during device switching, so the response of the depletion layer becomes faster and the switching loss can be reduced. Furthermore, by connecting the protective layer 7 to the source potential, the extension of the depletion layer from the protective layer 7 to the drift layer 2 is promoted when the device is turned off. As a result, the electric field strength at the bottom surface of the trench 6 can be reduced.

[0101] Here, Figure 1 and Figures 12 to 16 are used to describe the effects achieved by locally forming the electric field relaxation layer 9 below the connection layer 8. Figure 12 and Figure 13 are cross-sectional views showing silicon carbide semiconductor devices 901 and 902 related to comparative examples of the silicon carbide semiconductor device 100. In addition, Figures 14 to 16 are the electric field distributions at cutoff of the silicon carbide semiconductor devices 100, 901, and 902 calculated by simulation, respectively.

[0102] First, describe the differences in the structures of the silicon carbide semiconductor device 100 and the silicon carbide semiconductor devices 901 and 902 related to the comparative examples.

[0103] In Figure 1 the silicon carbide semiconductor device 100 shown, an electric field relaxation layer 9 is provided below the connection layer 8. On the other hand, in Figure 12In the silicon carbide semiconductor device 901 according to the first comparative example shown, the electric field relaxation layer 9 is not provided, and the bottom surface of the connection layer 8 is in contact with the drift layer 2, which is different in this respect.

[0104] In addition, in Figure 1 In the silicon carbide semiconductor device 100 shown, the side surface of the connection layer 8 facing the trench 6 is in contact with the drift layer 2. On the other hand, in Figure 13 In the silicon carbide semiconductor device 902 according to the second comparative example shown, a second connection layer 91 having an impurity concentration lower than that of the connection layer 8 is formed so as to cover the side surface and the bottom surface of the connection layer 8, which is different in this respect.

[0105] Next, the electric field distribution at the cut-off of the silicon carbide semiconductor devices 100, 901, and 902 will be described.

[0106] In Figures 14 to 16 , the electric field distribution in the region from near the bottom surface of the body region 3 to several μm below the protective layer 7 is shown longitudinally, indicating that the higher the electric field strength, the closer to the white region, and the lower the electric field strength, the closer to the black region.

[0107] As Figures 14 to 16 shown, when the drain voltage is applied to the silicon carbide semiconductor devices 100, 901, and 902 at the cut-off, a high electric field is formed at the bottom surface of the gate insulating film 10 and the protective layer 7 formed at the bottom corner of the trench 6 inside the element. That is, when a high voltage is applied, the electric field tends to concentrate at these points.

[0108] Regarding this point, as Figure 15 shown, in the silicon carbide semiconductor device 901 without the electric field relaxation layer 9, the electric field particularly concentrates on the lower part of the connection layer 8. On the other hand, as Figure 14 shown, although electric field concentration also occurs at the same part in the silicon carbide semiconductor device 100, the depletion layer expands in the electric field relaxation layer 9, so that the electric field strength at the junction and the bottom of the connection layer 8 decreases. As a result, it can be said that the electric field strength at the bottom surface of the electric field relaxation layer 9 under the avalanche voltage of the silicon carbide semiconductor device 100 is about 7% lower than the electric field strength at the bottom surface of the connection layer 8 of the silicon carbide semiconductor device 901. By relaxing the junction electric field in the semiconductor layer 15 through the electric field relaxation layer 9, the breakdown voltage of the device is improved.

[0109] In addition, as Figure 16 shown, in the silicon carbide semiconductor device 902 provided with the second connection layer 91 having an impurity concentration lower than that of the connection layer 8, the second connection layer 91 is provided on the side surface side of the connection layer 8. Therefore, it can be said that the width of the region of the second conductivity type near the side surface of the trench 6 becomes larger, but the electric field strength at the bottom of the connection layer 8 is the same as that in Figure 14Similar to the silicon carbide semiconductor device 100 shown, the effect of alleviating the electric field generated by forming the second connection layer 91 is small. In addition, if the second connection layer 91 is formed on the side surface of the connection layer 8, the width of the adjacent drift layer 2 becomes narrow, the JFET resistance increases, and as a result, the on-resistance increases. On the other hand, in Figure 14 In the silicon carbide semiconductor device 100 shown, the electric field alleviating effect is equivalent to that of the silicon carbide semiconductor device 902. In addition, since the width of the adjacent drift layer 2 does not become narrow, an increase in the JFET resistance can be suppressed. As a result, the on-resistance can be decreased.

[0110] As described above, in the silicon carbide semiconductor device 100, by locally forming the electric field alleviating layer 9 below the connection layer 8, the effect of being able to increase the electric field strength at device cutoff, that is, the breakdown voltage, and decrease the on-resistance can be achieved. In this way, it can be said that the trade-off between the breakdown voltage and the on-resistance can be improved.

[0111] Use Figure 17 and Figure 18 to illustrate the first modification example of the silicon carbide semiconductor device of Embodiment 1. Figure 17 is a cross-sectional view showing a silicon carbide semiconductor device 101 obtained by deforming the silicon carbide semiconductor device 100 of the present embodiment. In addition, Figure 18 is a cross-sectional view showing one process of the manufacturing method of the silicon carbide semiconductor device 101.

[0112] As Figure 17 shown, a current diffusion layer 18 having a higher impurity concentration of the first conductivity type than that of the drift layer 2 may also be formed below the body region 3. In this case, in the manufacturing process, in the process described in Figure 5 , when the body region 3, the body contact region 4, and the source region 5 are respectively formed by ion implantation in the upper part of the semiconductor layer 15, the current diffusion layer 18 is also formed as Figure 18 shown.

[0113] In the silicon carbide semiconductor device 101 configured in this way, below the body region 3, current easily diffuses laterally, or the depletion layer width below the body region 3 becomes small, whereby the current path can be expanded. As a result, the effect of being able to increase the on-current density in the drift layer 2 other than the formation site of the connection layer 8 and decrease the on-resistance can be achieved.

[0114] Use Figures 19 to 25 to illustrate the second modification example of the silicon carbide semiconductor device of Embodiment 1. Figure 19 is a cross-sectional view showing a silicon carbide semiconductor device 102 obtained by deforming the silicon carbide semiconductor device 100 of the present embodiment. In addition, Figures 20 to 25 is a cross-sectional view showing each process of the manufacturing method of the silicon carbide semiconductor device 102.

[0115] As Figure 19 shown, the silicon carbide semiconductor device 102 has a drift layer with a two-layer structure including a first drift layer 21 and a second drift layer 22, instead of the drift layer 2 included in the semiconductor layer 15 of the silicon carbide semiconductor device 100, and is different from the silicon carbide semiconductor device 100 in this regard. This is due to the manufacturing method of the silicon carbide semiconductor device 102.

[0116] Use Figures 20 to 25 to illustrate the manufacturing method of the silicon carbide semiconductor device 102.

[0117] As Figure 20 shown, a first drift layer 21 of the first conductivity type is formed on a substrate 1 which is a silicon carbide substrate of the first conductivity type by epitaxial crystal growth. At this time, it is formed in such a manner that the impurity concentration of the first conductivity type in the first drift layer 21 is included in the impurity concentration range of the first conductivity type in the drift layer 2 described in the silicon carbide semiconductor device 100 according to Embodiment 1.

[0118] As Figure 21 shown, a mask 26 having an opening is formed on the semiconductor layer 15. Then, a part of an electric field relaxation layer 9 and a connection layer 8 of the second conductivity type are formed by ion implantation using the mask 16. At this time, the impurity concentration of the second conductivity type of the electric field relaxation layer 9 is lower than the impurity concentration of the second conductivity type of the connection layer 8.

[0119] As Figure 22 shown, a mask 27 having an opening narrower than the mask 26 in the pitch ratio Figure 21 is formed. By ion implantation using the mask 27, a protective layer 7 of the second conductivity type is formed in a part of the region of the electric field relaxation layer 9 and the connection layer 8 formed in Figure 21 .

[0120] As Figure 23 shown, a second drift layer 22 of the first conductivity type is formed on the first drift layer 21 by epitaxial crystal growth. At this time, it is sufficient that the impurity concentration of the first conductivity type of the second drift layer 22 is included in the impurity concentration range of the first conductivity type in the above-described drift layer 2, and it may be the same as or different from the impurity concentration of the first conductivity type of the first drift layer 21.

[0121] As Figure 24 shown, a body region 3, a body contact region 4, and a source region 5 are formed in the second drift layer 22. The body region 3 can be formed by ion implantation or epitaxial crystal growth.

[0122] As Figure 25As shown, a mask 28 having an opening is formed on the body contact region 4 and the source region 5. Through reactive ion etching (RIE), a trench 6 is formed that penetrates the surface of the source region 5 exposed in the opening of the mask 28, passes through the source region 5 and the body region 3, and reaches the surface of the protective layer 7, which is the bottom surface of the second drift layer 22.

[0123] After that, inclined ion implantation is performed on the side surface of the trench 6 facing the semiconductor layer 15 from a direction perpendicular to the surface, whereby the remaining part of the connection layer 8 that is in contact with the body region 3 is formed in the second drift layer 22 in a manner that is in contact with a part of the surface of the connection layer 8 already formed in the first drift layer 21. At this time, the width of the connection layer 8 may also be uneven. In addition, the connection layer 8 may also be formed by performing ion implantation in a direction perpendicular to the surface.

[0124] Furthermore, a gate insulating film 10 is formed on the bottom surface and the side surface inside the trench 6, and a gate electrode 11 is formed on the gate insulating film 10 so as to be buried in the trench 6. Then, after forming an interlayer insulating film 14 so as to cover the gate electrode 11, a source electrode 12 is formed in a manner that is in contact with the surface of the source region 5 and the surface of the body contact region 4, and a drain electrode 13 is formed on the back surface of the substrate 1.

[0125] Through the above processes, the Figure 19 shown silicon carbide semiconductor device 102 is completed.

[0126] In the silicon carbide semiconductor device 102 configured in this way, a device structure is adopted in which the second drift layer 22 is formed after the electric field relaxation layer 9 is formed, so that the electric field relaxation layer 9 can be formed at a deeper position in the drift layer. As a result, an effect is achieved in which the width of the electric field relaxation layer 9 can be formed wide regardless of the width of the trench 6 below the trench 6.

[0127] Embodiment 2.

[0128] Use Figure 26 to illustrate the silicon carbide semiconductor device of Embodiment 2. Figure 26 is a cross-sectional view showing the silicon carbide semiconductor device 200 of this embodiment.

[0129] Compared with the silicon carbide semiconductor device 100 of Embodiment 1, the structure of the protective layer 7 and its manufacturing method are different in the silicon carbide semiconductor device 200. Regarding other structures and manufacturing methods of the silicon carbide semiconductor device 200, they are the same as those of the silicon carbide semiconductor device 100, so the description is omitted.

[0130] As Figure 26As shown, in the silicon carbide semiconductor device 200, the second-conductive-type protective layer 7 provided below the trench 6 includes two layers: a first protective layer 7a with a high impurity concentration and a second protective layer 7b provided below the first protective layer 7a and having an impurity concentration lower than that of the first protective layer 7a.

[0131] Describe the manufacturing method of the silicon carbide semiconductor device 200.

[0132] In the manufacturing method of the silicon carbide semiconductor device 100 of Embodiment 1, after forming the trench 6 in the same manner as described in Figures 4 to 6 After forming the trench 6, the second protective layer 7b is formed in the drift layer 2 at the bottom surface of the trench 6 by ion implantation.

[0133] After that, the first protective layer 7a having an impurity concentration higher than that of the second protective layer 7b is formed by ion implantation below the trench 6 and above the second protective layer 7b with an implantation energy smaller than that when forming the second protective layer 7b.

[0134] After forming the protective layer 7 including the first protective layer 7a and the second protective layer 7b in this way, other structures are formed by the same processes as the processes described later in the manufacturing method of the silicon carbide semiconductor device 100 of Embodiment 1, and the silicon carbide semiconductor device 200 is completed. Figure 8 After that, other structures are formed by the same processes as the processes described later, and the silicon carbide semiconductor device 200 is completed.

[0135] In addition, the protective layer 7 including the first protective layer 7a and the second protective layer 7b is not limited to the manufacturing method of forming after forming the trench 6. For example, the first protective layer 7a and the second protective layer 7b can also be locally formed in the semiconductor layer 15 from the surface of the semiconductor layer 15 shown in the manufacturing method of the silicon carbide semiconductor device 100 of Embodiment 1. Figure 4 As shown, the first protective layer 7a and the second protective layer 7b are locally formed in the semiconductor layer 15 from the surface of the semiconductor layer 15.

[0136] In addition, the first protective layer 7a and the second protective layer 7b can also be formed by ion implantation through the same process as the process of forming the protective layer 7 by ion implantation described in the manufacturing method of the silicon carbide semiconductor device 102 shown in Figure 22 As shown, after forming the first protective layer 7a and the second protective layer 7b by ion implantation, the second drift layer 22 is formed by epitaxial crystal growth.

[0137] Describe the effects of the silicon carbide semiconductor device 200 configured in this way.

[0138] In a trench gate type silicon carbide semiconductor device, when the device is turned off, the electric field concentrates near the bottom surface of the protective layer 7. Therefore, by forming the protective layer 7 from a first protective layer 7a and a second protective layer 7b provided below the first protective layer 7a and having an impurity concentration lower than that of the first protective layer 7a, the width of the depletion layer extending in the second protective layer 7b with a low impurity concentration is enlarged, and the electric field strength at the junction in the depletion layer can be reduced. Thus, the effect of further improving the breakdown voltage can be achieved.

[0139] In addition, it is preferable that the impurity concentration of the second protective layer 7b is equal to or higher than the impurity concentration of the adjacent electric field relaxation layer 9. When the electric field concentrates at the bottoms of the protective layer 7 and the electric field relaxation layer 9, the corners of the electric field relaxation layer 9 where the bottom surface and the side surface are exposed to the drift layer 2 are most likely to have a high electric field. Therefore, by making the impurity concentration of the second protective layer 7b equal to or higher than that of the electric field relaxation layer 9, the width of the depletion layer extending in the second protective layer 7b from the junction becomes equal to or less than the width of the depletion layer extending in the electric field relaxation layer 9. Thereby, by making it easier for the electric field to be applied to the bottom surface of the second protective layer 7b, the effect of further relaxing the electric field concentrated on the electric field relaxation layer 9 and improving the breakdown voltage can be achieved.

[0140] Embodiment 3.

[0141] Use Figure 27 to illustrate the silicon carbide semiconductor device of Embodiment 3. Figure 27 is a cross-sectional view showing the silicon carbide semiconductor device 300 of the present embodiment.

[0142] Compared with the silicon carbide semiconductor device 100 of Embodiment 1, the structures and manufacturing methods of the connection layer 8 and the electric field relaxation layer 9 of the silicon carbide semiconductor device 300 are different. Regarding other structures and manufacturing methods of the silicon carbide semiconductor device 300, they are the same as those of the silicon carbide semiconductor device 100, so the description is omitted.

[0143] As Figure 27 shown, in the silicon carbide semiconductor device 300, an electric field relaxation layer 9 is provided in contact with the bottom surface of the connection layer 8 and the bottom surface of the protective layer 7. That is, the electric field relaxation layer 9 located below the connection layer 8 facing each other across the trench 6 is provided continuously below the protective layer 7.

[0144] Describe the manufacturing method of the silicon carbide semiconductor device 300.

[0145] In the manufacturing method of the silicon carbide semiconductor device 100 of Embodiment 1, at Figures 4 to 7After the formation of the protective layer 7 is completed in the same manner as the description in , while the mask 16 is formed or the mask 16 is removed, inclined ion implantation is performed from the inner wall of the trench 6. At this time, ion implantation is performed on the side surface of the trench 6 at a small implantation angle and with an energy higher than the implantation energy when forming the protective layer 7, and an electric field relaxation layer 9 is formed below the bottom surface of the protective layer 7.

[0146] After the electric field relaxation layer 9 is formed below the protective layer 7 in this way, other structures are formed in the same manner as the description after in the manufacturing method of the silicon carbide semiconductor device 100 in the first embodiment, and the silicon carbide semiconductor device 300 is completed. Figure 9 After that, other structures are formed in the same manner as the description, and the silicon carbide semiconductor device 300 is completed.

[0147] In addition, the electric field relaxation layer 9 is not limited to being continuously provided on the bottom surface of the protective layer 7, and may be separately provided in a manner that abuts at least a part of the bottom surface of the protective layer.

[0148] In addition, when the connection layer 8 and the electric field relaxation layer 9 are formed only on one of the first side surface 6a or the second side surface 6b of the trench 6, the electric field relaxation layer 9 may be provided in a manner that at least a part of the electric field relaxation layer 9 abuts the bottom surface of the protective layer 7. Alternatively, the electric field relaxation layer 9 may be formed by ion implantation to form the first drift layer 21 as in the silicon carbide semiconductor device 102, and then the second drift layer 22 is formed so that the protective layer 7 abuts the electric field relaxation layer 9.

[0149] Describe the effects of the silicon carbide semiconductor device 300 configured in this way.

[0150] In the silicon carbide semiconductor device 300, since the electric field relaxation layer 9 is formed below the protective layer 7, the depletion layer expands in the electric field relaxation layer 9 when the device is turned off, and the electric field in this part can be relaxed. The impurity concentration of the electric field relaxation layer 9 is lower than that of the protective layer 7, so the depletion layer width in the layer is wider than the depletion layer width in the protective layer 7. As a result, the electric field strength at the junction becomes lower, and as a result, the effect of improving the breakdown voltage of the element can be achieved.

[0151] In addition, since the electric field relaxation layer 9 is formed so as to straddle the bottom surfaces of the connection layer 8 and the protective layer 7, the position of the part that is joined to the drift layer 2 is constant, and local electric field concentration caused by the unevenness of the junction can be suppressed. In addition, in this case, it is preferable that the depths of the bottom surface of the protective layer 7 and the bottom surface of the connection layer 8 are constant. By making them constant, the concentration curves of the bottom surfaces of the protective layer 7 and the connection layer 8 become the same, and further, the effect of relaxing the local electric field concentration at the corners of the protective layer 7 and the bottom of the connection layer 8 and improving the breakdown voltage can be achieved. In addition, the thickness of the electric field relaxation layer 9 in the device longitudinal direction is constant in the device transverse direction, so the depletion layer expands uniformly in the longitudinal direction, and the effect of reducing the electric field strength near the lower part of the protective layer 7 can be achieved.

[0152] Embodiment 4

[0153] Use Figure 28 to describe the silicon carbide semiconductor device of Embodiment 4. Figure 28 is a cross-sectional view showing the silicon carbide semiconductor device 400 of the present embodiment.

[0154] The silicon carbide semiconductor device 400 is different from the silicon carbide semiconductor device 100 of Embodiment 1 in that a low-resistance layer 23 of the first conductivity type is provided on the side surface of the connection layer 8. Other structures and manufacturing methods of the silicon carbide semiconductor device 400 are the same as those of the silicon carbide semiconductor device 100, and thus the description thereof is omitted.

[0155] As Figure 28 shown, in the silicon carbide semiconductor device 400, a low-resistance layer 23 having a higher impurity concentration of the first conductivity type than the drift layer 2 is provided in contact with the side surface of the connection layer 8. The low-resistance layer 23 is provided in contact with the first side surface facing the side surface of the trench 6 of the connection layer 8.

[0156] Describe the manufacturing method of the silicon carbide semiconductor device 400.

[0157] In the manufacturing method of the silicon carbide semiconductor device 100 of Embodiment 1, after the formation of the trench 6 is completed by the same process as described in Figures 4 to 6 , donor ions are obliquely implanted toward the side surface of the trench 6, thereby forming a low-resistance layer 23 having a higher impurity concentration of the first conductivity type than the drift layer 2.

[0158] After the low-resistance layer 23 is formed in this way, other structures are formed by the same process as the description Figure 7 after in the manufacturing method of the silicon carbide semiconductor device 100 of Embodiment 1, and the silicon carbide semiconductor device 400 is completed.

[0159] In addition, when forming the low-resistance layer 23, donor ions may also be vertically implanted from the surface of the semiconductor layer 15, and the low-resistance layer 23 may be formed in contact with at least a part of the side surface of the protective layer 7.

[0160] Describe the effects of the silicon carbide semiconductor device 400 configured in this way.

[0161] The connection layer 8 is formed on the side of the trench 6, and thus can be said to be formed near the channel and the current conduction path. Therefore, by providing a low-resistance layer 23 that is in contact with the side surface of the connection layer 8 and has a higher concentration than the drift layer 2, the width of the depletion layer extending from the connection layer 8 toward the drift layer 2 is reduced, and the JFET resistance of this portion can be decreased. As a result, the JFET resistance of the region between the connection layers 8 facing each other across the drift layer 2 can be decreased. By doing so, the distance between the adjacent connection layers 8 in the direction perpendicular to the extending direction of the trench 6 in which the connection layer 8 is formed can be reduced. That is, the pitch of the trenches 6 and the cell pitch can be reduced, and thus the following effects can be achieved: the on-resistance can be decreased, and the electric field concentration near the bottom of the protective layer 7 when the device is turned off can be suppressed, and the breakdown voltage can be increased.

[0162] In addition, since the JFET resistance is decreased by the low-resistance layer 23, the interval between the adjacent connection layers 8 in the extending direction of the trench 6 in which the connection layer 8 is formed can be reduced. As a result, when the device is turned off, the electric field concentration at the bottom of the connection layer 8 can be suppressed to increase the breakdown voltage, and the total area of contact between the protective layer 7 and the connection layer 8 can be further increased. Therefore, the resistance between the protective layer 7 and the source electrode 12 can be decreased, and as a result, the effect of being able to decrease the loss during switching can be achieved.

[0163] Use Figure 29 to illustrate a modification example of the silicon carbide semiconductor device of Embodiment 4. Figure 29 is a plan view showing a silicon carbide semiconductor device obtained by deforming the silicon carbide semiconductor device 400 of the present embodiment.

[0164] As Figure 29 shown, the first side surface of the connection layer 8 facing the side surface of the trench 6 may be in contact with the drift layer 2, and the low-resistance layer 23 may be provided so as to be in contact with the second side surface intersecting the first side surface and the third side surface facing the second side surface. At this time, it is preferable that the side surface of the trench 6 not in contact with the connection layer 8 is covered with the low-resistance layer 23 within the active region where the channel is formed.

[0165] In the silicon carbide semiconductor device 400 configured in this way, the effect of being able to further decrease the JFET resistance around the connection layer 8 can be achieved. When the low-resistance layer 23 is formed on the side surface of the connection layer 8 facing the trench 6, the cell pitch can be reduced, and thus the decrease in the on-resistance and the increase in the breakdown voltage can be achieved simultaneously. Furthermore, when the connection layers 8 are formed separately in the extending direction of the trench 6 and the low-resistance layer 23 is formed between the connection layers 8, the interval between the connection layers 8 is made narrow, and the effect of being able to decrease the switching loss caused by the expansion of the connection area between the protective layer 7 and the connection layer 8 and being able to decrease the electric field intensity at the bottom surface of each connection layer can be achieved.

[0166] Embodiment 5.

[0167] This embodiment is a mode in which the silicon carbide semiconductor device according to the above-described Embodiments 1 to 4 is applied to a power conversion device. The present disclosure is not limited to a specific power conversion device. Hereinafter, as Embodiment 5, a case where the present invention is applied to a three-phase inverter will be described.

[0168] Figure 30 It is a block diagram showing the structure of a power conversion system to which the power conversion device according to this embodiment is applied.

[0169] Figure 30 The power conversion system shown includes a power supply 510, a power conversion device 500, and a load 520. The power supply 510 is a DC power supply that supplies DC power to the power conversion device 500. The power supply 510 can be composed of various power supplies. For example, it can be composed of a DC system, a solar cell, a storage battery, or can also be composed of a rectifier circuit or an AC / DC converter connected to an AC system. In addition, the power supply 510 can also be composed of a DC / DC converter that converts the DC power output from the DC system into specified power.

[0170] The power conversion device 500 is a three-phase inverter connected between the power supply 510 and the load 520, which converts the DC power supplied from the power supply 510 into AC power and supplies the AC power to the load 520. As Figure 30 shown, the power conversion device 500 includes: a main conversion circuit 501 that converts DC power into AC power and outputs it; a drive circuit 502 that outputs drive signals for driving each switching element of the main conversion circuit 501; and a control circuit 503 that outputs control signals for controlling the drive circuit 502 to the drive circuit 502.

[0171] The load 520 is a three-phase motor driven by the AC power supplied from the power conversion device 500. In addition, the load 520 is not limited to a specific use and is a motor mounted on various electrical devices. For example, it is used as a motor for hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioning equipment.

[0172] Hereinafter, the details of the power conversion device 500 will be described. The main conversion circuit 501 includes switching elements and freewheeling diodes (not shown). By switching the switching elements, the DC power supplied from the power source 510 is converted into AC power and supplied to the load 520. The specific circuit structure of the main conversion circuit 501 has various structures. The main conversion circuit 501 according to the present embodiment is a two-level three-phase full-bridge circuit, and can include six switching elements and six freewheeling diodes connected in anti-parallel with each switching element. The semiconductor device according to any one of the above-described Embodiments 1 to 4 is applied to each switching element of the main conversion circuit 501. The six switching elements are connected in series in pairs of two switching elements to form upper and lower branches, and each upper and lower branch forms each phase (U phase, V phase, W phase) of the full-bridge circuit. Moreover, the three output terminals of the main conversion circuit 501, which are the output terminals of each upper and lower branch, are connected to the load 520.

[0173] The drive circuit 502 generates drive signals for driving the switching elements of the main conversion circuit 501 and supplies them to the control electrodes of the switching elements of the main conversion circuit 501. Specifically, in accordance with the control signals from the control circuit 503 described later, drive signals that turn the switching elements on and drive signals that turn the switching elements off are output to the control electrodes of the respective switching elements. When the switching element is maintained in the on state, the drive signal is a voltage signal (on signal) that is equal to or higher than the threshold voltage of the switching element. When the switching element is maintained in the off state, the drive signal is a voltage signal (off signal) that is lower than the threshold voltage of the switching element.

[0174] The control circuit 503 controls the switching elements of the main conversion circuit 501 to supply desired power to the load 520. Specifically, the time (on time) during which each switching element of the main conversion circuit 501 should be in the on state is calculated based on the power to be supplied to the load 520. For example, the main conversion circuit 501 can be controlled by PWM control that modulates the on time of the switching elements according to the voltage to be output. Then, at each time point, a control command (control signal) is output to the drive circuit 502 so that an on signal is output to the switching element that should be in the on state and an off signal is output to the switching element that should be in the off state. The drive circuit 502 outputs an on signal or an off signal as a drive signal to the control electrode of each switching element in accordance with this control signal.

[0175] In the power conversion device according to the present embodiment, the silicon carbide semiconductor device according to Embodiments 1 to 4 is applied as the switching element of the main conversion circuit 501, so that efficient operation can be achieved.

[0176] In this embodiment, an example in which the present invention is applied to a two-level three-phase inverter has been described. However, the present invention is not limited thereto, and can be applied to various power conversion devices. In this embodiment, a two-level power conversion device is assumed. However, it may also be a three-level or multi-level power conversion device. When supplying power to a single-phase load, the present invention can also be applied to a single-phase inverter. In addition, when supplying power to a DC load or the like, the present invention can also be applied to a DC / DC converter or an AC / DC converter.

[0177] In addition, the power conversion device in the present disclosure is not limited to the case where the above load is a motor. For example, it can also be used as a power supply device for an electric discharge machine, a laser processing machine, an induction heating cooker, or a non-contact power supply system, and can also be used as a power conditioner for a solar power generation system, a power storage system, or the like.

[0178] In addition, appropriate combination, modification, or omission of each embodiment is also included within the scope of the present disclosure.

Claims

1. A silicon carbide semiconductor device comprising: a substrate of a first conductivity type; A drift layer of the first conductivity type is disposed on the substrate and is composed of silicon carbide; A body region of the second conductivity type, disposed on the drift layer; A source region of a first conductivity type, disposed on the body region; A source electrode connected to the source region; A gate insulating film is disposed on an inner surface of a trench, the trench penetrates the body region and the source region, and the bottom surface of the trench is located in the drift layer; a gate electrode, disposed in the trench via the gate insulating film; A second conductive type protection layer is disposed below the gate insulating film; A second conductive type connection layer is disposed in the drift layer and is connected to the protection layer and the body region; as well as The second conductivity type electric field relaxation layer is provided below the connection layer in contact with the bottom surface of the connection layer, and the second conductivity type impurity concentration of the second conductivity type electric field relaxation layer is lower than that of the connection layer.

2. The silicon carbide semiconductor device according to claim 1, It is characterized in that The second conductivity type impurity concentration of the electric field relaxation layer is lower than the second conductivity type impurity concentration of the protective layer.

3. The silicon carbide semiconductor device according to claim 1 or 2, It is characterized in that The protective layer comprises: a high-concentration protective layer disposed on the bottom surface side of the trench, wherein the second conductivity type impurity concentration of the high-concentration protective layer is higher than that of the body region; and The low-concentration protective layer is provided in contact with the lower portion of the high-concentration protective layer, and the second conductivity type impurity concentration of the low-concentration protective layer is lower than that of the high-concentration protective layer.

4. The silicon carbide semiconductor device according to claim 1 or 2, It is characterized in that It also includes a first conductivity type low resistance layer, which is disposed in contact with the side surface of the connection layer, and the first conductivity type impurity concentration of the first conductivity type low resistance layer is higher than that of the drift layer.

5. The silicon carbide semiconductor device according to claim 1 or 2, It is characterized in that The electric field relaxation layer is in contact with a bottom surface of the protective layer.

6. The silicon carbide semiconductor device according to claim 1 or 2, It is characterized in that The connection layers are arranged to face each other across the groove, The electric field relaxation layer is in contact with the bottom surface of the connection layer and the bottom surface of the protection layer which face each other via the groove, and is provided in a continuous manner below the protection layer.

7. The silicon carbide semiconductor device according to claim 1 or 2, It is characterized in that The width of the electric field relaxation layer is less than or equal to the width of the connection layer.

8. The silicon carbide semiconductor device according to claim 1 or 2, It is characterized in that The drift layer includes two layers: a first drift layer and a second drift layer.

9. A power conversion device comprising: A main conversion circuit, comprising the silicon carbide semiconductor device according to any one of claims 1 to 8, the main conversion circuit converting input power and outputting the converted power; A driving circuit outputting a driving signal to the silicon carbide semiconductor device; as well as The control circuit outputs a control signal to the driving circuit.

10. A method for manufacturing a silicon carbide semiconductor device, include: A step of forming a semiconductor layer of a first conductivity type made of silicon carbide on a substrate; A step of forming a body region of a second conductivity type in an upper portion within the semiconductor layer; A step of forming a source region of a first conductivity type on a surface of the body region; A step of forming a trench that penetrates the body region from a surface of the source region; A step of forming a gate insulating film on an inner surface of the trench; A step of forming a gate electrode in the trench with the gate insulating film interposed therebetween; A step of forming a protective layer of a second conductivity type below the gate insulating film; A step of forming an electric field relaxation layer of a second conductivity type by performing inclined ion implantation on a side region of the protective layer; And A step of forming a connection layer of a second conductivity type having a higher impurity concentration of the second conductivity type than the electric field relaxation layer by performing inclined ion implantation on an upper region of the electric field relaxation layer, The connection layer of the second conductivity type is in contact with the protective layer and the body region, The electric field relaxation layer of the second conductivity type is in contact with a bottom surface of the connection layer.

11. The method for manufacturing a silicon carbide semiconductor device according to claim 10, Characterized in that The connection layer is formed by inclined ion implantation having an angle θ1 with respect to a direction perpendicular to a surface of the source region, The electric field relaxation layer is formed by inclined ion implantation having an angle θ2 with respect to a direction perpendicular to a surface of the source region, The angle θ1 is greater than the angle θ2.

12. A method for manufacturing a silicon carbide semiconductor device, Comprising: A step of forming a first drift layer of a first conductivity type made of silicon carbide on a substrate; A step of forming an electric field relaxation layer of a second conductivity type within the first drift layer; A step of forming a part of a connection layer of a second conductivity type having a higher impurity concentration of the second conductivity type than the electric field relaxation layer in an upper portion within the first drift layer in contact with a surface of the electric field relaxation layer; A step of forming a protective layer in a part of a region where the electric field relaxation layer and the connection layer are formed; A step of forming a second drift layer of a first conductivity type by epitaxial crystal growth on the first drift layer; A step of forming a body region of a second conductivity type in an upper portion within the second drift layer; A step of forming a source region of a first conductivity type on a surface of the body region; A step of forming a trench that penetrates the source region and the body region from a surface of the source region and reaches a bottom surface of the second drift layer and a surface of the protective layer; A step of forming another part of the connection layer within the second drift layer in contact with a part of the connection layer on a surface side; A step of forming a gate insulating film on an inner surface of the trench; And A step of forming a gate electrode in the trench with the gate insulating film interposed therebetween.

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