Capacitive synapse component and control method thereof

Abstract

The present invention relates to a capacitive synaptic component, which is composed of a layered structure consisting of a gate electrode (1), the capacitive synaptic component comprising a first dielectric layer (2) connected to the gate electrode (1), a second dielectric layer (4), a readout electrode (5) connected to the second dielectric layer (4), and an intermediate layer (3) arranged between the first dielectric layer (2) and the second dielectric layer (4). The present invention also relates to a method for writing and reading the component. The problem that the present invention aims to solve is to achieve a high capacitance deviation rate without changing the plate spacing, surface area, relative dielectric constant or limiting lateral scalability. The solution to this problem is to design the intermediate layer as a layer with adjustable shielding behavior in the electric field, the layer being able to extend from the gate electrode to the readout electrode, and the intermediate layer being provided with one or more suitable contacts that enable charge to flow into or out of the intermediate layer.

Description

Technical Field

[0001] The present invention relates to a capacitive synapse component, comprising a layered structure composed of a gate electrode, the capacitive synapse component including a first dielectric layer connected to the gate electrode, a second dielectric layer, a readout electrode connected to the second dielectric layer, and an intermediate layer arranged between the first dielectric layer and the second dielectric layer. The capacitive synapse component is composed of a conductive material, a semiconductor material, an insulating material, or graphene.

[0002] The invention further relates to an arrangement for such a capacitive synapse component and a method according to the invention for writing to and reading from such a capacitive synapse component.

[0003] The capacitive synapse component refers to a capacitive component that can be used for weighted multiplication in an artificial neural network. Background Art

[0004] In recent years, artificial neural networks have played an increasingly important role in image and object recognition, as well as in data processing, and in the future, they will have significant relevance in the application of artificial intelligence.

[0005] Inspired by biology, artificial neural networks consist of information-processing neurons that are connected to many other neurons via weighted connections, so-called synapses. In this case, the output signal of a neuron is either greatly weakened in the weighted connections or transmitted very well to the next neuron. In the case of plasticity in the synaptic connections, the output signal of a neuron can be strengthened or weakened in stages. In biological neural networks, the input signals of a neuron are weighted and then summed, and these input signals are integrated over time. When the signal reaches a threshold, the neuron emits a new signal. In so-called multilayer perceptrons, the input signals of neurons can also be summed, but these input signals are distorted nonlinearly in the multilayer perceptron in the form of sigmoid functions, hyperbolic tangent functions or rectified linear units (ReLUs).

[0006] The problem with today's computer architectures is that they are largely based on the so-called von Neumann architecture, which maintains a strict separation between memory and processors. The computations in artificial neural networks also require a large number of multiplications and summations. Weighted multiplications are ultimately made up of synaptic weights, while summations are performed at the neuron inputs. Because not all weights can be stored close to the processor, they must typically be loaded from main memory into the processor before the multiplications and summations are performed, a process that consumes considerable energy.

[0007] For this reason, various neuromorphic computer architectures have been developed in recent years to achieve high energy efficiency in artificial neural networks. For example, since weighted multiplication in artificial neural networks can be viewed as vector-matrix multiplication, the matrix structure that stores weights is particularly suitable for achieving high energy efficiency in artificial neural networks. In this matrix structure, the input vectors applied to the matrix word lines correspond to the output signals of the neuron layer. These input vectors are multiplied at the intersection of the matrix, where the weights are stored as quasi-analog values ​​and the signals are summed on the bit lines. The output signal of the sum on the bit lines can be connected to the neurons in the next layer (Tsai et al.: Recent progress in analog memory-based accelerators for deep learning).

[0008] Examples of implementing weighting in matrices include resistive memory components, such as memristors (US20180019011A1), phase-change memory, or floating-gate transistors. For resistive memory components, multiplication is performed using Ohm's law: I = G x U, where the voltage U is the input on the word line and G is the freely adjustable conductance of the resistive memory component. The current I is summed on the bit lines. This approach allows calculations to be performed directly in the memory, avoiding the data transfer required in von Neumann architectures.

[0009] A fundamental disadvantage of resistive components is that they all have power losses. Therefore, embodiments using capacitive components are advantageous, as the latter ideally only produce reactive power and no static power consumption (Di Ventra et al.: Circuit elements with memory-memristors, memcapacitors, and meminductors, Proceedings of the IEEE or WO2016068886A1, US5146542A, WO1991018360A1).

[0010] Various components have been proposed for application to such memory capacitor components.

[0011] What most memristor components have in common is that the capacitance can be expressed by the equation C = ε r ε0·A / d is used for adjustment, and the components can be subdivided into components that use the change of plate spacing d, components that use the change of area A, or components that use the relative dielectric constant ε rComponents that vary the plate spacing d. Examples of components that utilize a variation in the plate spacing d are memristor-like components, where the doping front of oxygen vacancies affects the plate spacing of the capacitor (US20120014170A1, WO2011025495A1). Micromechanical components have also been disclosed (Emara et al.: Non-volatile low-power crossbar memcapacitor-based memory), where the plate spacing is mechanically adjusted. Metal-ferroelectric-semiconductor-metal layer structures can also serve as components with a variable plate spacing d, where the width of the depletion layer in the semiconductor is non-volatilely adjusted by the polarization state of the ferroelectric (DE102014105639B3, US5524092A1, Min et al.: Tristate Memory Using Ferroelectric-Insulator-Semiconductor Heterojunctions for 50% Increased Data Storage). The width of the depletion layer varies with the plate spacing.

[0012] In US2019303744A1 or in the document Wang et al.: Capacitive neural network with neuro-transistors, an example of a component with an area change is disclosed. The publication includes a memristor with a parallel parasitic capacitance and a series capacitance, wherein the capacitance of the parallel parasitic capacitance must be much lower than the series capacitance, which is achieved by the small area in the example. If a higher total capacitance is set, the memristor will short-circuit the parasitic capacitance. In the document Zheng et al.: Artificial Neural Network Based on Doped HfO2 Ferroelectric Capacitors with Multilevel Characteristics or in the document Driscoll et al.: Memory metamaterials, examples of components with a relative dielectric constant change are provided. These concepts are entirely based on ion-based components (Krems et al.: Ionic Memcapacitive Effects in Nanopores) or components based on the tunnel effect (Martinez et al.: Solid-state memcapacitor).

[0013] Since it is desirable to achieve as high a ratio of minimum to maximum capacitance (dynamic ratio) as possible in the synaptic component in order to be able to store as many capacitance values ​​as possible, it is necessary to achieve a high contrast between the minimum and maximum plate spacings d, given that the component can vary the plate spacing. The problem is that a very large plate spacing d for the minimum capacitance will limit lateral scaling relative to small technology nodes of the component. With a large plate spacing d, stray coupling will primarily occur between adjacent cells, which is undesirable. On the other hand, a very small plate spacing d for the maximum capacitance will result in very large tunneling currents between the capacitor plates. For example, if the swing ratio between the minimum and maximum capacitance is greater than 1:100 and the maximum thickness d is 30 nm, it is necessary to set the minimum thickness of the maximum capacitance to 0.3 nm. At this thickness, direct tunneling will occur, and the advantage of low power loss in the capacitor component will disappear.

[0014] Different plate dimensions A also present lateral scaling issues, and variations in relative permittivity can also limit material choices or make them possible only with low dynamic swing ratios.

[0015] Patent WO002018069359A1 has proposed a capacitor matrix structure with a layer of variable shielding length, but it is mainly used to store digital information, and the method described in the patent on how to select a single storage unit is not very relevant to neuromorphic applications.

[0016] Patent US2018 / 0166448 describes a memory cell containing a ferroelectric dielectric and a method for manufacturing the same. Although this memory cell differs from the present invention in purpose and function, it describes a physical structure similar to the structure according to the present invention. Therefore, the following will be based on this prior art. The patent describes an improved DRAM memory, in which the speed in the fin field effect transistor (FinFET) is improved by a ferroelectric in the gate dielectric, and the retention rate is optimized by a lower subthreshold leakage current (negative capacitance). However, this technical solution does not describe a variable capacitor with a non-volatile memory effect, but describes a layer structure comprising the following: a first metal layer-a buffer layer-a ferroelectric layer-a layer with charge traps-an insulating layer-a second metal layer. The layer with charge traps can be composed of a conductive material, a semiconductor material, an insulating material, or graphene. In this case, the layer is not used as a shielding layer, but as another storage layer located next to the ferroelectric. A good shielding layer must enable fast charge carrier transfer, which is not possible with the layer described in US2018 / 0166448 because the layer is potential-free / floating and the transfer of charge carriers, if possible at all, can only occur slowly via tunneling.

[0017] In the future, synaptic components that will also become highly correlated will not have just two terminals, but an additional modulatory terminal that can change the connection based on the activity of another variable. This has only been possible with resistive components so far (Yang et al.: Memristive Physically Evolving Networks Enabling the Emulation of Heterosynaptic Plasticity).

[0018] Furthermore, in addition to weighted multiplication with fixed weights, multiplication between all variables also plays a role in artificial neural networks. While multiplication between analog voltage values ​​requires complex analog circuits, it is advantageous to use a single electronic component to perform this multiplication in a manner similar to weighted multiplication. Summary of the Invention

[0019] One of the objectives of the present invention is to define a capacitive synaptic component with multiple non-volatile memory states that can achieve a high capacitance swing ratio without changing the plate spacing, area, or relative permittivity, or without limiting lateral scalability. Furthermore, there should be an additional modulation terminal.

[0020] The type of capacitive synapse component mentioned in the introduction is configured according to the invention in that the intermediate layer behaves as a layer with adjustable shielding behavior in the electric field, the intermediate layer can extend from the gate electrode in the direction of the readout electrode, and the intermediate layer has one or more dedicated contacts that enable charge to flow into or out of the intermediate layer.

[0021] In the case of strong shielding by the intermediate layer, the electric field lines from the gate electrode will terminate on or in the intermediate layer; in the case of weak shielding, the electric field lines will terminate mainly on the readout electrode. In other words, the through-coupling of the electric field from the gate electrode to the readout electrode is controlled by the degree of shielding by the intermediate layer. The high swing ratio is mainly ensured by the effective shielding of the intermediate layer, which enables the electric field to be effectively completely interrupted. This is the fundamental difference from the prior art mentioned in the introduction, in which the swing ratio is achieved by methods such as changing the spacing between the capacitor plates, which have the disadvantages mentioned. Now, even thin layers can achieve a sufficiently high swing ratio, which can better achieve lateral scalability. In addition, the component has a third terminal on the intermediate layer, which enables further modulation.

[0022] For convenience, the first dielectric layer and / or the intermediate layer are defined as active storage media. The shielding strength of the intermediate layer can be stored in a non-volatile manner, or by virtue of the intermediate layer itself having a storage function; and / or by virtue of the storage function of the first dielectric layer through interaction between the first dielectric layer and the intermediate layer.

[0023] The first dielectric layer can serve as an active storage medium for storing different charge states.

[0024] The storage of different charge states in the dielectric layer can change the voltage point of the screen in the intermediate layer. This means that the capacitance-gate voltage curve in the semiconductor intermediate layer, for example, is shifted depending on the charge state. The charge state is stored in a non-volatile manner.

[0025] In one embodiment of this aspect, it is provided that the first dielectric layer serving as the active storage medium is composed of a ferroelectric material, the electric polarization state of which can be adjusted arbitrarily between positive and negative polarizations by domain formation.

[0026] In the case that the first dielectric layer behaves as an active storage medium storing different charge states, the first dielectric layer as an active storage medium may have charge traps.

[0027] Charge traps can be generated by, for example, a nitride layer or a polycrystalline layer in the first dielectric layer. Charges are trapped in the first dielectric layer in a non-volatile manner.

[0028] If the first dielectric layer and / or the intermediate layer function as an active storage medium, the intermediate layer can be configured to function as an active storage medium that stores different resistance values. This is because the intermediate layer has a variable resistance and can store the resistance value of the variable resistor in a non-volatile manner. Therefore, in addition to the first dielectric layer, the intermediate layer itself also possesses a non-volatile storage function. High resistance reduces the influx of screening charges, resulting in an electric field transmission from the gate electrode to the readout electrode. Low resistance in the intermediate layer, however, results in strong screening.

[0029] In this case, the intermediate layer may consist of a metal-insulator junction, a memristive material, or a phase-change memory material. For example, a metal-insulator junction is observed in vanadium dioxide, where the band gap can be closed and opened (e.g., by temperature, pressure, light, or electric fields). This results in different concentrations of mobile charge carriers, thus creating a screening effect. In memristive materials (such as titanium dioxide or tantalum oxide), the resistance is varied by mobile oxygen vacancies. In phase-change memory materials, the phase transition from amorphous to crystalline is accompanied by a change in resistance.

[0030] In another embodiment, it may be provided that the intermediate layer is composed of a semiconductor material and that the intermediate layer has a nonlinear characteristic in a capacitance-voltage ratio between the gate electrode and the readout electrode.

[0031] Semiconductor materials are well-suited as intermediate layers to achieve alternating shielding. If the semiconductor operates in an inversion or accumulation mode via a gate voltage, its shielding effect is very strong; however, in a fully depleted state, with field coupling to the readout electrode, the shielding effect is weak. Consequently, a capacitive coupling window appears within a specific gate voltage range. Because the inversion and accumulation layers are very thin in the two primary cases of strong inversion and accumulation, the semiconductor layer also becomes thinner. However, this thin semiconductor layer can still achieve a very high dynamic swing rate, a significant difference from patents DE102014105639B3 and US Patent No. 5524092A1.

[0032] In another variant embodiment, provision is made for the intermediate layer to have lateral highly doped p-type and n-type regions, and for the intermediate region to be only weakly doped or intrinsic, forming a lateral psn region or pin region.

[0033] Lateral doping of p-type and n-type regions enables the injection of holes and electrons, resulting in excellent inversion and accumulation capabilities in the semiconductor region. This ultimately results in symmetrical screening for positive and negative gate voltages. This symmetry is essential for achieving high precision in synaptic components (Tsai et al.: Recent progress in analog memory-based accelerators for deep learning). Furthermore, the PSN or PIN junction offers further possibilities for modulation by applying a lateral voltage difference. The "s" in PSN denotes weak doping compared to the p-type and n-type regions.

[0034] Furthermore, it can be provided that between the first dielectric layer and the readout electrode there is a semiconductor region having a first subregion forming the intermediate layer and a second subregion having charge carrier depletion, thus forming the second dielectric layer.

[0035] The depleted semiconductor can be considered a similar dielectric layer and can therefore form the second dielectric layer. Thus, the intermediate layer and the second dielectric layer consist of a continuous semiconductor region, where the dielectric layer is characterized by depletion. In this case, the readout electrode can be embodied by the underlying doped semiconductor region or a metal region on the semiconductor bottom surface. One advantage of this arrangement is that the intermediate layer and the second dielectric layer can be composed of a continuous semiconductor material, which makes their manufacture simpler.

[0036] An arrangement using a capacitive synapse component according to the present invention achieves the objectives of the present invention by forming a matrix of multiple capacitive synapse components, wherein in each capacitive synapse component, a word line is connected to a gate electrode, a readout electrode is connected to a bit line, and an intermediate layer is connected to a shield line. Each lateral doped region has a shield line, and the shield line is embodied in a manner corresponding to the bit line, and the bit line forms an angle with the word line that is non-zero, preferably 90°.

[0037] For artificial neural network calculations, many vector-matrix multiplications must be performed, with weights stored in matrices. Therefore, it's advantageous to arrange the synaptic components in a matrix. In this arrangement, the gate electrode of the capacitive synaptic component is connected to the wordline, the readout electrode is connected to the bitline, and the terminal in the middle layer is connected to the shield line. In this case, the shield line is parallel to the bitline, which in turn is perpendicular to the wordline. The input signal, which is the vector value weighted (depending on the adjusted shield) in the capacitive synaptic component, is applied to the wordline, and the summed result is read on the bitline. Writing is performed between the shield line and the wordline.

[0038] The method for writing and reading a capacitive synapse component according to the present invention and the manner of achieving the object according to the present invention are composed of the following steps defined according to the specific circumstances:

[0039] a. In the case of non-volatile adjustment of the shield, a write voltage can be applied between the gate electrode and the intermediate layer, and different electrical states of the active storage medium can be adjusted by changing the write pulse height, write pulse duration or write pulse number, thereby achieving hierarchical writing.

[0040] That is, for example, by creating a potential difference between the gate electrode and the intermediate layer, a charge state can be stored in the first dielectric. For example, in the case of charge traps, charge is injected via quantum mechanical tunneling. For ferroelectrics, this can be achieved by changing the polarization state. For adjustable resistors in the intermediate layer, writing can be achieved by, for example, creating a metal-insulator junction or by the movement of oxygen vacancies. In this case, different states can be adjusted by varying the write pulse duration, write pulse height, or the number of write pulses, meaning that quasi-analog value storage is possible.

[0041] b. If you want to adjust the volatility of the shield one by one in the middle layer according to the specific situation, you can apply a DC voltage or a symmetrical reverse or forward voltage to the pin junction or psn junction.

[0042] In addition to enabling non-volatile adjustment of shielding, the latter approach also allows for volatile adjustment via the voltage across the interlayer. For lateral p-type and n-type regions, reverse or forward switching at a lateral pin or psn diode can cause depletion or enhancement of mobile charge carriers, thereby adjusting shielding. Furthermore, applying the same DC voltage to the terminals of the interlayer of a semiconductor material can result in a change in the gate voltage range of depletion, thereby adjusting shielding / transmission (a change in the capacitance-voltage curve).

[0043] c. In case a, the intermediate layer is grounded during readout with capacitive coupling between the gate electrode and the readout electrode, and / or in case b, the voltage of the intermediate layer during readout is as described in case b.

[0044] d. In both cases a and b, a variable voltage signal is applied to the gate electrode during readout, and a current or charge change is measured on the readout electrode, which depends on the shielding state.

[0045] In a simple readout without additional nonvolatile modulation, the interlayer is grounded and an AC voltage signal is applied to the gate electrode. The shielding in the interlayer determines the occurrence of through-coupling in the readout electrode, and an AC current with charge change can be detected in the readout electrode.

[0046] In the case of readout with additional non-volatile modulation of the intermediate layer, the voltage ratio at the intermediate layer remains the same as that required to achieve the modulation, and the AC signal is again applied to the gate electrode.

[0047] When the method according to the present invention is applied to the device according to the present invention (i.e., a matrix), it can be provided that during readout, variable voltage signals are applied in parallel to all word lines, weighted multiplication is performed at the intersections, and the current or charge changes in the bit lines are summed. In this case, the input (i.e., the vector values ​​of the vector-matrix multiplication) corresponds to the AC signal on the word lines, and the matrix summation result corresponds to the current or accumulated charge on the bit lines.

[0048] In the case of a configuration where the intermediate layer has laterally highly doped p-type and n-type regions and the intermediate region is only weakly doped or implemented in an intrinsic manner, the writing of the active storage medium can be additionally modulated by means of symmetrical reverse or forward voltages applied to the pin or psn junctions, as a lateral psn or pin region is formed.

[0049] Active depletion or enhancement of the PSN or PIN junction in the intermediate layer can suppress or enhance, respectively, writing to the first dielectric. This is because sufficient charge must be present on the intermediate layer to achieve a sufficiently high electric field in the first dielectric layer. In the depletion case, the electric field is primarily coupled to the readout electrode, resulting in a lower potential drop for writing to the first dielectric.

[0050] For configurations where components are used to simulate sigmoid or ReLU neurons, during the dropout algorithm, the components are turned on or off by symmetrical reverse or forward voltages at the PIN or PSN junctions.

[0051] During neural network training, overfitting can occur, which is undesirable. This can be avoided by switching off some neurons during training and then gradually switching them back on. Capacitive synaptic components are also generally suitable for modeling rectified linear units (ReLUs) and sigmoid neurons, as the transfer functions of capacitive coupling behave similarly. These neurons can be switched on or off by flooding or depleting the intermediate layers with charge carriers.

[0052] In another method of writing to the device, Fowler-Nordheim tunneling or hot carrier injection can be used, where the hot carriers are generated by applying a voltage across a pin or psn junction.

[0053] During writing to the first dielectric layer with charge traps, charge carriers can be injected into the charge traps via Fowler-Nordheim tunneling or hot carrier injection. Lateral PSN or PIN junctions can also be used to generate hot carriers. In the off-state region, sufficient hot carriers can be generated given a sufficiently high reverse voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] The present invention will be explained in more detail below based on a number of exemplary embodiments. The accompanying drawings show:

[0055] Figure 1 The general structure of a capacitive synapse component of the present application with typical capacitive coupling between a gate electrode and a readout electrode is shown.

[0056] Figure 2 The structure of the capacitive synapse component of the present application with lateral p-doped and n-doped regions is shown.

[0057] Figure 3 The structure of the capacitive synapse component of the present application with lateral doping and bisecting semiconductor regions is shown.

[0058] Figure 4 The structure of the capacitive synapse component with variable resistance of the present application is shown.

[0059] Figure 5 The arrangement of capacitive synapse components in the matrix of the present application is shown.

[0060] Figure 6 The present application shows a capacitive synapse component having a ferroelectric material as the first dielectric layer, or a capacitive synapse component having charge traps in the first dielectric layer.

[0061] Figure 7 The present application shows graded writing to an active storage dielectric as a function of write pulse height, write pulse length, or number of write pulses.

[0062] Figure 8 The present invention shows the reading of a capacitive synaptic component with a variable voltage signal in the gate electrode, and stores the related capacitance-voltage curve in a non-volatile manner.

[0063] Figure 9 The present invention shows the fluctuating adjustment of the shielding with symmetrical forward or reverse voltage at the pin junction (along with a variable voltage signal on the gate electrode for readout) and the associated capacitance-voltage curves.

[0064] Figure 10 The present invention shows the fluctuating adjustment of the shielding by a DC voltage on the intermediate layer (along with a variable voltage signal on the gate electrode for readout) and the related capacitance-voltage curve.

[0065] Figure 11 The present invention shows the use of a symmetrical forward or reverse voltage at a pin junction to modulate writing to an active storage medium and the related capacitance-voltage curve. DETAILED DESCRIPTION

[0066] The intermediate layer 3 can either shield the electric field from the gate electrode 1 or transmit it to the underlying readout electrode 5. This transmission is accompanied by capacitive coupling 16, where the swing ratio between transmission and shielding can be quite large. The active storage medium ultimately adjusts the degree of coupling according to a specific voltage, with the goal of enabling multiple states to be stored to form a quasi-analog value. Figure 1 The general structure is shown with a gate electrode 1, a first dielectric layer 2, an intermediate layer 3 with lateral terminals, a second dielectric layer 4 and a readout electrode 5. If the intermediate layer 3 consists of a semiconductor material, then Figure 1The curve on the right side of the center plots the capacitance-voltage relationship between the gate electrode and the readout electrode. The semiconductor shields the electric field during inversion and accumulation, while transmitting the electric field during full depletion. Despite the extremely thin inversion and accumulation layers, and the semiconductor being only a few nanometers thick, the device still achieves a high dynamic swing ratio.

[0067] Figure 2 The same structure is shown with lateral p-type and n-type regions, the latter of which can inject both holes and electrons, thus achieving symmetry. Furthermore, an additional modulation voltage can be applied. The p-type and n-type regions each have a dedicated terminal.

[0068] like Figure 3 As shown, the second dielectric layer 4 can also be composed of a depleted semiconductor region, thereby forming a continuous semiconductor region together with the intermediate layer 3. The readout electrode 5 can be implemented as a doped region, such as Figure 3 As shown in the figure on the right, it can also be implemented as a metal area under the semiconductor. The advantage of this arrangement is that there can be a continuous semiconductor area, which makes production simpler.

[0069] For example, Figure 4 As shown, the shielding of the intermediate layer 3 can be achieved by a variable resistor 9 in the intermediate layer, or it can be achieved in a non-volatile manner, for example, by a memristor, a metal-insulator junction, or a phase change memory. In the case of high resistance, the intermediate layer 3 does not receive sufficient shielding charge, thus achieving low shielding.

[0070] Figure 5 A matrix arrangement of multiple capacitive synapse components is shown. In this case, word line 10 is connected to gate electrode 1, applying an input signal. Readout electrode 5 is connected to bit line 12, and the signal is summed on bit line 12. Intermediate layer 3 is connected to shield lines 11. Both the lateral p-type and n-type regions have two shield lines 11 each. This matrix efficiently implements vector-matrix multiplication.

[0071] exist Figure 6 In FIG, the first dielectric layer 2 forms an active storage medium. The active storage medium may be a ferroelectric material 13 shown on the left, where polarization charges represent charge states, or a charge trap 14 in the first dielectric layer 2 that stores charge states.

[0072] like Figure 7 As shown, when writing to the active storage medium, a potential difference, a write voltage, is generated between the gate electrode 1 and the intermediate layer 3. Different storage states can be set by varying the write pulse duration 19, the write pulse height 20, or the number of write pulses 21. In the case of the ferroelectric material 13, this is accompanied by a gradual change in the polarization state, while in the case of the charge traps 14, this is accompanied by varying degrees of quantum mechanical tunneling of the charge carriers in the intermediate layer 3.

[0073] After writing is completed, Figure 8 As shown on the right, the nonlinear capacitance-voltage curve shifts. During readout, a variable voltage signal 15 is applied to the gate electrode 1, while the intermediate layer 3 can be grounded. In this case, a current or charge change 17 can be measured from the readout electrode 5. This current or charge change 17 depends on the screening current of the intermediate layer 3. The amount of charge is proportional to the area under the capacitance-voltage curve, which is derived from the variable voltage signal 15 at the gate electrode 1. Figure 8 If the capacitance-voltage curve in is shifted to the right, the charge change will be very small.

[0074] like Figure 9 As shown, the capacitive coupling can also be adjusted in a variable manner by applying a symmetrical reverse or forward voltage 22 at the pin or psn junction. In this case, the mobile charge carriers of the intermediate layer 3 are either depleted or filled. The corresponding capacitance-voltage curve is shown in Figure 9 As shown on the right, in the case of charge carrier depletion, the curve becomes wider, while in the case of charge carrier abundance, the curve becomes narrower and lower, and can also be completely turned off. In the case of charge carrier depletion, the variable voltage signal 15 can produce a large charge change at the readout electrode 5 if applied during the readout of the gate electrode 1.

[0075] like Figure 10 As shown, the capacitance-voltage curve can be realized not only by the charge state in the dielectric Figure 8 The offset can also be realized in a variable manner by means of a DC voltage 26 at the intermediate layer 3. The readout can also be realized by means of a variable voltage signal 15 at the gate electrode 1 and measuring the charge change at the readout electrode 5.

[0076] like Figure 11 As shown, writing to the active storage medium can also be modulated by applying a reverse or forward voltage 22 to the lateral pin junction of the intermediate layer 3. If the intermediate layer is depleted of charge carriers, it may not be possible to provide sufficient charge carriers to ensure a sufficiently high electric field in the first dielectric layer 2 for writing. This electric field is primarily coupled to the readout electrode 5, while the voltage drop across the first dielectric layer 2 is too low or reduced. In the case of charge carrier abundance, the opposite occurs. Writing to capacitive synapse components can also be modulated in this manner.

[0077] Reference Signs List

[0078] 1-Gate electrode

[0079] 2 – First dielectric layer

[0080] 3-Middle layer

[0081] 4-Second dielectric layer

[0082] 5–Readout Electrode

[0083] 6 – p-doped region

[0084] 7 – n-doped region

[0085] 8-Doped region

[0086] 9-Variable resistor, which can store its resistance value in a non-volatile manner

[0087] 10 – Word Line

[0088] 11 – Shielded wire

[0089] 12 – bit line

[0090] 13 – Ferroelectric Materials

[0091] 14–Charge Trap

[0092] 15 – Variable voltage signal

[0093] 16 – Capacitive coupling between gate electrode and readout electrode

[0094] 17 – Current or Charge Change

[0095] 18 – Capacitive coupling offset

[0096] 19 – Write pulse duration

[0097] 20 – Write pulse height

[0098] 21-Write pulse number

[0099] 22 – Symmetrical reverse or forward voltage

[0100] 23 – Reverse

[0101] 24 – Forward

[0102] 25-The second part of the semiconductor region, which is depleted of charge carriers

[0103] 26 – DC voltage

Claims

1. A capacitive synapse component comprising a layered structure consisting of a gate electrode (1), the capacitive synapse component comprising a first dielectric layer (2), a second dielectric layer (4), a readout electrode (5) connected to the second dielectric layer (4), and an intermediate layer (3) arranged between the first dielectric layer (2) and the second dielectric layer (4), wherein the first dielectric layer (2) is connected to the gate electrode (1), and the capacitive synapse component is composed of a conductive material, a semiconductor material, an insulating material or graphene, characterized in that: The intermediate layer (3) is implemented as a layer with adjustable shielding behavior in an electric field, the intermediate layer (3) extends from the gate electrode (3) in the direction of the readout electrode (5), and the intermediate layer is provided with one or more dedicated contacts for enabling charge to flow into or out of the intermediate layer; The intermediate layer (3) is made of semiconductor material and has a laterally highly doped p-type region and n-type region, and the middle region is only weakly doped or implemented in an intrinsic manner, thereby forming a laterally psn region or pin region.

2. The capacitive synapse component according to claim 1, wherein The first dielectric layer (2) and / or the intermediate layer (3) are implemented as active storage media.

3. The capacitive synapse component according to claim 2, wherein: The first dielectric layer (2) is implemented as an active storage medium that stores different charge states.

4. The capacitive synapse component according to claim 3, wherein: The first dielectric layer (2) serving as an active storage medium is composed of a ferroelectric material (13).

5. The capacitive synapse component according to claim 3, characterized in that The first dielectric layer (2) as an active storage medium has charge traps (14).

6. The capacitive synapse component according to claim 2, wherein: The intermediate layer (3) has a variable resistor (9) so that it is implemented as an active storage medium storing different resistance values, and the intermediate layer (3) stores its resistance value in a non-volatile manner.

7. The capacitive synapse component according to claim 6, characterized in that The middle layer is composed of metal-insulator junction material, memristive material or phase change memory.

8. The capacitive synapse component according to any one of claims 1 to 5, characterized in that The intermediate layer (3) has nonlinearity in the capacitance-voltage ratio of the capacitive coupling (16) between the gate electrode (1) and the readout electrode (5).

9. The capacitive synapse component according to claim 8, characterized in that A semiconductor region is arranged between the first dielectric layer and the readout electrode (5), the semiconductor region comprising a first partial region forming the intermediate layer (3) and a second partial region (25) provided with charge carrier depletion, thereby forming a second dielectric layer (4).

10. An arrangement using a capacitive synapse component according to any one of claims 1 to 9, characterized in that The matrix is ​​composed of a plurality of capacitive synaptic components, wherein in each capacitive synaptic component, a word line (10) is connected to a gate electrode (1), a readout electrode (5) is connected to a bit line (12), and an intermediate layer (3) is connected to a shielding line (11), wherein in each lateral doping region, a shielding line (11) is present, the shielding line (11) is arranged corresponding to the bit line (12), and the bit line (12) forms an angle not equal to zero with respect to the word line (10).

11. The arrangement according to claim 10, characterized in that During readout, a variable voltage signal (15) is applied in parallel to all word lines (10), weighted multiplication is performed at the intersections, and the current or charge changes (17) in the bit lines (12) are summed.

12. A method for writing and reading a capacitive synapse component according to any one of claims 1 to 9, characterized in that: a. In the case of shielded non-volatile adjustment, a write voltage is applied between the gate electrode (1) and the intermediate layer (3), and different electrical states of the active storage medium can be adjusted by different write pulse heights (20), write pulse durations (19) or write pulse numbers (21) to achieve hierarchical writing, b. applying a DC voltage (26) or a symmetrical reverse or forward voltage (22) at the pin junction or psn junction, if the shielding is volatile adjusted at the intermediate layer (3), as the case may be, c. in case a, the intermediate layer (3) is grounded during readout of the capacitive coupling (16) between the gate electrode (1) and the readout electrode (5), and / or in case b, during readout, the voltage at the intermediate layer (3) is implemented as in case b, and d. In both cases a and b, during readout, a variable voltage signal (15) is applied to the gate electrode (1) and the current or charge change (17) is measured at the readout electrode (5) depending on the shielding state.

13. The method according to claim 12, characterized in that During readout, a variable voltage signal (15) is applied in parallel to all word lines (10), weighted multiplication is performed at the intersections, and the current or charge changes (17) in the bit lines (12) are summed.

14. The method according to claim 12, characterized in that It is also possible to modulate the writing of active storage media by applying a symmetrical reverse or forward voltage (22) to the pin junction or psn junction.

15. The method of claim 12, wherein the component is used to model a sigmoid or ReLU neuron, characterized in that During the discarding algorithm, the component can be turned on or off by a symmetrical reverse or forward voltage (22) at the pin junction or psn junction.

16. The method according to claim 12, characterized in that During writing, either Forno tunneling or hot carrier injection can be used, wherein hot carriers are generated by applying a voltage in a pin junction or a psn junction.

Images