Method, device, and system for operating a device

By synchronizing the internal clock of the device with the grid frequency and adjusting the frequency by using the voltage crossing point of the power grid, the problem of inconsistency of the internal clock of the device is solved, and high-precision synchronization and time resolution are improved.

CN114731206BActive Publication Date: 2025-07-15BECKHOFF AUTOMATION GMBH
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Patent Information

Application Number
CN202080069471.1
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Priority Date
2019-11-25
Filing Date
2020-11-17
Publication Date
2025-07-15
Estimated Expiration
2040-11-17

AI Technical Summary

Technical Problem

In the prior art, the internal clock of the device is inconsistent in frequency due to changes in manufacturing tolerances and external conditions, and cannot be synchronized with high precision.

Method used

By synchronizing the internal clock of the device with the grid frequency, the frequency of the internal clock is adjusted using the voltage zero-crossing point detection of the power grid to ensure that it matches the grid frequency.

Benefits of technology

It realizes high-precision synchronization of the internal clock of the device, improves the time resolution, and ensures the synchronization of timestamps and signal outputs in the data network.

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Abstract

In a method for operating a device (100) having an internal clock generator (110) and an internal clock (120) and connected to an electrical grid (200), the internal clock (120) is incremented by means of the internal clock generator (110). Furthermore, the internal clock (120) is synchronized with the grid frequency (230) of the electrical grid (200).
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Description

Field of the Invention

[0001] The present invention relates to a method for operating a device, a device, and a system comprising at least two devices. Background Art

[0002] This patent application claims the priority of German Patent Application DE 10 2019 131 848.3, the disclosure of which is incorporated herein by reference.

[0003] It is known from the prior art that a device is equipped with an internal clock, which is incremented by means of an internal clock generator. However, it is known that the frequency of such an internal clock generator is affected by manufacturing tolerances and can also have a correlation with external conditions, such as temperature. This enables the internal clocks of two devices to run at different speeds.

[0004] Various possibilities for synchronizing the internal clocks of multiple devices are known from the prior art. Such synchronization can be achieved, for example, by means of a time source connected to the device via a data network or by means of time information contained in a GPS signal.

[0005] It is also known from the prior art to synchronize a clock, the time base of which is derived from the mains frequency of the power supply network. Summary of the Invention

[0006] The object of the present invention is to provide a method for operating a device. Another object of the present invention is to provide a device. Another object of the present invention is to provide a system having a first such device and a second such device. These objects are achieved by a method, a device, and a system for operating a device having the features of the present invention. Different improvements are given in the embodiments.

[0007] In a method for operating a device having an internal clock generator and an internal clock and connected to a power grid, the internal clock is incremented by means of the internal clock generator. Here, the internal clock is synchronized with the mains frequency of the power grid. The power grid can be, for example, a power supply grid. Advantageously, by this method, it is ensured that the internal clock of the device runs synchronously with the mains frequency of the power grid. Thereby, it is advantageously ensured that the internal clock of the device runs as fast as the internal clocks of other devices that are also synchronized with the mains frequency of the power grid. Thus, the internal clocks of these devices run synchronously. Since the internal clock of the device is incremented by means of the internal clock generator, the internal clock of the device can advantageously have a high time resolution, especially a time resolution higher than the mains frequency of the power grid.

[0008] In one embodiment of the method, the internal clock is periodically synchronized with the grid frequency of the power grid. This advantageously ensures that the time progression of the internal clock of the device regularly matches the time base predefined by the grid frequency of the power grid.

[0009] In one embodiment of the method, the power grid is a supply grid. Here, the zero-crossing of the voltage of the power grid is detected. The internal clock is synchronized with the grid frequency of the power grid at each zero-crossing of the voltage. Advantageously, the zero-crossing of the voltage of the power grid can be detected with high precision. This advantageously enables a particularly precise synchronization of the internal clock with the grid frequency of the power grid.

[0010] In one embodiment of the method, the internal clock generator has a frequency higher than the grid frequency of the power grid. The frequency of the internal clock generator can, for example, be higher by several orders of magnitude than the grid frequency of the power grid. Advantageously, the internal clock of the device can thus have a finer time resolution than the period of the grid frequency of the power grid.

[0011] In one embodiment of the method, the method includes steps for detecting a measured value and providing a time stamp of the internal clock for the measured value. The time stamp of the internal clock can here indicate the time point at which the measured value was detected. By synchronizing the internal clock with the grid frequency of the power grid according to the method, it is advantageously achieved that the time stamp relates to a time system synchronized with the grid frequency of the power grid.

[0012] In one embodiment of the method, the method includes another step for sending the time-stamped measured value via a data network. This advantageously enables further processing of the time-stamped measured value at another location, for example in another network user of the data network.

[0013] In one embodiment of the method, the method includes a step for outputting a signal at a determined time value of the internal clock. Here, it is advantageous that the internal clock is synchronized with the grid frequency of the power grid in order to ensure the synchronization of the time values of different network users of the data network.

[0014] A device includes an internal clock that can be incremented by means of an internal clock generator and a grid interface for connection to a power grid. Here, the device is configured to synchronize the internal clock with the grid frequency of the power grid. Advantageously, the internal clock of the device thus operates synchronously with the grid frequency of the power grid. This ensures that the internal clock of this device runs at the same speed as the internal clocks of other devices, whose internal clocks also synchronize their internal clocks with the grid frequency of the power grid. Since the internal clock of the device is incremented by means of an internal clock generator, the internal clock of the device can advantageously have a finer time resolution than the period of the grid frequency of the power grid.

[0015] In one embodiment of the device, the grid interface can be connected to the power grid. Here, the device is configured to detect the zero crossing of the voltage of the grid. Advantageously, the zero crossing of the voltage of the grid can be detected with high precision, whereby a particularly precise synchronization of the internal clock with the grid frequency of the grid can be achieved.

[0016] In one embodiment of the device, the internal clock generator has a frequency higher than the grid frequency of the grid. The frequency of the internal clock generator can here, for example, be higher by several orders of magnitude than the grid frequency of the grid. Advantageously, the internal clock of the device can thus have a finer time resolution than the period of the grid frequency of the grid.

[0017] In one embodiment of the device, the device is configured to detect a measured value and to assign a timestamp of the internal clock to the detected measured value. In this case, the timestamp can indicate the value of the internal clock at the time point when the measured value was detected. Since the internal clock of the device can be synchronized with the grid frequency of the grid, the timestamp then exists in a time system synchronized with the grid frequency of the grid.

[0018] In one embodiment of the device, the device is configured to send the timestamped measured value via a data network. This advantageously enables the further processing of the timestamped measured value at another location, for example in another network user of the data network.

[0019] In one embodiment of the device, the device is configured to output a signal at a determined time value of the internal clock. Here, it is advantageous that the internal clock of the device can be synchronized with the grid frequency of the grid in order to ensure the synchronization of the time values of different network users of the data network.

[0020] In one embodiment of the device, the device is configured as an EtherCAT network user. Advantageously, the internal clock of the EtherCAT network user can be synchronized with the grid frequency of the grid.

[0021] A system comprises a first device and a second device each configured in the above-described manner. Here, the first device and the second device are connected to a common grid. Thus, the grid frequency of the common grid is available to the two devices in order to synchronize the respective internal clocks of the devices. If the first device synchronizes its internal clock with the grid frequency of the grid and the second device also synchronizes its internal clock with the same grid frequency of the common grid, the internal clocks of the two devices are advantageously synchronized with each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The present invention will be explained in detail below with reference to the drawings. Shown are:

[0023] Figure 1 A schematic diagram of a system showing two devices connected to a grid;

[0024] Figure 2 shows the voltage change curve of the power grid over time;

[0025] Figure 3 shows the first data packet; and

[0026] Figure 4 shows the second data packet. Detailed implementation

[0027] Figure 1 shows a schematic diagram of system 10. System 10 includes a plurality of devices 100. In Figure 1 the example shown, system 10 includes a first device 100, 101 and a second device 100, 102. However, system 10 may also include more than two devices 100.

[0028] The devices 100 of system 10 have the consistency described below. In addition, there may also be differences between the individual devices 100 of system 10. In Figure 1 the example of system 10 shown, there are similarities and differences between the first device 100, 101 and the second device 100, 102.

[0029] The devices 100 of system 10 each have an internal clock generator 110. The internal clock generator 110 provides a clock signal with a frequency 111. Here, the frequency 111 of the clock signal provided by the internal clock generator 110 of the first device 100, 101 may be different from the frequency 111 of the clock signal provided by the internal clock generator 110 of the second device 100, 102, such that the clock signal of the internal clock generator 110 of the first device 100, 101 has a first frequency 111, 113 and the clock signal of the internal clock generator 110 of the second device 100, 102 has a second frequency 111, 115. The frequency 111 of the internal clock generator 110 of the device 100 can be, for example, a few MHz or a few GHz.

[0030] Each device 100 of system 10 has an internal clock 120. The internal clock 120 can be configured, for example, as a data register. The numerical value stored in this data register represents the time value of the internal clock 120 of the device 100. The time value of the internal clock 120 can be represented here, for example, with a resolution of 1 μs or 1 ns.

[0031] Each device 100 is configured to increment its internal clock 120 by means of the internal clock generator 110. For this purpose, the corresponding device 100 can have, for example, an adaptable parameter 112, which specifies in what proportion the internal clock 120 increments with the frequency 111 of the internal clock generator 110.

[0032] Each device 100 of system 10 has a grid interface 130. The grid interface 130 is arranged to connect the respective device 100 to the power grid 200. Here, all devices 100 of system 10 are connected to the same power grid 200.

[0033] The power grid 200 provides a grid frequency 230.

[0034] The power grid 200 can be, for example, a power supply grid. In this case, the power grid 200 provides a voltage 210, the voltage value of which varies periodically with the grid frequency 230. In the example described according to the drawings, the power grid 200 is configured as a power supply grid.

[0035] However, the power grid 200 can also be another grid that provides the grid frequency 230. For example, the power grid 200 can be formed by a simple line, and the grid frequency 230 is coupled into this line.

[0036] If the power grid 200 is a power supply grid, the power grid 200 can be used to power the device 100. However, this is not absolutely necessary. The device 100 can also meet its energy requirements from other energy sources.

[0037] The frequencies 111 of the internal clock generators 110 of the respective devices 100 of system 10 can each have a deviation from their rated values caused by component tolerances. In addition, the frequencies 111 of the internal clock generators 110 of the devices 100 of system 10 can be subject to time fluctuations, which can be caused, for example, by temperature changes. This results in that when the internal clocks 120 are not synchronized, the internal clocks 120 of the devices 100 of system 10 can run at different speeds relative to each other. For example, if the internal clocks 120 of the first devices 100, 101 and the internal clocks 120 of the second devices 100, 102 run at different speeds, the time of the internal clocks 120 of the first devices 100, 101 and the time of the internal clocks 120 of the second devices 100, 102 gradually differ during the course of time changes.

[0038] To prevent this from happening, each device 100 of system 10 is configured to synchronize the internal clock 120 with the grid frequency 230 of the common power grid 200. Thereby, the internal clocks 120 of the respective devices 100 are also synchronized with each other.

[0039] The grid frequency 230 is generally several orders of magnitude smaller than the frequency 111 of the internal clock generator 110 of the device 100. The grid frequency 230 can be, for example, 50 Hz or 60 Hz.

[0040] Figure 2A change curve of the voltage 210 of the power grid 200 related to the time 400 is shown schematically. The voltage 210 has periodically occurring zero-crossing points 220 during the course of the time 400. At a first time point 401, a first zero-crossing point 220, 221 of the voltage 210 occurs. At a second time point 402, a second zero-crossing point 220, 222 of the voltage 210 occurs. There is a half-wave of the voltage 210 between the first zero-crossing point 220, 221 and the second zero-crossing point 220, 222, such that the time interval between the first time point 401 and the second time point 402 corresponds to a half-period duration 235, which is calculated as half of the reciprocal of the grid frequency 230 of the power grid 200. If the grid frequency 230 is, for example, 50 Hz, the half-period duration 235 is 10 ms.

[0041] In order to synchronize the corresponding internal clock 120 with the grid frequency 230 of the power grid 200, each device 100 can be configured to detect the zero-crossing point 220 of the voltage 210 of the power grid 200. Here, the current value of the internal clock 120 of the corresponding device 100 is determined at each zero-crossing point 220. This is schematically shown in Figure 2 In the case of the first zero-crossing point 220, 221 of the voltage 210 at the first time point 401, the internal clock 120 has a first clock value 121. In the second zero-crossing point 220, 222 at the second time point 402, the internal clock 120 has a second clock value 122. Since the internal clock 120 has incremented between the first time point 401 and the second time point 402, the second clock value 122 is greater than the first clock value 121. The difference between the first clock value 121 and the second clock value 122 can be referred to as the clock progress 123.

[0042] If the grid frequency 230 of the electrical grid 200 is known for the respective device 100, the synchronization of the internal clock 120 with the grid frequency 230 of the electrical grid 200 can be carried out as follows: The time period elapsed between a first time point 401 and a second time point 402 corresponds to the half-cycle duration 235 of the grid frequency 230 of the electrical grid 200, which is also known for the respective device 100. Thus, by comparing the clock progress 123 with the half-cycle duration 235, it can be determined whether the internal clock 120 of the respective device 100 is running too fast or too slow. If the clock progress 123 is greater than the half-cycle duration 235, the internal clock 120 is running too fast and must be slowed down. If the clock progress 123 is less than the half-cycle duration 235, the internal clock 120 is running too slow and must be accelerated. The deceleration or acceleration of the internal clock 120 can be achieved in each device 100 of the system 10, for example, by adapting an adaptable parameter 112, which indicates in what ratio the respective internal clock 120 increases with the frequency 111 of the internal clock generator 110.

[0043] An alternative possibility for synchronizing the internal clock 120 with the grid frequency 230 of the electrical grid 200 is to adjust the speed of the internal clock 120 such that the clock progress 123 between successive zero crossings 220 of the voltage 210 always remains approximately the same. If the clock progress 123 increases over time between successive zero crossings 220 of the voltage 210, the internal clock 120 is running too fast and must be slowed down. If the clock progress 123 decreases over time between successive zero crossings 220 of the voltage 210, the internal clock 120 is running too slow and must be accelerated. The deceleration or acceleration of the internal clock 120 can again be achieved in each device 100 of the system 10, for example, by adapting an adaptable parameter 112, which indicates in what ratio the respective internal clock 120 increases with the frequency 111 of the internal clock generator 110. In this possibility for synchronizing the internal clock 120 with the grid frequency 230 of the electrical grid 200, the device 100 does not have to know the grid frequency 230 of the electrical grid 200.

[0044] The described synchronization of the internal clock 120 with the grid frequency 230 of the electrical grid 200 is suitably carried out periodically. For example, the internal clock 120 can be synchronized with the grid frequency 230 of the electrical grid 200 at each zero crossing 220 of the voltage 210 of the electrical grid 200. However, it is also possible that the internal clock 120 is synchronized less frequently than in the case of each zero crossing 220 of the voltage 210 of the electrical grid 200. For example, the internal clock can be synchronized only at every second zero crossing 220 of the voltage 210 of the electrical grid 200.

[0045] In addition to the above components present in all devices 100, the devices 100 of system 10 may have other components and features, but alternatively these components and features may also be omitted. Some such features are described below by way of example. Each of the devices 100 of system 10 may selectively have one or more of these features or other features.

[0046] In Figure 1 the example shown, the first devices 100, 101 have a sensor input 140. The first devices 100, 101 are configured to detect a measured value 141 by means of the sensor input 140. The measured value 141 may be, for example, a voltage value. The first devices 100, 101 may be configured to provide a timestamp 124 for the measured value 141 by means of a first data packet 310 schematically shown in Figure 3 formed by the measured value 141 and the timestamp 124. Here, the timestamp 124 gives the value of the internal clock 120 of the first devices 100, 101 at the time point when the measured value 141 has been detected.

[0047] In Figure 1 the example shown, the first devices 100, 101 have a data interface 160 through which the first devices 100, 101 are connected to a data network 300. The data network 300 may be, for example, an Ethernet-based data network. For example, the data network 300 may be an EtherCAT data network. In this case, the first devices 100, 101 are configured as EtherCAT network users.

[0048] The first devices 100, 101 may be configured to send a first data packet 310 having the measured value 141 and the timestamp 124 associated with the measured value 141 shown in Figure 3 through the data network 300. Here, the first devices 100, 101 may, for example, send the first data packet 310 to another device 100 of system 10. Since this other device 100 also synchronizes its internal clock 120 with the grid frequency 230 of the power grid 200, the timestamp 124 contained in the first data packet 310 then relates to a time system synchronized with the internal clock 120 of the other device 100.

[0049] In Figure 1 the example shown, the first devices 100, 101 have a signal output 150. The first devices 100, 101 are configured to output a signal 151 through the signal output 150. The first devices 100, 101 may, for example, be configured to output a signal 151 having a determined signal value 152 at a determined time value 125 of the internal clock 120 of the first devices 100, 101. The first devices 100, 101 may, for example, at Figure 4The time value 125 and the signal value 152 are received via the data network 300 in the second data packet 320 schematically shown in FIG. The first devices 100, 101 may receive the second data packet 320, for example, from another device 100 of the system 10. Since the internal clock 120 of this other device 100 is also synchronized with the grid frequency 230 of the power grid 200, this other device 100 may determine the time value 125 based on its internal clock 120, which is synchronized with the internal clocks 120 of the first devices 100, 101.

[0050] The device 100 of the system 10 may, for example, be configured as an Internet of Things (IoT) device. The device 100 of the system 10 may be, for example, a distributed control and measurement device for an industrial facility, a wind farm, a solar farm, or other facilities. For example, the first devices 100, 101 of the system 10 may be arranged on the blades of a wind energy device, while the second devices 100, 102 are arranged on the hub of the wind energy device.

[0051] List of reference numerals

[0052] 10 System

[0053] 100 Device

[0054] 101 First Device

[0055] 102 Second Device

[0056] 110 Internal Clock Generator

[0057] 111 Frequency

[0058] 112 Parameter

[0059] 113 First Frequency

[0060] 115 Second Frequency

[0061] 120 Internal Clock

[0062] 121 First Clock Value

[0063] 122 Second Clock Value

[0064] 123 Clock Progression

[0065] 124 Timestamp

[0066] 125 Time Value

[0067] 130 Grid Interface

[0068] 140 Sensor Input

[0069] 141 Measurement value

[0070] 150 Signal output terminal

[0071] 151 Signal

[0072] 152 Signal value

[0073] 160 Data interface

[0074] 200 Power grid

[0075] 210 Voltage

[0076] 220 Zero crossing point

[0077] 221 First zero crossing point

[0078] 222 Second zero crossing point

[0079] 230 Power grid frequency

[0080] 235 Half - cycle duration

[0081] 300 Data network

[0082] 310 First data packet

[0083] 320 Second data packet

[0084] 400 Time

[0085] 401 First time point

[0086] 402 Second time point

Claims

1. A method for operating a device (100), wherein the device has an internal clock generator (110) and an internal clock (120) and is connected to a power grid (200), Among them, wherein the power grid (200) is a power supply grid, wherein a zero crossing (220) of the voltage (210) of the power grid (200) is detected, wherein the internal clock (120) is incremented by means of the internal clock generator (110), wherein the internal clock (120) is periodically synchronized with the grid frequency (230) of the power grid (200), wherein the method comprises the following steps: - Detecting a measured value (141); - Assigning a time stamp (124) of the internal clock (120) to the measured value (141).

2. The method according to claim 1, Among them, wherein the internal clock (120) is synchronized with the grid frequency (230) of the power grid (200) at each zero crossing (220) of the voltage (210).

3. The method according to claim 1, Among them, wherein the internal clock generator (110) has a frequency (111) higher than the grid frequency (230) of the power grid (200).

4. The method according to claim 1, Among them, wherein the method comprises the following additional steps: - Sending the measured value (141) with the time stamp (124) via a data network (300).

5. The method according to claim 1, Among them, wherein the method comprises the following steps: - Outputting a signal (151) at a determined time value (125) of the internal clock (120).

6. A device (100), having an internal clock (120) which can be incremented by means of an internal clock generator (110), and having a grid interface (130) for connection to a power grid (200), Among them, wherein the grid interface (130) can be connected to a power supply grid, wherein the device (100) is configured to detect a zero crossing (220) of the voltage (210) of the power grid (200), wherein the device (100) is configured to synchronize the internal clock (120) with the grid frequency (230) of the power grid (200), wherein the device (100) is configured to detect a measured value (141), and the detected measured value (141) is assigned a time stamp (124) of the internal clock (120).

7. The device (100) according to claim 6, Among them, wherein the internal clock generator (110) has a frequency (111) higher than the grid frequency (230) of the power grid (200).

8. The device (100) according to claim 6, Among them, wherein the device (100) is configured to send the measured value (141) with the time stamp (124) via a data network (300).

9. The device (100) according to claim 6, Among them, wherein the device (100) is configured to output a signal (151) at a determined time value (125) of the internal clock (120).

10. The device (100) according to claim 6, Among them, The device (100) is configured as an EtherCAT network user.

11. A system (10), comprising a first device (100, 101) and a second device (100, 102) each configured according to any one of claims 6 to 10, Among them, wherein the first device (100, 101) and the second device (100, 102) are connected to a common power grid (200).