Merge estimation region for multi-type tree block structure

Abstract

A video encoder can encode pictures of video data using a merge estimation region (MER). The video encoder can determine a merge candidate list in parallel for coding units within a MER. The video encoder can also partition a picture of video data into coding units according to a constraint that specifies that the partitioning is constrained such that, for each MER containing one or more coding units, the one or more coding units are all in the MER, and for each coding unit containing one or more MERs, the MERs are all in the coding unit.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Application No. 17 / 084,119, filed on October 29, 2020, U.S. Provisional Application No. 62 / 929,680, filed on November 1, 2019, and U.S. Provisional Application No. 62 / 932,950, filed on November 8, 2019, each of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to video encoding and video decoding. Background Art

[0004] Digital video capabilities can be integrated into a wide variety of devices, including digital televisions, digital live broadcast systems, wireless broadcast systems, personal digital assistants (PDAs), laptop or desktop computers, tablet computers, e-book readers, digital cameras, digital recording devices, digital media players, video game devices, video game consoles, cellular or satellite wireless telephones, so-called "smart phones", video teleconferencing devices, video streaming devices, and the like. Digital video devices implement video codec technologies, such as those described in the standards defined by MPEG-2, MPEG-4, ITU-T H.263, ITU-TH.264 / MPEG-4 Part 10, Advanced Video Codec (AVC), ITU-T H.265 / High Efficiency Video Codec (HEVC), and extensions of these standards. By implementing these video codec technologies, these video devices can more efficiently transmit, receive, encode, decode, and / or store digital video information.

[0005] Video coding techniques include spatial (intra-picture) prediction and / or temporal (inter-picture) prediction to reduce or remove redundancy inherent in video sequences. For block-based video coding, a video slice (e.g., a video picture or a portion of a video picture) may be divided into video blocks, which may also be referred to as codec tree units (CTUs), codec units (CUs), and / or codec nodes. For video blocks in an intra-coded (I) slice of a picture, spatial prediction relative to reference samples in neighboring blocks in the same picture is used for encoding. For video blocks in an inter-coded (P or B) slice of a picture, spatial prediction relative to reference samples in neighboring blocks in the same picture or temporal prediction relative to reference samples in other reference pictures may be used. Pictures may be referred to as frames, and reference pictures may be referred to as reference frames. Summary of the Invention

[0006] In general, this disclosure describes techniques for video encoding and decoding, including techniques for defining and / or signaling merge estimation regions (MERs) in a picture of video data. A video encoder and / or a video decoder can be configured to perform a merge mode motion vector prediction process (e.g., motion vector predictor list construction, such as merge candidate list construction) on multiple blocks (e.g., coding units) within an MER in parallel.

[0007] In some example video codecs (i.e., video encoders and / or video decoders), pictures of video data can be partitioned according to a variety of different partitioning structures. For example, a video codec can use binary tree partitioning and ternary tree partitioning to partition pictures of video data. Generally, a video encoder uses binary tree partitioning to divide a block into two blocks and ternary tree partitioning to divide a block into three blocks. According to the techniques of this disclosure, when coding a picture using MERs, a video codec can be configured to partition a picture according to a constraint that includes a constraint on both binary tree partitioning and ternary tree partitioning.

[0008] In one example, the constraint ensures that, for each MER containing one or more coding units, the coding units are all within the MER. Additionally, the constraint ensures that, for each coding unit containing one or more MERs, the MERs are all within the coding unit. In this way, a video encoder can partition a picture such that both the video encoder and a video decoder can perform parallel merge candidate list construction in all of the MERs. As a result, inter prediction processing can be performed more quickly.

[0009] In one example, this disclosure describes a method of encoding video data, the method comprising: determining one or more MERs for a picture of the video data; partitioning the picture of the video data into coding units according to a constraint, wherein the constraint specifies that the partitioning is constrained such that: for each MER containing one or more coding units, the one or more coding units are all within the MER, and for each coding unit containing one or more MERs, the MERs are all within the coding unit; and encoding the coding units according to the MERs.

[0010] In another example, this disclosure describes a device configured to encode video data, the device comprising: a memory configured to store a picture of video data; and one or more processors in communication with the memory. The one or more processors are configured to: determine one or more MERs for the picture of video data; partition the picture of video data into coding units according to a constraint, wherein the constraint specifies that the partitioning is constrained such that: for each MER containing one or more coding units, the one or more coding units are all in the MER, and for each coding unit containing one or more MERs, the MERs are all in the coding unit; and encode the coding units according to the MERs.

[0011] In another example, this disclosure describes a device configured to encode video data, the device comprising: means for determining one or more MERs for a picture of video data; means for partitioning the picture of video data into coding units according to a constraint, wherein the constraint specifies that the partitioning is constrained such that: for each MER containing one or more coding units, the one or more coding units are all in the MER, and for each coding unit containing one or more MERs, the MERs are all in the coding unit; and means for encoding the coding units according to the MERs.

[0012] In another example, this disclosure describes a non-transitory computer- readable storage medium storing instructions that, when executed, cause one or more processors configured to encode video data to: determine one or more MERs for a picture of video data; partition the picture of video data into coding units according to a constraint, wherein the constraint specifies that the partitioning is constrained such that: for each MER containing one or more coding units, the one or more coding units are all in the MER, and for each coding unit containing one or more MERs, the MERs are all in the coding unit; and encode the coding units according to the MERs.

[0013] The details of one or more examples are set forth in the accompanying drawings and the description below. Other features, objects, and advantages will be apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 FIG. 1 is a block diagram illustrating one example video encoding and decoding system that can perform the techniques of this disclosure.

[0015] Figure 2A and Figure 2B FIG. 2 is a schematic diagram illustrating one example quad-tree binary tree (QTBT) structure and corresponding coding tree unit (CTU).

[0016] Figure 3 FIG. 1 is a block diagram illustrating one example video encoder that can perform the techniques of this disclosure.

[0017] Figure 4 FIG. 2 is a block diagram illustrating one example video decoder that can perform the techniques of this disclosure.

[0018] Figure 5 FIG. 3 is a diagram illustrating an example merge estimation region.

[0019] Figure 6 FIG. 4 is a diagram illustrating an example coding unit partitioning with respect to a 32x32 MER.

[0020] Figure 7 FIG. 5 is a diagram illustrating an example partitioned coding order.

[0021] Figure 8 FIG. 6 is a diagram illustrating an example of unwanted merge estimation regions for ternary tree partitioning and binary tree partitioning.

[0022] Figure 9 FIG. 7 is a diagram illustrating an example of allowed merge estimation regions for ternary tree partitioning and binary tree partitioning.

[0023] Figure 10 FIG. 8 is a flowchart illustrating one example encoding method of this disclosure.

[0024] Figure 11 FIG. 9 is a flowchart illustrating one example decoding method of this disclosure.

[0025] Figure 12 FIG. 10 is a flowchart illustrating another example encoding method of this disclosure. DETAILED DESCRIPTION

[0026] In general, this disclosure describes techniques for video encoding and decoding, including techniques for defining and / or signaling merge estimation regions (MERs) in pictures of video data. A video encoder and / or video decoder can be configured to perform a merge mode motion vector prediction process (e.g., motion vector predictor list construction, such as merge candidate list construction) in parallel on multiple blocks (e.g., coding units) within an MER.

[0027] In some example video codecs, pictures of video data can be partitioned according to a number of different partitioning structures. For example, a video encoder can use both binary tree partitioning and ternary tree partitioning to partition pictures of video data. Generally, the video encoder uses binary tree partitioning to divide a block into two blocks and ternary tree partitioning to divide a block into three blocks. According to the techniques of this disclosure, when encoding a picture using MERs, the video encoder can be configured to partition the picture according to a constraint that includes a constraint on both binary tree partitioning and ternary tree partitioning.

[0028] In one example, the constraint ensures that for each MER containing one or more coding units, the coding units are all in the MER. Additionally, the constraint ensures that for each coding unit containing one or more MERs, the MERs are all in the coding unit. In this way, the video encoder can partition the picture such that both the video encoder and the video decoder can perform parallel merge candidate list construction in all of the MERs. As a result, inter prediction processing can be performed more quickly.

[0029] In one specific example of the disclosure, the size of a MER can be M x N samples, where M is the height of the MER in samples and N is the width of the MER in samples. The size of a block to be partitioned is H x W samples, where H is the height of the block in samples and W is the width of the block in samples. In this example, to ensure that partitioned coding units that can be split from the current block comply with the above constraint, the video encoder can be configured to disable horizontal binary tree partitioning of the block if W is greater than M and H is less than or equal to N, disable vertical binary tree partitioning of the block if W is less than or equal to M and H is greater than N, disable horizontal ternary tree partitioning of the block if W is greater than M and H is less than or equal to 2*N, and disable vertical ternary tree partitioning of the block if W is less than or equal to 2*M and H is greater than N.

[0030] Figure 1 FIG. 1 is a block diagram illustrating one example of a video encoding and decoding system 100 that can perform the techniques of this disclosure. The techniques of this disclosure are generally directed to coding (encoding and / or decoding) video data. Generally, video data includes any data for processing video. As such, video data can include raw, uncoded video, coded video, decoded (e.g., reconstructed) video, and video metadata, such as signaling data.

[0031] As Figure 1As shown, in this example, system 100 includes a source device 102 that provides encoded video data to be decoded and displayed by a destination device 116. In particular, the source device 102 provides the video data to the destination device 116 via a computer-readable medium 110. The source device 102 and the destination device 116 can comprise any of a wide variety of devices, including desktop computers, notebook (i.e., laptop) computers, mobile devices, tablet computers, set-top boxes, telephone handsets such as smartphones, televisions, cameras, display devices, digital media players, video gaming consoles, video streaming devices, broadcast receiver devices, and the like. In some cases, the source device 102 and the destination device 116 are configured for wireless communication, and thus are referred to as wireless communication devices.

[0032] In Figure 1 In the example of FIG. 1, source device 102 includes a video source 104, a storage 106, a video encoder 200, and an output interface 108. Destination device 116 includes an input interface 122, a video decoder 300, a storage 120, and a display device 118. In accordance with this disclosure, video encoder 200 of source device 102 and video decoder 300 of destination device 116 can be configured to apply techniques for merge estimation region (MER) determination. Thus, source device 102 represents an example of a video encoding device, while destination device 116 represents an example of a video decoding device. In other examples, a source device and a destination device can include other components or arrangements. For example, source device 102 can receive video data from an external video source, such as an external camera. Likewise, destination device 116 can connect to an external display device, rather than include an integrated display device.

[0033] Figure 1 The system 100 illustrated in FIG. 1 is merely one example. In general, any digital video encoding and / or decoding device can perform techniques for merge estimation region determination. Source device 102 and destination device 116 are merely examples of such coding devices in which source device 102 creates encoded video data for transmission to destination device 116. This disclosure refers to a "coding" device as a device that performs coding (encoding and / or decoding) of data. Thus, video encoder 200 and video decoder 300 represent examples of coding devices, in particular examples of a video encoder and a video decoder, respectively. In some examples, source device 102 and destination device 116 can operate in a substantially symmetrical manner, such that each of source device 102 and destination device 116 includes video encoding and video decoding components. Hence, system 100 can support one-way or two-way video transmission between source device 102 and destination device 116, e.g., for video streaming, video playback, video broadcasting, or video telephony.

[0034] In general, video source 104 represents a source of video data (i.e., raw, unencoded video data) and provides a continuous series of pictures (also referred to as “frames”) of the video data to video encoder 200. Video encoder 200 encodes data for the pictures. Video source 104 of source device 102 can include a video capture device, such as a video camera, a video archive containing previously captured raw video, and / or a video feed interface to receive video from a video content provider. As a further alternative, video source 104 can generate computer graphics-based data as the source video, or a combination of live video with computer-generated or pre-recorded video. In each case, video encoder 200 encodes the captured, pre-captured, or computer-generated video data. Video encoder 200 can rearrange the pictures from the received order (sometimes referred to as “display order”) into the coding order for coding. Video encoder 200 can generate a bitstream including encoded video data. Source device 102 can then output the encoded video data onto computer-readable medium 110 via output interface 108 for reception and / or retrieval by, e.g., input interface 122 of destination device 116.

[0035] Memory 106 of source device 102 and memory 120 of destination device 116 represent general purpose memories. In some examples, memories 106 and 120 can store raw video data, e.g., raw video from video source 104 and raw, decoded video data from video decoder 300. Additionally or alternatively, memories 106 and 120 can store software instructions executable by, e.g., video encoder 200 and video decoder 300, respectively. Although memories 106 and 120 are shown separately from video encoder 200 and video decoder 300 in this example, it should be understood that video encoder 200 and video decoder 300 can also include internal memories to accomplish functionally similar or equivalent purposes. In addition, memories 106 and 120 can store encoded video data, e.g., output from video encoder 200 and input to video decoder 300. In some examples, portions of memories 106 and 120 can be allocated as one or more video buffers, e.g., to store raw video data, decoded video data, and / or encoded video data.

[0036] Computer-readable medium 110 can represent any type of medium or device capable of transporting encoded video data from source device 102 to target device 116. In one example, computer-readable medium 110 represents a communication medium to enable source device 102 to transmit encoded video data directly to target device 116 in real-time, e.g., via a radio frequency network or a computer-based network. Output interface 108 can modulate a transmission signal including the encoded video data, and input interface 122 can demodulate the received transmission signal, according to a communication standard, such as a wireless communication protocol. The communication medium can comprise any wireless or wired communication medium, such as a radio frequency (RF) spectrum or one or more physical transmission lines. The communication medium can form part of a packet-based network, such as a local area network, a wide-area network, or a global network such as the Internet. The communication medium can include routers, switches, base stations, or any other equipment that can be useful to facilitate communication from source device 102 to target device 116.

[0037] In some examples, source device 102 can output encoded data from output interface 108 to storage device 112. Similarly, target device 116 can access encoded data from storage device 112 via input interface 122. Storage device 112 can include any of a variety of distributed or locally accessed data storage media such as a hard drive, Blu-ray discs, DVDs, CD-ROMs, flash memory, volatile or non-volatile memory, or any other suitable digital storage media for storing encoded video data.

[0038] In some examples, source device 102 can output encoded video data to file server 114, which can store the encoded video data generated by source device 102. Target device 116 can access stored video data from file server 114 in a streaming or download manner.

[0039] The file server 114 can be any type of server device capable of storing encoded video data and transmitting that encoded video data to the destination device 116. The file server 114 can represent a web server (e.g., for a website), a server configured to provide file transfer protocol services (e.g., File Transfer Protocol (FTP) or File Delivery over Unidirectional Transport (FLUTE) protocol), a content delivery network (CDN) device, a hypertext transfer protocol (HTTP) server, a Multimedia Broadcast Multicast Service (MBMS) or enhanced MBMS (eMBMS) server, and / or a network attached storage (NAS) device. The file server 114 can additionally or alternatively implement one or more HTTP streaming protocols, such as Dynamic Adaptive Streaming over HTTP (DASH), HTTP Live Streaming (HLS), Real Time Streaming Protocol (RTSP), HTTP Dynamic Streaming, and the like.

[0040] The destination device 116 can access the encoded video data from the file server 114 through any standard data connection including an Internet connection. This can include a wireless channel (e.g., a Wi-Fi connection), a wired connection (e.g., DSL, cable modem, etc.), or a combination of both that is suitable for accessing encoded video data stored on the file server 114. The input interface 122 can be configured to operate according to any one or more of the various protocols discussed in the foregoing or other such protocols used for retrieving or receiving media data from a file server 114.

[0041] Output interface 108 and input interface 122 can represent wireless transmitters / receivers, modems, wired networking components (e.g., Ethernet cards), wireless communication components under various IEEE 802.11 standards, or other physical components. In examples where output interface 108 and input interface 122 include wireless components, output interface 108 and input interface 122 can be configured to transmit data, e.g., encoded video data, under a cellular communication standard including, for example, 4G, 4G-LTE (Long-Term Evolution), LTE Advanced, 5G, or the like. In some examples where output interface 108 includes a wireless transmitter, output interface 108 and input interface 122 can be configured to transmit data, e.g., encoded video data, under other wireless standards, including IEEE 802.11 specifications, IEEE 802.15 specifications (e.g., ZigBee TM ), Bluetooth TM standards, or the like. In some examples, source device 102 and / or destination device 116 can include respective system on a chip (SoC) devices. For example, source device 102 can include an SoC device that performs the functions distributed to video encoder 200 and / or output interface 108, and destination device 116 can include an SoC device that performs the functions distributed to video decoder 300 and / or input interface 122.

[0042] The techniques of this disclosure can be applied to video encoding of any of a variety of multimedia applications. The multimedia applications include, for example, over-the-air television broadcasts, cable television transmissions, satellite television transmissions, Internet streaming video transmissions, such as dynamic adaptive streaming over HTTP (DASH), digital video that is encoded onto a data storage medium, decoding of digital video stored on a data storage medium, or other applications.

[0043] Input interface 122 of destination device 116 receives an encoded video bitstream from computer-readable medium 110 (e.g., a communication medium, storage device 112, file server 114, or the like). The encoded video bitstream can include signaling information defined by video encoder 200, which is also used by video decoder 300, such as syntax elements having values

[0044] Although Figure 1Although not shown, in some examples, video encoder 200 and video decoder 300 can each be integrated with an audio encoder and / or audio decoder, respectively, and can include appropriate MUX-DEMUX units or other hardware and / or software to handle multiplexed streams including both audio and video in a common data stream. If applicable, MUX-DEMUX units can comply with the ITU H.223 Multiplexer Protocol, or other protocols such as the user datagram protocol (UDP).

[0045] Video encoder 200 and video decoder 300 each can be implemented as any of a variety of suitable encoder and / or decoder circuitry, such as one or more microprocessors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), discrete logic, software, hardware, firmware or any combinations thereof. When the techniques are implemented partially in software, a device can store instructions for the software in a suitable, non- transitory computer-readable medium and execute the instructions in hardware using one or more processors to perform the techniques of this disclosure. Each of video encoder 200 and video decoder 300 can be included in one or more encoders or decoders, either of which can be integrated as part of a combined encoder / decoder (CODEC) in a respective device. A device including video encoder 200 and / or video decoder 300 can comprise an integrated circuit, a microprocessor, and / or a wireless communication device, such as a cellular telephone.

[0046] Video encoder 200 and video decoder 300 can operate according to a video coding standard, such as ITU-T H.265, also referred to as High Efficiency Video Coding (HEVC), or extensions thereof, such as the multi-view and / or scalable video coding extensions. Alternatively, video encoder 200 and video decoder 300 can operate according to other proprietary or industry standards, such as the Joint Exploration Test Model (JET) or ITU-T H.266, also referred to as Versatile Video Coding (VVC). Bross et al., “Versatile Video Coding (Draft 7),” JVET-P2001-v9, Section B in the Proposal of the 16th Meeting of ITU-T SG 16 WP 3 and ISO / IEC JTC 1 / SC 29 / WG 11 Joint Video Expert Team (JVET), Geneva, CH, 1-11 October 2019, describes a recent draft of the VVC standard (hereinafter “VVC Draft 7”). The techniques of this disclosure, however, are not limited to any particular coding standard.

[0047] In general, video encoder 200 and video decoder 300 can perform block-based picture coding. The term “block” generally refers to a structure comprising data to be processed (e.g., encoded, decoded, or used in the encoding and / or decoding process). For example, a block can include a two-dimensional matrix of samples of luma and / or chroma data. In general, video encoder 200 and video decoder 300 can code video data represented in a YUV (e.g., Y, Cb Cr) format. That is, rather than coding samples of pictures on a red, green, and blue (RGB) data, video encoder 200 and video decoder 300 can code luma and chroma components, where the chroma components can include both red chrominance components and blue chrominance components. In some examples, video encoder 200 converts received data in RGB format to a YUV representation prior to encoding, and video decoder 300 converts the YUV representation to the RGB format. Alternatively, pre- and post-processing units (not shown) can perform these conversions.

[0048] This disclosure can generally refer to coding (e.g., encoding and decoding) of a picture to include the process of encoding or decoding data of the picture. Similarly, this disclosure can refer to coding of a block of a picture to include the process of encoding or decoding data of the block, e.g., prediction and / or residual coding. A coded video bitstream typically includes a series of values for syntax elements that represent coding decisions (e.g., coding modes) and partitioning of a picture into blocks. Thus, descriptions of coding a picture or a block should generally be understood to refer to coding values of syntax elements used to form the picture or the block.

[0049] HEVC defines various blocks, including coding units (CUs), prediction units (PUs), and transform units (TUs). According to HEVC, a video coder (e.g., video encoder 200) partitions coding tree units (CTUs) into CUs according to a quadtree structure. That is, the video coder partitions a CTU and CUs into four equal and non overlapping squares, and each node of the quadtree has zero or four child nodes. Nodes with zero child nodes can be referred to as“leaf nodes,” and CUs of such leaf nodes can include one or more PUs and / or one or more TUs. The video coder can further partition PUs and TUs. For example, in HEVC, a residual quadtree (RQT) represents partitioning of TUs. In HEVC, PUs represent inter prediction data, while TUs represent residual data. CUs resulting from intra prediction include intra prediction information, such as an intra mode indication.

[0050] As another example, video encoder 200 and video decoder 300 can be configured to operate according to VVC. According to VVC, a video coder (e.g., video encoder 200) partitions a picture into coding tree units (CTUs). Video encoder 200 can partition a CTU according to a tree structure including, e.g., a quadtree-binary tree (QTBT) structure or Multi-Type Tree (MTT) structure. The QTBT structure removes the concepts of multiple partition types, such as the distinction between CUs, PUs, and TUs of HEVC. The QTBT structure includes two levels: a first level of partitioning according to quadtree partitioning, and a second level of partitioning according to binary tree partitioning. A root node of the QTBT structure corresponds to a CTU. Leaf nodes of the binary tree correspond to coding units (CUs).

[0051] In MTT partition structures, blocks can be partitioned using quad tree (QT) partitioning, binary tree (BT) partitioning, and one or more types of ternary tree (TT) (also referred to as triple tree (TT)) partitioning. In ternary or triple tree partitioning, a block is split into three sub-blocks. In some examples, ternary or triple tree partitioning partitions a block into three sub-blocks in a manner that does not partition the original block through the center. The partition types (e.g., QT, BT, and TT) in MTT can be symmetric or asymmetric.

[0052] In some examples, video encoder 200 and video decoder 300 can use a single QTBT or MTT structure to represent each of luma and chroma components. In other examples, video encoder 200 and video decoder 300 can use two or more QTBT or MTT structures, such as one QTBT / MTT structure for luma components and another QTBT / MTT structure for two chroma components (or two QTBT / MTT structures for respective chroma components).

[0053] Video encoder 200 and video decoder 300 can be configured to use HEVC-based quad tree partitioning, QTBT partitioning, MTT partitioning, or other partition structures. For purposes of illustration, techniques of this disclosure are described based on QTBT partitioning. However, it should be understood that techniques of this disclosure can also be applied to video coders configured to use quad tree partitioning or other types of partitioning.

[0054] In some examples, a CTU includes a coding tree block (CTB) of luma samples, two corresponding CTBs of chroma samples of a picture having three arrays of samples, or a CTB of samples of a monochrome picture or a picture coded using three separate color planes and syntax structures for coding samples. A CTB can be a block of NxN samples for some value of N such that the partitioning of components to CTBs is a partitioning. A component is an array or a single sample of one of three arrays (luma and two chroma) of a picture in a constituent color format of 4:2:0, 4:2:2, or 4:4:4, or an array or a single sample in an array of a picture in a constituent monochrome format. In some examples, a coding block is a block of MxN samples for some values of M and N such that the partitioning of CTBs to coding blocks is a partitioning.

[0055] Various blocks (e.g., CTUs or CUs) in a picture can be grouped in a variety of ways. As one example, a brick refers to a rectangular region of CTU rows within a particular tile in a picture. A tile refers to a rectangular region of CTUs within a particular tile column and a particular tile row in a picture. A tile column refers to a rectangular region of CTUs having a height equal to a height of the picture and a width specified (e.g., such as in a picture parameter set) by a syntax element. A tile row refers to a rectangular region of CTUs having a height specified (e.g., such as in a picture parameter set) by a syntax element and a width equal to a width of the picture.

[0056] In some examples, a tile can be divided into multiple bricks, each brick including one or more CTU rows within the tile. A tile that is not divided into multiple bricks can also be referred to as a brick. However, a brick that is a proper subset of a tile cannot be referred to as a tile.

[0057] Bricks in a picture can also be arranged in slices. A slice can be an integer number of bricks of a picture that can be exclusively contained in a single network abstraction layer (NAL) unit. In some examples, a slice includes multiple complete tiles or only a contiguous sequence of complete bricks of a single tile.

[0058] The disclosure can use "NxN" and "N by N" interchangeably to refer to the sample dimensions of a block (e.g., CU or other video block) in the vertical and horizontal dimensions, such as 16x16 samples or 16 by 16 samples. In general, a 16x16 CU will have 16 samples in the vertical direction (y = 16) and 16 samples in the horizontal direction (x = 16). Likewise, an NxN CU generally has N samples in the vertical direction and N samples in the horizontal direction, where N represents a non-negative integer value. The samples in a CU can be arranged in rows and columns. Moreover, the number of samples in a CU in the horizontal direction need not be the same as the number of samples in the vertical direction. For example, a CU can include NxM samples, where M need not equal N.

[0059] Video encoder 200 encodes video data for CUs that represent prediction and / or residual information, among other information. Prediction information indicates how a CU is to be predicted in order to form a prediction block for the CU. Residual information generally represents sample-by-sample differences between a prediction block and samples of the CU prior to encoding.

[0060] To code a CU, video encoder 200 generally can form a prediction block for the CU through inter prediction or intra prediction. Inter prediction generally refers to predicting the CU from data of a previously coded picture, while intra prediction generally refers to predicting the CU from previously coded data of the same picture. To perform inter prediction, video encoder 200 can use one or more motion vectors to generate the prediction block. Video encoder 200 can generally perform a motion search, e.g., to identify a reference block that closely matches the CU according to a difference between the CU and the reference block. Video encoder 200 can calculate a difference metric using sum of absolute differences (SAD), sum of squared differences (SSD), mean absolute difference (MAD), mean squared differences (MSD), or other such difference calculations to determine whether a reference block closely matches a current CU. In some examples, video encoder 200 can use uni -prediction or bi-prediction to predict the current CU.

[0061] Certain examples of VVC also provide an affine motion compensation mode that can be considered a type of inter prediction mode. In the affine motion compensation mode, video encoder 200 can determine two or more motion vectors that represent non-translational motion, e.g., zooming or scaling, rotation, perspective motion, or other irregular types of motion.

[0062] To perform intra prediction, video encoder 200 can select an intra prediction mode to generate the prediction block. Certain examples of VVC provide 67 intra prediction modes, including various directional modes as well as a planar mode and a DC mode. Generally, video encoder 200 selects an intra prediction mode that describes neighboring samples of the current block (e.g., a block of a CU) from which to predict samples of the current block. Assuming video encoder 200 is coding CTUs and CUs in a raster scan order (left to right, top to bottom), the neighboring samples are generally above, above and to the left, or to the left of the current block in the same picture.

[0063] Video encoder 200 encodes data that represents the prediction mode for the current block. For example, for inter prediction modes, video encoder 200 can encode data that indicates which of a plurality of available inter prediction modes to use, as well as motion information for the corresponding mode. For uni - or bi-prediction inter prediction, for example, video encoder 200 can use advanced motion vector prediction (AMVP) or merge mode to encode the motion vectors. For affine motion compensation modes, video encoder 200 can use a similar mode to encode the motion vectors.

[0064] Following prediction, such as intra prediction or inter prediction of a block, video encoder 200 can calculate residual data for the block. The residual data, e.g., a residual block, represents sample-by-sample differences between the block and a prediction block of the block formed using a corresponding prediction mode. Video encoder 200 can apply one or more transforms to the residual block to generate transformed data in a transform domain instead of the sample domain. By way of example, video encoder 200 can apply a discrete cosine transform (DCT), an integer transform, a wavelet transform, or a conceptually similar transform. Additionally, video encoder 200 can apply a secondary transform following the primary transform, e.g., a mode-dependent non-separable secondary transform (MDNSST), a signal-dependent transform, a Karhunen-Loeve transform (KLT), or the like. Video encoder 200 produces transform coefficients following application of the one or more transforms.

[0065] As described above, following any transforms that generate transform coefficients, video encoder 200 can quantize the transform coefficients. Quantization generally refers to a process in which transform coefficients are quantized to possibly reduce the amount of data used to represent the transform coefficients, thereby providing further compression. By performing the quantization process, video encoder 200 can reduce the bit depth associated with some or all of the transform coefficients. For example, video encoder 200 can round an n-bit value during quantization to an m-bit value, where n is greater than m. In some examples, to perform quantization, video encoder 200 can perform a bitwise right-shift of the value to be quantized.

[0066] Following quantization, video encoder 200 can scan the transform coefficients, thereby generating a one-dimensional vector from a two-dimensional matrix that includes the quantized transform coefficients. The scan can be designed to place higher energy, and thus lower frequency, transform coefficients at the front of the vector, and lower energy, and thus higher frequency, transform coefficients at the back of the vector. In some examples, video encoder 200 can utilize a pre-defined scan order to scan the quantized transform coefficients to generate a serialized vector, and then entropy encode the quantized transform coefficients of the vector. In other examples, video encoder 200 can perform an adaptive scan. Following scanning of the quantized transform coefficients to form a one-dimensional vector, video encoder 200 can entropy encode the one-dimensional vector, e.g., according to context-adaptive binary arithmetic coding (CABAC). Video encoder 200 can also entropy encode values for syntax elements that describe metadata associated with the encoded video data that video decoder 300 uses in decoding the video data.

[0067] To perform CABAC, video encoder 200 can assign a context within a context model to a symbol to be transmitted. The context can relate to, for example, whether a neighboring value of the symbol is zero or not. Probability determination can be based on a context assigned to the symbol.

[0068] Video encoder 200 can further generate syntax data, such as block-based, picture-based, and sequence-based syntax data, or other syntax data, such as a sequence parameter set (SPS), picture parameter set (PPS), or video parameter set (VPS), to video decoder 300, e.g., in a picture header, a block header, a slice header. Video decoder 300 can likewise decode such syntax data to determine how to decode corresponding video data.

[0069] In this manner, video encoder 200 can generate a bitstream. The bitstream includes encoded video data, e.g., syntax elements describing partitioning of a picture into blocks (e.g., CUs) and prediction and / or residual information for the above blocks. Ultimately, video decoder 300 can receive the bitstream and decode the encoded video data as described above.

[0070] In general, video decoder 300 performs a reciprocal process to that of video encoder 200 to decode the encoded video data of the bitstream. For instance, although reciprocal to the CABAC encoding process of video encoder 200, video decoder 300 can use CABAC in generally similar fashion to decode values for syntax elements of the bitstream. The syntax elements can define partitioning information of a picture into CTUs, and partitioning of each CTU according to a corresponding partition structure, such as a QTBT structure, defining CUs of the CTU. The syntax elements can further define prediction and residual information for blocks (e.g., CUs) of video data.

[0071] The residual information can be represented by, for example, quantized transform coefficients. Video decoder 300 can inverse quantize and inverse transform the quantized transform coefficients of a block to reproduce a residual block for the block. Video decoder 300 uses the signaled prediction mode (intra- or inter-prediction) and related prediction information (e.g., motion information for inter-prediction) to form a prediction block for the block. Video decoder 300 can then combine the prediction block and the residual block (on a sample-by-sample basis) to reproduce the original block. Video decoder 300 can perform additional processing, such as deblocking process to reduce visual artifacts along boundaries of the blocks.

[0072] According to techniques of this disclosure, as will be detailed below, video encoder 200 can be configured to determine one or more merge estimation regions (MERs) for a picture of video data, partition the picture of video data into coding units according to a constraint, where the constraint specifies that the partitioning is constrained such that, for each MER containing one or more coding units, the one or more coding units are all in the MER, and for each coding unit containing one or more MERs, the MERs are all in the coding unit, and encode the coding units according to the MERs.

[0073] This disclosure can generally refer to “signaling” certain information, such as syntax elements. The term “signaling” can generally refer to the communication of values of syntax elements and / or other data used to decode encoded video data. That is, video encoder 200 can signal values of syntax elements in a bitstream. In general, signaling refers to generating values in a bitstream. As described above, source device 102 can communicate the bitstream to destination device 116 in substantially real time, or can not be in real time, such as can occur when syntax elements are stored to storage device 112 for later retrieval by destination device 116.

[0074] Figure 2A and Figure 2B FIG. 1 is a schematic diagram illustrating an example quad-tree-binary tree (QTBT) structure 130 and a corresponding coding tree unit (CTU) 132. Solid lines represent quad-tree splitting, while dashed lines represent binary tree splitting. In each split (i.e., non-leaf) node of the binary tree, a flag is signaled to indicate which type of splitting is used (i.e., horizontal or vertical), where 0 indicates horizontal splitting and 1 indicates vertical splitting in this example. For quad-tree splitting, no splitting type indication is needed because a quad-tree node splits a block horizontally and vertically into 4 equal-sized sub-blocks. Thus, video encoder 200 can encode and video decoder 300 can decode syntax elements (e.g., splitting information) for a region tree level (e.g., solid lines) of QTBT structure 130 and syntax elements (e.g., splitting information) for a prediction tree level (e.g., dashed lines) of QTBT structure 130. For a CU represented by a terminal leaf node of QTBT structure 130, video encoder 200 can encode and video decoder 300 can decode video data, such as prediction and transform data.

[0075] In general, Figure 2BA CTU 132 can be associated with parameters defining the sizes of blocks corresponding to nodes of the QTBT structure 130 at the first and second levels. These parameters can include a CTU size (representing the size of the CTU 132 in samples), a minimum quadtree size (MinQTSize, representing the minimum allowed quadtree leaf node size), a maximum binary tree size (MaxBTSize, representing the maximum allowed binary tree root node size), a maximum binary tree depth (MaxBTDepth, representing the maximum allowed binary tree depth), and a minimum binary tree size (MinBTSize, representing the minimum allowed binary tree leaf node size).

[0076] A root node of the QTBT structure corresponding to a CTU can have four child nodes at the first level of the QTBT structure, which can be partitioned according to quadtree partitioning. That is, nodes of this first level are either leaf nodes (having no child nodes) or have four child nodes. The example of the QTBT structure 130 represents such nodes as including a parent node and child nodes with solid lines as branches. If a node of this first level is not larger than the maximum allowed binary tree root node size (MaxBTSize), the node can be further partitioned by a corresponding binary tree. Binary tree splitting of a node can be iteratively performed until a node resulting from the splitting reaches the minimum allowed binary tree leaf node size (MinBTSize) or the maximum allowed binary tree depth (MaxBTDepth). The example of the QTBT structure 130 represents such nodes in a manner with dashed lines as branches. Binary tree leaf nodes are referred to as coding units (CUs), which are used for prediction (e.g., intra prediction or inter prediction) and transform without any further partitioning. As discussed above, a CU can also be referred to as a “video block” or “block.”

[0077] In one example of the QTBT partitioning structure, the size of the CTU is set to 128x128 (luma samples and two corresponding 64x64 chroma samples), MinQTSize is set to 16x16, MaxBTSize is set to 64x64, MinBTSize (for both width and height) is set to 4, and MaxBTDepth is set to 4. The QTBT structure is first applied to the CTU to generate quad-tree leaf nodes. The size of the quad-tree leaf nodes can range from 16x16 (i.e., MinQTSize) to 128x128 (i.e., the CTU size). If a quad-tree leaf node is 128x128, then the quad-tree leaf node is not further split by the binary tree because the size exceeds MaxBTSize (i.e., 64x64 in this example). Otherwise, the quad-tree leaf node is further partitioned by the binary tree. Thus, the quad-tree leaf node is also the root node of the binary tree and has a binary tree depth of 0. When the depth of the binary tree reaches MaxBTDepth (4 in this example), no further splitting is allowed. A binary tree node with a width equal to MinBTSize (4 in this example) indicates that no further vertical splitting (i.e., width partitioning) of the binary tree node is allowed. Similarly, a binary tree node with a height equal to MinBTSize indicates that no further horizontal splitting (i.e., height partitioning) of the binary tree node is allowed. As described above, the leaf nodes of the binary tree are referred to as CUs and are further processed according to prediction and transform without further partitioning.

[0078] Figure 3 FIG. 1 is a block diagram illustrating one example of a video encoder 200 that can implement the techniques of this disclosure. The video encoder 200 is illustrated as including functional blocks that can be implemented using software, hardware, firmware, or a combination thereof. In one example, the video encoder 200 is implemented as a software module executing on one or more general purpose computers. In another example, the video encoder 200 is implemented as a hardware module or a hardware and software module. Figure 3 The techniques of this disclosure should not be considered limited to the video encoder 200 illustrated in FIG. 1. For example, the techniques of this disclosure can be implemented by a video encoder configured to other video coding standards. For illustrative purposes, the video encoder 200 is described in terms of the techniques of VVC (ITU-T H.266 under development) and HEVC (ITU-T H.265). However, the techniques of this disclosure can be implemented by a video encoding device configured to other video coding standards.

[0079] In Figure 3In the example of FIG, the video encoder 200 includes a video data memory 230, a mode selection unit 202, a residual generation unit 204, a transform processing unit 206, a quantization unit 208, an inverse quantization unit 210, an inverse transform processing unit 212, a reconstruction unit 214, a filter unit 216, a decoded picture buffer (DPB) 218, and an entropy coding unit 220. Any or all of the video data memory 230, the mode selection unit 202, the residual generation unit 204, the transform processing unit 206, the quantization unit 208, the inverse quantization unit 210, the inverse transform processing unit 212, the reconstruction unit 214, the filter unit 216, the DPB 218, and the entropy coding unit 220 can be implemented in one or more processors or in processing circuitry. For example, the units of the video encoder 200 can be implemented as one or more circuits or logic elements as part of a hardware circuit, or as part of a processor, ASIC, or FPGA. In addition, the video encoder 200 can include additional or alternative processors or processing circuitry to implement these or other functions.

[0080] The video data memory 230 may store video data to be encoded by the components of the video encoder 200. The video encoder 200 may receive video data stored in the video data memory 230 (e.g., from the video source 104 ( Figure 1 ) video data). The DPB 218 can act as a reference picture memory that stores reference video data used by the video encoder 200 in predicting subsequent video data. The video data memory 230 and the DPB 218 can be formed by any of a variety of memory devices, such as dynamic random access memory (DRAM), including synchronous DRAM (SDRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM), or other types of memory devices. The video data memory 230 and the DPB 218 can be provided as the same memory device or as separate memory devices. In a number of examples, the video data memory 230 can be on-chip with the other components of the video encoder 200, as shown above, or off-chip relative to those components.

[0081] In the present disclosure, descriptions of the video data memory 230 should not be interpreted as being limited to memory internal to the video encoder 200, unless specifically described as such, or limited to memory external to the video encoder 200, unless specifically described as such. Rather, descriptions of the video data memory 230 should be understood as reference memory that stores video data received by the video encoder 200 for encoding (e.g., video data for a current block to be encoded). Figure 1The memory 106 may also provide temporary storage for outputs from the various units of the video encoder 200 .

[0082] right Figure 3 The various units of the video encoder 200 are described to help understand the operations performed by the video encoder 200. These units can be implemented as fixed-function circuits, programmable circuits, or a combination of the two. Fixed-function circuits refer to circuits that provide specific functions and are preset for the operations that can be performed. Programmable circuits refer to circuits that can be programmed to perform various tasks and provide flexible functions in the operations that can be performed. For example, a programmable circuit can execute software or firmware so that the programmable circuit operates in a manner defined by the instructions of the software or firmware. Fixed-function circuits can execute software instructions (for example, receive or output parameters), but the type of operations performed by fixed-function circuits is generally immutable. In some examples, one or more of the above units can be different circuit blocks (fixed function or programmable), and in some examples, one or more of the above units can be integrated circuits.

[0083] The video encoder 200 may include an arithmetic logic unit (ALU), an elementary function unit (EFU), a digital circuit, an analog circuit, and / or a programmable core formed by a programmable circuit. In an example where the operation of the video encoder 200 is performed using software executed by a programmable circuit, the memory 106 ( Figure 1 ) may store instructions (eg, object code) of software received and executed by the video encoder 200, or another memory (not shown) in the video encoder 200 may store these instructions.

[0084] The video data memory 230 is configured to store received video data. The video encoder 200 can retrieve a picture of the video data from the video data memory 230 and provide the video data to the residual generation unit 204 and the mode selection unit 202. The video data in the video data memory 230 can be the original video data to be encoded.

[0085] The mode selection unit 202 includes a motion estimation unit 222, a motion compensation unit 224, and an intra-frame prediction unit 226. The mode selection unit 202 may include additional functional units for performing video prediction according to other prediction modes. For example, the mode selection unit 202 may include a palette unit, an intra-block copy unit (which may be part of the motion estimation unit 222 and / or the motion compensation unit 224), an affine unit, a linear model (LM) unit, etc.

[0086] The mode selection unit 202 generally coordinates the multiple encoding passes to test combinations of encoding parameters and the resulting rate-distortion values for the combinations. The encoding parameters can include partitioning from CTUs to CUs, prediction modes for CUs, transform types for residual data of CUs, quantization parameters for residual data of CUs, and so on. The mode selection unit 202 can ultimately select the combination of encoding parameters that has a better rate-distortion value than other tested combinations.

[0087] As will be described in more detail below, when encoding video data using inter prediction according to a merge estimation region (MER), the video encoder 200 can be configured to partition the video data according to a constraint. For example, the video encoder 200 can be configured to determine one or more MERs for a picture of the video data, and partition the picture of the video data into coding units according to a constraint, where the constraint specifies that the partitioning is constrained such that, for each MER containing one or more coding units, the one or more coding units are all in the MER, and for each coding unit containing one or more MERs, the MERs are all in the coding unit.

[0088] The video encoder 200 can partition a picture retrieved from the video data memory 230 into a series of CTUs, and encapsulate one or more CTUs within a slice. The mode selection unit 202 can partition the CTUs of the picture according to a tree structure, such as the QTBT structure described above or the quad-tree structure of HEVC. As described above, the video encoder 200 can form one or more CUs from partitioning a CTU according to the tree structure. Such CUs can also be generally referred to as “video blocks” or “blocks.”

[0089] In general, the mode selection unit 202 also controls its components (e.g., the motion estimation unit 222, the motion compensation unit 224, and the intra prediction unit 226) to generate a prediction block for a current block (e.g., a current CU, or an overlapping portion of a PU and a TU in HEVC). For inter prediction of a current block, the motion estimation unit 222 can perform a motion search to identify one or more closely matching reference blocks in one or more reference pictures (e.g., one or more previously coded pictures stored in the DPB 218). Specifically, the motion estimation unit 222 can calculate a value that represents how similar a potential reference block is to the current block, e.g., according to a sum of absolute differences (SAD), a sum of squared differences (SSD), a mean absolute difference (MAD), a mean squared difference (MSD), and the like. The motion estimation unit 222 can generally use pixel-by-pixel differences between the current block and a considered reference block to perform these calculations. The motion estimation unit 222 can identify the reference block with the smallest value resulting from these calculations, indicating the reference block that most closely matches the current block.

[0090] Motion estimation unit 222 can form one or more motion vectors (MVs) that define the position of a reference block in a reference picture relative to the position of the current block in the current picture. Motion estimation unit 222 can then provide the motion vector(s) to motion compensation unit 224. For example, for single directional inter prediction, motion estimation unit 222 can provide a single motion vector, while for bi-directional inter prediction, motion estimation unit 222 can provide two motion vectors. Motion compensation unit 224 can then use the motion vector(s) to generate the predictive block. For example, motion compensation unit 224 can use the motion vector(s) to retrieve data for the reference block. As another example, if the motion vector(s) have fractional sample precision, motion compensation unit 224 can interpolate values for the predictive block according to one or more interpolation filters. Moreover, for bi-directional inter prediction, motion compensation unit 224 can retrieve data for two reference blocks identified by the respective motion vectors and combine the retrieved data, e.g., by pixel-wise averaging or weighted averaging.

[0091] As will be detailed below, motion estimation unit 222 and motion compensation unit 224 can be configured to perform inter prediction according to a MER. For example, motion estimation unit 222 and motion compensation unit 224 can be configured to perform a merge candidate list construction process in parallel for all coding units contained within the MER.

[0092] As another example, for intra prediction or intra prediction coding, intra prediction unit 226 can generate a predictive block from samples neighboring the current block. For example, for directional modes, intra prediction unit 226 can typically mathematically combine values of the neighboring samples and fill these computed values across the current block in a defined direction to produce the predictive block. As another example, for a DC mode, intra prediction unit 226 can compute an average of the neighboring samples of the current block and generate a predictive block that includes the resulting average for each sample of the predictive block.

[0093] Mode selection unit 202 provides the predictive block to residual generation unit 204. Residual generation unit 204 receives the original, unencoded version of the current block from video data memory 230 and the predictive block from mode selection unit 202. Residual generation unit 204 computes the pixel-wise difference between the current block and the predictive block. The resulting pixel-wise differences define a residual block for the current block. In some examples, residual generation unit 204 can also determine the difference between the values of the samples in the residual block to generate the residual block using residual differential pulse code modulation (RDPCM). In some examples, residual generation unit 204 can be formed using one or more subtractor circuits that perform binary subtraction.

[0094] In some examples, the mode selection unit 202 divides the CU into PUs, each of which can be associated with a luma prediction unit and a corresponding chroma prediction unit. The video encoder 200 and the video decoder 300 can support PUs of various sizes. As shown above, the size of the CU refers to the size of the luma codec block of the CU, and the size of the PU refers to the size of the luma prediction unit of the PU. Assuming that the size of a particular CU is 2N×2N, the video encoder 200 can support PUs of sizes 2N×2N or N×N for intra-frame prediction, and symmetric PUs of sizes 2N×2N, 2N×N, N×2N, N×N, or similar for inter-frame prediction. The video encoder 200 and the video decoder 300 can also support asymmetrically partitioned PUs of sizes 2N×nU, 2N×nD, nL×2N, and nR×2N for inter-frame prediction.

[0095] In some examples, the mode selection unit 202 no longer divides the CU into PUs. Each CU can be associated with a luma codec block and a corresponding chroma codec block. As described above, the size of the CU refers to the size of the luma codec block of the CU. The video encoder 200 and the video decoder 300 can support CU sizes of 2N×2N, 2N×N, or N×2N.

[0096] For other video codecs (such as intra-block copy mode codecs, affine mode codecs, and linear model (LM) mode codecs), as some examples, the mode selection unit 202 generates a prediction block for the current block being encoded via the corresponding unit associated with the codec. In some examples, such as palette mode codecs, the mode selection unit 202 does not generate a prediction block, but instead generates syntax elements indicating how to reconstruct the block based on the selected palette. In this mode, the mode selection unit 202 can provide these syntax elements to the entropy coding unit 220 for encoding.

[0097] As described above, the residual generation unit 204 receives the video data of the current block and the video data of the corresponding prediction block. The residual generation unit 204 then generates a residual block for the current block. The residual generation unit 204 calculates the sample-by-sample difference between the prediction block and the current block to generate the residual block.

[0098] Transform processing unit 206 applies one or more transforms to the residual block to produce a block of transform coefficients (referred to herein as a "transform coefficient block"). Transform processing unit 206 can apply multiple transforms to the residual block to form the transform coefficient block. For example, transform processing unit 206 can apply a discrete cosine transform (DCT), a directional transform, a Karhunen-Loeve transform (KLT), or a conceptually similar transform to the residual block. In some examples, transform processing unit 206 applies multiple transforms to the residual block, e.g., a primary transform and a secondary transform such as a rotational transform. In some examples, transform processing unit 206 does not transform the residual block.

[0099] Quantization unit 208 can quantize the transform coefficients in the transform coefficient block to generate a quantized transform coefficient block. Quantization unit 208 can quantize transform coefficients of the transform coefficient block according to a quantization parameter (QP) value associated with the current block. Video encoder 200 (e.g., via mode select unit 202) can adjust the degree of quantization applied to the transform coefficient block associated with the current block by adjusting the QP value associated with the CU. Quantization introduces loss of information, thus, quantized transform coefficients can have less precision than the original transform coefficients generated by transform processing unit 206.

[0100] Inverse quantization unit 210 and inverse transform processing unit 212 can apply inverse quantization and inverse transformation, respectively, to the quantized transform coefficient block to reconstruct a residual block based on the transform coefficient block. Reconstruction unit 214 generates a reconstructed block corresponding to the current block (albeit with some degree of distortion) based on the reconstructed residual block and the prediction block generated by mode select unit 202. For example, reconstruction unit 214 can add the samples of the reconstructed residual block to the corresponding samples of the prediction block generated by mode select unit 202 to generate the reconstructed block.

[0101] Filter unit 216 can perform one or more filter operations on the reconstructed block. For example, filter unit 216 can perform a deblocking operation to reduce blocking artifacts along boundaries of the CU. In some examples, the operations of filter unit 216 can be skipped.

[0102] Video encoder 200 stores the reconstructed blocks in DPB 218. For instance, in examples where operations of filter unit 216 are not performed, reconstructed unit 214 can store the reconstructed blocks to DPB 218. In examples where operations of filter unit 216 are performed, filter unit 216 can store the filtered reconstructed blocks to DPB 218. Motion estimation unit 222 and motion compensation unit 224 can retrieve reference pictures formed from reconstructed (and possibly filtered) blocks in DPB 218 to inter-predict blocks of subsequent coded pictures. In addition, intra-prediction unit 226 can use reconstructed blocks of a current picture in DPB 218 to intra-predict other blocks of that current picture.

[0103] In general, entropy encoding unit 220 can entropy encode syntax elements received from other functional components of video encoder 200. For example, entropy encoding unit 220 can entropy encode quantized transform coefficient blocks from quantization unit 208. As another example, entropy encoding unit 220 can entropy encode prediction syntax elements (e.g., motion information for inter-prediction or intra-mode information for intra-prediction) from mode select unit 202. Entropy encoding unit 220 can perform one or more entropy encoding operations on syntax elements, as another example of video data, to generate encoded data. For example, entropy encoding unit 220 can perform a context- adaptive variable length coding (CAVLC) operation, a CABAC operation, a variable to variable (V2V) length coding operation, a syntax-based context-adaptive binary arithmetic coding (SBAC) operation, a Probability Interval Partitioning Entropy (PIPE) coding operation, an Exponential-Golomb coding operation, or another entropy encoding operation on the data. In some examples, entropy encoding unit 220 can operate in a bypass mode in which syntax elements are not entropy encoded.

[0104] Video encoder 200 can output a bitstream that includes the entropy encoded syntax elements required to reconstruct blocks of a slice or picture. In particular, entropy encoding unit 220 can output the bitstream.

[0105] The operations described above are described with respect to blocks. Such description should be understood to be operations for luma coding blocks and / or chroma coding blocks. As described above, in some examples, luma coding blocks and chroma coding blocks are luma components and chroma components of CUs, respectively. In some examples, luma coding blocks and chroma coding blocks are luma components and chroma components of PUs.

[0106] In some examples, operations performed on luma coded blocks need not be repeated for chroma coded blocks. As one example, operations to identify motion vectors (MVs) and reference pictures for luma coded blocks need not be repeated for identifying MVs and reference pictures for chroma blocks. To be precise, the MVs for luma coded blocks can be scaled to determine the MVs for chroma blocks, and the reference pictures can be the same. As another example, the intra prediction process can be the same for luma and chroma coded blocks.

[0107] Video encoder 200 represents an example of a device configured to encode video data. The device includes a memory configured to store the video data and one or more processors implemented in circuitry configured to: determine one or more merge estimation regions (MERs) for a picture of the video data; partition the picture of the video data into coding units according to a constraint, wherein the constraint specifies that the partitioning is constrained such that: for each MER containing one or more coding units, the one or more coding units are all in the MER, and for each coding unit containing one or more MERs, the MERs are all in the coding unit; and encode the coding units according to the MERs.

[0108] Figure 4 FIG. 3 is a block diagram illustrating an example video decoder 300 that can incorporate the techniques of this disclosure. Video decoder 300 is for illustrative purposes only and should not be construed as limiting the techniques broadly exemplified and described in this disclosure. For illustrative purposes, this disclosure describes video decoder 300 based on the techniques of VVC (ITU-T H.266 under development) and HEVC (ITU-T H.265). However, the techniques of this disclosure can be performed by video coding devices configured for other video coding standards. Figure 4

[0109] In Figure 4 ​In the example of FIG, video decoder 300 includes a coded picture buffer (CPB) memory 320, an entropy decoding unit 302, a prediction processing unit 304, an inverse quantization unit 306, an inverse transform processing unit 308, a reconstruction unit 310, a filter unit 312, and a decoded picture buffer (DPB) 314. Any or all of CPB memory 320, entropy decoding unit 302, prediction processing unit 304, inverse quantization unit 306, inverse transform processing unit 308, reconstruction unit 310, filter unit 312, and DPB 314 may be implemented in one or more processors or processing circuits. For example, the units of video decoder 300 may be implemented as one or more circuits or logic elements as part of a hardware circuit or as part of a processor, ASIC, or FPGA. Furthermore, video decoder 300 may include additional or alternative processors or processing circuits to perform these or other functions.

[0110] The prediction processing unit 304 includes a motion compensation unit 316 and an intra prediction unit 318. The prediction processing unit 304 may include additional units to perform predictions according to other prediction modes. As an example, the prediction processing unit 304 may include a palette unit, an intra-block copy unit (which may form part of the motion compensation unit 316), an affine unit, a linear model (LM) unit, etc. In other examples, the video decoder 300 may include more, fewer, or different functional components.

[0111] The CPB memory 320 may store video data, such as an encoded video bitstream, to be decoded by components of the video decoder 300. The video data stored in the CPB memory 320 may be, for example, read from the computer readable medium 110 ( Figure 1 ) is obtained. The CPB memory 320 may include a CPB for storing encoded video data (e.g., syntax elements) based on the encoded video bitstream. Furthermore, the CPB memory 320 may store video data other than syntax elements of encoded and decoded pictures, such as temporary data representing outputs from multiple units of the video decoder 300. The DPB 314 typically stores decoded pictures. The video decoder 300 may output and / or use the decoded pictures as reference video data when decoding subsequent data and pictures of the encoded video bitstream. The CPB memory 320 and the DPB 314 may be formed by any of a variety of memory devices, such as DRAM. The various memory devices include SDRAM, MRAM, RRAM, or other types of memory devices. The CPB memory 320 and the DPB 314 may be provided by the same memory device or separate memory devices. In various examples, the CPB memory 320 may be on-chip with other components of the video decoder 300, or off-chip relative to those components.

[0112] Additionally or alternatively, in some examples, video decoder 300 can retrieve coded video data from memory 120 Figure 1 ) as described above in conjunction with CPB memory 320. Likewise, when some or all of the functionality of video decoder 300 is implemented by software to be executed by the processing circuitry of video decoder 300, memory 120 can store the instructions to be executed by video decoder 300.

[0113] The various units shown in FIG. 3 are utilized in the processing of video data as described in further detail below. These units can be implemented as fixed function Figure 4 circuitry, programmable circuitry, or a combination of the two. Similar to FIG. 2, the fixed function circuitry refers to circuitry that provides specific functionality and is preset on the operations that can be performed. The programmable circuitry refers to circuitry that can be programmed to perform a variety of tasks and provides flexible functionality in the operations that can be performed. For instance, the programmable circuitry can execute software or firmware that cause the programmable circuitry to operate in the manner defined by the instructions of the software or firmware. The fixed function circuitry can execute software instructions (e.g., receive parameters or output parameters), but the types of operations that the fixed function circuitry performs are generally unchangeable. In some examples, one or more of the units described above can be distinct circuit blocks (fixed or programmable), while in some examples, one or more of the units described above can be integrated circuitry. Figure 3 Video decoder 300 can include ALUs, EFUs, digital circuits, analog circuits, and / or programmable cores formed from programmable circuitry. In examples where the operations of video decoder 300 are performed by software executing on the programmable circuitry, on-chip or off-chip memory can store instructions (e.g., object code) for the software that video decoder 300 receives and executes.

[0114] Entropy decoding unit 302 can receive encoded video data from the CPB and entropy decode the video data to reproduce syntax elements. Prediction processing unit 304, inverse quantization unit 306, inverse transform processing unit 308, reconstruction unit 310, and filter unit 312 can generate decoded video data based on the syntax elements extracted from the bitstream.

[0115] In general, video decoder 300 reconstructs a picture on a block-by-block basis. Video decoder 300 can perform reconstruction operations individually for each block (where the block that is currently being reconstructed, i.e., decoded, can be referred to as the “current block”).

[0116]

[0117] ​Entropy decoding unit 302 can entropy decode syntax elements and transform information defining quantized transform coefficients of a quantized transform coefficient block, such as a quantization parameter (QP) and / or transform mode indication(s). Inverse quantization unit 306 can use the QP associated with the quantized transform coefficient block to determine a degree of quantization and, likewise, a degree of inverse quantization for application by inverse quantization unit 306. Inverse quantization unit 306 can, for example, perform a bitwise left shift operation to inverse quantize the quantized transform coefficients. Inverse quantization unit 306 can thereby form a transform coefficient block comprising transform coefficients.

[0118] After inverse quantization unit 306 forms the transform coefficient block, inverse transform processing unit 308 can apply one or more inverse transforms to the transform coefficient block to generate a residual block associated with the current block. For example, inverse transform processing unit 308 can apply an inverse DCT, an inverse integer transform, an inverse Karhunen-Loeve Transform (KLT), an inverse rotational transform, an inverse directional transform, or another inverse transform to the transform coefficient block.

[0119] Furthermore, prediction processing unit 304 generates a prediction block from the prediction information syntax elements entropy decoded by entropy decoding unit 302. For example, if the prediction information syntax elements indicate that the current block is inter-predicted, motion compensation unit 316 can generate the prediction block. In this case, the prediction information syntax elements can indicate a reference picture in DPB 314 from which to retrieve a reference block and a motion vector identifying a location of the reference block in the reference picture relative to the current block in the current picture. Motion compensation unit 316 can generally perform the inter-prediction process in a manner substantially similar to that described for motion compensation unit 224 Figure 3 ) above.

[0120] As will be described in greater detail below, motion compensation unit 316 can be configured to perform inter-prediction according to MER. For example, motion compensation unit 316 can be configured to perform a merge candidate list construction process in parallel for all coding units contained within the MER.

[0121] As another example, if the prediction information syntax elements indicate that the current block is intra-predicted, intra-prediction unit 318 can generate the prediction block according to an intra-prediction mode indicated by the prediction information syntax elements. Again, intra-prediction unit 318 can generally perform the intra-prediction process in a manner substantially similar to that described for intra-prediction unit 226 Figure 3 ) above. Intra-prediction unit 318 can retrieve data for neighboring samples of the current block from DPB 314.

[0122] Reconstruction unit 310 can reconstruct the current block using the prediction block and the residual block. For example, reconstruction unit 310 can add the samples of the residual block to corresponding samples of the prediction block to reconstruct the current block.

[0123] Filter unit 312 can perform one or more filter operations on the reconstructed block. For example, filter unit 312 can perform a deblocking operation to reduce blocking artifacts along the edges of the reconstructed block. The operations of filter unit 312 need not be performed in all examples.

[0124] Video decoder 300 can store the reconstructed block in DPB 314. For example, in examples in which the operations of filter unit 312 are not performed, reconstruction unit 310 can store the reconstructed block to DPB 314. In examples in which the operations of filter unit 312 are performed, filter 312 can store the filtered reconstructed block to DPB 314. As described above, DPB 314 can provide reference information, such as samples of a current picture for intra-prediction and previously decoded pictures for subsequent motion compensation, to prediction processing unit 304. Meanwhile, video decoder 300 can output decoded pictures (e.g., decoded video) from DPB 314 for subsequent presentation on a display device, such as display device 118 of FIG. 1. Figure 1

[0125] In this way, video decoder 300 represents an example device configured to decode video data. The device includes a memory configured to store the video data and one or more processing units implemented in circuitry. The one or more processing units are configured to determine merge estimation regions (MERs) for pictures of the video data such that, for each MER containing one or more coding units, the one or more coding units are all in the MER, and for each coding unit containing one or more MERs, the MERs are all in the coding unit, and perform motion estimation in parallel on the coding units in the MERs.

[0126] A motion vector predictor list (or motion vector candidate list) can include a merge candidate list and an AMVP candidate list. The motion vector predictor list can be used to encode and decode motion vectors for different inter prediction modes (e.g., merge mode and AMVP mode). For purposes of description, examples are described with reference to merge candidate list construction, but the techniques of this disclosure can be extended to other candidate list construction techniques, such as techniques for AMVP candidate list construction.

[0127] ​The merge candidate list construction process in certain example video coding techniques (e.g., HEVC and VVC) can introduce dependencies between neighboring blocks due to the use of spatial merge candidates. In certain example video encoder implementations, the motion estimation phase (e.g., performed by motion estimation unit 222 of FIG. 2) of neighboring blocks is typically performed in parallel or at least pipelined to improve throughput. Due to the dependencies between neighboring blocks, the merge candidate lists for neighboring blocks cannot be generated in parallel and can represent a bottleneck for parallel encoder / decoder designs. Figure 3

[0128] Accordingly, a parallel merge estimation process was introduced in HEVC. The parallel merge estimation process in HEVC uses an indication of a region (referred to as a merge estimation region (MER)) in which video encoder 200 and video decoder 300 can simultaneously derive merge candidate lists for two or more blocks. That is, video encoder 200 (e.g., via motion estimation unit 222 and motion compensation unit 224) and video decoder 300 (e.g., via motion compensation unit 316) can perform the merge candidate list construction process in parallel for multiple blocks within the indicated region (e.g., MER).

[0129] Video encoder 200 and video decoder 300 can determine blocks for which to perform the parallel merge candidate list construction process by checking whether a candidate block is in the indicated merge estimation region (MER). Candidate blocks that are in the same MER as the current block are not included in the merge candidate list. As such, the motion data for such candidates does not need to be available at the time of merge candidate list construction.

[0130] In an example in which the size of the MER is 32x32 samples, video encoder 200 and video decoder 300 can be configured to construct merge candidate lists in parallel for all blocks (e.g., coding units or prediction units) in a 32x32 sample region, as all merge candidates within the same 32x32 MER are not added to the merge candidate list. Figure 5 An example is shown in which CTU 500 is partitioned into seven CUs and ten PUs. The first CU includes PU0 and PU1, the second CU includes PU2, the third CU includes PU3, the fourth CU includes PU4, the fifth CU includes PU5 and PU6, the sixth CU includes PU7, and the seventh CU includes PU8 and PU9. In Figure 5 In the example of FIG. 5, CTU 500 includes a 64x64 luma coding tree block. Motion estimation for PUs within 32x32 MERs 510 (dashed blocks) is performed independently such that motion estimation (e.g., including merge candidate list construction) is performed in parallel for PUs within each MER 510. To illustrate, Figure 5 Possible spatial merge candidates are shown for PU0, PU5, and PU9.​

[0131] exist Figure 5 In the example of , merge candidate 520 for PU0 is available in the merge candidate list because these candidates are outside the 32×32 MER that includes PU0. For the 32×32 MER that includes PU2-PU6, the merge candidate list for PU2-PU6 cannot include motion data from any of PU2-PU6 because the merge estimation and merge candidate list construction within the MER should be independent (e.g., to be performed in parallel). Therefore, for PU5, merge candidate 530 is not available because these candidates are in the same MER that includes PU5. Merge candidate 540 for PU5 is not available because this candidate position has not yet been coded. Therefore, the merge list for PU5 can only include temporary candidates (if available) and zero MV candidates. For PU9, merge candidate 520 is available because these candidates are outside the MER that includes PU9, merge candidate 530 is not available because it is in the same MER as PU9, and merge candidate 540 is also not available because those candidate positions have not yet been coded.

[0132] To enable an encoder (e.g., video encoder 200) to balance parallelism and codec efficiency, the parallel merge estimation level (e.g., the size of the MER) can be adaptive and can be signaled using a syntax element. For example, the video encoder 200 can signal a syntax element (e.g., log2_parallel_merge_level_minus2) that indicates the size of the MER in the picture parameter set (PPS). The following MER sizes are allowed in HEVC: 4×4 (parallel merge list construction is not possible), 8×8, 16×16, 32×32, and 64×64. The higher degree of parallelism enabled by a larger MER excludes more potential candidates from the merge candidate list. However, a larger MER can reduce codec efficiency.

[0133] In VVC, both binary tree (BT) partitioning and ternary tree (TT) partitioning are used. In BT partitioning, a block can be split into two blocks. In TT partitioning, a block can be split into three blocks. Due to BT and TT partitioning and the VVC encoding and decoding order, the HEVC merged estimated region technique cannot be directly applied to pictures partitioned according to VVC. First, a VVC codec unit can extend over more than one MER, but such a codec unit does not contain a complete MER. Figure 6 An example is shown. Codec unit A and codec unit D do not completely fall into any 32×32 area, nor do they completely contain the entire MER. Figure 6In the example of FIG. 2, the left merge candidate of B should be marked as unavailable because the left merge candidate of B is in the same 32x32 region as B; while the bottom-left merge candidate of B should be marked as available because the bottom-left merge candidate of B is in a different 32x32 region. However, this results in a situation where both the left and bottom-left merge candidates of coding unit B are inside coding unit A, but only the bottom-left merge candidate (which is inside coding unit A) is marked as available, while the left merge candidate (which is also inside coding unit A) is marked as unavailable.

[0134] Additionally, the block coding order in VVC does not necessarily follow the z-scan order, as shown in Figure 7 Figure 7 In the example of FIG. 2, the left merge candidate of B should be marked as unavailable because the left merge candidate of B is in the same 32x32 region as B; while the bottom-left merge candidate of B should be marked as available because the bottom-left merge candidate of B is in a different 32x32 region. However, this results in a situation where both the left and bottom-left merge candidates of coding unit B are inside coding unit A, but only the bottom-left merge candidate (which is inside coding unit A) is marked as available, while the left merge candidate (which is also inside coding unit A) is marked as unavailable.

[0135] In view of these deficiencies, this disclosure describes techniques for parallel merge estimation (e.g., parallel merge candidate list construction) of pictures of video data partitioned in BT partition structures and TT partition structures (e.g., at least one of BT partition structures and TT partition structures). For example, in certain examples, pictures can be partitioned in BT partition structures, and these techniques are applicable to such pictures. In other examples, pictures can be partitioned in TT partition structures, and these techniques are also applicable to such pictures. In other instances, the techniques of this disclosure are applicable to pictures partitioned in both BT partition structures and TT partition structures.

[0136] According to the techniques of this disclosure, video encoder 200 and video decoder 300 are configured to perform parallel motion estimation in merge estimation regions (MERs) defined as rectangular regions such that the following conditions are satisfied:

[0137] Condition 1: For each MER containing one or more coding units, all of the coding units are in the MER.

[0138] Condition 2: For each coding unit containing one or more MERs, all of the MERs are in the coding unit.​

[0139] Example 1

[0140] In one example technique of this disclosure, a MER is defined as a square region of size N x N, where N is a unit of luma and / or chroma samples. In one example, N is greater than or equal to a maximum size of BT partitioning and / or a maximum size of TT partitioning. In this way, all BT partitions and TT partitions are within the MER region; thus conditions 1 and 2 above are satisfied. BT partitions or TT partitions are typically partitions of a larger block into multiple blocks according to a BT partition structure or a TT partition structure. A maximum BT size (e.g., a maxBTSize syntax element) and a maximum TT size (e.g., a maxTTSize syntax element) can be signaled separately and can be different from each other.

[0141] In one example, video encoder 200 can signal a syntax element mer enable flag with a value indicating whether a MER is applied. If the value of mer enable flag is true (e.g., equal to 1), video decoder 300 can set the MER size N equal to the maximum of the BT size and the TT size (e.g., max(maxBTSize, maxTTSize)). That is, video decoder 300 can receive and decode mer enable flag and determine whether a MER is used. If a MER is used, video decoder 300 can set the MER size based on max(maxBTSize, maxTTSize).

[0142] In another example, video encoder 200 can signal a syntax element of the MER size N indicated in a high-level syntax structure. Video encoder 200 can operate under a bitstream conformance constraint that the MER size N should be greater than or equal to the maximum of the BT size and the TT size (e.g., max(maxBTSize, maxTTSize)) or the MER is not applied (e.g., the MER size N is equal to a minimum block size). Video encoder 200 can be configured to signal a value of N as log2(N / 4) in the case that the minimum block size is 4.

[0143] In another example, video encoder 200 can signal a syntax element whose value indicates a difference of the MER size N and the maximum of the BT size and the TT size (e.g., max(maxBTSize, maxTTSize)). In certain examples, video encoder 200 can signal a syntax element mer enable flag to indicate whether MER is applied, and if the value of mer enable flag is true, the difference is signaled as a non-negative value log2DiffMERSizeMaxBtTtSize. If the value of mer enable flag is true, video decoder 300 can derive N as max(maxBTSize, maxTTSize) « log2DiffMERSizeMaxBtTtSize; otherwise, video decoder 300 can set N equal to the minimum block size.

[0144] Example 2

[0145] In a second example of the disclosure, a MER can be defined as a region of size M x N samples, where M and N can be different values. That is, in this example, a MER can be non-square. Video encoder 200 and video decoder 300 can be configured to constrain BT partitioning and TT partitioning such that the above two conditions are satisfied. That is, video encoder 200 can partition a picture of video data into coding units using BT partitioning and / or TT partitioning (e.g., BT and / or TT partition structures) such that the following conditions are satisfied.

[0146] Condition 1: For each MER containing one or more coding units, all of the coding units are in the MER.

[0147] Condition 2: For each coding unit containing one or more MERs, all of the MERs are in the coding unit.

[0148] Accordingly, in a general example of the disclosure, video encoder 200 can be configured to determine one or more MERs for a picture of video data. For example, video encoder 200 can be configured to determine an MxN size in samples of the MERs. Video encoder 200 is further configured to partition the picture of video data into coding units according to a constraint, where the constraint specifies that, for each MER containing one or more coding units, the one or more coding units are all in the MER, and for each coding unit containing one or more MERs, the MERs are all in the coding unit. In a more particular example, video encoder 200 can be configured to partition the picture of video data into coding units according to the constraint using one or more of binary tree partitioning or ternary tree partitioning, where the constraint specifies that binary tree partitioning and ternary tree partitioning are constrained such that, for each MER containing one or more coding units, the one or more coding units are all in the MER, and for each coding unit containing one or more MERs, the MERs are all in the coding unit. Video encoder 200 can then encode the coding units according to the MERs. For example, video encoder 200 can perform merge candidate list construction in parallel on the coding units in the MERs.

[0149] Figure 8 and Figure 9 Examples of disallowed and allowed BT partitions and TT partitions for a 128x128 CTU (in luma samples) of a 64x64 MER are shown according to the constraints described in the disclosure. Specifically, Figure 8 the BT partitions and TT partitions in Figure 9 the BT partitions and TT partitions in Figure 8 Examples of disallowed TT partitions and BT partitions for a 64x64-L (luma) / 32x32-C (chroma) pipeline are shown. A 64x64 luma block with a corresponding 32x32 chroma block is a basic unit of hardware processing for some example implementations (e.g., for a 4:2:0 chroma subsampling format). Figure 8 The dashed lines in Figure 8 each example of Figure 8 each of the example BT partitions and TT partitions results in at least one coding unit that crosses at least one MER boundary. That is, the example coding units in

[0150] Figure 9Examples of allowed TT partitions and BT partitions for 64x64-L / 32x32-C stream are shown. As such, the dashed lines indicate MERs, and the solid lines represent the coding units resulting from BT partitions and TT partitions. As in each of the examples of Figure 9 As can be seen in each of the examples, each of the example BT partitions and TT partitions results in coding units that are all within one or more MERs, or results in one or more MERs that are all within one coding unit. That is, either the coding units are all within the MERs, or one or more MERs are all within each coding unit, satisfying conditions 1 and 2 above.

[0151] In certain examples, M is equal to N (e.g., the MERs are square) and video encoder 200 can signal the value of M in a high-level syntax as log2_parallel_merge_level_minusS. In this example, "S" is the log2 of the minimum block size (e.g., 2). In another example, video encoder 200 can signal a syntax element that indicates both the value of M and the value of N (e.g., log2_parallel_merge_level_M_minusS and log2_parallel_merge_level_N_minusS) in a high-level syntax. In this example, "S" is the log2 of the minimum block size (e.g., 2). In another example, the values of M and N can be fixed values and need not be signaled.

[0152] In another example of the disclosure, video encoder 200 can be configured to partition a certain block (e.g., the current block) of a picture according to the constraints based on the size of the MERs and the size of the current block. As one specific example, video encoder 200 can be configured to apply the following rules to limit BT partitions and TT partitions.

[0153] - If W > M and H <= N, then horizontal BT partitioning of the current block is prohibited.

[0154] - If W <= M and H > N, then vertical BT partitioning of the current block is prohibited.

[0155] - If W > M and H <= 2*N, then horizontal TT partitioning of the current block is prohibited.

[0156] - If W <= 2*M and H > N, then vertical TT partitioning of the current block is prohibited.

[0157] In the above examples, W and H are the width and height of the current block, respectively. Thus, in general examples, video encoder 200 can be configured to disable horizontal binary tree splitting based on comparing the width and height of the block to the width and height of the MER. Similarly, video encoder 200 can be configured to disable vertical binary tree splitting based on comparing the width and height of the block to the width and height of the MER. Video encoder 200 can also be configured to disable horizontal ternary tree splitting based on comparing the width and height of the block to the width and height of the MER, and disable vertical ternary tree splitting based on comparing the width and height of the block to the width and height of the MER.

[0158] In more specific examples, video encoder 200 can be configured to disable horizontal binary tree splitting for a block if W is greater than M and H is less than or equal to N, disable vertical binary tree splitting for a block if W is less than or equal to M and H is greater than N, disable horizontal ternary tree splitting for a block if W is greater than M and H is less than or equal to 2*N, and disable vertical ternary tree splitting for a block if W is less than or equal to 2*M and H is greater than N. In this way, video encoder 200 can partition a picture such that both video encoder 200 and video decoder 300 can perform parallel merge candidate list construction in all MERs. Thus, inter prediction processing can be performed more quickly.

[0159] In the above examples, when a certain BT or TT split is disabled, video encoder 200 will not make that split. If a certain BT or TT split is not disabled, it does not mean that video encoder 200 must make that split, only that video encoder 200 can determine to make that split in certain cases.

[0160] In certain example implementations, video encoder 200 and video decoder 300 can be configured to restrict BT splitting at picture boundaries as follows:

[0161] - If the lower-left corner of the current block is inside the picture and the lower-right corner of the current block is outside the picture boundary, i.e., x+W> = picW and y+H

[0162] - If the lower-left corner of the current block is outside the picture boundary and the lower-right corner of the current block is inside the picture boundary, i.e., x+W

[0163] In the above example, picW and picH are the width and height of the picture, respectively. Variables x and y are the coordinates of the top-left pixel / sample of the current block. If MER is applied, the video encoder 200 can run according to the modified constraints on BT splitting at picture boundaries such that if the vertical BT splitting is disabled by the MER condition, the horizontal BT splitting is not disabled at picture boundaries. Likewise, if the horizontal BT splitting is disabled by the MER condition, the vertical BT splitting is not disabled at picture boundaries. Thus, the following applies to picture boundaries:

[0164] - If W <= M and H > N and x + W >= picW and y + H < picH, disable horizontal BT splitting for the current block.

[0165] - If W > M and H <= N and x + W < picW and y + H >= picH, disable vertical BT splitting for the current block.

[0166] Example 3

[0167] In the present example, the above MER condition 2 is modified at picture boundaries as follows:

[0168] - For each coding unit containing one or more MERs, the MERs are all in the coding unit or outside the picture boundary.

[0169] In the present example, when MER is applied, there is no need to necessarily modify the BT and TT restrictions at picture boundaries.

[0170] In one example, the video encoder 200 can apply the following constraints to limit BT splitting and TT splitting:

[0171] - If y + H < picH and W > M and H <= N, disable horizontal BT splitting for the current block.

[0172] - If x + W < picW and W <= M and H > N, disable vertical BT splitting for the current block.

[0173] - If W > M and H <= 2 * N, disable horizontal TT splitting for the current block.

[0174] - If W <= 2 * M and H > N, disable vertical TT splitting for the current block.

[0175] In the present example, picW and picH are the width and height of the picture, respectively. Variables x and y are the coordinates of the top-left pixel of the current block.

[0176] Strip conditions for enabling MER

[0177] In some examples, video encoder 200 and video decoder 300 can be configured to apply MER only in inter-prediction slices or in intra slices with in-loop copy mode enabled. Thus, in one example, video encoder 200 can apply one or more of the above-described constraints on BT partitioning and TT partitioning only for inter-prediction slices or intra slices with in-loop copy mode enabled.

[0178] In some examples, video encoder 200 and video decoder 300 can be configured to apply MER only if merge mode is enabled in the slice.

[0179] The above-described techniques can apply to both video encoder 200 and video decoder 300. In other examples, the above-described techniques can apply only to video encoder 200.

[0180] Figure 10 is a flowchart illustrating one example method for encoding a current block. The current block can include a current CU. Although described with reference to video encoder 200 Figure 1 and Figure 3 It should be understood that other devices can be configured to perform similar methods as the method of Figure 6

[0181] In this example, video encoder 200 initially predicts (350) the current block. For example, video encoder 200 can form a prediction block for the current block. Next, video encoder 200 can calculate a residual block for the current block (352). To calculate the residual block, video encoder 200 can calculate the difference between the original, unencoded block and the prediction block for the current block. Thereafter, video encoder 200 can transform and quantize the coefficients of the residual block (354). Next, video encoder 200 can scan the quantized transform coefficients of the residual block (356). During or after the scan, video encoder 200 can entropy encode the transform coefficients (358). For example, video encoder 200 can use CAVLC or CABAC to encode the transform coefficients. Video encoder 200 can then output the entropy encoded data for the block (360).

[0182] Video encoder 200 can also be configured to perform partitioning according to the constraints on MER, as described above. The example techniques are described in more detail below with reference to Figure 12

[0183] Figure 11 is a flowchart illustrating one example method for decoding a current block of video data. The current block can include a current CU. Although described with reference to video decoder 300 Figure 1 and Figure 4 ​​described, but it should be understood that other devices can be configured to perform similarly to Figure 7 the similar method.

[0184] Video decoder 300 can receive entropy encoded data for a current block, such as entropy encoded prediction information and entropy encoded data for coefficients of a residual block corresponding to the current block (370). Video decoder 300 can entropy decode the entropy encoded data to determine prediction information for the current block and to reproduce the coefficients of the residual block (372). Video decoder 300 can predict the current block (374), e.g., using an intra- or inter-prediction mode indicated by the prediction information for the current block, to calculate a prediction block for the current block. Video decoder 300 can then inverse scan the reproduced coefficients (376) to create a block of quantized transform coefficients. Next, video decoder 300 can inverse quantize and inverse transform the transform coefficients to produce a residual block (378). Video decoder 300 can finally decode the current block by combining the prediction block and the residual block (380).

[0185] Figure 12 is a flowchart showing another example encoding method of the present disclosure. Figure 12 The techniques of FIG. 1 can be performed by one or more structural components of video encoder 200.

[0186] In one example of the disclosure, video encoder 200 can be configured to determine one or more MERs for a picture of video data (1200). Video encoder 200 can also partition the picture of video data into coding units according to a constraint, where the constraint specifies that the partitioning is constrained such that, for each MER containing one or more coding units, the one or more coding units are all in the MER, and for each coding unit containing one or more MERs, the MERs are all in the coding unit (1210). Video encoder 200 can then encode the coding units according to the MERs (1220). For example, video encoder 200 can perform merge candidate list construction in parallel on the coding units in the MERs.

[0187] In one example, to partition the picture of video data, video encoder 200 can be configured to partition the picture of video data into coding units according to a constraint using one or more of binary tree partitioning or ternary tree partitioning, where the constraint specifies that the binary tree partitioning and the ternary tree partitioning are constrained such that, for each MER containing one or more coding units, the one or more coding units are all in the MER, and for each coding unit containing one or more MERs, the MERs are all in the coding unit.

[0188] In another example, to divide a picture of video data into codec units according to a constraint, the video encoder 200 may be configured to divide the block of the picture according to the constraint based on the size of the MER and the size of the block. For example, the video encoder 200 may be configured to: disable horizontal binary tree splitting based on comparing the width and height of the block with the width and height of the MER; disable vertical binary tree splitting based on comparing the width and height of the block with the width and height of the MER; disable horizontal ternary tree splitting based on comparing the width and height of the block with the width and height of the MER; and disable vertical ternary tree splitting based on comparing the width and height of the block with the width and height of the MER.

[0189] In another example, each MER in the MER has a size of M×N samples, where M is the height of the MER in terms of samples and N is the width of the MER in terms of samples. In this example, the size of the block is H×W samples, where H is the height of the block in terms of samples and W is the width of the block in terms of samples. In this example, to partition the blocks of the picture according to the constraints, the video encoder 200 can be configured to: prohibit horizontal binary tree partitioning of the block when W is greater than M and H is less than or equal to N, prohibit vertical binary tree partitioning of the block when W is less than or equal to M and H is greater than N, prohibit horizontal ternary tree partitioning of the block when W is greater than M and H is less than or equal to 2*N, and prohibit vertical ternary tree partitioning of the block when W is less than or equal to 2*M and H is greater than N.

[0190] In another example of the present disclosure, the video encoder 200 may be configured to generate a syntax element indicating a value of M and a value of N.

[0191] Other illustrative examples of the present disclosure are described below.

[0192] Aspect 1—A method of encoding and decoding video data, the method comprising: determining a merged estimation region (MER) for a picture of the video data such that: for each MER containing one or more codec units, the one or more codec units are all within the MER, and for each codec unit containing one or more MERs, the MER is all within the codec unit; and performing motion estimation on the codec units in the MER in parallel.

[0193] Aspect 2 - The method according to aspect 1, wherein performing motion estimation on the codec units in the MER in parallel comprises performing merge candidate list construction on the codec units in the MER in parallel.

[0194] Aspect 3 - The method according to aspect 1, wherein the MER has a size of N×N and N is greater than or equal to a maximum binary tree size or a maximum ternary tree size.

[0195] Aspect 4 - The method of aspect 1, wherein the MERs have a size of MxN and wherein the method further comprises: partitioning the picture such that at least one of the binary tree partitioning and the ternary tree partitioning is constrained such that for each MER containing one or more coding units, the one or more coding units are all in the MER, and for each coding unit containing one or more MERs, the MERs are all in the coding unit.

[0196] Aspect 5 - The method of aspect 4, wherein partitioning the picture comprises: disabling horizontal binary tree splitting based on a width and a height of the current block; disabling vertical binary tree splitting based on the width and the height of the current block; disabling horizontal ternary tree splitting based on the width and the height of the current block; and disabling vertical ternary tree splitting based on the width and the height of the current block.

[0197] Aspect 6 - The method of aspect 4, wherein partitioning the picture comprises: disabling horizontal binary tree splitting at a picture boundary if a lower left corner of the current block is inside the picture boundary and a lower right corner of the current block is outside the picture boundary; and disabling vertical binary tree splitting at the picture boundary if the lower left corner of the current block is outside the picture boundary and the lower right corner of the current block is inside the picture boundary.

[0198] Aspect 7 - A method of coding video data, the method comprising: determining one or more merge estimation regions (MERs) for a picture of the video data such that: for each MER containing one or more coding units at a picture boundary, the one or more coding units are all in the MER, and for each coding unit containing one or more MERs, the one or more MERs are all in the coding unit or outside the picture boundary; and performing motion estimation on the coding units in the MERs in parallel.

[0199] Aspect 8 - The method of any combination of aspects 1-7, further comprising: determining to use the MERs only for inter prediction slices or intra slices with in-loop copy mode enabled.

[0200] Aspect 9 - The method of any combination of aspects 1-7, further comprising: determining to use the MERs only for slices in which merge mode is enabled.

[0201] Aspect 10 - The method of any of aspects 1-9, wherein coding comprises decoding.

[0202] Aspect 11 - The method of any of aspects 1-9, wherein coding comprises encoding.

[0203] Aspect 12 - A device for coding video data, the device comprising one or more means for performing the method of any of aspects 1-11.

[0204] Aspect 13 - The device of aspect 12, wherein the one or more means comprise one or more processors implemented in circuitry.

[0205] Aspect 14 - The device of any of aspects 12 and 13, further comprising a memory for storing video data.

[0206] Aspect 15 - The device of any of aspects 12-14, further comprising a display configured to display decoded video data.

[0207] Aspect 16 - The device of any of aspects 12-15, wherein the device comprises one or more of a camera, a computer, a mobile device, a broadcast receiver device, or a set-top box.

[0208] Aspect 17 - The device of any of aspects 12-16, wherein the device comprises a video decoder.

[0209] Aspect 18 - The device of any of aspects 12-17, wherein the device comprises a video encoder.

[0210] Aspect 19 - A computer-readable storage medium having stored thereon instructions that, when executed, cause one or more processors to perform the method of any of aspects 1-9.

[0211] Aspect 20 - Any combination of the techniques described in this disclosure.

[0212] It should be appreciated that according to examples, certain actions or events of any of the techniques described herein can be performed in a different order, can be added, merged or omitted altogether (e.g., not all described actions or events are necessary for practice of these techniques), and some actions or events can be performed concurrently in a multithreaded manner (e.g., according to multithreaded processing, interrupt processing, or multiple processors). Moreover, in certain examples, actions or events can be performed by a processing unit or other processing device, rather than a processor.

[0213] In one or more examples, the functions described can be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions can be stored on or transmitted over as one or more instructions or code on a computer-readable medium and executed by a hardware-based processing unit. Computer-readable media can include computer-readable storage media, which corresponds to a tangible medium such as data storage media, or communication media including any medium that facilitates transfer of a computer program from one place to another, e.g., according to a communication protocol. In this manner, computer- readable media generally can correspond to (1) tangible computer-readable storage media which is non-transitory or (2) a communication medium such as a signal or carrier wave. Data storage media can be any available media that can be accessed by one or more computers or one or more processors to retrieve instructions, code, and / or data structures for implementation of the techniques described in this disclosure. A computer program product can include a computer-readable medium.

[0214] By way of example, and not limitation, such computer-readable storage media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage, or other magnetic storage devices, flash memory, or any other storage medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. Also, any

[0215] Instructions can be executed by one or more processors, such as one or more signal processors (DSPs), general purpose microprocessors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or other equivalent integrated or discrete logic circuitry. Accordingly, the terms "processor" and "processing circuitry," as used herein can refer to any of the foregoing structures or any other structure suitable for implementation of the techniques described herein. In addition, in some aspects, the functionality described herein can be provided within dedicated hardware and / or software modules configured for encoding and decoding, or incorporated in a combined codec. Also, the techniques could be fully implemented in one or more circuits or logic elements.

[0216] The techniques of this disclosure can be implemented in a wide variety of devices or apparatuses, including a wireless handset, an integrated circuit (IC) or a set of ICs (e.g., a chip set). There are multiple ways of implementing the present disclosure. Examples of which are described in further detail below.

[0217] A great variety of examples have been described. These and other examples are within the scope of the following claims.

Claims

1. A method for encoding video data, the method comprising: determining one or more merged estimation regions MER for a picture of the video data; Partitioning the picture of the video data into codec units according to a constraint, wherein the constraint specifies that the partitioning is constrained such that: for each MER containing one or more codec units, the one or more codec units are all within the MER, and for each codec unit containing one or more MERs, the MERs are all within the codec unit; as well as The codec unit is encoded according to the MER.

2. The method according to claim 1, wherein Dividing the pictures of the video data includes: Partitioning the picture of the video data into codec units according to the constraint using one or more of a binary tree partitioning or a ternary tree partitioning, wherein the constraint specifies that the binary tree partitioning and the ternary tree partitioning are constrained such that: for each MER containing one or more codec units, the one or more codec units are all within the MER, and for each codec unit containing one or more MERs, the MERs are all within the codec unit.

3. The method according to claim 1, wherein Dividing the picture of the video data into codec units according to the constraint includes: The block of the picture is divided according to the constraint based on the size of the MER and the size of the block.

4. The method according to claim 3, wherein: Dividing the block of the picture according to the constraint based on the size of the MER and the size of the block includes: disabling horizontal binary tree splitting based on comparing the width and height of the block to the width and height of the MER; disabling vertical binary tree splitting based on comparing the width and height of the block to the width and height of the MER; disabling horizontal ternary tree splitting based on comparing the width and height of the block to the width and height of the MER; and Vertical ternary tree splitting is disabled based on comparing the width and height of the block to the width and height of the MER.

5. The method according to claim 3, wherein Each of the MERs has a size of M×N samples, where M is a height of the MER in terms of samples, where N is a width of the MER in terms of samples, wherein a size of the block has a size of H×W samples, where H is a height of the block in terms of samples, where W is a width of the block in terms of samples, and wherein partitioning the block of the picture according to the constraint comprises: If W is greater than M and H is less than or equal to N, horizontal binary tree partitioning of the block is prohibited; If W is less than or equal to M and H is greater than N, vertical binary tree partitioning of the block is prohibited; prohibiting horizontal ternary tree partitioning of the block if W is greater than M and H is less than or equal to 2*N; and If W is less than or equal to 2*M and H is greater than N, vertical ternary tree partitioning of the block is prohibited.

6. The method according to claim 5, further comprising: A syntax element indicating the value of M and the value of N is generated.

7. The method according to claim 1, wherein Encoding the codec unit according to the MER includes: The merge candidate list construction is performed in parallel on the codec units in the MER.

8. The method according to claim 1, further comprising: The picture of the video data is captured with a camera.

9. An apparatus configured to encode video data, the apparatus comprising: a memory configured to store pictures of the video data; as well as one or more processors in communication with the memory, the one or more processors configured to: determining one or more merged estimation regions MER for the picture of the video data; Partitioning the picture of the video data into codec units according to a constraint, wherein the constraint specifies that the partitioning is constrained such that: for each MER containing one or more codec units, the one or more codec units are all within the MER, and for each codec unit containing one or more MERs, the MERs are all within the codec unit; as well as The codec unit is encoded according to the MER.

10. The device according to claim 9, wherein In order to divide the picture of the video data, the one or more processors are further configured to: The picture of the video data is divided into codec units according to the constraint using one or more of a binary tree partitioning or a ternary tree partitioning, wherein the constraint specifies that the binary tree partitioning and the ternary tree partitioning are constrained such that: for each MER containing one or more codec units, the one or more codec units are all within the MER, and for each codec unit containing one or more MERs, the MERs are all within the codec unit.

11. The device according to claim 9, wherein To divide the picture of the video data into coding units according to the constraint, the one or more processors are further configured to: The block of the picture is divided according to the constraint based on the size of the MER and the size of the block.

12. The device according to claim 11, wherein To partition the block of the picture according to the constraint based on the size of the MER and the size of the block, the one or more processors are further configured to: disabling horizontal binary tree splitting based on comparing the width and height of the block to the width and height of the MER; disabling vertical binary tree splitting based on comparing the width and height of the block to the width and height of the MER; disabling horizontal ternary tree splitting based on comparing the width and height of the block to the width and height of the MER; and Vertical ternary tree splitting is disabled based on comparing the width and height of the block to the width and height of the MER.

13. The device according to claim 11, wherein Each of the MERs has a size of M×N samples, where M is a height of the MER in terms of samples, where N is a width of the MER in terms of samples, wherein a size of the block has a size of H×W samples, where H is a height of the block in terms of samples, where W is a width of the block in terms of samples, and wherein to partition the block of the picture according to the constraint, the one or more processors are further configured to: If W is greater than M and H is less than or equal to N, horizontal binary tree partitioning of the block is prohibited; If W is less than or equal to M and H is greater than N, vertical binary tree partitioning of the block is prohibited; If W is greater than M and H is less than or equal to 2*N, horizontal ternary tree splitting of the block is prohibited; as well as If W is less than or equal to 2*M and H is greater than N, vertical ternary tree partitioning of the block is prohibited.

14. The device according to claim 13, wherein The one or more processors are further configured to: A syntax element indicating the value of M and the value of N is generated.

15. The device according to claim 9, wherein To encode the codec unit according to the MER, the one or more processors are further configured to: The merge candidate list construction is performed in parallel on the codec units in the MER.

16. The apparatus according to claim 9, further comprising: A camera configured to capture said picture of the video data.

17. An apparatus configured to encode video data, the apparatus comprising: means for determining one or more merged estimation regions (MERs) for a picture of the video data; means for partitioning the picture of the video data into codec units according to a constraint, wherein the constraint specifies that the partitioning is constrained such that: for each MER containing one or more codec units, the one or more codec units are all within the MER, and for each codec unit containing one or more MERs, the MERs are all within the codec unit; as well as Means for encoding the codec unit according to the MER.

18. The device according to claim 17, wherein The component for dividing the picture of the video data includes: Means for partitioning the picture of the video data into codec units using one or more of a binary tree partitioning or a ternary tree partitioning according to the constraint, wherein the constraint specifies that the binary tree partitioning and the ternary tree partitioning are constrained such that: for each MER containing one or more codec units, the one or more codec units are all within the MER, and for each codec unit containing one or more MERs, the MERs are all within the codec unit.

19. The device according to claim 17, wherein The means for dividing the picture of the video data into coding units according to the constraint comprises: means for partitioning the block of the picture according to the constraint based on a size of the MER and a size of the block.

20. The apparatus according to claim 19, wherein The means for dividing the block of the picture according to the constraint based on the size of the MER and the size of the block comprises: disabling a component of a horizontal binary tree partition based on comparing the width and height of the block to the width and height of the MER; means for disabling vertical binary tree partitioning based on comparing the width and height of the block to the width and height of the MER; disabling components of horizontal ternary tree partitioning based on comparing the width and height of the block to the width and height of the MER; and Components of the vertical ternary tree partitioning are disabled based on comparing the width and height of the block to the width and height of the MER.

21. The apparatus according to claim 19, wherein Each of the MERs has a size of M×N samples, where M is the height of the MER in terms of samples, where N is the width of the MER in terms of samples, wherein the block has a size of H×W samples, where H is the height of the block in terms of samples, where W is the width of the block in terms of samples, and wherein the means for partitioning the block of the picture according to the constraint comprises: a component for prohibiting horizontal binary tree partitioning of the block when W is greater than M and H is less than or equal to N; a component for prohibiting vertical binary tree partitioning of the block when W is less than or equal to M and H is greater than N; means for prohibiting horizontal ternary tree partitioning of the block if W is greater than M and H is less than or equal to 2*N; and If W is less than or equal to 2*M and H is greater than N, the component that performs vertical ternary tree partitioning on the block is prohibited.

22. The apparatus according to claim 21, further comprising: Means for generating a syntax element indicating a value of M and a value of N.

23. The apparatus according to claim 17, wherein The component for encoding the codec unit according to the MER includes: A component for performing merge candidate list construction on the coding and decoding units in the MER in parallel.

24. A non-transitory computer-readable storage medium storing instructions that, when executed, cause one or more processors configured to encode video data to: determining one or more merged estimation regions (MERs) for a picture of the video data; Partitioning the picture of the video data into codec units according to a constraint, wherein the constraint specifies that the partitioning is constrained such that: for each MER containing one or more codec units, the one or more codec units are all within the MER, and for each codec unit containing one or more MERs, the MERs are all within the codec unit; and The codec unit is encoded according to the MER.

25. The non-transitory computer-readable storage medium of claim 24, wherein: To partition the pictures of the video data, the instructions further cause the one or more processors to: Partitioning the picture of the video data into codec units according to the constraint using one or more of a binary tree partitioning or a ternary tree partitioning, wherein the constraint specifies that the binary tree partitioning and the ternary tree partitioning are constrained such that: for each MER containing one or more codec units, the one or more codec units are all within the MER, and for each codec unit containing one or more MERs, the MERs are all within the codec unit.

26. The non-transitory computer-readable storage medium of claim 24, wherein: To divide the picture of the video data into codec units according to the constraint, the instructions further cause the one or more processors to: The block of the picture is divided according to the constraint based on the size of the MER and the size of the block.

27. The non-transitory computer-readable storage medium of claim 26, wherein: To partition the block of the picture according to the constraint based on the size of the MER and the size of the block, the instructions further cause the one or more processors to: disabling horizontal binary tree splitting based on comparing the width and height of the block to the width and height of the MER; disabling vertical binary tree splitting based on comparing the width and height of the block to the width and height of the MER; disabling horizontal ternary tree splitting based on comparing the width and height of the block to the width and height of the MER; and Vertical ternary tree splitting is disabled based on comparing the width and height of the block to the width and height of the MER.

28. The non-transitory computer-readable storage medium of claim 26, wherein: Each of the MERs has a size of M×N samples, where M is a height of the MER in terms of samples, where N is a width of the MER in terms of samples, wherein a size of the block has a size of H×W samples, where H is a height of the block in terms of samples, where W is a width of the block in terms of samples, and wherein to partition the block of the picture according to the constraint, the instructions further cause the one or more processors to: If W is greater than M and H is less than or equal to N, horizontal binary tree partitioning of the block is prohibited; If W is less than or equal to M and H is greater than N, vertical binary tree partitioning of the block is prohibited; If W is greater than M and H is less than or equal to 2*N, horizontal ternary tree splitting of the block is prohibited; as well as If W is less than or equal to 2*M and H is greater than N, vertical ternary tree partitioning of the block is prohibited.

29. The non-transitory computer-readable storage medium of claim 28, wherein: The instructions further cause the one or more processors to: A syntax element indicating the value of M and the value of N is generated.

30. The non-transitory computer-readable storage medium of claim 24, wherein: To encode the codec unit according to the MER, the instructions further cause the one or more processors to: The merge candidate list construction is performed in parallel on the codec units in the MER.

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