Data processing method and data processing apparatus based on a memristor array

Abstract

A data processing method and a data processing device based on a memristor array. The method comprises: obtaining a Bayesian neural network, wherein the Bayesian neural network has a trained weight matrix; obtaining a plurality of target conductance values corresponding to the weight matrix of the Bayesian neural network, and mapping the plurality of target conductance values to the memristor array; inputting a current state feature vector and a hidden input variable corresponding to a dynamic system as input signals to the memristor array after weight mapping, processing the current state feature vector and the hidden input variable according to the Bayesian neural network through the memristor array, and obtaining an output signal corresponding to a processing result from the memristor array, wherein the output signal is used to obtain a prediction result of a next state of the dynamic system. The method uses a Bayesian neural network with a hidden input variable based on a memristor array to predict a dynamic system, and has low power consumption, high calculation speed and high calculation energy efficiency.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a data processing method and a data processing apparatus based on a memristor array. BACKGROUND

[0002] Artificial neural networks (ANNs) have been widely used in modeling dynamic systems. However, it remains a challenge to use traditional ANNs for long-term task planning due to the lack of ability to model uncertainty. The inherent randomness (uncertainty) of real systems-process noise and approximation errors introduced by data-driven modeling can cause long-term estimates of ANNs to deviate from the actual behavior of the system. Probabilistic models provide a way to address uncertainty, which allow people to make informed decisions using the predictions of the model while being cautious about the uncertainty of these predictions. SUMMARY

[0003] At least one embodiment of the present disclosure provides a data processing method based on a memristor array, comprising: obtaining a Bayesian neural network having a trained weight matrix; obtaining a plurality of target conductance values corresponding to the weight matrix of the Bayesian neural network, and mapping the plurality of target conductance values into a memristor array; inputting a current state feature vector and a hidden input variable corresponding to a dynamic system as input signals into the memristor array after weight mapping, processing the current state feature vector and the hidden input variable according to the Bayesian neural network through the memristor array, and obtaining an output signal corresponding to a processing result from the memristor array, wherein the output signal is used to obtain a prediction result of a next state of the dynamic system.

[0004] For example, in the data processing method provided by an embodiment of the present disclosure, the processing according to the Bayesian neural network through the memristor array can be expressed as y=f(x,z,W,ε), wherein x is the current state feature vector of the dynamic system, z is the hidden input variable, W is the weight matrix of the Bayesian neural network, ε is the additive noise corresponding to the memristor array, and y is the prediction result of the next state of the dynamic system; wherein the hidden input variable z satisfies the first distribution z~p(z), the weight matrix W of the Bayesian neural network satisfies the second distribution W~q(W), and the additive noise ε is additive Gaussian noise ε~N(0,σ 2 ).

[0005] For example, the data processing method provided by an embodiment of the present disclosure further comprises: obtaining the uncertainty of the data processing method.

[0006] For example, in a data processing method provided in one embodiment of this disclosure, the uncertainty of the data processing method is obtained, including: the random uncertainty of the data processing method and the cognitive uncertainty of the data processing method, wherein the random uncertainty is caused by the latent input variable and the cognitive uncertainty is caused by the intrinsic noise of the memristor array.

[0007] For example, in a data processing method provided in one embodiment of this disclosure, obtaining the uncertainty of the data processing method includes: obtaining the initial state s corresponding to time t-1 corresponding to uniform sampling of the dynamic system. t-1 Using a memristor array and based on implicit input variables, the predicted state s corresponding to time t after t-1 is obtained. t And obtain the corresponding predicted state s t The cost c t An M×N matrix, where s t =f(s) t-1 ,z,W,ε); and according to the cost c t The method for calculating M×N matrix data processing is applicable to the uncertainty of dynamic systems, where M and N are both integers greater than 1.

[0008] For example, in a data processing method provided in one embodiment of this disclosure, a memristor array is used and a hidden input variable is used to obtain the predicted state s corresponding to time t. t And obtain the corresponding predicted state s t The cost c t The M×N matrix includes: M samples {z1, z2, ..., zn} obtained by sampling the latent input variable z from the p(z) distribution M times. m ,…,z M}; For each of the M samples, the latent input variable z m and initial state s t-1 The input to the weighted memristor array yields N predicted states s. t The predicted state s is obtained from M samples. t An M×N matrix, where 1≤m≤M; for the predicted state s t For each element in the M×N matrix, calculate the cost c. t =c(s) t ), and obtain the cost c t An M×N matrix.

[0009] For example, in a data processing method provided in one embodiment of this disclosure, the uncertainty of the dynamic system at time t is expressed as: in, It is a matter of chance and uncertainty, and E p(z) [σ 2 (ct The cognitive uncertainty is a cognitive uncertainty.

[0010] For example, in the data processing method provided by an embodiment of the present disclosure, the MxN matrix of the predicted state s t is used to determine the accidental uncertainty; and the MxN matrix of the predicted state s t is used to determine the cognitive uncertainty.

[0011] For example, in the data processing method provided by an embodiment of the present disclosure, the Bayesian neural network includes a full connection structure or a convolutional neural network structure.

[0012] For example, in the data processing method provided by an embodiment of the present disclosure, for the memristor array, the input signal is a voltage signal, the output signal is a current signal, the output signal is read and analog-to-digital converted for subsequent processing.

[0013] The data processing apparatus provided by at least one embodiment of the present disclosure comprises: an acquisition unit configured to acquire a Bayesian neural network, wherein the Bayesian neural network has a trained weight matrix; an array device comprising a memristor array and configured to map a plurality of target conductance values corresponding to the weight matrix of the Bayesian neural network to the memristor array; and a control unit configured to input a current state feature vector and a hidden input variable corresponding to a dynamic system as an input signal to the memristor array after weight mapping, process the current state feature vector and the hidden input variable according to the Bayesian neural network through the memristor array, and acquire an output signal as a processing result from the memristor array, wherein the output signal is used to obtain a prediction result of a next state of the dynamic system. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings described below only relate to some embodiments of the present disclosure, but not limit the present disclosure.

[0015] Figure 1 A schematic flowchart of a data processing method based on a memristor array provided by at least one embodiment of the present disclosure is shown;

[0016] Figure 2A A schematic structure of a memristor array is shown;

[0017] Figure 2B A schematic diagram of a memristor device provided by at least one embodiment of the present disclosure is shown;

[0018] Figure 2C ​​Another schematic diagram of a memristor device provided by at least one embodiment of the present disclosure is shown;

[0019] Figure 2D A schematic diagram showing mapping of a weight matrix to a memristor array is shown;

[0020] Figure 3 An architecture of a Bayesian neural network with hidden input variables based on a memristor array is shown;

[0021] Figure 4 A schematic flowchart of a method for obtaining uncertainty of a data processing method provided by at least one embodiment of the present disclosure is shown;

[0022] Figure 5 A schematic diagram of a method for obtaining a predicted state matrix provided by at least one embodiment of the present disclosure is shown;

[0023] Figure 6 A schematic block diagram of a data processing device provided by at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0024] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without any creative effort fall within the scope of protection of the present disclosure.

[0025] Unless otherwise defined, technical terms or scientific terms used in the present disclosure should be understood as having the same meaning as commonly understood by a person of ordinary skill in the art to which the present disclosure belongs. The terms “first”, “second” and similar terms used in the present disclosure do not indicate any order, number or importance, but are only used to distinguish different components. Similarly, the terms “one”, “a” or “the” and similar terms do not indicate a quantity limitation, but indicate that at least one exists. The terms “include” or “contain” and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, without excluding other elements or objects. The terms “connect” or “connected” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “up”, “down”, “left”, “right” and the like only indicate relative positional relationships, which can change accordingly when the absolute positions of the described objects change.

[0026] A Bayesian network (BNN) is a probabilistic model that places a neural network in a Bayesian framework. A Bayesian network with latent input variables (BNN+LV) can describe complex stochastic patterns through the distribution over the latent input variables (aleatoric uncertainty) and consider the uncertainty of the model through the distribution over the weights (epistemic uncertainty).

[0027] The structure of the Bayesian network includes but is not limited to a fully connected structure, a convolutional neural network (CNN) structure, etc., and the network weight W of the Bayesian network is a random variable (W ~ q(W)). It is assumed that there is a dataset D = {X, Y} for the dynamic system of the Bayesian network, where X is the state feature vector of the dynamic system, and Y is the next state of the dynamic system. The input of the Bayesian network is the state feature vector X of the dynamic system and the latent input variable z (z ~ p(z), the parameters of the Bayesian network can be trained, and the output of the Bayesian network superimposed with independent additive Gaussian noise ε (ε ~ N(0, σ 2 )) is the prediction y of the next state of the dynamic system, that is, y = f(X, z, W, ε). For example, after training, each weight of the Bayesian network is a distribution.

[0028] On a traditional hardware computing platform (for example, a central processing unit, a graphics processing unit), BNN+LV requires a relatively large computing cost. The core sampling method of this method, the Markov chain Monte Carlo method, is highly dependent on the speed of the computer due to a large number of sampling calculations.

[0029] The at least one embodiment of the present disclosure provides a data processing method based on a memristor array, including: obtaining a Bayesian neural network, wherein the Bayesian neural network has a trained weight matrix; obtaining a plurality of target conductance values corresponding to the weight matrix of the Bayesian neural network, and mapping the plurality of target conductance values to a memristor array; inputting a current state feature vector and a latent input variable corresponding to a dynamic system as input signals to the memristor array after weight mapping, processing the current state feature vector and the latent input variable according to the Bayesian neural network through the memristor array, and obtaining an output signal corresponding to a processing result from the memristor array, wherein the output signal is used to obtain a prediction result of a next state of the dynamic system.

[0030] The data processing method provided by the embodiments of the present disclosure is based on a Bayesian neural network of a memristor, uses the random characteristics of the memristor to model a dynamic system, and introduces input latent variables. The required weight sampling and vector matrix multiplication of BNN+LV can be completed by performing parallel read operations on a simulated memristor cross array, thereby greatly improving the energy efficiency of the calculation.

[0031] The data processing device corresponding to the data processing method is also provided in at least one embodiment of the present disclosure.

[0032] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings, but the present disclosure is not limited to these specific embodiments.

[0033] Figure 1 A schematic flowchart of a data processing method based on a memristor array is shown.

[0034] As Figure 1 shown, the data processing method includes the following steps S101-S103.

[0035] Step S101: Obtain a Bayesian neural network, wherein the Bayesian neural network has a trained weight matrix.

[0036] For example, the structure of the Bayesian neural network includes a fully connected structure or a convolutional neural network structure, etc. The network weight of the Bayesian neural network is a random variable. For example, after the training of the Bayesian neural network is completed, each weight is a distribution, such as a Gaussian distribution or a Laplace distribution.

[0037] For example, the Bayesian neural network can be trained offline to obtain the weight matrix. The method for training the Bayesian neural network can refer to a conventional method, such as using a central processing unit (CPU), an image processing unit, a neural network processing unit (NPU), etc., which will not be described herein.

[0038] Step S102: Obtain a plurality of target conductance values corresponding to the weight matrix of the Bayesian neural network, and map the plurality of target conductance values to a memristor array.

[0039] After the training of the Bayesian neural network is completed to obtain the weight matrix, the weight matrix is processed to obtain a plurality of target conductance values. For example, in this process, the weight matrix can be biased and scaled until the weight matrix meets a suitable conductance window. After the biasing and scaling of the weight matrix are completed, the target conductance values are calculated according to the processed weight matrix and the conductance values of the memristor. The specific process of calculating the target conductance values can refer to the related description of the Bayesian neural network based on the memristor, which will not be described herein.

[0040] Figure 2A A schematic structure of a memristor array is shown, for example, composed of a plurality of memristor cells, which form an array of M rows and N columns, M and N being positive integers. Each memristor cell comprises a switching element and one or more memristors. In Figure 2A WL<1>, WL<2>... WL <m>BL<1>, BL<2>... BL <n>bit lines of the first column, the second column,..., the Nth column respectively, the memristor in the memristor unit circuit of each column and the bit line corresponding to the column are connected; SL<1>, SL<2>,..., SL <m>source lines representing the first row, the second row, …, the Mth row, respectively, and the source of the transistor in each row of the memristor cell circuit is connected to the source line corresponding to the row. According to Kirchhoff's law, the above-mentioned memristor array can complete the multiply-accumulate calculation in parallel by setting the state (for example, the resistance value) of the memristor unit and applying corresponding word line signals and bit line signals to the word line and the bit line.

[0041] Figure 2B A schematic diagram of a memristor device is provided for at least one embodiment of the present disclosure, which includes a memristor array and its peripheral driving circuit. For example, as shown in Figure 2B The memristor device includes a signal acquisition device, a word line driving circuit, a bit line driving circuit, a source line driving circuit, a memristor array, and a data output circuit.

[0042] For example, the signal acquisition device is configured to convert a digital signal into a plurality of analog signals through a digital to analog converter (DAC) to input to a plurality of column signal input terminals of the memristor array.

[0043] For example, the memristor array includes M source lines, M word lines, and N bit lines, and the array is arranged as a plurality of memristor units in M rows and N columns.

[0044] For example, the operation of the memristor array is realized through the word line driving circuit, the bit line driving circuit, and the source line driving circuit.

[0045] For example, the word line driving circuit includes a plurality of multiplexers (Muxes) for switching the word line input voltage; the bit line driving circuit includes a plurality of multiplexers for switching the bit line input voltage; and the source line driving circuit also includes a plurality of multiplexers (Muxes) for switching the source line input voltage. For example, the source line driving circuit further includes a plurality of ADCs for converting analog signals into digital signals. In addition, a trans-impedance amplifier (TIA) (not shown in the figure) can be further provided between the Mux and the ADC in the source line driving circuit to complete the conversion from current to voltage, so as to facilitate the processing of the ADC.

[0046] For example, the memristor array includes an operation mode and a calculation mode. When the memristor array is in the operation mode, the memristor unit is in an initialization state, and the numerical values of the parameter elements in the parameter matrix can be written into the memristor array. For example, the source line input voltage, the bit line input voltage, and the word line input voltage of the memristor are switched to the corresponding preset voltage interval through the multiplexers.

[0047] For example, by Figure 2B The control signal WL_sw[1:M] of the multiplexer in the word line driver circuit switches the word line input voltage to the corresponding voltage range. For example, when setting the memristor, the word line input voltage is set to 2V (volts); when resetting the memristor, the word line input voltage is set to 5V. The word line input voltage can be adjusted by... Figure 2B The voltage signal V_WL[1:M] in the middle is obtained.

[0048] For example, through Figure 2B The control signal SL_sw[1:M] of the multiplexer in the source line drive circuit switches the source line input voltage to the corresponding voltage range. For example, when setting the memristor, the source line input voltage is set to 0V; when resetting the memristor, the source line input voltage is set to 2V. The source line input voltage can be adjusted by... Figure 2B The voltage signal V_SL[1:M] is obtained.

[0049] For example, through Figure 2B The control signal BL_sw[1:N] of the multiplexer in the bit line drive circuit switches the bit line input voltage to the corresponding voltage range. For example, when setting the memristor, the bit line input voltage is set to 2V; when resetting the memristor, the bit line input voltage is set to 0V. The bit line input voltage can be... Figure 2B The DAC is obtained.

[0050] For example, when the memristor array is in compute mode, the memristors in the array are in a conductive state that can be used for computation. The bit line input voltage at the column signal input terminal does not change the conductance of the memristors. For example, calculations can be performed by multiplying and adding operations using the memristor array. Figure 2B The control signal WL_sw[1:M] of the multiplexer in the word line driver circuit switches the word line input voltage to the corresponding voltage range. For example, when an enable signal is applied, the word line input voltage of the corresponding row is set to 5V; when no enable signal is applied, the word line input voltage of the corresponding row is set to 0V. For example, the GND signal is turned on. Figure 2B The control signal SL_sw[1:M] of the multiplexer in the source line drive circuit switches the source line input voltage to the corresponding voltage range, for example, setting the source line input voltage to 0V, so that the current signals of multiple row signal output terminals can flow into the data output circuit. Figure 2C The control signal BL_sw[1:N] of the multiplexer in the bit line drive circuit switches the bit line input voltage to the corresponding voltage range, for example, setting the bit line input voltage to 0.1V-0.3V, thereby using the memristor array to perform multiplication and addition operations.

[0051] For example, the data output circuit can include a plurality of TIAs, ADCs, which can convert the current signals of the plurality of row signal output ends into voltage signals, and then into digital signals for subsequent processing.

[0052] Figure 2C Another schematic diagram of a memristor device provided for at least one embodiment of the present disclosure. Figure 2B The memristor device shown is substantially the same as Figure 2C The structure of the memristor device shown is substantially the same as the previous embodiment, and also includes a memristor array and a peripheral driving circuit thereof. For example, as Figure 2D The memristor device shown includes a signal acquisition device, a word line driving circuit, a bit line driving circuit, a source line driving circuit, a memristor array, and a data output circuit.

[0053] For example, the memristor array includes M source lines, 2M word lines, and 2N bit lines, and is arranged in a plurality of memristor units in M rows and N columns. For example, each memristor unit is a 2T2R structure, and the mapping of the parameter matrix for transformation processing is performed on different plurality of memristor units in the memristor array, which will not be described here. It should be noted that the memristor array can also include M source lines, M word lines, and 2N bit lines, and is arranged in a plurality of memristor units in M rows and N columns.

[0054] The description of the signal acquisition device, the control driving circuit, and the data output circuit can refer to the previous description, which will not be described here.

[0055] Figure 2D The process of mapping the weight matrix to the memristor array is shown. The memristor array with N memristors is used as the weight matrix between layers in the Bayesian neural network. The weight matrix in the Bayesian neural network is converted into a target conductance value mapped into a cross sequence of the memristor array.

[0056] As shown in Figure 2D The left side of the figure is a three-layer Bayesian neural network, which includes three layers of neuron layers connected one by one. For example, the input layer includes the first layer of neuron layers, the hidden layer includes the second layer of neuron layers, and the output layer includes the third layer of neuron layers. For example, the input layer transmits the received input data to the hidden layer, the hidden layer performs calculation and conversion on the input data and sends it to the output layer, and the output layer outputs the output structure of the Bayesian neural network.

[0057] As shown in Figure 2D As shown in the figure, the input layer, the hidden layer, and the output layer each include a plurality of neuron nodes, and the number of neuron nodes in each layer can be set according to different application situations. For example, the number of neurons in the input layer is 2 (including N1 and N2), the number of neurons in the intermediate hidden layer is 3 (including N3, N4, and N5), and the number of neurons in the output layer is 1 (including N6).

[0058] As shown in the right side of FIG. 1, the neurons in two adjacent layers of the Bayesian neural network are connected through a weight matrix. For example, the weight matrix is implemented by a memristor array as shown in the right side of FIG. 2. For example, the weight parameters can be directly programmed as the conductance of the memristor array. For example, the weight parameters can also be mapped to the conductance of the memristor array according to a certain rule. For example, the difference between the conductance of two memristors can also represent a weight parameter. Although the technical solutions of the present disclosure are described in the way of directly programming the weight parameters as the conductance of the memristor array or mapping the weight parameters to the conductance of the memristor array according to a certain rule, it is only exemplary and not a limitation of the present disclosure. Figure 2D Figure 2D As shown in the right side of FIG. 1, the neurons in two adjacent layers of the Bayesian neural network are connected through a weight matrix. For example, the weight matrix is implemented by a memristor array as shown in the right side of FIG. 2. For example, the weight parameters can be directly programmed as the conductance of the memristor array. For example, the weight parameters can also be mapped to the conductance of the memristor array according to a certain rule. For example, the difference between the conductance of two memristors can also represent a weight parameter. Although the technical solutions of the present disclosure are described in the way of directly programming the weight parameters as the conductance of the memristor array or mapping the weight parameters to the conductance of the memristor array according to a certain rule, it is only exemplary and not a limitation of the present disclosure.

[0059] Figure 2A As shown in the right side of FIG. 1, the neurons in two adjacent layers of the Bayesian neural network are connected through a weight matrix. For example, the weight matrix is implemented by a memristor array as shown in the right side of FIG. 2. For example, the weight parameters can be directly programmed as the conductance of the memristor array. For example, the weight parameters can also be mapped to the conductance of the memristor array according to a certain rule. For example, the difference between the conductance of two memristors can also represent a weight parameter. Although the technical solutions of the present disclosure are described in the way of directly programming the weight parameters as the conductance of the memristor array or mapping the weight parameters to the conductance of the memristor array according to a certain rule, it is only exemplary and not a limitation of the present disclosure. Figure 3 As shown in the right side of FIG. 1, the neurons in two adjacent layers of the Bayesian neural network are connected through a weight matrix. For example, the weight matrix is implemented by a memristor array as shown in the right side of FIG. 2. For example, the weight parameters can be directly programmed as the conductance of the memristor array. For example, the weight parameters can also be mapped to the conductance of the memristor array according to a certain rule. For example, the difference between the conductance of two memristors can also represent a weight parameter. Although the technical solutions of the present disclosure are described in the way of directly programming the weight parameters as the conductance of the memristor array or mapping the weight parameters to the conductance of the memristor array according to a certain rule, it is only exemplary and not a limitation of the present disclosure. 11 12 13

[0060] Step S103: input the current state feature vector and the hidden input variable corresponding to the dynamic system as input signals to the weight-mapped memristor array, process the current state feature vector and the hidden input variable according to the Bayesian neural network through the memristor array, and obtain an output signal corresponding to the processing result from the memristor array, wherein the output signal is used to obtain the prediction result of the next state of the dynamic system.

[0061] For example, in some embodiments of the present disclosure, the processing according to the Bayesian neural network through the memristor array can be expressed as y=f(x,z,W,ε), wherein x is the current state feature vector of the dynamic system, z is the hidden input variable, W is the weight matrix of the Bayesian neural network, ε is the additive noise corresponding to the memristor array, and y is the prediction result of the next state of the dynamic system; wherein the hidden input variable z satisfies the first distribution z~p(z), the weight matrix W of the Bayesian neural network satisfies the second distribution W~q(W), and the additive noise ε is additive Gaussian noise ε~N(0,σ 2 ).

[0062] The architecture of BNN+LV based on the memristor array corresponding to the above data processing method can be shown in FIG. 3.​​​​ Figure 3 As shown in the image. Figure 2B As shown, the current state feature vector x and the hidden input variable z are used as the inputs of the Bayesian neural network based on the memristor array. The memristor array processes x and z according to the Bayesian neural network to obtain the output y, which is the prediction result of the next state of the dynamic system.

[0063] Traditional Bayesian neural networks first sample all the weights of a layer to obtain a weight sample value matrix during prediction calculation. Then, the input vector is multiplied by this weight sample value matrix to obtain the prediction result. This method consumes a lot of power and is slow.

[0064] In some embodiments of this disclosure, for memristor arrays, the input signal is a voltage signal, the output signal is a current signal, the output signal is read, and the output signal is converted from analog to digital for subsequent processing. For example, the input sequence is applied to the BL (Bit-line) as voltage pulses, and then the output current flowing from the SL (Source-line) is acquired for further calculations. For example, for such... Figure 4 Or, as shown in 2C, the memristor device can convert the input sequence into an analog voltage signal via a DAC, which is then applied to BL via a multiplexer. The output current is obtained from SL, which is converted into a voltage signal by a transimpedance amplifier, and then into a digital signal by an ADC. This digital signal can be used for subsequent processing. When reading the current from N memristors and N is large, the total output current exhibits a Gaussian distribution. The total output current of all voltage pulses is the result of multiplying the input vector by the weight matrix. In a cross-array memristor, such a parallel read operation is equivalent to performing both sampling and vector-matrix multiplication.

[0065] According to the memristor-based data processing method proposed in this disclosure, the weight matrix of the Bayesian neural network is mapped to the memristor array. The memristor array is used to implement distributed sampling and matrix-vector multiplication, and the intrinsic noise of the memristor array during reading is used to sample random variables. BNN+LV is implemented through a memristor cross array. The dynamic system is modeled using BNN+LV based on the memristor array. It has low power consumption, fast calculation speed, and high computational energy efficiency.

[0066] Since the read operation of a simulated memristor cross array is a continuous sampling process, the sampling weight values ​​of the memristor-based BNN+LV have a one-time characteristic. Therefore, by modeling the dynamic system using a memristor array-based BNN+LV, the uncertainty of the data processing method proposed in this embodiment can be obtained.

[0067] For example, in some embodiments of the present disclosure, the obtaining the uncertainty of the data processing method can comprise: obtaining a chance uncertainty of the data processing method, and obtaining a cognitive uncertainty of the data processing method, wherein the chance uncertainty is caused by the hidden input variable, and the cognitive uncertainty is caused by the intrinsic noise of the memristor array.

[0068] For example, the uncertainty of the data processing method is the chance uncertainty plus the cognitive uncertainty.

[0069] Figure 4 A schematic flowchart of a method for obtaining the uncertainty of a data processing method is shown.

[0070] As Figure 5 shown, the method comprises the following steps S401-S403.

[0071] Step S401: obtaining an initial state s t-1 corresponding to a t-1 moment corresponding to uniform sampling of a dynamic system.

[0072] According to the Monte Carlo sampling method, the initial state s t-1 corresponding to the t-1 moment can be uniformly sampled from the data set of the dynamic system.

[0073] Step S402: obtaining a predicted state s t corresponding to a t moment after the t-1 moment by using the memristor array and based on the hidden input variable, and obtaining an MxN matrix of the cost c t corresponding to the predicted state s t , wherein s t =f(s t-1 ,z,W,ε).

[0074] For example, in some embodiments of the present disclosure, step S402 can comprise: sampling M times from the p(z) distribution to obtain M samples {z1, z2, …, z m ,…,z M} of the hidden input variable z; for each of the M samples, inputting the hidden input variable z m and the initial state s t-1 to the weight-mapped memristor array to obtain N predicted states s t , obtaining an MxN matrix of the predicted states s t from the M samples, wherein 1≤m≤M; for each element in the MxN matrix of the predicted states s t , calculating the cost c t =c(s t ) to obtain an MxN matrix of the cost c t .

[0075] For example, first sample the latent input variable z from the p(z) distribution M times, then sample the state feature vector s at time t-1. t-1 One of the M hidden input variables is applied to BL with a READ voltage pulse, and then the output current flowing out of SL is sampled for further calculation. With N columns in the memristor array, N predicted states s can be obtained. t By performing the above operation on all M hidden input variables, we can obtain M×N predicted states s. t For each s t The cost c can be obtained by performing cost calculation. t An M×N matrix.

[0076] Figure 5 A schematic diagram of a method for obtaining a predicted state matrix provided in at least one embodiment of the present disclosure is shown.

[0077] like Figure 6 As shown, a dataset {x,y} for a dynamic system used in a Bayesian neural network is provided, where x represents the state feature vector of the dynamic system (e.g., the state feature vector at time t-1), and y represents the next predicted state of the dynamic system (e.g., the predicted state at time t after t-1). M samples are taken M times from a p(z) distribution (e.g., a Gaussian or Laplace distribution) for the latent input variable z. Each time, one of the M samples and the state feature vector x are input into a weighted memristor array. The output current of the memristor array is further calculated to obtain a dataset {x',y'} of N predicted states for each z sample. y' is the calculated next predicted state. The M×N matrix of the next predicted state y' is obtained from the M samples of the latent input variable z.

[0078] Step S403: Based on the cost c t The method for calculating M×N matrix data processing is applicable to the uncertainty of dynamic systems, where M and N are both integers greater than 1.

[0079] For example, in some embodiments of this disclosure, the uncertainty of the dynamic system at time t is expressed as:

[0080]

[0081] in, It is a matter of chance and uncertainty, and E p(z) [σ 2 (c t |z)] represents cognitive uncertainty.

[0082] For example, in some embodiments of this disclosure, for the predicted state s t An M×N matrix, through determining an accidental uncertainty; and t an M x N matrix of determining a cognitive uncertainty.

[0083] an M x N matrix of t for the predicted state s can be expressed as:

[0084]

[0085] E p(z) [σ 2 (c t |z)] can be expressed as:

[0086]

[0087] The flow of obtaining the M x N matrix of t is as follows:

[0088] Input: initial policy given a dynamic environment model based on memristor array

[0089] Sample {z1, z2,..., z m ,..., z M} from p(z) for M times

[0090] Sample {ε1, ε2,..., ε 2 ,..., ε m} from N(0, σ M ) for M times

[0091] m = 1 to M, loop

[0092] n = 1 to N, loop

[0093] Sample W from q(W) based on memristor BNN

[0094] s t = f(s t-1 ; z m , W, ε m )

[0095] c t = c(s t )

[0096] End the loop of n

[0097] End the loop of m

[0098] Output: M x N matrix of cost c t

[0099] ​ Figure 1 A schematic block diagram of a data processing apparatus 600 is shown, which can be used to execute Figure 6 the data processing method shown.

[0100] As shown in the data processing apparatus 600 includes an acquisition unit 601, an array apparatus 602 and a control unit 603. Figure 1

[0101] The acquisition unit 601 is configured to acquire a Bayesian neural network, wherein the Bayesian neural network has a trained weight matrix.

[0102] The array apparatus 602 includes a memristor array, and is configured to map a plurality of corresponding target conductance values obtained according to the weight matrix of the Bayesian neural network into the memristor array.

[0103] The control unit 603 is configured to input a current state feature vector and a hidden input variable corresponding to a dynamic system as input signals to the weight-mapped memristor array, process the current state feature vector and the hidden input variable according to the Bayesian neural network through the memristor array, and obtain an output signal as a processing result from the memristor array, wherein the output signal is used to obtain a prediction result of a next state of the dynamic system.

[0104] For example, the data processing apparatus 600 can be implemented by hardware, software, firmware and any feasible combination thereof, and the present disclosure does not limit this.

[0105] The technical effects of the data processing apparatus described above are the same as those of the data processing method shown, and will not be repeated here. ​

[0106] The following points need to be explained:

[0107] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can refer to the usual design.

[0108] (2) In the case of no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0109] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be subject to the protection scope of the claims.​​< / m> < / n> < / m>

Claims

1. A data processing method based on a memristor array, comprising: Obtain a Bayesian neural network, wherein the Bayesian neural network has a trained weight matrix; Multiple target conductance values ​​are obtained based on the weight matrix of the Bayesian neural network, and these multiple target conductance values ​​are mapped onto the memristor array. The current state feature vector and latent input variables corresponding to the dynamic system are input as input signals to the weighted memristor array. The current state feature vector and latent input variables are processed by the memristor array according to the Bayesian neural network. The output signal corresponding to the processing result is obtained from the memristor array. The output signal is used to obtain the prediction result of the next state of the dynamic system. The memristor array, processed according to the Bayesian neural network, is expressed as y = f(x,z,W,ε). Where x is the current state feature vector of the dynamic system, z is the hidden input variable, W is the weight matrix of the Bayesian neural network, ε is the additive noise corresponding to the memristor array, and y is the prediction result of the next state of the dynamic system. Wherein, the latent input variable z satisfies the first distribution z~p(z), the weight matrix W of the Bayesian neural network satisfies the second distribution W~q(W), and the additive noise ε is additive Gaussian noise ε~N(0,σ) 2 ); The method further includes: obtaining the uncertainty of the data processing method.

2. The data processing method according to claim 1, wherein, The uncertainty of the data processing method includes: The random uncertainty of the data processing method is obtained, and The cognitive uncertainty of the data processing method is obtained. The random uncertainty is caused by the hidden input variable, and the cognitive uncertainty is caused by the intrinsic noise of the memristor array.

3. The data processing method according to claim 1, wherein, The uncertainty of the data processing method includes: Obtain the initial state s corresponding to time t-1 of the uniformly sampled dynamic system. t-1 ; Using the memristor array and based on the hidden input variables, the predicted state s corresponding to time t after t-1 is obtained. t And obtain the corresponding predicted state s t The cost c t An M×N matrix, where s t =f(s) t-1 ,z,W,ε); and According to the cost c t The uncertainty of the data processing method for the dynamic system is calculated using an M×N matrix, where M and N are both integers greater than 1.

4. The data processing method according to claim 3, wherein, The predicted state s corresponding to time t is obtained using the memristor array and based on the hidden input variable. t And obtain the corresponding predicted state s t The cost c t An M×N matrix includes: M samples {z1, z2, ..., z3} are obtained by sampling the latent input variable z from the p(z) distribution M times. m ,…,z M }; For each of the M samples, the latent input variable z m and the initial state s t-1 The input to the weighted memristor array yields N predicted states s. t The predicted state s is obtained from the M samples. t An M×N matrix, where 1≤m≤M; For the predicted state s t For each element in the M×N matrix, calculate the cost c. t =c(s) t ), thus obtaining the cost c t An M×N matrix.

5. The data processing method according to claim 4, wherein, At time t, the uncertainty of the dynamic system is expressed as: in, It is a matter of chance and uncertainty, and E p(z) [σ 2 (c t |z)] represents cognitive uncertainty.

6. The data processing method according to claim 5, wherein, For the predicted state s t An M×N matrix, through Determine the aforementioned random uncertainty; as well as For the predicted state s t An M×N matrix, through The cognitive uncertainty is determined.

7. The data processing method according to claim 1, wherein, The Bayesian neural network includes a fully connected structure or a convolutional neural network structure.

8. The data processing method according to claim 1, wherein, For the memristor array, the input signal is a voltage signal, and the output signal is a current signal. The output signal is read and converted from analog to digital for subsequent processing.

9. A data processing apparatus, comprising: The acquisition unit is configured to acquire a Bayesian neural network, wherein the Bayesian neural network has a trained weight matrix; An array device, including a memristor array, is configured to map a plurality of target conductance values ​​obtained according to the weight matrix of the Bayesian neural network onto the memristor array. The control unit is configured to input the current state feature vector and latent input variables corresponding to the dynamic system as input signals to the weighted memristor array, process the current state feature vector and latent input variables through the memristor array according to the Bayesian neural network, and obtain the output signal as the processing result from the memristor array. The output signal is used to obtain the prediction result of the next state of the dynamic system; The control unit is further configured to process the data through the memristor array according to the Bayesian neural network, expressing it as y = f(x,z,W,ε). Where x is the current state feature vector of the dynamic system, z is the hidden input variable, W is the weight matrix of the Bayesian neural network, ε is the additive noise corresponding to the memristor array, and y is the prediction result of the next state of the dynamic system. Wherein, the latent input variable z satisfies the first distribution z~p(z), the weight matrix W of the Bayesian neural network satisfies the second distribution W~q(W), and the additive noise ε is additive Gaussian noise ε~N(0,σ) 2 ); The data processing device is further configured to acquire the uncertainty of the data processing method.

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