A gallium oxide diode device and its preparation method

Abstract

This application applies to the field of semiconductor device manufacturing technology and provides a gallium oxide diode device and a method for fabricating the same. The method comprises: preparing a dielectric mask layer with a preset pattern on a gallium oxide epitaxial layer; rotating the gallium oxide substrate in two opposite directions at a first tilt angle and a second tilt angle, respectively, with a horizontal plane as a reference, and etching the gallium oxide epitaxial layer covered by the dielectric mask layer, wherein the first tilt angle and the second tilt angle are both less than 90°; preparing a polyimide layer with a preset shape on the gallium oxide epitaxial layer and the dielectric mask layer; removing the dielectric mask layer, and forming a NiO layer on the upper surface of the gallium oxide epitaxial layer in an area corresponding to the dielectric mask layer and in an area of the polyimide layer near the dielectric mask layer; forming a first electrode layer on the NiO layer; and forming a second electrode layer on the lower surface of the gallium oxide substrate. This application can easily achieve a gallium oxide positive-angle ground terminal structure, thereby improving the device's voltage resistance.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor device manufacturing technology, and in particular relates to a gallium oxide diode device and a preparation method thereof. Background Art

[0002] Ultra-wide bandgap power electronics, exemplified by gallium oxide (GaO), have emerged as a key development area for power semiconductors in recent years, poised to replace traditional silicon-based power devices in certain applications. However, the image-induced barrier lowering effect is a bottleneck limiting the performance of GaO Schottky diodes. Due to the significant difficulty of P-type implantation in GaO, the demanding dielectric quality requirements of the field plate structure, and dielectric reliability issues, the development of novel terminal structures is imperative.

[0003] Grinded termination is a key technology for improving the performance of power diodes. Conventional fabrication methods involve first creating a P-type layer through implantation or epitaxy, followed by a small-angle tilted etching process to achieve the ground termination. However, gallium oxide lacks P-type doping technology, making it impossible to create the P-type layer and then use etching to achieve the ground termination. Therefore, new fabrication techniques are urgently needed to achieve a gallium oxide ground termination structure, particularly a positive ground termination, to improve device voltage resistance. Summary of the Invention

[0004] To overcome the problems existing in the related art, the embodiments of the present application provide a gallium oxide diode device and a preparation method thereof, which can easily realize a gallium oxide positive-grinding terminal structure and effectively improve the voltage resistance of the diode device.

[0005] This application is achieved through the following technical solutions:

[0006] In a first aspect, an embodiment of the present application provides a method for preparing a gallium oxide diode device, comprising:

[0007] preparing a dielectric mask layer with a preset pattern on the gallium oxide epitaxial layer, wherein a portion of the gallium oxide epitaxial layer is not covered by the dielectric mask layer; the gallium oxide epitaxial layer is formed on the upper surface of the gallium oxide substrate;

[0008] With a horizontal plane as a reference, rotating the gallium oxide substrate in two opposite directions by a first tilt angle and a second tilt angle, respectively, to etch the gallium oxide epitaxial layer covered by the dielectric mask layer, wherein the first tilt angle and the second tilt angle are both less than 90°;

[0009] preparing a polyimide layer of a preset shape on the gallium oxide epitaxial layer and the dielectric mask layer, wherein a portion of the dielectric mask layer is not covered by the polyimide layer;

[0010] removing the dielectric mask layer, and forming a NiO layer on the upper surface of the gallium oxide epitaxial layer in an area corresponding to the dielectric mask layer and in an area on the polyimide layer close to the dielectric mask layer;

[0011] forming a first electrode layer on the NiO layer;

[0012] A second electrode layer is formed on the lower surface of the gallium oxide substrate.

[0013] In a possible implementation of the first aspect, preparing a dielectric mask layer with a preset pattern on the gallium oxide epitaxial layer includes:

[0014] preparing a dielectric mask layer on the gallium oxide epitaxial layer;

[0015] preparing a first photoresist layer on the dielectric mask layer;

[0016] Etching the first photoresist layer to expose a portion of the dielectric mask layer;

[0017] preparing a metal mask layer on the first photoresist layer and the dielectric mask layer;

[0018] Stripping the metal mask layer on the first photoresist layer and removing the first photoresist layer to form a metal mask layer with a preset pattern;

[0019] The exposed portion of the dielectric mask layer is etched to form the dielectric mask layer of the preset pattern.

[0020] In a possible implementation manner of the first aspect, the first inclination angle and the second inclination angle are both in a range of 30° to 60°.

[0021] In a possible implementation manner of the first aspect, the first inclination angle is equal to the second inclination angle.

[0022] In a possible implementation of the first aspect, preparing a polyimide layer of a preset shape on the gallium oxide epitaxial layer and the dielectric mask layer includes:

[0023] Before preparing the polyimide layer of a preset shape, the metal mask layer of the preset pattern on the dielectric mask layer is first removed.

[0024] Preparing a polyimide layer of a preset shape on the gallium oxide epitaxial layer and the dielectric mask layer, comprising:

[0025] Spin-coating polyimide on the surface of the gallium oxide epitaxial wafer and the dielectric mask layer;

[0026] etching the polyimide to expose the dielectric mask layer;

[0027] The polyimide is cured at high temperature to form a polyimide layer with a preset shape.

[0028] In a possible implementation of the first aspect, forming a NiO layer in a region corresponding to the dielectric mask layer on the gallium oxide epitaxial layer and at an edge of the upper surface of the polyimide layer includes:

[0029] forming a second photoresist layer at an edge of the upper surface of the polyimide layer so that a portion of the upper surface of the polyimide layer is exposed;

[0030] forming the NiO layer on the exposed upper surface of the polyimide layer and the gallium oxide epitaxial layer;

[0031] The second photoresist layer is removed.

[0032] In a possible implementation manner of the first aspect, the NiO layer is filled in a self-aligned manner.

[0033] In a possible implementation of the first aspect, the gallium oxide substrate is an N-type highly doped gallium oxide substrate;

[0034] The gallium oxide epitaxial wafer is an N-type low-doped gallium oxide epitaxial wafer

[0035] In a second aspect, an embodiment of the present application provides a gallium oxide diode device, comprising the gallium oxide diode device prepared by the method according to any one of claims 1 to 9.

[0036] It can be understood that the beneficial effects of the second aspect mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here.

[0037] Compared with the prior art, the embodiments of the present application have the following beneficial effects:

[0038] In an embodiment of the present application, the gallium oxide substrate is rotated in two opposite directions, the gallium oxide epitaxial layer is etched, and then a NiO layer is prepared. The NiO layer is used to replace the doped gallium oxide to form a P-type layer, and finally an electrode layer is prepared. This makes it easier to achieve a gallium oxide positive-grinding angle terminal structure, effectively improving the voltage resistance of the diode device.

[0039] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0041] Figure 1 This is a schematic flow chart of a method for preparing a gallium oxide diode device provided in one embodiment of the present application;

[0042] Figure 2 1 is a schematic structural diagram of a dielectric mask layer for preparing a preset pattern provided in one embodiment of the present application;

[0043] Figure 3 This is a schematic structural diagram of a gallium oxide epitaxial layer after etching provided by an embodiment of the present application;

[0044] Figure 4 This is a schematic structural diagram of a polyimide layer of a preset shape provided in one embodiment of the present application;

[0045] Figure 5 This is a schematic diagram of the structure of forming a NiO layer provided in one embodiment of the present application;

[0046] Figure 6 is a schematic structural diagram of forming a first electrode layer according to an embodiment of the present application;

[0047] Figure 7 3 is a schematic structural diagram of forming a second electrode layer provided in one embodiment of the present application. DETAILED DESCRIPTION

[0048] In the following description, specific details such as specific system structures and techniques are provided for purposes of illustration rather than limitation to facilitate a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application may be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid obscuring the description of the present application with unnecessary detail.

[0049] It should be understood that when used in the present specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections thereof.

[0050] It will also be understood that the term "and / or" used in this specification and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0051] As used in this specification and the appended claims, the term "if" can be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrase "if it is determined" or "if [described condition or event] is detected" can be interpreted as meaning "upon determination" or "in response to determining" or "upon detection of [described condition or event]" or "in response to detecting [described condition or event]," depending on the context.

[0052] In addition, in the description of the present application specification and the appended claims, the terms "first", "second", "third", etc. are only used to distinguish the descriptions and cannot be understood as indicating or implying relative importance.

[0053] References to "one embodiment" or "some embodiments" in this specification mean that a particular feature, structure, or characteristic described in conjunction with that embodiment is included in one or more embodiments of the present application. Thus, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," and "in other embodiments" appearing in various places in this specification do not necessarily refer to the same embodiment, but rather mean "one or more but not all embodiments," unless otherwise specifically emphasized. The terms "including," "comprising," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized.

[0054] Corner-grinding termination is a key technology for improving the performance of power diodes. Conventional fabrication methods involve first creating a P-type layer through implantation or epitaxy, followed by low-angle tilted etching to achieve the corner-grinding termination. However, gallium oxide lacks P-type doping technology, making it impossible to create the P-type layer and then use etching to achieve the corner-grinding termination. Therefore, the development of new fabrication techniques is urgently needed.

[0055] Based on the above problems, the method for preparing a gallium oxide diode device in an embodiment of the present application includes: preparing a dielectric mask layer with a preset pattern on the gallium oxide epitaxial layer; rotating the gallium oxide substrate in two opposite directions at a first tilt angle and a second tilt angle, respectively, with a horizontal plane as a reference, and etching the gallium oxide epitaxial layer covered by the dielectric mask layer, wherein the first tilt angle and the second tilt angle are both less than 90°; preparing a polyimide layer with a preset shape on the gallium oxide epitaxial layer and the dielectric mask layer; removing the dielectric mask layer, and forming a NiO layer on the upper surface of the gallium oxide epitaxial layer in an area corresponding to the dielectric mask layer and in an area of the polyimide layer near the dielectric mask layer; forming a first electrode layer on the NiO layer; and forming a second electrode layer on the lower surface of the gallium oxide substrate.

[0056] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0057] Figure 1 This is a schematic flow chart of a navigation method provided by an embodiment of the present application, with reference to Figure 1 The preparation method of the gallium oxide diode device is described in detail as follows:

[0058] In step 101 , a dielectric mask layer 3 with a preset pattern is prepared on the gallium oxide epitaxial layer 2 , and a portion of the gallium oxide epitaxial layer 2 is not covered by the dielectric mask layer 3 ; the gallium oxide epitaxial layer 2 is formed on the upper surface of the gallium oxide substrate 1 .

[0059] In one possible implementation, in step 101, a dielectric mask layer 3 with a preset pattern is prepared on the gallium oxide epitaxial layer 2, including:

[0060] Step A1, prepare a dielectric mask layer 3 on the gallium oxide epitaxial layer 2, such as Figure 2 As shown in (a);

[0061] After cleaning the gallium oxide epitaxial layer 2, a dielectric mask layer 3 is prepared on the gallium oxide epitaxial layer 2;

[0062] Exemplary cleaning may be performed using acetone, isopropyl alcohol, and deionized water in sequence.

[0063] Exemplarily, the dielectric mask layer 3 is SiO 2 or SiN, and is grown by PECVD at a temperature of 300° C.

[0064] Step A2: prepare a first photoresist layer 4 on the dielectric mask layer 3, such as Figure 2 As shown in (b);

[0065] Wherein, photoresist is spin-coated on the dielectric mask layer 3 to form a first photoresist layer 4 .

[0066] Step A3, etching the first photoresist layer 4 to expose a portion of the dielectric mask layer 3, such as Figure 2 As shown in (c);

[0067] The etching of the first photoresist layer 4 includes performing photolithography, exposure, and development on the first photoresist layer 4 to expose a portion of the dielectric mask layer 3 .

[0068] Step A4, preparing a metal mask layer 5 on the first photoresist layer 4 and the dielectric mask layer 3, such as Figure 2 As shown in (d);

[0069] Exemplarily, the metal mask layer 5 is formed by electron beam evaporation or sputtering.

[0070] Step A5, stripping the metal mask layer 5 on the first photoresist layer 4, and removing the first photoresist layer 4, as shown in FIG. Figure 2 As shown in (e) in .

[0071] For example, the etching gas may be Ar and BCl 3 , and the power may be 100W.

[0072] Step A6, etching the exposed portion of the dielectric mask layer 3 to form a dielectric mask layer 3 with a preset pattern, such as Figure 2 As shown in (f) in .

[0073] In step 102, see Figure 3 , with the horizontal plane as a reference, the gallium oxide substrate is rotated in two opposite directions by a first tilt angle θ and a second tilt angle α, respectively, and the gallium oxide epitaxial layer 2 covered by the dielectric mask layer 3 is etched, wherein the first tilt angle θ and the second tilt angle α are both less than 90°.

[0074] In some embodiments, the first tilt angle θ and the second tilt angle α may be in a range of 30° to 60°.

[0075] The first inclination angle θ is equal to the second inclination angle α.

[0076] Exemplarily, the gallium oxide substrate 1 is rotated at a first tilt angle θ, and the gallium oxide epitaxial layer 2 is etched along the etching direction A by ICP etching; the gallium oxide substrate 1 is rotated at a second tilt angle α, and the gallium oxide epitaxial layer 2 is etched along the etching direction B by ICP etching; the etching gas is SF6, Ar, BCl3, or other etching gas; the first tilt angle θ is 90°>θ>0°, and the optimal range is 60°≥θ≥30°; the second tilt angle α is 90°>α>0°, and the optimal range is 60°≥θ≥30°, α and θ can be equal or different, and the equal effect is better.

[0077] After etching the gallium oxide epitaxial layer 2 , the metal mask layer 3 is removed, and the gallium oxide epitaxial layer 2 is cleaned.

[0078] For example, the gallium oxide epitaxial layer 2 may be cleaned with acetone, isopropyl alcohol, and deionized water.

[0079] In step 103 , a polyimide layer 6 of a preset shape is prepared on the gallium oxide epitaxial layer 2 and the dielectric mask layer 3 , and a portion of the dielectric mask layer 3 is not covered by the polyimide layer 6 .

[0080] Before preparing the polyimide layer 6 of a preset shape, the metal mask layer 5 on the dielectric mask layer 3 is first removed.

[0081] In one possible implementation, see Figure 4 In step 103, a polyimide layer 6 of a preset shape is prepared on the gallium oxide epitaxial layer 2 and the dielectric mask layer 3, including: spin coating polyimide on the surface of the gallium oxide epitaxial wafer 2 and the dielectric mask layer 3; etching the polyimide to expose the dielectric mask layer 3; and high-temperature curing the polyimide to form the polyimide layer 6 of the preset shape.

[0082] The etching of the polyimide includes: performing photolithography, exposure, and development on the polyimide to expose the dielectric mask layer 3 .

[0083] For example, the high temperature curing of polyimide may be 300° C., in a nitrogen atmosphere, and for half an hour.

[0084] In step 104 , the dielectric mask layer 3 is removed, and a NiO layer 8 is formed on the gallium oxide epitaxial layer 2 in the region corresponding to the dielectric mask layer 3 and on the upper surface of the polyimide layer 6 near the region corresponding to the dielectric mask layer 3 .

[0085] Exemplarily, step 104 may include:

[0086] Step B1, removing the dielectric mask layer 3, such as Figure 5 As shown in (a);

[0087] The dielectric mask layer 3 is removed by wet etching.

[0088] For example, the wet etching may be HF acid ultrasonic removal for 5 minutes.

[0089] Step B2: forming a second photoresist layer 7 at the edge of the upper surface of the polyimide layer 6 so that part of the upper surface of the polyimide layer 6 is exposed. Figure 5 As shown in (b) in .

[0090] Step B3, prepare a NiO layer 8 on the exposed upper surface of the polyimide layer 6 and the gallium oxide epitaxial layer 2, as shown in FIG. Figure 5 As shown in (c);

[0091] The NiO layer 8 can be formed by filling in a self-aligned manner, and the second photoresist layer 7 can be removed;

[0092] The thickness of the NiO layer 8 may be equal to or different from the thickness of the removed dielectric mask layer 3 region.

[0093] For example, when NiO is filled in a self-aligned manner, the target material purity may be 99.99% and the sputtering power may be 150W.

[0094] In step 105, see Figure 6 , a first electrode layer 9 is formed on the NiO layer 8 .

[0095] Among them, the first electrode layer 9 is the anode layer; photoresist is spin-coated on the entire upper surface, and the anode metal pattern area is photolithographically, exposed, and developed. The anode metal is evaporated by electron beam, and the excess metal is stripped off and then cleaned to form the anode layer.

[0096] Exemplarily, the material of the first electrode layer 9 may be Ni or Au. When the material of the first electrode layer 9 is Ni, the thickness of the first electrode layer 9 may be 50 nm; when the material of the first electrode layer 9 is Au, the thickness of the first electrode layer 9 may be 400 nm.

[0097] In step 106, see Figure 7 , a second electrode layer 10 is formed on the lower surface of the gallium oxide substrate 1 .

[0098] The second electrode layer 10 is a cathode layer; the cathode layer is formed by electron beam evaporation of anode metal.

[0099] For example, the second electrode layer 10 may be made of Ti or Au. When the second electrode layer 10 is made of Ti, the thickness of the second electrode layer 10 may be 20 nm; when the second electrode layer 10 is made of Au, the thickness of the second electrode layer 10 may be 400 nm.

[0100] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0101] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A method for preparing a gallium oxide diode device, characterized in that: include: preparing a dielectric mask layer with a preset pattern on the gallium oxide epitaxial layer, wherein a portion of the gallium oxide epitaxial layer is not covered by the dielectric mask layer; The gallium oxide epitaxial layer is formed on the upper surface of the gallium oxide substrate; With a horizontal plane as a reference, rotating the gallium oxide substrate in two opposite directions by a first tilt angle and a second tilt angle, respectively, to etch the gallium oxide epitaxial layer covered by the dielectric mask layer, wherein the first tilt angle and the second tilt angle are both less than 90°; preparing a polyimide layer of a preset shape on the gallium oxide epitaxial layer and the dielectric mask layer, wherein a portion of the dielectric mask layer is not covered by the polyimide layer; removing the dielectric mask layer, and forming a NiO layer on the upper surface of the gallium oxide epitaxial layer in an area corresponding to the dielectric mask layer and in an area on the polyimide layer close to the dielectric mask layer; forming a first electrode layer on the NiO layer; A second electrode layer is formed on the lower surface of the gallium oxide substrate.

2. The method for preparing a gallium oxide diode device according to claim 1, wherein: The method of preparing a dielectric mask layer with a preset pattern on the gallium oxide epitaxial layer includes: preparing a dielectric mask layer on the gallium oxide epitaxial layer; preparing a first photoresist layer on the dielectric mask layer; Etching the first photoresist layer to expose a portion of the dielectric mask layer; preparing a metal mask layer on the first photoresist layer and the dielectric mask layer; peeling off a portion of the metal mask layer on the first photoresist layer and removing the first photoresist layer to form a metal mask layer with a preset pattern; The exposed portion of the dielectric mask layer is etched to form the dielectric mask layer of the preset pattern.

3. The method for preparing a gallium oxide diode device according to claim 1, wherein: The first tilt angle and the second tilt angle are both in the range of 30° to 60°.

4. The method for preparing a gallium oxide diode device according to claim 1 or 3, wherein: The first inclination angle is equal to the second inclination angle.

5. The method for preparing a gallium oxide diode device according to claim 1, wherein: The step of preparing a polyimide layer of a preset shape on the gallium oxide epitaxial layer and the dielectric mask layer comprises: Before preparing the polyimide layer of a preset shape, the metal mask layer of the preset pattern on the dielectric mask layer is first removed.

6. The method for preparing a gallium oxide diode device according to claim 1, wherein: Preparing a polyimide layer of a preset shape on the gallium oxide epitaxial layer and the dielectric mask layer, comprising: Spin-coating polyimide on the surface of the gallium oxide epitaxial wafer and the dielectric mask layer; etching the polyimide to expose the dielectric mask layer; The polyimide is cured at high temperature to form a polyimide layer with a preset shape.

7. The method for preparing a gallium oxide diode device according to claim 1, wherein: The method comprises forming a NiO layer in an area corresponding to the dielectric mask layer on the gallium oxide epitaxial layer and at an edge of the upper surface of the polyimide layer, comprising: forming a second photoresist layer at an edge of the upper surface of the polyimide layer so that a portion of the upper surface of the polyimide layer is exposed; forming the NiO layer on the exposed upper surface of the polyimide layer and the gallium oxide epitaxial layer; The second photoresist layer is removed.

8. The method for preparing a gallium oxide diode device according to claim 5, wherein: The NiO layer is filled in a self-aligned manner.

9. The method for preparing a gallium oxide diode device according to claim 1, wherein: The gallium oxide substrate is an N-type highly doped gallium oxide substrate; The gallium oxide epitaxial wafer is an N-type low-doped gallium oxide epitaxial wafer.

10. A gallium oxide diode device, characterized in that: The gallium oxide diode device is prepared by the method according to any one of claims 1 to 9.

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