Method for manufacturing gallium oxide field effect transistor

Abstract

The application provides a preparation method of a gallium oxide field effect transistor, which comprises the following steps: providing a substrate; epitaxially growing an n-type gallium oxide channel layer on the substrate; depositing a source electrode and a drain electrode on both ends of the n-type gallium oxide channel layer respectively; preparing a photoetching mask pattern in a preset channel region of the n-type gallium oxide channel layer; etching the n-type gallium oxide channel layer to obtain a plurality of discontinuous etching pits, and forming a fin-shaped mesa on the n-type gallium oxide channel layer by two side walls of adjacent etching pits close to each other; the two side walls of the fin-shaped mesa extend from the source electrode side to the drain electrode side in a way of moving away from each other; performing a thermal oxygen annealing treatment on the fin-shaped mesa region by using a dielectric protection; and depositing a gate electrode on the upper surface and the two side walls of the fin-shaped mesa and the n-type gallium oxide channel layer close to the source electrode. The application prepares an inclined Fin channel, so that the gate electrode has a higher surface area to volume ratio and has a better gate control capability, thereby improving the breakdown characteristics of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a preparation method of a gallium oxide field effect transistor. BACKGROUND

[0002] In recent years, super-wide bandgap power electronic devices represented by gallium oxide have gradually become an important development field of power semiconductor devices, and are expected to replace traditional Si-based power devices in certain specific fields. As a new semiconductor material, super-wide bandgap gallium oxide has outstanding advantages in breakdown field strength, Baliga figure of merit, and cost. The Baliga figure of merit is usually used internationally to represent the degree to which a material is suitable for a power device. The Baliga figure of merit of β-Ga2O3 material is 4 times that of GaN material, 10 times that of SiC material, and 3444 times that of Si material. Under the same withstand voltage, the β-Ga2O3 power device has lower on-resistance and lower power consumption, which can greatly reduce the electrical energy loss of the device during operation.

[0003] In 2016, NICT used Al2O3 as a gate dielectric and combined a gate field plate structure to prepare a Ga2O3 MOSFET device with a breakdown voltage of 750V. In 2019, ETRI used a source field plate structure, and during the test process, the device was isolated from air breakdown by a fluorinated liquid, and the device had a breakdown voltage of 2320V. In 2020, Buffalo University used SU-8 photoresist passivation, and the device had a breakdown voltage of 8000V.

[0004] However, the breakdown voltage and on-state characteristics of the Ga2O3 field effect transistor (FET) devices reported so far are still far lower than the expected values of the material. How to further improve the breakdown characteristics of the device has become a problem that needs to be solved. SUMMARY

[0005] The embodiment of the present application provides a preparation method of a gallium oxide field effect transistor to solve the problem of poor breakdown characteristics of the Ga2O3 field effect transistor.

[0006] In a first aspect, the embodiment of the present application provides a preparation method of a gallium oxide field effect transistor, comprising:

[0007] providing a substrate;

[0008] epitaxially growing an n-type gallium oxide channel layer on the substrate;

[0009] depositing a source electrode and a drain electrode at both ends of the n-type gallium oxide channel layer, respectively;

[0010] preparing a photoresist pattern in a preset channel region of the n-type gallium oxide channel layer;

[0011] The n-type gallium oxide channel layer is etched to obtain a plurality of discontinuous etching pits, and two side walls of adjacent etching pits close to each other form a fin-shaped mesa on the n-type gallium oxide channel layer; the two side walls of the fin-shaped mesa extend from the source electrode side to the drain electrode side in a manner of moving away from each other;

[0012] A dielectric layer is prepared on the n-type gallium oxide channel layer, and the dielectric layer avoids the preset channel region; the preset channel region is subjected to thermal oxidation treatment, and after the thermal oxidation treatment, the dielectric layer is removed;

[0013] A gate electrode is deposited on the upper surface and the two side walls of the fin-shaped mesa and the n-type gallium oxide channel layer close to the source electrode.

[0014] In a possible implementation, before the gate electrode is deposited on the upper surface and the two side walls of the fin-shaped mesa and the n-type gallium oxide channel layer close to the source electrode, the method further includes:

[0015] A gate dielectric layer is deposited in a target sub-region on the n-type gallium oxide channel layer; wherein the target sub-region is only a region in which the gate electrode is deposited on the upper surface and the two side walls of the fin-shaped mesa and the n-type gallium oxide channel layer close to the source electrode.

[0016] In a possible implementation, before the gate electrode is deposited on the upper surface and the two side walls of the fin-shaped mesa and the n-type gallium oxide channel layer close to the source electrode, the method further includes:

[0017] A gate dielectric layer is deposited on the n-type gallium oxide channel layer, and the gate dielectric layer avoids the source electrode and the drain electrode.

[0018] For example, the dielectric layer is SiO2 or SiN x ; the thermal oxidation treatment is an annealing treatment in an oxygen atmosphere.

[0019] In a possible implementation, the gate dielectric layer is one or more of p-type dielectric, Al2O3, HfO2 or SiO2.

[0020] In a possible implementation, the n-type gallium oxide channel layer is epitaxially grown on the substrate, including:

[0021] An undoped gallium oxide layer is grown on the substrate;

[0022] The n-type doped gallium oxide channel layer is epitaxially grown on the undoped gallium oxide layer.

[0023] In a possible implementation, a top view of the etching pit on the n-type gallium oxide channel layer is isosceles trapezoidal, wherein one side close to the source electrode side is a lower base, and one side close to the drain electrode side is an upper base.

[0024] Exemplarily, the included angle between the oblique side of the isosceles trapezoid and the lower base is greater than or equal to 5 degrees and less than or equal to 85 degrees.

[0025] Exemplarily, the length of the lower base is 20 nm-4000 nm, and the length of the upper base is 10 nm-2000 nm.

[0026] The preparation method of the gallium oxide field effect transistor provided by the embodiment of the present application first epitaxially grows an n-type gallium oxide channel layer on a substrate, and deposits a source electrode and a drain electrode at two ends of the n-type gallium oxide channel layer; then, after a photoetching mask pattern is prepared in a preset channel region of the n-type gallium oxide channel layer, the n-type gallium oxide channel layer is etched to obtain a plurality of discontinuous etching pits, and two side walls of adjacent etching pits close to each other form a fin-shaped mesa on the n-type gallium oxide channel layer, wherein the two side walls of the fin-shaped mesa extend from the source electrode side to the drain electrode side in a manner of moving away from each other. Finally, a gate electrode is deposited on the upper surface and the two side walls of the fin-shaped mesa and the n-type gallium oxide channel layer close to the source electrode. Thus, an inclined Fin channel is prepared. And the gate electrode prepared on the fin-shaped mesa has different heights in the vertical direction, thereby forming a three-dimensional gate electrode.

[0027] Since the conventional right-angle gate electrode has a sharp peak electric field below the end point close to the drain, the breakdown of the device often occurs in this area. The gate electrode prepared by the preparation method provided by the present application has a higher surface area to volume ratio, thus having a better gate control capability, thereby adjusting the threshold voltage of the device to make the threshold voltage positively shift. The three-dimensional gate electrode also functions as a field plate, which can make the electric field distribution of the device more uniform, thereby reducing the peak field strength of the device, and the breakdown characteristics of the device can be further improved. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0029] Figures 1-6 is a partial process schematic diagram of the preparation method of the gallium oxide field effect transistor provided by the embodiment of the present application;

[0030] Figure 7 is a structural schematic diagram of the gallium oxide field effect transistor prepared by the method provided by the embodiment of the present application;

[0031] Figure 8 is a structural schematic diagram of the gallium oxide field effect transistor prepared by another method provided by the embodiment of the present application. DETAILED DESCRIPTION

[0032] In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular architectures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known methods, devices, circuits, and

[0033] In order to make the objects, technical solutions and advantages of the present application clearer, the following will be described with specific embodiments in conjunction with the accompanying drawings.

[0034] Fin Field-Effect Transistor (FinFET) is a new complementary metal-oxide-semiconductor transistor. Fin is the meaning of fish fin, and the naming of FinFET is based on the similarity between the shape of the transistor and the fish fin.

[0035] With the continuous expansion of field effect transistors, FinFET has become a research hotspot. The main advantage of the FinFET device structure is its superior electrostatic integrity, but to a large extent, it depends on the channel topography, and how to change the channel topography and improve the breakdown characteristics of the device has become a technical problem that needs to be solved at present.

[0036] The preparation method of the gallium oxide field effect transistor is described in detail as follows:

[0037] A preparation method of a gallium oxide field effect transistor, please refer to Figures 1-8 , comprising the following steps:

[0038] S110, providing a substrate, epitaxially growing an n-type gallium oxide channel layer on the substrate.

[0039] The substrate 10 can be a high-resistance gallium oxide substrate, a semi-insulating silicon carbide substrate, a magnesium oxide substrate or a sapphire substrate.

[0040] The n-type gallium oxide channel layer 20 can be realized by doping Si or Sn, etc., and the doping concentration is 1.0×10 15 cm -3 to 1.0×10 20 cm -3The thickness of the n-type gallium oxide channel layer 20 can be 10 nm to 1000 nm. In addition, the doping concentration of the n-type gallium oxide channel layer 20 can be gradually changed along the growth direction thereof or gradiently changed, or can be the same, which can be selected according to requirements. The doping concentration can be gradually increased or gradiently increased along the growth direction thereof, or can be gradually decreased or gradiently decreased along the growth direction thereof, which is not limited herein.

[0041] In some embodiments, before the n-type gallium oxide channel layer 20 is epitaxially grown on the substrate 10, an undoped gallium oxide layer can be grown on the substrate first, and then the n-type doped gallium oxide channel layer 20 is epitaxially grown on the undoped gallium oxide layer.

[0042] S120, a source electrode and a drain electrode are respectively deposited at both ends of the n-type gallium oxide channel layer, and a photoetching mask pattern is prepared in a preset channel region of the n-type gallium oxide channel layer.

[0043] The preset channel region can be a middle channel of the n-type gallium oxide channel layer 20, or can be another region, which can be selected according to requirements.

[0044] The n+ region under the electrode can be realized by ion implantation, and the deposition of the source electrode 30 and the drain electrode 40 can be realized by electron beam evaporation, and the deposited metal can be Ti / Au or Ti / Al / Ni / Au.

[0045] In some embodiments, the photoetching mask can include one pattern or a plurality of repeatedly arranged patterns, such as Figure 3 As shown in the figure, specifically, the photoetching mask pattern 51 can be a quadrilateral, and the length of the side of the photoetching mask pattern 51 close to the source electrode 30 is greater than the length of the side close to the drain electrode 40, that is, the two side walls of the quadrilateral extend from the drain electrode 40 side to the source electrode 30 side in a way of moving away from each other.

[0046] The photoetching mask can be realized by contact photoetching or electron beam photoetching, and the mask can be photoresist or metal prepared by photoetching stripping process.

[0047] S130, etching the n-type gallium oxide channel layer to obtain a plurality of discontinuous etching pits, and two side walls of adjacent etching pits close to each other form a fin-shaped mesa on the n-type gallium oxide channel layer.

[0048] The two side walls of the fin-shaped mesa extend from the source electrode 30 side to the drain electrode 40 side in a way of moving away from each other.

[0049] In some embodiments, the top view of the etching pit 50 on the n-type gallium oxide channel layer 20 is isosceles trapezoid, in which the side close to the source electrode 30 is the lower base and the side close to the drain electrode 40 is the upper base, thereby forming an inclined channel. Specifically, the angle between the inclined side of the isosceles trapezoid and the lower base is greater than or equal to 5 degrees and less than or equal to 85 degrees, so that the angle between the long side of the Fin mesa and the inclined side is greater than or equal to 5 degrees and less than or equal to 85 degrees, forming an inclined Fin channel. The length of the lower base can be 20 nm-4000 nm, and the length of the upper base can be 10 nm-2000 nm. The specific size and angle can be determined according to user requirements.

[0050] Dry etching can be used to etch the n-type gallium oxide channel layer 20, in which the area protected by the mask will not be etched, and the etching depth can be greater than the thickness of the n-type gallium oxide channel layer, or only a certain thickness of the n-type gallium oxide channel layer can be etched.

[0051] S140, a dielectric layer is prepared on the n-type gallium oxide channel layer, the dielectric layer avoids the preset channel region, the preset channel region is subjected to thermal oxidation treatment, and the dielectric layer is removed after the thermal oxidation treatment.

[0052] In some embodiments, in order to improve the breakdown characteristics of the gallium oxide field effect transistor, the preset channel region can be subjected to thermal oxidation treatment before depositing the gate electrode 70 to improve the characteristics of the channel.

[0053] The specific thermal oxidation process is as follows:

[0054] First, a dielectric layer 52 is prepared on the n-type gallium oxide channel layer 20, as shown in Figure 5 , and the dielectric layer avoids the preset channel region.

[0055] The dielectric layer 52 can be SiO2 or SiN x , which can be grown by PECVD or PLD method. Then, the dielectric layer on the Fin mesa is removed by photolithography and etching method, and the Fin mesa is exposed.

[0056] Then, the preset channel region is subjected to thermal oxidation treatment. The thermal oxidation treatment is annealing treatment of the preset channel region in an O2 atmosphere, the treatment temperature is 400-600°C, and the treatment time is 3-60 minutes. The other regions of the n-type gallium oxide channel layer 20 are not treated due to the protection of the dielectric layer 52, and the dielectric layer 52 is removed after the treatment.

[0057] The thermal oxidation treatment of the preset channel region can reduce the oxygen vacancies in the material and improve the control ability of the threshold voltage.

[0058] S150, depositing a gate electrode on the upper surface of the fin-shaped mesa and the two sidewalls and the n-type gallium oxide channel layer close to the source electrode.

[0059] In some embodiments, after the plurality of discontinuous etching pits 50 are etched, the two sidewalls of adjacent etching pits 50 close to each other form a fin-shaped mesa on the n-type gallium oxide channel layer, and then the above thermal oxidation process can be performed first, and then the gate electrode 70 is prepared on the n-type gallium oxide channel layer 20. The above thermal oxidation process can also not be performed, and the gate electrode 70 can be directly prepared on the n-type gallium oxide channel layer 20.

[0060] It should be noted here that the gate electrode 70 on the side close to the drain electrode 40 can at most cover the entire fin-shaped mesa, but cannot exceed the fin-shaped mesa. Thus, an inclined Fin channel is formed, but there can be a gate electrode 70 on the n-type gallium oxide channel layer 20 on the side close to the source electrode 30. In addition, in the etching pits 50, there can also be a gate electrode 70 on the sidewall of the etching pit 50 connected to the n-type gallium oxide channel layer 20 on the side of the etching pit 50 close to the source electrode 30. The gate electrode can also only cover part of the fin-shaped mesa, that is, no gate electrode is provided on the fin-shaped mesa on the side close to the drain electrode 40. That is, the height of the gate electrode formed on the n-type gallium oxide channel layer not etched on the side close to the source electrode is higher than that of the gate electrode on the two sidewalls of the fin-shaped mesa and in the etching pit. Thus, part of the gate electrode covers the Fin structure, and part of the gate electrode covers the channel not etched on one end of the source electrode. The gate electrode on the Fin mesa structure has a higher surface area to volume ratio, and thus has better gate control capability, thereby adjusting the threshold voltage of the device and making the threshold voltage positively shift. The three-dimensional gate structure also functions as a field plate, which can make the electric field distribution of the device more uniform, thereby reducing the peak field strength of the device and improving the breakdown characteristics of the device.

[0061] In some embodiments, before the gate electrode 70 is prepared, a gate dielectric layer 60 can also be deposited on the n-type gallium oxide channel layer 20. The gate dielectric layer 60 can also be deposited only in a target sub-region on the n-type gallium oxide channel layer 20. The target sub-region is only the region on which the gate electrode 70 is deposited on the upper surface and the two sidewalls of the fin-shaped mesa and the n-type gallium oxide channel layer 20 close to the source electrode 30.

[0062] Specifically, the gate dielectric layer 60 can be one or more of a p-type dielectric, Al2O3, HfO2, or SiO2. When the p-type dielectric is grown as a gate dielectric, sputtering, PLD, ALD, etc. can be used for growth. The p-type dielectric can be, but is not limited to, NiO x / SnO2 / CuO x / MnO x / FeO x / CuMO2 / ZnM2O4, etc., with a growth thickness of 10 nm to 1000 nm.

[0063] When the p-type dielectric layer is prepared only in the target sub-region, i.e., only in the region where the gate electrode 70 is deposited on the upper surface and the two side walls of the fin-shaped mesa and the n-type gallium oxide channel layer 20 close to the source electrode 30, the photolithography pattern of the p-type dielectric layer can be prepared first, and then the p-type dielectric layer is prepared in the target sub-region.

[0064] The length of the gate electrode 70 can be greater than or equal to 50 nm and less than or equal to 10 μm, and the deposited metal is Ni / Au or Pt / Au.

[0065] The preparation method provided in the present application first epitaxially grows an n-type gallium oxide channel layer on a substrate, and then deposits a source electrode and a drain electrode at two ends of the n-type gallium oxide channel layer. Then, after preparing a photolithography mask pattern in a preset channel region of the n-type gallium oxide channel layer, the n-type gallium oxide channel layer is etched to obtain a plurality of discontinuous etching pits, and the two side walls of adjacent etching pits close to each other form a fin-shaped mesa on the n-type gallium oxide channel layer, wherein the two side walls of the fin-shaped mesa extend from the source electrode side to the drain electrode side in a manner of moving away from each other. In addition, the fin-shaped mesa region is subjected to thermal oxygen annealing treatment by using dielectric protection. Finally, a gate electrode is deposited on the upper surface and the two side walls of the fin-shaped mesa and the n-type gallium oxide channel layer close to the source electrode. Thus, an inclined Fin channel is prepared. The gate electrode prepared on the fin-shaped mesa has different heights in the vertical direction, thereby forming a three-dimensional gate electrode.

[0066] Since the conventional right-angle gate electrode has a sharp peak electric field below the end point close to the drain electrode, the breakdown of the device often occurs in this region. The gate electrode prepared by using the preparation method provided in the present application has a higher surface area to volume ratio, thus having a better gate control capability, thereby adjusting the threshold voltage of the device to make the threshold voltage positively shift. The three-dimensional gate electrode also functions as a field plate, which can make the electric field distribution of the device more uniform, thereby reducing the peak field strength of the device, and the breakdown characteristics of the device can be further improved.

[0067] The following will describe in detail several preparation methods of gallium oxide field effect transistors:

[0068] A preparation method of a gallium oxide field effect transistor, comprising:

[0069] S210, providing a substrate 10, growing an undoped gallium oxide layer on the substrate 10, and then epitaxially growing an n-type doped gallium oxide channel layer 20 on the undoped gallium oxide layer.

[0070] S220, depositing a source electrode 30 and a drain electrode 40 at two ends of the n-type gallium oxide channel layer 20, and preparing a photolithography mask pattern 51 in a preset channel region of the n-type gallium oxide channel layer. The photolithography mask pattern 51 comprises a plurality of periodically arranged isosceles trapezoids.

[0071] S230, etching the n-type gallium oxide channel layer 20 to obtain a plurality of discontinuous etching pits 50 in isosceles trapezoidal cross-sectional shape, and the two side walls of the adjacent etching pits 50 close to each other form a fin-shaped mesa on the n-type gallium oxide channel layer 20. And one side of the etching pit 50 close to the source electrode 30 is the lower base, and one side close to the drain electrode 40 is the upper base, thereby forming an inclined channel.

[0072] S240, preparing a dielectric layer 52 on the n-type gallium oxide channel layer 20, and the dielectric layer avoids the preset channel region. The preset channel region is subjected to a thermal oxidation treatment. The thermal oxidation treatment is an annealing treatment on the preset channel region in an O2 atmosphere, the treatment temperature is 400-600°C, and the treatment time is 3-60 minutes. After the heat treatment is completed, the dielectric layer is removed.

[0073] S250, depositing a gate dielectric layer 60 on the n-type gallium oxide channel layer 20 by atomic layer deposition, and the gate dielectric layer avoids the source electrode and the drain electrode. The gate dielectric layer can be Al2O3 / HfO2 / SiO2, or a composite dielectric of Al2O3 and HfO2.

[0074] S260, depositing a gate electrode 70 on the upper surface and the two side walls of the fin-shaped mesa and the n-type gallium oxide channel layer close to the source electrode, the gate electrode covering the upper surface and the two side walls of the fin-shaped mesa to form a FinFET structure.

[0075] Another preparation method of a gallium oxide field effect transistor comprises:

[0076] S310, providing a substrate 10, growing an undoped gallium oxide layer on the substrate 10, and then epitaxially growing an n-type doped gallium oxide channel layer 20 on the undoped gallium oxide layer.

[0077] S320, depositing a source electrode 30 and a drain electrode 40 at both ends of the n-type gallium oxide channel layer 20, and preparing a photoresist mask pattern 51 in the preset channel region of the n-type gallium oxide channel layer 20. The photoresist mask pattern 51 comprises a plurality of periodically arranged isosceles trapezoids.

[0078] S330, etching the n-type gallium oxide channel layer 20 to obtain a plurality of discontinuous etching pits 50 in isosceles trapezoidal cross-sectional shape, and the two side walls of the adjacent etching pits 50 close to each other form a fin-shaped mesa on the n-type gallium oxide channel layer. And one side of the etching pit 50 close to the source electrode 30 is the lower base, and one side close to the drain electrode 40 is the upper base, thereby forming an inclined channel.

[0079] S340, a dielectric layer 52 is prepared on the n-type gallium oxide channel layer 20, and the dielectric layer avoids the preset channel region. The preset channel region is subjected to a thermal oxidation treatment. The thermal oxidation treatment is an annealing treatment on the preset channel region in an O2 atmosphere, the treatment temperature is 400-600°C, and the treatment time is 3-60 minutes. After the heat treatment is completed, the dielectric layer is removed. The dielectric layer can be SiO2 or SiN x .

[0080] S350, a gate dielectric layer 60 is deposited on a target sub-region on the n-type gallium oxide channel layer 20, wherein the gate dielectric layer is a p-type dielectric layer. The target sub-region is only the upper surface and the two side walls of the fin-shaped mesa and the region close to the source electrode 30 on which the gate electrode 70 is deposited on the n-type gallium oxide channel layer.

[0081] S360, a gate electrode is deposited on the p-type dielectric layer.

[0082] It should be understood that the size of the serial number of each step in the above embodiment does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0083] The above-described embodiments are only used to illustrate the technical solutions of the present application, but not limit it; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A method for fabricating a gallium oxide field effect transistor, characterized by, The application relates to a method for manufacturing a gallium oxide field effect transistor. The method comprises the following steps: providing a substrate; epitaxially growing an n-type gallium oxide channel layer on the substrate; depositing a source electrode and a drain electrode on both ends of the n-type gallium oxide channel layer respectively; preparing a photoetching mask pattern in a preset channel region of the n-type gallium oxide channel layer; etching the n-type gallium oxide channel layer to obtain a plurality of discontinuous etching pits, and forming a fin-shaped mesa on the n-type gallium oxide channel layer by two side walls of the etching pits close to each other; the two side walls of the fin-shaped mesa extend from the source electrode side to the drain electrode side in a manner away from each other; and a top view of the etching pits on the n-type gallium oxide channel layer is isosceles trapezoidal, wherein one side close to the source electrode side is a lower base, and one side close to the drain electrode side is an upper base; preparing a dielectric layer on the n-type gallium oxide channel layer, and the dielectric layer avoids the preset channel region; performing a thermal oxidation treatment on the preset channel region, and removing the dielectric layer after the thermal oxidation treatment to improve the control ability of threshold voltage; 2. The production method according to claim 1, wherein depositing a gate electrode on the upper surface and the two side walls of the fin-shaped mesa and the n-type gallium oxide channel layer close to the source electrode. Before the step of depositing the gate electrode on the upper surface and the two side walls of the fin-shaped mesa and the n-type gallium oxide channel layer close to the source electrode, the method further comprises the following steps:

3. The production method according to claim 1, wherein depositing a gate dielectric layer on a target sub-region on the n-type gallium oxide channel layer; wherein the target sub-region is only the region of the upper surface and the two side walls of the fin-shaped mesa and the n-type gallium oxide channel layer close to the source electrode. Before the step of depositing the gate electrode on the upper surface and the two side walls of the fin-shaped mesa and the n-type gallium oxide channel layer close to the source electrode, the method further comprises the following steps:

4. The production method according to claim 1, wherein The medium layer is SiO2or SiN x ; depositing a gate dielectric layer on the n-type gallium oxide channel layer, and the gate dielectric layer avoids the source electrode and the drain electrode.

5. The production method according to claim 2 or 3, characterized by, The thermal oxidation treatment is an annealing treatment in an oxygen atmosphere.

6. The production method according to claim 1, wherein The gate dielectric layer is one or more of a p-type dielectric, Al2O3, HfO2 or SiO2. The step of epitaxially growing the n-type gallium oxide channel layer on the substrate comprises the following steps: growing an undoped gallium oxide layer on the substrate; 7. The production method according to claim 1, wherein epitaxially growing an n-type doped gallium oxide channel layer on the undoped gallium oxide layer.

8. The production method according to claim 1, wherein The included angle between the oblique side of the isosceles trapezoid and the lower base is greater than or equal to 5 degrees and less than or equal to 85 degrees. The length of the lower base is 20 nm-4000 nm, and the length of the upper base is 10 nm-2000 nm.

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