Advanced package structure with si and organic interposer and method of manufacturing the same

Abstract

The application discloses an advanced packaging structure with Si and organic interlayer and a manufacturing method thereof. The structure comprises a low-density wiring substrate, a high-density RDL wiring Si interlayer and a medium-density RDL wiring organic dielectric layer. The Si interlayer is embedded on the surface of the substrate, and the organic dielectric layer is packaged on the surface of the Si interlayer and the substrate by a fan-out panel level packaging process and is electrically connected with the substrate and the Si interlayer. The Si interlayer provides high-density RDL wiring, the organic dielectric layer of the fan-out panel level packaging process provides medium-density RDL wiring, and the FCBGA substrate provides low-density wiring. The advanced packaging structure of the application simultaneously uses the three kinds of media with different wiring densities, and can integrate processors, logics and multi-chips in the advanced packaging structure. Chips from 1 to 6 can be put into the package, and the more the number of chips is, the better the operation efficiency of the processor is.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of semiconductor packaging, and particularly relates to an advanced packaging structure with Si and organic interposer and a manufacturing method thereof. BACKGROUND

[0002] With the need of higher memory bandwidth for various applications such as artificial intelligence (AI), data center, high performance computing (HPC), network and graphics acceleration cards, advanced packaging becomes an increasingly important factor to support high bandwidth memory (HBM) wide I / O. Currently, there are three advanced packaging technologies used in the industry, TSMC's CoWoS (Chip on Wafer on Substrate), Intel's EMIB (Embedded Multi-Die Interconnect Bridge) and Samsung's H-Cube.

[0003] TSMC's CoWoS: Typical 2.5D packaging, the chips of Processor, logic and HBM are mounted on the Si interposer, and there are multiple layers of redistribution layer (RDL) on the Si interposer, the line width and pitch of the redistribution layer wiring is less than 1.2 microns (um). Such fine wiring can provide high and medium density signal connection between chips, which cannot be provided by FCBGA substrate (or called carrier board), and medium and low density signal connection. The Si interposer is mounted on the FCBGA substrate, and the Si interposer has TSV (through silicon via) to guide the upper layer signal to the lower layer, and then make signal conduction with the FCBGA substrate. The fabrication of Si interposer wafer is completed by wafer factory, because of the limitation of reticle and exposure process equipment, it is difficult to make the Si interposer large enough to place many chips, in addition, the high cost is the criticism of CoWoS.

[0004] Intel's EMIB: Intel's approach is to reduce the size of the expensive Si interposer, the Si interposer does not have TSV (through silicon via) to guide the upper layer signal to the lower layer, because the signal is only transmitted in the RDL on the surface of the Si interposer, there is no TSV to potentially reduce the performance of the chip.

[0005] Single or multiple Si interposer embedded in FCBGA substrate, high and medium density signal connection routing design on Si interposer, low density signal connection routing design on FCBGA substrate, although the size of Si interposer is reduced to reduce the cost, but the FCBGA substrate cannot design medium density signal connection routing (line width and line spacing between 8um to 1.5um), ABF material has silica filler, blind via hole cannot be opened by etching, laser drilling blind via hole, size is limited, too small hole cannot be drilled, so the size and pitch of the joint between the substrate and the chip cannot be reduced, the size of Si interposer and chip cannot be further reduced, and the cost cannot be reduced.

[0006] The pitch of the joint between the chip and the Si interposer is 55um, and the pitch of the joint between the chip and the FCBGA substrate is 130um.

[0007] Samsung's H-Cube: basically similar to TSMC's CoWoS, the chip is mounted on a large Si interposer, the Si interposer is mounted on a fine pitch substrate, and the fine pitch substrate is mounted on a high density interconnect (HDI) substrate. Because a large Si interposer and two substrates are used, the problem faced is the same as CoWoS, the Si interposer is difficult to be large enough and the cost is very high.

[0008] Therefore, the existing method is either a large size Si interposer (because all high, medium and low density routing is on it), resulting in high cost, or a reduced size Si interposer, high and medium density routing on it, FCBGA substrate can only design low density (line width and line spacing greater than 8um) routing, Si interposer size cannot be further reduced, even when more chips are placed, Si interposer size must be increased, and cost cannot be further reduced. SUMMARY

[0009] The present application aims to at least solve one of the technical problems existing in the prior art. To this end, the present application provides an advanced packaging structure with Si and organic interposer and a manufacturing method thereof, which has low cost and high input / output density, and is very helpful for integrating more HBM and processor chips (or logic chips) to improve the performance of operation.

[0010] The technical scheme adopted by the present application is:

[0011] An advanced packaging structure with Si and organic interposer, comprising a low-density routing substrate, a high-density RDL routing Si interposer embedded on the surface of the substrate, and an organic dielectric layer with middle-density RDL routing, which is fan-out panel-level packaged on the surface of the Si interposer and the substrate and electrically connected with the substrate and the Si interposer; the line width and distance of the low-density routing is larger than that of the middle-density RDL routing, and the line width and distance of the middle-density RDL routing is larger than that of the high-density RDL routing.

[0012] Optionally, the substrate is an FCBGA substrate, comprising a core layer and a plurality of layers of build-up routing layers stacked on both sides of the core layer, and each layer of the build-up routing layer and the core layer are electrically connected by laser drilling and metal plating in the hole.

[0013] Optionally, the line width and distance of the low-density routing is larger than 8 μm, the line width and distance of the middle-density RDL routing is between 8 μm and 1.5 μm, and the line width and distance of the high-density RDL routing is less than 1.5 μm.

[0014] Optionally, the organic dielectric layer comprises a plurality of layers of polyimide and a plurality of layers of middle-density RDL routing alternately stacked, and each layer of the middle-density RDL routing is electrically connected by etching the polyimide therebetween and metal plating in the hole.

[0015] Optionally, the Si interposer and the organic dielectric layer are arranged on the upper surface of the substrate, the lower surface of the substrate is provided with tin ball pads, and the upper surface contact points of the organic dielectric layer are provided with tin-copper bumps.

[0016] Optionally, the line width and distance of the middle-density RDL routing decreases with the distance to the position where the memory chip is to be mounted.

[0017] Optionally, a cavity is formed on the upper surface of the substrate corresponding to the position of the Si interposer, and the gap between the Si interposer and the cavity is filled with resin.

[0018] Optionally, the surface contact points of the Si interposer are provided with metal bumps, and the metal bumps are coplanar with the surface contact points of the substrate when the Si interposer is embedded in the substrate.

[0019] A manufacturing method for manufacturing the advanced packaging structure with Si and organic interposer as described above, the manufacturing method comprising:

[0020] manufacturing a high-density RDL routing Si interposer;

[0021] manufacturing a low-density routing substrate, and forming a cavity on the upper surface of the substrate corresponding to the position of the Si interposer;

[0022] Embedding the Si interposer into the cavity;

[0023] Attaching the lower surface of the substrate with the embedded Si interposer to a carrier, and using a fan-out panel-level package to make several layers of organic dielectric layers of middle-density RDL wiring on the upper surface, and making the RDL wiring of the organic dielectric layers electrically connected to the Si interposer and the substrate;

[0024] Making tin-copper bumps on the upper surface contacts of the Si interposer;

[0025] Removing the carrier and cutting into single pieces.

[0026] Optionally, the substrate is an FCBGA substrate, and the steps of making the FCBGA substrate include:

[0027] Making a substrate core layer, and making the circuit on both surfaces of the core layer by opening a via on the core layer and plating metal to make the circuit on both surfaces of the core layer;

[0028] Stacking several layers of build-up wiring layers on both surfaces of the core layer, respectively, and making electrical connection between each layer of the build-up wiring layer and the core layer by laser drilling and plating metal in the via.

[0029] Optionally, the upper surface contacts of the Si interposer are provided with metal bumps, after embedding the Si interposer into the cavity, filling resin between the Si interposer and the cavity, and continuing to stack build-up wiring layers on the upper surfaces of the Si interposer and the substrate, the height of the metal bumps is consistent with the height of the part of the build-up wiring layers that is laser drilled and plated with metal in the via.

[0030] Optionally, before making the organic dielectric layers on the upper surface of the substrate using a fan-out panel-level package, the method further includes the steps of:

[0031] Grinding the build-up wiring layers on the upper surfaces of the substrate and the Si interposer to expose the part of the build-up wiring layers that is laser drilled and plated with metal in the via between the metal bumps and the build-up wiring layers, and to achieve the designed thickness and flatness.

[0032] Optionally, the step of making the organic dielectric layers includes: alternately stacking multiple layers of polyimide and multiple layers of middle-density RDL wiring on the upper surfaces of the substrate and the Si interposer, and making electrical connection between each layer of the middle-density RDL wiring by etching the polyimide in the via and plating metal in the via.

[0033] Optionally, after the last layer of organic dielectric layer is made, a blind hole is made in the polyimide by exposure, development and etching, and tin-copper bumps are made that are electrically connected to the middle-density RDL wiring.

[0034] Optionally, the manufacturing method further includes the steps of:

[0035] Flip processor, logic and several high bandwidth memory chips on the Si interposer on the upper surface of the substrate cut into single, several tin copper bumps on the chip and tin copper bumps on the upper surface of the Si interposer are welded to conduct electricity;

[0036] The gap between the chip and the Si interposer is filled with underfill, and a heat sink is attached, the heat sink and the back of the chip have thermal interface material to help conduct heat;

[0037] Tin ball pads are made on the lower surface of the substrate.

[0038] Due to the adoption of the above technical scheme, the present application has the following beneficial effects:

[0039] The advanced packaging structure of the present application has Si and organic interposer, the Si interposer provides high-density RDL wiring, the organic dielectric layer of the fan-out panel level packaging process provides medium-density RDL wiring, and the substrate of the FCBGA provides low-density wiring, the advanced packaging structure of the present application uses the three different wiring density media at the same time, which can provide processor, logic and high bandwidth memory (HBM) multi-chip integration in the advanced packaging structure, HBM can be put into the package from 1 to 6, the more the number of HBM, the better the operation efficiency of the processor. BRIEF DESCRIPTION OF DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced below, and obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0041] Figures 1-5 The structure schematic diagram presented by each step of the FCBGA substrate process technology provided by the embodiment of the present application.

[0042] Figure 6 The structure schematic diagram presented by the FCBGA substrate embedded Si interposer process technology provided by the embodiment of the present application.

[0043] Figures 7-11 The structure schematic diagram presented by each step of the FCBGA substrate organic dielectric layer manufacturing process technology provided by the embodiment of the present application.

[0044] The correspondence of the figure numbers is as follows:

[0045] 1-FCBGA substrate; 11-core layer; 111-via; 112-copper foil; 12-buildup line layer; 121-ABF buildup film; 122-copper wire; 123-blind hole; 124-electroplated copper; 13-cavity; 2-Si interposer; 21-copper bump or copper pillar; 22-DAF adhesive film; 23-resin; 3-organic dielectric layer; 31-polyimide (PI); 32-medium-density RDL wiring; 33-photoresist or photoresist film; 4-tin copper bump; 5-tin ball pad; 6-glass carrier; 7-adhesive; 8-processor; 9-high-bandwidth inner-layer chip (HBM); 10-underfill. DETAILED DESCRIPTION

[0046] The specific embodiments of the present application will be further described with reference to the drawings. It is to be noted that the descriptions of these embodiments are intended to help understand the present application and are not intended to limit the present application. In addition, the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0047] First, the technical terms appearing in the text are explained as follows:

[0048] RDL: Redistribution Layer, redistribution layer, contains copper connection lines or traces, used to realize electrical connection between each part of the package, it is a metal or polymer dielectric material layer, the die can be stacked in the package, thereby reducing the I / O pitch of the chip set; RDL has become an indispensable part of 2.5D and 3D packaging solutions, so that the chips on it can communicate with each other through the interposer;

[0049] DAF: Die Attach Film, die attach film, the purpose is to cut and separate the wafer together when laser cutting, peeling, so that the cut wafer can still be attached to the film and will not be scattered due to cutting;

[0050] FCBGA (Flip Chip Ball Grid Array): flip chip ball grid array packaging format, which is also the main packaging format of graphics acceleration chips;

[0051] Buildup: a processing technology for forming a thin film on the surface of a wafer;

[0052] ABF: ABF material is a material developed by Intel, which is used for the production of Flip Chip and other high-level carriers. Compared with BT substrate, ABF material can make the line thinner, which is suitable for IC with high pin count and high transmission. It is mainly used for CPU, GPU and chip set and other large high-end chips. As a build-up material, ABF can be directly attached to the copper foil substrate to make the line, and there is no need for hot pressing process.

[0053] HBM: High Bandwidth Memory, high bandwidth memory chip

[0054] PI: Polyimide, polyimide, refers to a kind of polymer containing imide ring (-CO-N-CO-) in main chain, which is one of the best organic high molecular materials in comprehensive performance. Its high temperature resistance is up to 400 DEG C or more, the long-term use temperature range is-200-300 DEG C, some have no obvious melting point, high insulation performance, dielectric constant is 4.0 at 103 hertz, dielectric loss is only 0.004-0.007, belongs to F to H grade insulation.

[0055] At present, there are three kinds of packaging for high-efficiency operation combined with processor and HBM chip, TSMC's CoWoS, Intel's EMIB, and some companies' scheme of integrating CPU and HBM chip in FO packaging body, and then packaging FO in FCBGA. Among them, CoWoS can provide the best solution for high input / output density, but the cost is very high. The other two solutions have lower cost, but can provide lower input / output density. The present application has low cost and high input / output density, which is very helpful for integrating more HBM to improve the operation efficiency.

[0056] Specifically, as shown in 1-11, Figures 1-5 The structure schematic diagram provided by each step of the FCBGA substrate process technology provided by the embodiment of the present application; Figure 6 The structure schematic diagram provided by the FCBGA substrate embedded Si interlayer process technology provided by the embodiment of the present application; Figures 7-11 The structure schematic diagram provided by each step of the FCBGA substrate organic dielectric layer process technology provided by the embodiment of the present application.

[0057] The advanced packaging structure with Si and organic interlayer provided by the embodiment of the present application mainly utilizes interlayers of different materials to show different line widths and pitches to support the mutual connection of signals between high input / output (I / O: Input / Output) density chips.

[0058] The advanced packaging structure with Si and organic interposer mainly comprises a low-density wiring substrate 1, a high-density RDL wiring Si interposer 2, and a medium-density RDL wiring organic dielectric layer 3, wherein the Si interposer 2 is embedded on the surface of the substrate 1, and the organic dielectric layer 3 is fan-out panel-level packaged on the surface of the Si interposer 2 and the substrate 1 and electrically connected with the substrate 1 and the Si interposer 2; wherein the line width and distance of the low-density wiring are greater than those of the medium-density RDL wiring, and the line width and distance of the medium-density RDL wiring are greater than those of the high-density RDL wiring. Preferably, the line width and distance of the low-density wiring are greater than 8 μm, the line width and distance of the medium-density RDL wiring are between 8 μm and 1.5 μm, and the line width and distance of the high-density RDL wiring are less than 1.5 μm.

[0059] As shown in Figures 1-5 , the substrate 1 is preferably an FCBGA substrate, comprising a core layer 11 and a plurality of layers of build-up wiring layers 12 stacked on the two surfaces of the core layer 11, and each layer of build-up wiring layer 12 and the core layer 11 are electrically connected by laser drilling and metal plating in the hole.

[0060] As shown in Figure 1 , the core layer 11 of the FCBGA substrate 1 has a plurality of layers, and the main three layers are the middle layer of glass fiber and resin material, and the upper and lower layers of the middle layer are copper foil 112. The through hole 111 is opened on the core layer 11 substrate, the through hole 111 is plated with copper (or other equivalent metal), and the copper foil 112 outside the circuit part is removed by etching to form a circuit and the upper and lower two layers of circuit are conducted through the through hole 111 and the copper plating in the hole.

[0061] The upper and lower surfaces of the core layer 11 are respectively pressed with a plurality of layers of build-up wiring layers 12, and the build-up wiring layers 12 on the two surfaces of the core layer 11 are electrically connected through the through hole 111 and the copper plating in the hole. Each layer of build-up wiring layer 12 further comprises an ABF build-up film 121 and a circuit formed by copper conductive lines 122 (or other equivalent metal conductive lines) on the surface of the ABF build-up film 121. Specifically, a laminating process (or a build-up process) is used to press ABF (Ajinomoto Build-up Film) or equivalent materials on both surfaces of the core layer 11, the circuit pattern is exposed, and the copper conductive circuit is directly formed by developing, etching and copper plating treatment. The laminating process is repeated for a plurality of times to stack and build up, and the blind holes 123 are used for electrical connection between the copper conductive lines 122 in each layer, the blind holes 123 are drilled by laser, and the size is limited, too small holes cannot be drilled, and the blind holes 123 are filled with electroplated copper 124 (or other equivalent metal). The laminating process is repeated for a plurality of times to the required number of layers, as shown in Figures 2-4 .

[0062] A cavity 13 is formed in the ABF addition film 121 of the last addition layer 12 on the upper surface of the FCBGA substrate 1 to accommodate the Si interposer 2, such as... Figure 5 and Figure 6 As shown, the gap between the Si interposer 2 and the cavity 13 is filled with resin 23. The Si interposer 2 has high-density RDL wiring, and copper bumps or copper pillars 21 (or other equivalent metal bumps) are provided at the contact positions on the upper surface of the Si interposer 2. When the Si interposer 2 is embedded in the cavity 13 on the upper surface of the FCBGA substrate 1, these copper bumps or copper pillars 21 face upwards and are coplanar with the surface contacts of the FCBGA substrate 1, such as... Figure 7 As shown, after embedding the Si interposer 2 on the FCBGA substrate 1, the augmentation circuit layer 12 can be further laminated on the upper surface of the FCBGA substrate 1, and the height of the electroplated copper 124 in the laser opening between the augmentation circuit layers 12 can be made consistent with the height of the copper bump or copper pillar 21.

[0063] like Figures 8-10 As shown, the organic dielectric layer 3 includes alternating stacked multilayer polyimide 31 and multilayer medium-density RDL wiring 32. Electrical conduction between the medium-density RDL wiring 32 layers is achieved through etched openings in the polyimide 31 and electroplated copper (or other equivalent metal) within the openings. The medium-density RDL wiring 32 and polyimide 31 within the organic dielectric layer 3 are fabricated on the FCBGA substrate 1 and the Si interposer layer 2 using a fan-out panel-level package. The medium-density RDL wiring 32 electrically connects the low-density wiring on the FCBGA substrate 1 and the high- and medium-density RDL wiring on the Si interposer layer 2. The Si interposer layer 2 and the organic dielectric layer 3 are disposed on the upper surface of the FCBGA substrate 1, and solder ball pads 5 are provided on the lower surface of the FCBGA substrate 1. Figure 11 As shown, the upper surface of the organic dielectric layer 3 has tin-copper bumps 4. The tin-copper bumps 4 can be used to solder the tin-copper bumps on the memory chip 9. Approximately close to the position of the memory chip 8, the line width and spacing of the medium-density RDL wiring 32 in the organic dielectric layer 3 are finer, even as fine as 1.5μm to 2.0μm.

[0064] Embedding a smaller Si interposer in an FCBGA can reduce costs, simplify the packaging process, and lower the packaging cost. However, because high- and medium-density wiring is located on the Si interposer, the size of the Si interposer cannot be further reduced; in fact, when more chips are placed on it, the size of the Si interposer needs to be increased.

[0065] This invention removes medium-density wiring from the Si interposer and places it in a polyimide organic dielectric layer, which can be designed with medium-density wiring (RDL linewidth and spacing capabilities between 10 and 1.5 micrometers) and at a lower cost.

[0066] Throughout the electronic and semiconductor supply chain, the wafer foundry process mainly handles 1 micron (um) to 3 nanometer (nm) line width and spacing, the printed circuit board process handles several millimeters (mm) or more line width and spacing, the packaging factory process handles several millimeters (mm) to several microns (um) line width and spacing, and the substrate used in the packaging factory process handles 8 microns (um) to several hundred microns line width and spacing, and the bump of the packaging factory, the fan-in / fan-out packaging process can handle tens of microns to 1 micron line width and spacing, which is used to solve the bottleneck encountered by the current advanced packaging.

[0067] The difference between the fan-in wafer level package (FI-WLP) and the fan-out wafer level package (FO-WLP) is mainly that the tin balls of the fan-in package are within the range of the chip, and the tin balls of the fan-out package are outside the range of the chip.

[0068] The fan-out wafer level packaging process of the packaging factory (some wafer factories also have) is to pull the required circuit from the end point (PAD) of the semiconductor bare die to the redistribution layer (Redistribution Layer), and then form a package. Therefore, there is no need for a packaging substrate, no need for wire (Wire) and bump (Bump), which can reduce production costs and make the chip and package thinner. In order to form the redistribution layer, the front-end process must be introduced to the packaging, which greatly improves the process capability of the packaging factory from several millimeters to several microns.

[0069] Wafer level packaging is mainly based on wafer level process, and the process handles one or more wafers as a unit.

[0070] FOWLP process is divided into two categories:

[0071] Chip-first FO: Place on wafer level carrier, pick out qualified dies (KGD, known good die) from raw device wafers, cover with re-constitution wafer by molding resin, further process RDL on wafer, ball planting, carrier removal, singulation.

[0072] RDL-first FO: Wafer level carrier establishes RDL layer and temporary bonding, places KGD on the top and covers with molding resin, grinding, carrier removal, ball planting, singulation.

[0073] Under these two process architectures, various changes can also be derived according to different customer needs, such as die facing up bonding, die facing down bonding, RDL fine line first, RDL thick line first type. The RDL line width and spacing capability of FOWLP can be as small as 1.5 microns.

[0074] FOWLP is more suitable for chip size less than 5mm 2 If the chip is very large, the wafer level is arc-shaped, which will waste a lot of wafer space. The solution is to use fan-out packaging FOPLP (fan-out panel level package) to save space and increase the output per unit, thereby greatly reducing the cost.

[0075] The panel level process capability can be the same as the wafer level, if the working area of the wafer level equipment is enlarged, of course, this must be developed with the material and equipment suppliers to develop suitable materials and process equipment to achieve the same process capability, the RDL line width and spacing capability can be as small as 1.5 microns.

[0076] With the newly developed materials and equipment, the RDL process line width and spacing capability of fan-out panel level packaging can be as small as 1.5 microns, which meets the demand of medium-density wiring (RDL line width and spacing capability between 10-1.5 microns), so the process of fan-out panel level packaging can be used to make medium-density interlayers.

[0077] Si interlayer provides high RDL wiring density, fan-out panel level packaging process provides medium-density RDL wiring, and FCBGA substrate provides low-density wiring. Advanced packaging can provide processor, logic and HBM multi-chip integration in advanced packaging, and HBM from 1 to 6 can be placed in the package. The more HBM, the better the processor Processor operation efficiency.

[0078] The scheme provided by the present application is to embed the Si interlayer with high-density RDL wiring in the FCBGA substrate with low-density wiring, which can be completed in the substrate factory. The process of the substrate factory is panel level, so it is not cut into single pieces first, and then sent to the place with fan-out panel level packaging process (RDL line width and spacing capability as small as 1.5 microns). The organic dielectric layer with multiple layers of RDL (medium-density wiring) is made on the surface of the substrate, and the top has copper-tin bumps as the electrical connection for subsequent chip mounting. Finally, it is cut into single pieces and shipped to the packaging factory for subsequent FCBGA process.

[0079] Cooperation Figures 1-11 As shown in the figure, the manufacturing method for manufacturing the advanced packaging structure with Si and organic interlayer as in the above embodiment is provided, and the manufacturing method comprises:

[0080] Step 1: Make Si interposer with high-density RDL wiring, which is provided with high-density RDL wiring and copper bumps or pillars 21 (or other equivalent metal bumps) at the surface contact position of the Si interposer 2, and the copper bumps or pillars 21 are electrically connected to the high-density RDL wiring.

[0081] Step 2: Make FCBGA substrate 1 with low-density wiring, and open a cavity 13 on the upper surface of the FCBGA substrate 1 corresponding to the position of the Si interposer 2.

[0082] Specifically, the steps for making the FCBGA substrate 1 further include:

[0083] Making the substrate core layer 11, which is etched to form a circuit by opening a through hole 111 on the core layer 11, plating copper (or other equivalent metal), and etching the copper foil 122 on both sides of the core layer 11 to make the circuit, as shown in Figure 1

[0084] Stacking several layers of build-up wiring layers 12 on both sides of the core layer 11, respectively, and electrically connecting each layer of build-up wiring layers 12 and the core layer 11 through laser blind holes 123 and blind holes 123 filled with electroplated copper 124 (or other equivalent metal).

[0085] More specifically, the build-up wiring layer 12 adopts a laminate process (or build-up process). ABF (Ajinomoto Build-up Film) build-up film 121 or equivalent material is pressed on both sides of the core layer, the circuit pattern is exposed, and the circuit (i.e. the circuit composed of copper wires 122) is directly formed by copper plating treatment. Repeat the process multiple times to stack the build-up (laminate), and the blind holes 123 are used for electrical connection between the copper wires 122 of each layer, which are drilled by laser, with limited size, and too small holes cannot be drilled. The laminate process is repeated several times to the required number of layers, as shown in Figures 2-4

[0086] ​​Step 3: Hollow out the cavity on the top surface of the FCBGA substrate 1 at the location where the Si interposer 2 (with multiple layers of RDL lines with line width and pitch less than 1.5 microns) is to be placed. The contact pads on the top surface of the Si interposer 2 have copper bumps or pillars 21. The copper bumps or pillars 21 of the Si interposer 2 are facing upwards. The bottom of the Si interposer 2 is fixed in the cavity 13. The gap between the Si interposer 2 and the cavity 13 is filled with resin 23. After that, the ABF build-up film 121 is pressed to cover the Si interposer 2 (with copper bumps or pillars 21 on the top surface) and the copper traces 122 on the substrate 1. Laser is used to create blind via holes 123 on the substrate 1. The blind via holes 123 are filled with electroplated copper 124 (or other equivalent metals) to the same height as the copper bumps or pillars 21 on the top surface of the Si interposer 2, as shown in Figures 5-7 .

[0087] Step 4: After the build-up process, the outer layer process is carried out. The substrate 1 is cleaned, inspected for appearance and electrical properties, and the process of the FCBGA substrate 1 is completed.

[0088] Step 5: The substrate 1 panel is sent to the fan-out panel level packaging production line. The surface topography of the substrate panel prepared by the substrate factory is not flat, which has a negative impact on the formation of subsequent fine lines (such as broken lines and short circuits). After cleaning the panel, the lower surface is adhered to the glass carrier 6 with adhesive 7. The upper surface is the ABF build-up film 121 (with multiple blind via holes 123 and electroplated copper 124 filled in the blind via holes 123). The surface of the ABF build-up film 121 is polished by mechanical polishing or chemical mechanical polishing (CMP). The polishing is performed until the copper bumps or pillars 21 on the top surface of the Si interposer 2 and the electroplated copper 124 filled in the blind via holes 123 are exposed and reach the designed thickness and flatness.

[0089] Step 6: After polishing, the substrate 1 panel is cleaned. Multiple layers of medium-density RDL wiring 32 and multiple layers of dielectric layer (polyimide or equivalent material) are formed on the flat surface. The polyimide 31 between the layers of medium-density RDL wiring 32 is opened with blind via holes. The blind via holes are opened by etching, and electroplated buried holes are used for electrical connection between the copper traces of each layer. The closer to the chip, the finer the line width and pitch of the medium-density RDL wiring 32, even as fine as 1.5-2.0 microns. Therefore, by controlling the thickness of the layers of medium-density RDL wiring 32 and dielectric layer, selecting the material of the dielectric layer, and optimizing the process, the surface topography of the dielectric layer can be made as flat as possible. Only in this way can the patterned RDL copper traces meet the requirement of fine lines. As shown in Figures 8-10 .

[0090] Step 7: After the last layer of the middle density RDL wiring 32 and the polyimide 31 are completed, the polyimide 31 is opened by exposure, development and etching. Because the opening is achieved by etching, the size and pitch of the opening can be reduced, and the tin-copper bump 4 is formed on the contact part of the chip (die). The panel is cut into multiple single FCBGA substrates, and the appearance and electrical properties are checked, and the package factory continues the subsequent process. The polyimide 31 is opened by etching, which has smaller size and pitch than the laser opening of ABF, so the pitch between the contacts of the chip and the Si interposer can be reduced to 35-40um (currently 55um). The size of the chip and the Si interposer can be reduced. The cost is reduced. As shown in Figure 11

[0091] Step 8: The package factory flips the processor 8, logic and 1-6 high bandwidth memory (HBM) chips 9 on the upper surface of the FCBGA substrate 1, the tin-copper bumps on the chip 9 are welded to the contacts of the tin-copper bumps 4 on the upper surface of the FCBGA substrate 1 to make electrical conduction, the gap between the chip 9 and the substrate 1 is filled with underfill 10, a heat sink is attached, the heat sink and the back of the chip have thermal interface material (TIM), which helps heat conduction. Finally, the ball pads on the lower surface of the FCBGA substrate 1 are planted with multiple tin balls to form a tin ball pad 5, and the heat sink is covered with a stamp, the appearance and electrical properties are checked, and the packaging process of the FCBGA substrate is completed, as shown in Figure 11

[0092] In the description of the present application, it should be noted that unless otherwise specified and limited, the terms "mounting", "connecting", "connecting" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be directly connected, or indirectly connected through an intermediate medium; it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0093] In the description of the present application, it should be understood that the terms "upper", "lower", "vertical", "inner", "outer" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, therefore it cannot be understood as a limitation on the present application.

[0094] ​​The terms "first", "second", etc. are used only for the purpose of description and do not indicate or imply relative importance or a number of indicated technical features. Thus, features defined with "first", "second" can explicitly or implicitly include one or more of such features.

[0095] The embodiments of the present application described above are merely given as non-limiting examples. It is understood by those skilled in the art that various modifications, equivalent replacements, changes and variations of the embodiments can be made without departing from the principles and spirit of the present application, and such modifications, equivalent replacements, changes and variations should be within the scope of the present application.

Claims

1. An advanced package structure with Si and organic interposer, characterized by: The substrate with low-density wiring, the Si interposer with high-density RDL wiring, and the organic dielectric layer with medium-density RDL wiring are embedded on the surface of the substrate, and the organic dielectric layer is packaged in a fan-out panel level and electrically connected to the substrate and the Si interposer; The line width and distance of the low-density wiring are larger than those of the medium-density RDL wiring, and the line width and distance of the medium-density RDL wiring are larger than those of the high-density RDL wiring; The surface of the substrate with low-density wiring is formed with a cavity corresponding to the position of the Si interposer with high-density RDL wiring, and the gap between the Si interposer and the cavity is filled with resin; The medium-density RDL wiring in the organic dielectric layer is arranged on the substrate and the Si interposer, and the medium-density RDL wiring electrically connects the low-density wiring on the substrate and the high-density RDL wiring on the Si interposer.

2. The advanced package structure with Si and organic interposer of claim 1, wherein: The substrate is an FCBGA substrate, which comprises a core layer and a plurality of layers of increased circuit layers stacked on both sides of the core layer, and each layer of the increased circuit layer and the core layer are electrically connected by laser drilling and metal plating in the hole.

3. The advanced package structure with Si and organic interposer of claim 1, wherein: The line width and distance of the low-density wiring are larger than 8 μm, the line width and distance of the medium-density RDL wiring are between 8 μm and 1.5 μm, and the line width and distance of the high-density RDL wiring are less than 1.5 μm.

4. The advanced package structure with Si and organic interposer of claim 1, wherein: The organic dielectric layer comprises a plurality of layers of polyimide and a plurality of layers of medium-density RDL wiring stacked alternately, and each layer of the medium-density RDL wiring is electrically connected by etching the polyimide between the layers and metal plating in the hole.

5. The advanced package structure with Si and organic interposer of claim 1, wherein: The Si interposer and the organic dielectric layer are arranged on the upper surface of the substrate, the lower surface of the substrate is provided with a tin ball pad, and the upper surface contact of the organic dielectric layer is provided with a tin-copper bump.

6. The advanced package structure with Si and organic interposer of claim 1, wherein: The line width and distance of the medium-density RDL wiring decrease with the distance to the position where the memory chip is to be mounted.

7. The advanced package structure with Si and organic interposer of claim 1, wherein: The surface contact of the Si interposer is provided with a metal bump, and when the Si interposer is embedded in the substrate, the metal bump is coplanar with the surface contact of the substrate.

8. A manufacturing method for manufacturing the advanced package structure with Si and organic interposer according to any one of claims 1 to 7, characterized in that, The manufacturing method comprises: manufacturing a Si interposer with high-density RDL wiring; manufacturing a substrate with low-density wiring, and forming a cavity on the upper surface of the substrate corresponding to the position of the Si interposer; embedding the Si interposer in the cavity; adhering the lower surface of the substrate with the embedded Si interposer to a carrier, and using a fan-out panel level packaging to manufacture a plurality of layers of organic dielectric layer with medium-density RDL wiring, so that the RDL wiring of the organic dielectric layer is electrically connected to the Si interposer and the substrate; manufacturing a tin-copper bump on the upper surface contact of the Si interposer; removing the carrier and cutting into a single piece.

9. The production method according to claim 8, wherein The substrate is an FCBGA substrate, and the steps of manufacturing the FCBGA substrate comprise: manufacturing a substrate core layer, and electrically connecting the circuits on both sides of the core layer by drilling holes on the core layer and metal plating; stacking a plurality of layers of increased circuit layers on both sides of the core layer, and electrically connecting each layer of the increased circuit layer and the core layer by laser drilling and metal plating in the hole.

10. The manufacturing method according to claim 9, wherein The upper surface of the Si interposer is provided with a metal bump. After the Si interposer is embedded in the cavity, resin is filled between the Si interposer and the cavity. The Si interposer and the upper surface of the substrate are further laminated with a build-up circuit layer. The height of the metal bump is consistent with the height of the metal part in the laser-drilled hole filled with metal between the build-up circuit layers.

11. The manufacturing method according to claim 10, wherein Before the organic dielectric layer is made on the upper surface of the substrate using a fan-out panel level package, the following steps are further included: The build-up circuit layer on the upper surface of the substrate and the Si interposer is polished until the metal bump and the metal part in the laser-drilled hole filled with metal between the build-up circuit layers are exposed and the designed thickness and flatness are achieved.

12. The manufacturing method according to claim 8, wherein The step of making the organic dielectric layer includes: alternately stacking multiple layers of polyimide and multiple layers of medium-density RDL wiring on the upper surface of the substrate and the Si interposer. Each layer of the medium-density RDL wiring is electrically connected by etching the polyimide between the layers and filling the hole with metal.

13. The manufacturing method according to claim 12, wherein After the last layer of the organic dielectric layer is made, a blind hole is made in the polyimide by exposure, development, and etching. A tin-copper bump is made for electrical connection with the medium-density RDL wiring.

14. The manufacturing method according to claim 8, wherein The following steps are further included: A processor, logic, and several high-bandwidth memory chips are flip-chip mounted on the Si interposer on the upper surface of the substrate cut into single pieces. The tin-copper bumps on the chips are soldered to the tin-copper bumps on the upper surface of the Si interposer for electrical conduction. Bottom filling is performed between the chips and the Si interposer. A heat sink is attached. The heat sink and the back surface of the chip have a thermal interface material to assist heat conduction. Tin ball pads are made on the lower surface of the substrate.

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