Semiconductor device

Abstract

The present disclosure relates to a semiconductor device including: a first silicon layer; a second silicon layer bonded to the first silicon layer; and a wiring layer configured to electrically connect the first silicon layer to the second silicon layer, wherein a first hollow region is formed in the wiring layer.

Description

[0001] This application is a divisional application of Patent Application No. 201680015741.4, filed on March 17, 2016, entitled "Solid-state image capturing element and electronic apparatus." TECHNICAL FIELD

[0002] The present disclosure relates to a solid-state image capturing element and an electronic apparatus, and more particularly to a solid-state image capturing element and an electronic apparatus capable of reducing capacitance by using a hollow region. BACKGROUND

[0003] In a complementary metal-oxide semiconductor (CMOS) image sensor, as miniaturization of pixels continues to progress, an opening area of a photodiode decreases, and sensitivity decreases. Further, a size of a pixel transistor decreases, and random noise becomes deteriorated. As a result, a signal-to-noise ratio (S / N) decreases and image quality deteriorates.

[0004] Therefore, a method of improving a signal-to-noise ratio by reducing a parasitic capacitance of a floating diffusion (FD) and improving charge-voltage conversion efficiency has been proposed.

[0005] The parasitic capacitance of the FD includes a diffusion capacitance of the FD, a capacitance of a gate electrode of an amplification transistor connected to the FD wiring, a capacitance of the FD wiring, and any other capacitance. The diffusion capacitance of the FD can be reduced by lowering a concentration of N-type impurities of the FD. However, in this case, there is a concern for contact failure.

[0006] The capacitance of the gate electrode of the amplification transistor can be reduced by reducing a size of the amplification transistor. However, when the size of the amplification transistor is reduced, random noise is more deteriorated.

[0007] Further, the capacitance of the FD wiring can be reduced to some extent by designing a wiring layout. However, because the FD needs to be connected to the amplification transistor, the wiring layout is limited based on a sharing system of pixels. Therefore, it is difficult to reduce the capacitance of the FD wiring by designing the wiring layout.

[0008] Therefore, a method of reducing the capacitance of the FD wiring by changing an entire periphery of a wiring layer to a low dielectric constant film has been proposed (for example, refer to PTL 1).

[0009] [LIST OF CITATIONS]

[0010] [PATENT LITERATURE]

[0011] [PTL 1]

[0012] JP 2009-231501 A SUMMARY

[0013] [TECHNICAL PROBLEM]

[0014] As a method to reduce capacitance, it is desirable to use a method different from that described in PTL 1.

[0015] This disclosure takes such a scenario into account and makes it possible to reduce capacitance by using a hollow region.

[0016] [Solution to the problem]

[0017] According to one aspect of this disclosure, a solid-state image capture element is such that at least a portion of the region between the FD wiring connected to the floating diffusion node and wiring other than the FD wiring is a hollow region.

[0018] An electronic device according to one aspect of the present disclosure corresponds to a solid-state image capture element of that aspect of the present disclosure.

[0019] According to one aspect of this disclosure, at least a portion of the area between the FD wiring connected to the floating diffusion node and wiring other than the FD wiring is a hollow area.

[0020] [Beneficial Effects of the Invention]

[0021] According to one aspect of this disclosure, capacitance can be reduced. Furthermore, according to one aspect of this disclosure, capacitance can be reduced by using a hollow region.

[0022] The beneficial effects described in this disclosure are not necessarily limited and can be any of the effects described in this disclosure. Attached Figure Description

[0023] [ Figure 1 ]

[0024] Figure 1 This is a schematic diagram illustrating a configuration example of a CMOS image sensor as a solid-state image capture element according to a first embodiment of the present disclosure.

[0025] [ Figure 2 ]

[0026] Figure 2 To show in Figure 1 A schematic diagram of a circuit configuration example for one pixel in a two-dimensional arrangement of pixels in a pixel region.

[0027] [ Figure 3 ]

[0028] Figure 3 This is a schematic diagram illustrating a first structural example of a CMOS image sensor.

[0029] [ Figure 4]

[0030] Figure 4 A schematic diagram showing a second structural example of a CMOS image sensor.

[0031] [ Figure 5 ]

[0032] Figure 5 A schematic diagram showing a third structural example of a CMOS image sensor.

[0033] [ Figure 6 ]

[0034] Figure 6 A schematic diagram showing a fourth structural example of a CMOS image sensor.

[0035] [ Figure 7 ]

[0036] Figure 7 A schematic diagram showing a circuit configuration example of a pixel of a CMOS image sensor according to the second embodiment of the present disclosure.

[0037] [ Figure 8 ]

[0038] Figure 8 A view showing an example of a layout of each part of a CMOS image sensor according to the third embodiment.

[0039] [ Figure 9 ]

[0040] Figure 9 A plan view of a first structural example of a pixel region in Figure 8 from the wiring layer side.

[0041] [ Figure 10 ]

[0042] Figure 10 including a cross-sectional view taken along the A-A' cut in Figure 9 and a cross-sectional view taken along the B-B' cut in Figure 9 .

[0043] [ Figure 11 ]

[0044] Figure 11 Schematic diagrams for explaining a method of manufacturing a semiconductor substrate in Figure 9 and Figure 10 .

[0045] [ Figure 12 ]

[0046] Figure 12 Schematic diagrams for explaining a method of manufacturing a semiconductor substrate in Figure 9 andFigure 10 schematic view of a method of manufacturing a semiconductor substrate.

[0047] [ Figure 13 ]

[0048] Figure 13 schematic view of a method of manufacturing a semiconductor substrate. Figure 9 Figure 10 schematic view of a method of manufacturing a semiconductor substrate.

[0049] [ Figure 14 ]

[0050] Figure 14 schematic view of a method of manufacturing a semiconductor substrate. Figure 9 Figure 10 schematic view of a method of manufacturing a semiconductor substrate.

[0051] [ Figure 15 ]

[0052] Figure 15 schematic view of a second structure example of a pixel region in Figure 9 cut along A-A' in Figure 8 .

[0053] [ Figure 16 ]

[0054] Figure 16 schematic view of a method of manufacturing a semiconductor substrate. Figure 15

[0055] [ Figure 17 ]

[0056] Figure 17 schematic view of a method of manufacturing a semiconductor substrate. Figure 15

[0057] [ Figure 18 ]

[0058] Figure 18 schematic view of a method of manufacturing a semiconductor substrate. Figure 15

[0059] [ Figure 19 ]

[0060] Figure 19 schematic view of a method of manufacturing a semiconductor substrate. Figure 15

[0061] [ Figure 20 ]

[0062] Figure 20 schematic view of a second structure example of a pixel region in Figure 9 cut along A-A' in Figure 8 ​​​​​​Cross-sectional view of a third structure example of the pixel region.

[0063] [ Figure 21 ]

[0064] Figure 21 Cross-sectional view of a third structure example of the pixel region. Figure 9 Figure 8 Cross-sectional view of a third structure example of the pixel region.

[0065] [ Figure 22 ]

[0066] Figure 22 Cross-sectional view of a third structure example of the pixel region. Figure 21

[0067] [ Figure 23 ]

[0068] Figure 23 Cross-sectional view of a third structure example of the pixel region. Figure 21

[0069] [ Figure 24 ]

[0070] Figure 24 Cross-sectional view of a third structure example of the pixel region.

[0071] [ Figure 25 ]

[0072] Figure 25 Cross-sectional view of a third structure example of the pixel region. Figure 8

[0073] [ Figure 26 ]

[0074] Figure 26 Cross-sectional view of a third structure example of the pixel region. Figure 8

[0075] [ Figure 27 ]

[0076] Figure 27 Cross-sectional view of a third structure example of the pixel region. Figure 8

[0077] [ Figure 28 ]

[0078] Figure 28 Cross-sectional view of a third structure example of the pixel region. Figure 8 ​​​​​​​

[0079] [ Figure 29 ]

[0080] Figure 29 is a schematic diagram for explaining a second method of manufacturing a CMOS image sensor in Figure 8 .

[0081] [ Figure 30 ]

[0082] Figure 30 is a schematic diagram for explaining a second method of manufacturing a CMOS image sensor in Figure 8 .

[0083] [ Figure 31 ]

[0084] Figure 31 is a schematic diagram for explaining a second method of manufacturing a CMOS image sensor in Figure 8 .

[0085] [ Figure 32 ]

[0086] Figure 32 is a schematic diagram showing other structure examples of a hollow region around a through silicon via (TSV).

[0087] [ Figure 33 ]

[0088] Figure 33 is a plan view for explaining the arrangement of a hollow region of a CMOS image sensor according to a fourth embodiment.

[0089] [ Figure 34 ]

[0090] Figure 34 is a schematic diagram showing an example of other shapes of a hollow region around an FD wiring in Figure 33 .

[0091] [ Figure 35 ]

[0092] Figure 35 is a plan view showing shape examples of a hollow region formed around a TSV.

[0093] [ Figure 36 ]

[0094] Figure 36 is a block diagram showing a configuration example of an image capturing device as an electronic device according to the present disclosure.

[0095] [ Figure 37 ]

[0096] Figure 37A diagram showing a use example of the CMOS image sensor. DETAILED DESCRIPTION

[0097] Hereinafter, modes for carrying out the present application (hereinafter, referred to as embodiments) will be explained. The explanation will be made in the following order.

[0098] 1. First Embodiment: CMOS Image Sensor Figures 1 to 6

[0099] 2. Second Embodiment: CMOS Image Sensor Figure 7

[0100] 3. Third Embodiment: CMOS Image Sensor Figures 8 to 32

[0101] 4. Fourth Embodiment: CMOS Image Sensor Figures 33 to 35

[0102] 5. Fifth Embodiment: Electronic Device Figure 36

[0103] 6. Use Example of CMOS Image Sensor Figure 37

[0104] <First Embodiment>

[0105] (Configuration Example of CMOS Image Sensor According to First Embodiment)

[0106] Figure 1 A diagram showing a configuration example of a CMOS image sensor as a solid-state image capturing element according to the first embodiment of the present disclosure.

[0107] The CMOS image sensor 50 includes a pixel region 51, pixel drive lines 52, vertical signal lines 53, a vertical drive unit 54, a column processor 55, a horizontal drive unit 56, a system controller 57, a signal processor 58, and a memory unit 59, all of which are formed on a semiconductor substrate (chip) (such as a silicon substrate) not shown.

[0108] The pixel region 51 of the CMOS image sensor 50 includes pixels arranged in a two-dimensional array shape, each of which has a photoelectric conversion element that generates charges in an amount corresponding to the amount of incident light and accumulates the charges within the photoelectric conversion element, so that the CMOS image sensor 50 performs image capturing. Further, in the pixel region 51, for the pixels in the array shape, the pixel drive lines 52 are formed for each row, and the vertical signal lines 53 are formed for each column.

[0109] ​​​​​​The vertical drive unit 54 includes a shift register, an address decoder, or any other unit, and drives each pixel of the pixel region 51 in units of rows. One end of the pixel drive line 52 is connected to an output not shown corresponding to each row of the vertical drive unit 54. Although the detailed configuration of the vertical drive unit 54 is not shown, the vertical drive unit 54 has two scanning systems of a readout scanning system and a reset scanning system.

[0110] The readout scanning system sequentially selects each row so as to read pixel signals from each pixel in units of rows, and outputs the selected signals from the output connected to the pixel drive line 52 of the selected row. In this arrangement, the pixel of the row selected by the readout scanning system is read as a pixel signal, which is an electrical signal of the charge accumulated in the photoelectric conversion element. The readout scanning system supplies the pixel signal to the vertical signal line 53.

[0111] The reset scanning system turns on a reset signal output from the output connected to the pixel drive line 52 of each row, to reset (reset) unnecessary charge from the photoelectric conversion element. By the scanning of the reset scanning system, a so-called electronic shutter operation is sequentially performed for each row. In this case, the electronic shutter operation is an operation of discarding the charge of the photoelectric conversion element and starting new exposure (starting accumulation of charge).

[0112] The column processor 55 includes a signal processing circuit for each column of the pixel region 51. Each signal processing circuit of the column processor 55 performs signal processing such as analog / digital (A / D) conversion processing on the pixel signal output from each pixel of the selected row through the vertical signal line 53. After this signal processing, the column processor 55 temporarily holds these pixel signals.

[0113] The horizontal drive unit 56 includes a shift register, an address decoder, or any other unit, and sequentially selects the signal processing circuits of the column processor 55. Based on the selective scanning of the horizontal drive unit 56, the pixel signal processed by each signal processing circuit of the column processor 55 is sequentially output to the signal processor 58.

[0114] The system controller 57 includes a timing generator or any other unit that generates various timing signals. Based on the respective timing signals generated by the timing generator, the system controller 57 controls the vertical drive unit 54, the column processor 55, and the horizontal drive unit 56.

[0115] The signal processor 58 performs various signal processing on the pixel signal output from the column processor 55. At this time, when necessary, the signal processor 58 stores the intermediate result of the signal processing in the memory unit 59, and refers to this memory unit 59 at the necessary timing. After this signal processing, the signal processor 58 outputs the pixel signal.

[0116] Memory cell 59 includes dynamic random access memory (DRAM) or static random access memory (SRAM).

[0117] (Example of circuit configuration for a pixel)

[0118] Figure 2 To show in Figure 1 A schematic diagram of a circuit configuration example for one pixel in a two-dimensional arrangement of pixels in a pixel region.

[0119] Pixel 90 has a photodiode 91, a transmission transistor 92, an FD 93, a reset transistor 94, an amplification transistor 95, and a selection transistor 96 as photoelectric conversion elements.

[0120] The photodiode 91 generates and accumulates charge based on the amount of light received. The anode terminal of the photodiode 91 is grounded, and it has a cathode terminal connected to the FD 93 via the transfer transistor 92.

[0121] The gate terminal of the transmission transistor 92 is connected to a line in the pixel drive line 52 formed for the pixel 90 to provide a transmission signal. When turned on by the transmission signal, the transmission transistor 92 reads out the charge generated by the photodiode 91 and transfers the charge to the FD 93.

[0122] FD 93 retains the charge read from photodiode 91. The gate terminal of reset transistor 94 is connected to a line in pixel drive line 52 formed for pixel 90 to provide a reset signal. When turned on by this reset signal, reset transistor 94 discharges the charge accumulated in FD 93 to power supply 97 at potential VDD and resets the potential of FD 93.

[0123] The gate terminal of the amplifying transistor 95 is connected to the FD 93, and the amplifying transistor 95 outputs a pixel signal corresponding to the potential of the FD 93 by using the power supply 97.

[0124] The gate terminal of the select transistor 96 is connected to a line in the pixel drive line 52 formed for the pixel 90 to provide a select signal. When activated by the select signal, the select transistor 96 provides the pixel signal output from the amplifying transistor 95 via the vertical signal line 53. Figure 1 The column processor 55.

[0125] FD 93 can be shared among multiple pixels 90.

[0126] (First structural example of a CMOS image sensor)

[0127] Figure 3 This is a schematic diagram illustrating a first structural example of a CMOS image sensor 50.

[0128] As Figure 3 shown in FIG. 1, the CMOS image sensor 50 includes wiring layers 112 stacked on a semiconductor substrate 111 such as a silicon substrate. The wiring layers 112 include, for example, five wiring layers 121 to 125.

[0129] On the semiconductor substrate 111, a photodiode 91, an FD 93, a power supply 97, and the like are formed. Between the photodiode 91 and the FD 93 on the semiconductor substrate 111, a transfer transistor 92 is formed. An amplification transistor 95 is connected to the power supply 97. Further, in the wiring layer 124, a vertical signal line 53 is formed.

[0130] The amplification transistor 95 is connected to an FD wiring 132 formed in the wiring layer 122 through a via 131 formed in the wiring layer 121. Meanwhile, the FD 93 is connected to the FD wiring 132 through the via 131 formed in the wiring layer 121. With this arrangement, the amplification transistor 95 is connected to the FD 93 through the via 131 and the FD wiring 132.

[0131] The power supply 97 is connected to a wiring 133 formed in the wiring layer 122 through a via 131 formed in the wiring layer 121. The transfer transistor 92 is connected to a TRG wiring 134 formed in the wiring layer 122 through the via 131 formed in the wiring layer 121.

[0132] In regions of the wiring layers 121 to 125 where no wiring is formed, an interlayer film 130 such as a SiO film is formed. However, in Figure 3 the example, a region around the FD wiring 132 (the region includes the entire region between the FD wiring 132 and the adjacent wiring 133 and between the FD wiring 132 and the adjacent TRG wiring 134, the wiring 133 and the TRG wiring 134 being formed in the wiring layer 122 other than the wiring layer 122 in which the FD wiring 132 is formed) is a hollow region 135. The FD wiring 132 and the hollow region 135 are in contact with each other.

[0133] When the interlayer film 130 is a SiO film, the dielectric constant of the hollow region (air) 135 is 1 / 4 of that of the interlayer film 130. Therefore, by forming the hollow region 135, the capacitance of the FD wiring 132 is reduced to about 1 / 4 of the capacitance of the FD wiring 132 in the case where the hollow region 135 is not formed.

[0134] Further, because the interlayer film 130 is formed in regions of the wiring layer 122 other than the hollow region 135, the mechanical strength is higher than in the case where the interlayer film 130 is not formed in the entire wiring layer 122.

[0135] (CMOS image sensor: second structure example)

[0136] Figure 4 A schematic diagram showing a second structure example of the CMOS image sensor 50.

[0137] In Figure 4 In the configuration shown, those components that are the same as in Figure 3 The same reference numerals are assigned to those components that are the same as in the first structure example. Repetitive explanation is omitted as appropriate.

[0138] Figure 4 The structure of the CMOS image sensor 50 in Figure 3 The structure of the CMOS image sensor 50 in

[0139] In Figure 4 In the example of FIG. 12, the hollow regions 201 to 206 are formed in the region around the FD wiring 132 (including the entire region between the FD wiring 132 and the wiring 133 and between the FD wiring 132 and the TRG wiring 134) so as not to contact the FD wiring 132, the wiring 133, and the TRG wiring 134.

[0140] (CMOS image sensor of a third structure example)

[0141] Figure 5 A schematic diagram showing a third structure example of the CMOS image sensor 50.

[0142] In Figure 5 In the configuration shown, those components that are the same as in Figure 3 The same reference numerals are assigned to those components that are the same as in the first structure example. Repetitive explanation is omitted as appropriate.

[0143] Figure 5 The structure of the CMOS image sensor 50 in Figure 3 The structure of the CMOS image sensor 50 in

[0144] In Figure 5 In the example of FIG. 12, the hollow regions 201 to 206 are formed in the region around the FD wiring 132 (including the entire region between the FD wiring 132 and the wiring 133 and between the FD wiring 132 and the TRG wiring 134) so as not to contact the FD wiring 132, the wiring 133, and the TRG wiring 134.

[0145] That is, because FD wiring 132 processes analog signals, it is less resistant to noise compared to wiring that processes digital signals, such as vertical signal line 53. Therefore, it is desirable to reduce the capacitance between wiring 133 and wiring 132, which becomes a noise source due to their connection to power supply 97. However, in some cases, it is better to maintain the capacitance between TRG wiring 134 and FD wiring 132.

[0146] Therefore, in Figure 5 In this example, the area surrounding the FD wiring (including only the area between FD wiring 132 and adjacent wiring 133, and the area between FD wiring 132 and adjacent TRG wiring 134) is designated as a hollow area 221. That is, within the areas between FD wiring 132 and adjacent wiring 133, and between FD wiring 132 and adjacent TRG wiring 134, the area excluding the area between FD wiring 132 and TRG wiring 134 becomes the hollow area 221.

[0147] As a result, noise propagation through the capacitance between FD wiring 132 and wiring 133, which becomes a noise source, can be suppressed. Furthermore, the capacitance between TRG wiring 134 and FD wiring 132 can be maintained.

[0148] like Figure 5 As shown, the hollow region 221 may or may not be in contact with FD wiring 132 and wiring 133.

[0149] (A fourth structural example of a CMOS image sensor)

[0150] Figure 6 This is a schematic diagram illustrating a fourth structural example of a CMOS image sensor 50.

[0151] exist Figure 6 In the configuration shown, for the purpose of... Figure 3 Components that are identical to those in the drawing are labeled with the same reference numerals. Where appropriate, repeated descriptions are omitted.

[0152] Figure 6 The structure of the CMOS image sensor 50 in the middle and Figure 3 The difference in the structure is that, in addition to the hollow region 135, a hollow region 241 is also formed.

[0153] exist Figure 6 In this example, the entire area surrounding the vertical signal line 53 is a hollow region 241.

[0154] That is, when the number of vertical signal lines 53 is large, high-speed driving can be performed, but the wiring density increases, and the capacitance of the vertical signal lines 53 increases. As a result, the response deteriorates, the change in the pixel signal increases, and the image quality of the captured image deteriorates. Therefore, in the example of Figure 6 the entire area around the vertical signal line 53 is the hollow area 241. With this arrangement, the capacitance of the vertical signal line 53 can be reduced. As a result, by suppressing the change in the pixel signal during high-speed driving, the image quality of the captured image can be improved.

[0155] In the example of Figure 6 although the entire area around the vertical signal line 53 is the hollow area 241, only a part of the area around the vertical signal line 53 can be the hollow area 241. Further, the hollow areas 201 to 206 or the hollow area 221 can be formed instead of the hollow area 135.

[0156] Further, as shown in Figure 6 the hollow area 241 can or can not be in contact with the wiring adjacent to the vertical signal line 53.

[0157] As described above, in the CMOS image sensor 50, at least a part of the area between the FD wiring 132 and the wiring 133 and between the FD wiring 132 and the TRG wiring 134 is the hollow area 135 (201 to 206, or 221). Therefore, the capacitance of the FD wiring 132 can be reduced, and the charge-voltage conversion efficiency can be improved without changing the wiring layout.

[0158] Further, because the wiring layout does not need to be changed, any system can be used as a system that shares the pixels of the CMOS image sensor 50.

[0159] In the area of the wiring layers 121 to 125, in addition to the wiring and the hollow area 135 (201 to 206, 221, and / or 241), a low dielectric constant film can be formed instead of the inter-wiring film 130.

[0160] <Second Embodiment>

[0161] (Circuit configuration example of pixel of CMOS image sensor according to second embodiment)

[0162] Except for the circuit configuration of each pixel arranged two-dimensionally in the pixel region 51 and the operation of the reset scanning system, the configuration of the CMOS image sensor as a solid-state image capturing element according to the second embodiment of the present disclosure is the same as that of the CMOS image sensor shown in Figure 1 Therefore, hereinafter, only the circuit configuration of each pixel and the operation of the reset scanning system will be described. The description of the configuration of the CMOS image sensor according to the second embodiment will be made by using Figure 1The reference numerals in the drawings describe configuration elements of the pixel different from the CMOS image sensor.

[0163] Figure 7 A schematic diagram showing an example of a circuit configuration of a pixel of a CMOS image sensor according to the second embodiment of the present disclosure.

[0164] In Figure 7 In the configuration shown, the reset signal to be supplied to the reset transistor 303 is turned on by the clearing scan system of the vertical drive unit 54 to clear unnecessary charges from the photodiode 91. Figure 3 The same reference numerals are given to those components that are the same as in the CMOS image sensor. Repetitive explanations are omitted where appropriate.

[0165] Figure 7 The circuit configuration of the pixel 300 in the CMOS image sensor 200 is different from the circuit configuration of the pixel 90 in the CMOS image sensor 100 in that the FDs 301 and 302 are provided instead of the FD 93, and the reset transistors 303 and 304 are provided instead of the reset transistor FD 94. By switching between the on and off states of the reset transistor 304 of the pixel 300, it is possible to switch between the high charge-voltage conversion efficiency mode and the low charge-voltage conversion efficiency mode of the imaging mode. Figure 2 Specifically, in the pixel 300, the gate terminal of the amplification transistor 95 is connected to the FD 301. Between the power supply 97 and the FD 301, the reset transistor 303 and the reset transistor 304 are connected in series via the FD 302.

[0166] Different lines in the pixel drive lines 52 in the corresponding row are connected to the gate terminal of the reset transistor 303 and the gate terminal of the reset transistor 304. Different reset signals are supplied to these gate terminals via the different lines. The reset signal to be supplied to the reset transistor 303 is turned on by the clearing scan system of the vertical drive unit 54 to clear unnecessary charges from the photodiode 91.

[0167] When the image capturing mode is the low charge-voltage conversion efficiency mode, the reset signal to be supplied to the reset transistor 304 is always maintained in the on state by the clearing scan system. Therefore, in this case, when the reset signal supplied to the reset transistor 303 is turned on, the potential of the FD 301 becomes the potential VDD of the power supply 97, and the capacitance of the FD of the pixel 300 becomes only the capacitance of the FD 301. As a result, the charge-voltage conversion efficiency becomes high.

[0168]

[0169] ​On the other hand, when the image capturing mode is the low charge-voltage conversion efficiency mode, the reset signal to be supplied to the reset transistor 304 is always maintained in the off state by the clear scanning system. Therefore, in this case, when the reset signal to be supplied to the reset transistor 303 is turned on, the potential of the FD 302 becomes the potential VDD of the power supply 97, and the capacitance of the FD of the pixel 300 becomes the sum of the capacitances of the FD 301 and the FD 302. As a result, the charge-voltage conversion efficiency becomes low.

[0170] In the pixel 300 configured as described above, the ratio of the charge-voltage conversion efficiency in the high charge-voltage conversion efficiency mode to the charge-voltage conversion efficiency in the low charge-voltage conversion efficiency mode (hereinafter referred to as the mode ratio) is determined based on the proportion of the capacitance of the FD 301 to the sum of the capacitances of the FD 301 and the FD 302. The capacitance of the FD 301 and the capacitance of the FD 302 respectively contribute to the capacitance of an FD wire not shown that is connected to the FD 301 and the capacitance of an FD wire not shown that is connected to the FD 302.

[0171] Therefore, in the pixel 300, in order to obtain a desired mode ratio, a hollow region similar to the hollow regions 135 (201 to 206 or 221) is formed around the FD wire connected to the FD 301 among the two FD wires connected to the FD 301 and the FD 302, for example.

[0172] That is, as described above, by forming a hollow region around the FD wire, the capacitance of the FD wire can be reduced compared to a case where no hollow region is formed. Therefore, the hollow region is formed so that the capacitance of the FD wire connected to the FD 301 becomes the capacitance of the FD wire corresponding to the capacitance of the FD 301, which is determined based on the capacitance of the FD 302 and the desired mode ratio.

[0173] The hollow region can be formed only around the FD wire connected to the FD 302, or the hollow region can be formed around both of the FD wires connected to the FD 301 and the FD 302. Further, the FD 301 and the FD 302 can be shared among a plurality of pixels 300.

[0174] As described above, in the CMOS image sensor according to the second embodiment, two FDs of the FD 301 and the FD 302 are formed. FD wires are connected to the FD 301 and the FD 302. A hollow region is formed around at least one of the FD wires. With this arrangement, the capacitance of the FD wire around which the hollow region is formed is reduced compared to the capacitance of the FD wire around which no hollow region is formed. As a result, the mode ratio can be set to a desired proportion.

[0175] On the other hand, when the hollow region is not formed around the FD wiring connecting the FD 301 and the FD 302, it is necessary to adjust the mode ratio by the wiring layout. However, when the pixel 300 is small, the degree of freedom of the wiring layout is low. Further, there is a restriction on the wiring layout based on the sharing system of the pixel 300. Therefore, it is difficult to adjust the mode ratio by the wiring layout.

[0176] <Third Embodiment>

[0177] (Layout example of each part of CMOS image sensor)

[0178] The configuration of the CMOS image sensor as a solid-state image capturing element according to the third embodiment of the present disclosure is the same as that of the CMOS image sensor 50 shown in Figure 1 Therefore, the explanation of the configuration is omitted. Further, in the subsequent drawings, the same reference numerals are given to the same parts as those of the CMOS image sensor 50. The repeated explanation is omitted as appropriate.

[0179] Figure 8 A view showing a layout example of each part of the CMOS image sensor according to the third embodiment is shown.

[0180] According to Figure 8 In the CMOS image sensor 320 inThe pixel region 51 is provided on the semiconductor substrate 321, and the control circuit 331 and the logic circuit 332 are provided on the semiconductor substrate 322. One or more wiring layers are stacked on each of the semiconductor substrates 321 and 322. The semiconductor substrate 321 is stacked on the semiconductor substrate 322 so that the wiring layers are joined together.

[0181] For example, the control circuit 331 is a circuit including a vertical drive unit 54, a column processor 55, a horizontal drive unit 56, and a system controller 57. For example, the logic circuit 332 is a circuit including a signal processor 58 and a memory unit 59.

[0182] In this case, the number of layers of the semiconductor substrates of the CMOS image sensor 320 is two, but can be one or three or more. Further, the control circuit 331 can be formed on the semiconductor substrate 321 on which the pixel region 51 is provided.

[0183] (First structure example of semiconductor substrate 321)

[0184] Figure 9 A plan view of the first structure example of the pixel region 51 in Figure 8 Figure 10 includes a vertical drive unit 54, a column processor 55, a horizontal drive unit 56, and a system controller 57. For example, the logic circuit 332 is a circuit including a signal processor 58 and a memory unit 59.Figure 9 The sectional view obtained by cutting along A-A' and along Figure 9 A sectional view obtained by cutting along line B'. For ease of explanation, Figure 9 The semiconductor substrate 321 and only the bottommost wiring layer are shown. Figure 10 The semiconductor substrate 321 and only the two bottommost wiring layers are shown.

[0185] like Figure 9 and 10 As shown, in the CMOS image sensor 320, two adjacent pixels 90 in the horizontal direction share FD93. Figure 10 As shown, in the wiring layer 351 at the bottom of the pixel region 51, an FD wiring 361 is formed, which is used to connect the source of the reset transistor 94 between the FD 93 and the gate of the amplification transistor 95.

[0186] like Figure 10 As shown, FD wiring 361 is connected to FD93 through via 361A, to the source of reset transistor 94 formed on semiconductor substrate 321 through via 361B, and to the gate of amplification transistor 95 through via 361C.

[0187] Furthermore, such as Figure 9 As shown, the gate of the transmission transistor 92 is connected to a TRG line 362, which is a line configuring the pixel drive line 52. Further, as... Figure 10 As shown, various wirings 363 are formed in wiring layer 352 on wiring layer 351.

[0188] like Figure 9 and 10 In wiring layer 351, between FD wiring 361 and other wirings not shown, multiple (in) Figure 10 The example in the text is four) hollow regions (air gaps) 364A. Furthermore, multiple ( ) are formed between the FD wiring 361 with different potentials and the semiconductor substrate 321. Figure 10 In the example, this is 6) hollow region 364B. Further, multiple hollow regions 364C are formed in the region above the FD wiring 361 of the wiring layer 352.

[0189] As described above, hollow regions 364A to 364C are formed between the FD wiring 361 and other wirings or electrodes of the semiconductor substrate 321. This arrangement reduces the dielectric constant between the FD wiring 361 and other wirings or electrodes, and also reduces the capacitance of the FD wiring 361. As a result, the charge-to-voltage conversion efficiency is improved.

[0190] Further, the hollow region formed between the FD wiring and the other wiring is not configured by one hollow region but by a plurality of hollow regions 364A. Therefore, even when the distance between the FD wiring 361 and the other wiring is increased to reduce the capacitance of the FD wiring 361, the size of one hollow region can be made small. As a result, the hollow region can be easily formed.

[0191] In the wiring layer 351 and the wiring layer 352, in regions where the FD wiring 361, the TRG wiring 362, and the wiring 363, the hollow regions 364A to 364C, and a transistor such as the transfer transistor 92 are not formed, an insulating film 353 (a wiring layer interlayer film) such as a SiO film is formed. In the third embodiment, the material of the insulating film 353 is silicon dioxide, but is not limited to this material.

[0192] As described above, the insulating film 353 is present between the hollow regions 364A to 364C. Because the hollow regions 364A to 364C are supported by the insulating film 353, the capacitance of the FD wiring 361 can be reduced compared to a case where the hollow regions 364A to 364C are supported by a conductor.

[0193] (Method of manufacturing the first structure example of the semiconductor substrate 321)

[0194] Figures 11 to 14 To show a schematic view of the method of manufacturing the semiconductor substrate 321, the wiring layer 351 and the wiring layer 352 in the Figure 9 and Figure 10 are stacked on the semiconductor substrate 321.

[0195] First, in the first process of the Figure 11 , the photodiode 91, the FD 93, and the transistors (such as the transfer transistor 92, the reset transistor 94, and the amplification transistor 95) configuring the pixel 90 are formed on the semiconductor substrate 321. After that, the insulating film 353 is formed on the semiconductor substrate 321.

[0196] In the second process of the Figure 11 , on the insulating film 353, a resist pattern is formed by applying a resist 381 in a region other than a region corresponding to the hollow region between the FD wiring 361 and the semiconductor substrate 321. After that, the insulating film 353 is etched using the resist pattern. As a result, the insulating film 353 is removed from a region where the resist 381 is not formed, that is, a region corresponding to the hollow region 364B. The size of the hollow region 364B can be controlled by modifying the resist pattern.

[0197] In the third process of the Figure 12In the third process, the photoresist pattern is peeled off, and the insulating film 353 is formed by a weakly covering film formation method. As a result, the hollow region 364B between the FD wiring 361 and the semiconductor substrate 321 is formed. In the fourth process in Figure 12 In the fourth process in the insulating film 353, the wiring 361 and the vias 361A to 361C are formed by a damascene method so that the FD 93 is connected to the source of the reset transistor 94 and the gate of the amplification transistor 95.

[0198] In the fifth process in Figure 13 In the fifth process in the insulating film 353, a photoresist pattern is formed by applying a photoresist 381 to a region other than a region corresponding to the hollow region 364A between the FD wiring 361 and other wirings not shown in the wiring layer 351 in which the FD wiring 361 is formed. Thereafter, the insulating film 353 is etched using the photoresist pattern. As a result, the insulating film 353 is removed from the region corresponding to the hollow region 364A.

[0199] In the sixth process in Figure 13 In the sixth process in the insulating film 353, the photoresist pattern is peeled off, and the insulating film 353 is formed by a weakly covering film formation method. As a result, the hollow region 364A is formed. In the seventh process in Figure 14 In the seventh process, the wiring 363 of the wiring layer 352 is formed by a damascene method.

[0200] In the eighth process in Figure 14 In the eighth process in Figure 11 the second process in Figure 12 the third process in Figure 13 the fifth and sixth processes in

[0201] Specifically, a photoresist pattern is formed on the insulating film 353 by applying a photoresist 381 to a region other than a region corresponding to the hollow region 364C above the FD wiring 361. Thereafter, the insulating film 353 is etched using the photoresist pattern. As a result, the insulating film 353 is removed from the region corresponding to the hollow region 364C. Thereafter, the photoresist pattern is peeled off, and the insulating film 353 is formed by a weakly covering film formation method.

[0202] Figure 11 the thickness (length in the direction perpendicular to the semiconductor substrate 321) of the insulating film 353 to be etched in the second process in Figure 13 the fifth process in Figure 14 the eighth process in

[0203] As described above, because the insulating film 353 above the hollow regions 364A to 364C is formed by a weak-coverage film-forming method, it is possible to form the insulating film 353 above the hollow regions 364A to 364C while maintaining the cavity of the hollow regions 364A to 364C. The mass of the insulating film 353 below the hollow regions 364A to 364C can be the same as or different from the mass of the insulating film 353 above the hollow regions 364A to 364C.

[0204] (Second structural example of semiconductor substrate 321)

[0205] Figure 15 For along Figure 9 A-A' cut Figure 8 A cross-sectional view of a second structural example of the pixel region 51 of the semiconductor substrate 321. For ease of explanation, Figure 15 The semiconductor substrate 321 and only the two bottommost wiring layers are shown.

[0206] exist Figure 15 In the configuration shown, for the purpose of... Figure 10 Components that are identical to those in the drawing are labeled with the same reference numerals. Where appropriate, repeated descriptions are omitted.

[0207] Figure 15 The configuration of the semiconductor substrate 321 on which wiring layers 351 and 352 are stacked is different. Figure 10 The configuration in this case involves forming a barrier membrane 401 to contact the bottom surface of the FD wiring 361 and the hollow region 364A.

[0208] The barrier film 401 is a film such as a SiOC film, used to prevent etching of the insulating film 353 when the FD wiring 361 is formed by the Damascus method.

[0209] (Method description of a second structural example of manufacturing semiconductor substrate 321)

[0210] Figures 16 to 19 To illustrate the manufacturing process, stacked on top of it Figure 15 A schematic diagram of the method of the semiconductor substrate 321 of wiring layer 351 and wiring layer 362.

[0211] First, proceed Figure 11 and 12 The first to third processes are performed, forming a hollow region 364B between the FD wiring 361 and the semiconductor substrate 321. Next, in... Figures 16 to 18 In the first to sixth processes, FD wiring 361 and through holes 361A to 361C are formed by the Damascus method.

[0212] That is, in Figure 16In the first process, the insulating film 353 is formed on the semiconductor substrate 321 on which the hollow region 364B is formed. Thereafter, the insulating film 353 is planarized.

[0213] In the second process, Figure 16 In the second process, the barrier film 401 is formed on the insulating film 353. In the third process, Figure 17 In the third process, the insulating film 353 having a predetermined thickness is formed on the barrier film 401.

[0214] In the fourth process, Figure 17 In the fourth process, regions corresponding to the through holes 361A to 361C of the insulating film 353 below the barrier film 401 are etched, and a region corresponding to the FD wiring 361 of the insulating film 353 above the barrier film 401 is etched. The etching of the insulating film 353 above the barrier film 401 is prevented by the barrier film 401. That is, a bottom surface of the etched region of the insulating film 353 above the barrier film 401 is in contact with an upper surface of the barrier film 401.

[0215] In the fifth process, Figure 18 In the fifth process, the copper (Cu) film 402 is formed on the uppermost insulating film 353. In the sixth process, Figure 18 In the sixth process, unnecessary copper 402 above the insulating film 353 is removed. As a result, the FD wiring 361 and the through holes 361A to 361C are formed.

[0216] Next, in the seventh process, Figure 19 In the seventh process, on the insulating film 353, a resist pattern is formed by applying a resist 381 in a region other than a region corresponding to the hollow region 364A between the FD wiring 361 and other wirings not shown in the wiring layer 351 in which the FD wiring 361 is formed. Thereafter, the insulating film 353 is etched using the resist pattern, and the etching is prevented by the barrier film 401. As a result, the insulating film 353 is removed from a region in which the resist 381 is not formed, that is, a region corresponding to the hollow region 364A.

[0217] Thereafter, the sixth to eighth processes in the first embodiment and the second embodiment are performed, and the hollow region 364A and the hollow region 364C are formed. Figure 13 Figure 14 With the above arrangement, a bottom surface of all the hollow regions 364A is in contact with an upper surface of the barrier film 401. That is, positions in a thickness direction of the bottom surfaces of all the hollow regions 364A are the same. Therefore, variation in depth (length in a direction perpendicular to the semiconductor substrate) of the hollow regions 364A is reduced. As a result, variation in capacitance of the FD wiring 361 is reduced.

[0218] With the above arrangement, a bottom surface of all the hollow regions 364A is in contact with an upper surface of the barrier film 401. That is, positions in a thickness direction of the bottom surfaces of all the hollow regions 364A are the same. Therefore, variation in depth (length in a direction perpendicular to the semiconductor substrate) of the hollow regions 364A is reduced. As a result, variation in capacitance of the FD wiring 361 is reduced.

[0219] In the seventh process, Figure 19 ​In the seventh process, after the etching of the insulating film 353 is prevented by the blocking film 401, further etching can be performed, such as... Figure 20 As shown in the image.

[0220] (Third structural example of semiconductor substrate 321)

[0221] Figure 21 For along Figure 9 A-A' cut Figure 8 A cross-sectional view of a third structural example of pixel region 51 of semiconductor substrate 321. For ease of explanation, Figure 21 The semiconductor substrate 321 and only the two bottommost wiring layers are shown.

[0222] exist Figure 21 In the configuration shown, for the purpose of... Figure 10 Components that are identical to those in the drawing are labeled with the same reference numerals. Where appropriate, repeated descriptions are omitted.

[0223] Figure 21 The configuration of the semiconductor substrate 321 on which wiring layers 351 and 352 are stacked is different. Figure 10 The configuration is such that the lower parts of four consecutive hollow regions 364A are connected together, and the insulating film around the upper part of the hollow region 364A is an insulating film 421, the material of which is different from the material of the insulating film 353.

[0224] For example, the material of insulating film 421 is SiN.

[0225] (Method description of a third structural example of manufacturing semiconductor substrate 321)

[0226] Figure 22 and 23 To illustrate the manufacturing process, stacked on top of it Figure 21 A schematic diagram of the method for wiring layer 351 and wiring layer 352.

[0227] First, proceed Figure 11 and 12 The first to third processes are performed, forming a hollow region 364B between the FD wiring 361 and the semiconductor substrate 321. Next, in... Figure 22 In the first process, an insulating film 421 is formed on the insulating film 353. Then, FD wiring 361 and through holes 361A to 361C are formed in the insulating film 353 and the insulating film 421 to make contact with FD93 by the damascus method.

[0228] Next, in Figure 22 In the second process, a photoresist pattern is formed on the insulating film 421 by coating a photoresist 381 in an area other than the area corresponding to the hollow region 364A.

[0229] Subsequently, insulating film 353 and insulating film 421 are etched using the photoresist pattern. As a result, insulating film 353 and insulating film 421 are removed from the area where photoresist 381 is not formed (i.e., the area corresponding to hollow region 364A).

[0230] exist Figure 23 In the third process, isotropic etching of insulating films 353 and 421 is performed under the condition that the etching rate of insulating film 353 becomes greater than that of insulating film 421. As a result, only insulating film 353 is etched, and the lower parts of the four hollow regions 364A are connected together.

[0231] exist Figure 23 In the fourth process, the photoresist pattern is stripped, and an insulating film 353 is formed using a weak-coverage film deposition method. In this case, although the lower portion of the hollow region 364A has a large size and the upper portion has a small size, the hollow region 364A closes before the material of the insulating film 353 reaches the lower portion. As a result, the cavity of the hollow region 364A is preserved. Afterwards, [further processing is performed]. Figure 14 The seventh and eighth processes in the process form a hollow region 364C.

[0232] like Figure 24 As shown, in a manner similar to that applied to hollow region 364A, an insulating film 421 can be formed around the upper portion of hollow region 364B, and the lower portions of hollow regions 364B can be connected together. Further, the lower portion of each of hollow regions 364A to 364C can be larger than the upper portion of each of hollow regions 364A to 364C, and the lower portions of hollow regions 364A to 364C are not connected together.

[0233] (The first method for manufacturing CMOS image sensors)

[0234] Figures 25 to 27 For the purpose of illustrating manufacturing Figure 8 A schematic diagram of a first method using a CMOS image sensor 320 is shown. By using... Figures 11 to 14 The semiconductor substrate 321 manufactured by the method described herein is bonded to the semiconductor substrate 322 to manufacture a CMOS image sensor 320.

[0235] In passing Figures 11 to 14 After fabricating a semiconductor substrate 321 on which wiring layers 351 and 352 are stacked, the wiring layer 431 is further stacked on the semiconductor substrate 321. Then, in... Figure 25In the first process, a photoresist pattern is formed on the insulating film 353 of the wiring layer 352 by coating photoresist 381 around the area outside the pixel region 51 where the TSV 452 will be formed. Then, the insulating film 353 is etched using this photoresist pattern. With this arrangement, the insulating film 353 is removed from the areas where the photoresist 381 is not formed (i.e., the area around the region where the TSV 452 will be formed).

[0236] exist Figure 25 In the second process, the photoresist pattern is stripped, and an insulating film 353 is formed by a weak-coverage film deposition method. As a result, a hollow region 432 is formed in the area surrounding the region where the TSV 452 (connection portion) will be formed.

[0237] exist Figure 26 In the third process, semiconductor substrate 321 and semiconductor substrate 322 are bonded together.

[0238] Specifically, in Figure 26 In one example, four wiring layers 441 to 444, in which various wirings 440 are formed, are stacked on a semiconductor substrate 322. An insulating film 445 is formed in the regions in which the wirings 440 and the like are not formed in the wiring layers 441 to 444.

[0239] The wiring 440 of the uppermost wiring layer 444 is made of aluminum (Al), for example. Unlike the wiring 440 of the uppermost wiring layers 441 to 443, which are made of copper (Cu), the wiring 440 of the uppermost wiring layers 441 to 443 are made of copper (Cu). The semiconductor substrate 321 is bonded to the semiconductor substrate 322 such that the uppermost wiring layer 431 of the semiconductor substrate 321 is bonded to the uppermost wiring layer 444 of the semiconductor substrate 322.

[0240] After semiconductor substrates 321 and 322 are bonded together, an insulating film 451 is formed on the surface of the wiring layer 351 on which semiconductor substrates 321 are stacked. Further, color filters, on-chip lenses, etc. (not shown), are formed in the region corresponding to the pixel region 51 on the surface of the wiring layer 351 on which semiconductor substrates 321 are stacked. Further, after bonding, semiconductor substrates 321 and 322 are thinned. With this arrangement, a CMOS image sensor 320 is formed at a desired thickness.

[0241] Next, in Figure 27 In the fourth process, the regions of insulating film 451, semiconductor substrate 321, insulating film 353, and insulating film 445 in which TSV 452 is formed are etched, and TSV 452 is formed. TSV 452 is connected to wiring 440 of wiring layer 444 and wiring 363 of wiring layer 351, so that semiconductor substrate 321 and semiconductor substrate 322 are electrically connected to each other.

[0242] (Second method of manufacturing CMOS image sensor)

[0243] Figures 28 to 31 A schematic diagram for illustrating a second method of manufacturing a CMOS image sensor 320 in FIG. 12A is shown. The sensor is manufactured by joining a semiconductor substrate 321 manufactured by the method in FIG. 11A with a semiconductor substrate 322. Figure 8 Figures 11 to 14 After the semiconductor substrate 321 on which the wiring layer 351 and the wiring layer 352 are stacked is manufactured by the manufacturing method in FIG. 11A, a wiring layer 431 is further stacked. Thereafter, in the first process of FIG. 12A, the semiconductor substrate 321 is joined with the semiconductor substrate 322 so that the uppermost wiring layer 352 of the semiconductor substrate 321 is joined together with the uppermost wiring layer 442 of the semiconductor substrate 322.

[0244] After the semiconductor substrate 321 is joined together with the semiconductor substrate 322, an insulating film 451 is formed on a surface facing a surface on which the wiring layer 351 of the semiconductor substrate 321 is stacked. Further, in a region corresponding to the pixel region 51 of the surface facing the surface on which the wiring layer 351 of the semiconductor substrate 321 is stacked, a color filter, an on-chip lens, and the like, which are not shown, are formed. Further, after the joining, the semiconductor substrate 321 and the semiconductor substrate 322 are thinned. With this arrangement, the CMOS image sensor 320 is formed in a desired thickness. Figures 11 to 14 Figure 28 In the second process of FIG. 12A, on the insulating film 451, a photoresist pattern is formed by applying a photoresist 381 in a region of the non-pixel region 51 around a region in which the TSV 452 is to be formed. Then, the semiconductor substrate 321, the insulating film 451, and the insulating film 353 are etched using the photoresist pattern. With this arrangement, the semiconductor substrate 321, the insulating film 451, and the insulating film 353 are removed from a region in which the photoresist 381 is not formed, i.e., a region around the region in which the TSV 452 is to be formed.

[0245] In the third process of FIG. 12A, the photoresist pattern is peeled off, and the insulating film 451 is formed by a weakly covering film formation method. As a result, a hollow region 432 that penetrates the semiconductor substrate 321 is formed in a region around the region in which the TSV 452 is to be formed.

[0246] In the fourth process of FIG. 12A, a TSV 452 is formed in the hollow region 432. With this arrangement, the CMOS image sensor 320 is manufactured. Figure 29 In the fifth process of FIG. 12A, the photoresist 381 is peeled off, and the insulating film 451 is formed by a weakly covering film formation method. As a result, a hollow region 432 that penetrates the semiconductor substrate 321 is formed in a region around the region in which the TSV 452 is to be formed.

[0247] Figure 30 In the sixth process of FIG. 12A, a TSV 452 is formed in the hollow region 432. With this arrangement, the CMOS image sensor 320 is manufactured.

[0248] In the seventh process of FIG. 12A, the photoresist 381 is peeled off, and the insulating film 451 is formed by a weakly covering film formation method. As a result, a hollow region 432 that penetrates the semiconductor substrate 321 is formed in a region around the region in which the TSV 452 is to be formed. Figure 31 ​​​In the fourth process, a region of the insulating film 451 in which the TSV 452 is to be formed, the semiconductor substrate 321, the insulating film 353, and the insulating film 445 are etched, and the TSV 452 is formed.

[0249] As shown in FIG. 4B, in the third process, the insulating film 451 can be buried in the hollow region 432 in the semiconductor substrate 321 when the insulating film 451 is formed. Further, the TSV 452 can connect the wiring 440 of the wiring layer 444 to the wiring 363 of the wiring layer 351 through one or two vias. Figure 32

[0250] As described above, by forming the hollow region 432 around the TSV 452, the capacitance between the TSV 452 and the potential portion (e.g., GND) of the semiconductor substrate 321 can be reduced.

[0251] In the third embodiment, the number of the hollow regions 364A to 364C and the hollow region 432 can be any number equal to or more than 1. The hollow regions 364A to 364C and the hollow region 432 can have any shape in which an insulating film is not formed by a weakly covered film formation method.

[0252] <Fourth Embodiment>

[0253] (Explanation of Arrangement of Hollow Regions in Pixel Region)

[0254] The configuration and structure of the CMOS image sensor as a solid-state image capturing element according to the fourth embodiment of the present disclosure is the same as that of the CMOS image sensor 320 except that the CMOS image sensor in the fourth embodiment has the FD 93 shared between 2 (horizontal) x 2 (vertical) pixels 90 and the arrangement and shape of the hollow regions 364A to 364C and the hollow region 432 are different.

[0255] Therefore, only the arrangement and shape of the hollow regions 364A to 364C and the hollow region 432 are explained below. Further, in the following drawings, the same reference numerals are given to those components of the CMOS image sensor 320 as appropriate. Repetitive explanations are omitted as appropriate.

[0256] Figure 33 is a plan view for explaining the arrangement of the hollow regions in the pixel region 51 of the CMOS image sensor according to the fourth embodiment. Figure 33 is a plan view of the pixel region 51 of the semiconductor substrate 321 on which the wiring layer 351, the wiring layer 352, and the wiring layer 431 are stacked, as viewed from the side on which the wiring layer 431 is located.

[0257] Figure 33 ​In the diagram, only semiconductor substrate 321 and wiring layer 351 are shown, and Figure 33 B in the diagram only shows the semiconductor substrate 321 and the wiring layer 431.

[0258] like Figure 33 As shown in Figure A, in the CMOS image sensor according to the fourth embodiment, a hollow region 472 is formed between the FD wiring 361 and other wirings such as wiring 471 in the same wiring layer 351. This arrangement reduces the dielectric constant between the FD wiring 361 and other wirings in the wiring layer 351. As a result, the charge-to-voltage conversion efficiency is improved.

[0259] Furthermore, such as Figure 33 As shown in Figure B, in wiring layer 431, a hollow region 474 is formed between the vertical signal line 53 and other wirings such as wiring 473 in the same wiring layer 431. This arrangement reduces the dielectric constant between the vertical signal line 53 and other wirings in wiring layer 431, and also reduces the capacitance of the vertical signal line 53. As a result, delays in pixel signal readout can be prevented.

[0260] exist Figure 33 In Example A, two hollow regions 472 are formed between FD wiring 361 and other wirings. The number of hollow regions 472 can be any number equal to or greater than one. Similarly, the number of hollow regions 474 formed between vertical signal line 53 and other wirings can be any number equal to or greater than one.

[0261] exist Figure 33 In this example, when viewed from above the wiring layer 431, each of the hollow regions 472 and 474 appears rectangular (strip-shaped). However, each of the hollow regions 472 and 474 can have any shape.

[0262] (Example of the shape of a hollow region within a pixel area)

[0263] Figure 34 The plan view of the pixel region 51 of the semiconductor substrate 321 on which the wiring layer 352 is stacked is shown from the side where the wiring layer 351 is located, which shows other examples of the shape of the hollow region 472.

[0264] like Figure 34 As shown in A, when viewed from above the wiring layer 351, each of the hollow regions 472 can be circular (hole-shaped), or for example... Figure 34 As shown in B, it can be in the form of a mesh (net shape).

[0265] Although not shown, each of the hollow regions 474 may have the same shape as the hollow region 472.

[0266] (Non-pixel region hollow region shape example)

[0267] Figure 35 A plan view of the CMOS image sensor according to the fourth embodiment as viewed from above the insulating film 451 shows an example of the shape of each hollow region 432 formed around the TSV 452 that is not in the pixel region 51 of the CMOS image sensor.

[0268] As shown in A in FIG. 34, Figure 35 each hollow region 432 can appear as a ring of a rectangular shape, or for example, as shown in B in FIG. 34, can appear as a ring of a circular shape as viewed from above the insulating film 451. Figure 35 Further, as shown in C in FIG. 34, each hollow region 432 can appear as a straight line (strip shape). Figure 35

[0269] In the examples of A and C in FIG. 34, the number of hollow regions 432 formed around the TSV 452 is two, and in the example of B in FIG. 34, the number is one. However, the number of hollow regions 432 is not limited to these numbers, and can be any number. Figure 35 Figure 35 The shapes of the hollow regions 432, the hollow regions 472, and the hollow regions 474 are not limited to the shapes shown in and

[0270] as long as the hollow regions have shapes in which the insulating film is not formed by the weakly covering film formation method. Figure 34 Figure 35 Further, in the fourth embodiment, hollow regions can be formed in the lower and upper portions of the FD wiring 361 in a similar manner to that in the third embodiment.

[0271] Further, in the third embodiment, hollow regions can be formed around the vertical signal line 53 in a similar manner to that in the fourth embodiment. In the third and fourth embodiments, the regions in which the hollow regions are formed can be formed around wirings other than the FD wiring 361 and the vertical signal line 53, for which it is desired to reduce the capacitance.

[0272] Further, in the third embodiment, hollow regions can be formed around the vertical signal line 53 in a similar manner to that in the fourth embodiment. In the third and fourth embodiments, the regions in which the hollow regions are formed can be formed around wirings other than the FD wiring 361 and the vertical signal line 53, for which it is desired to reduce the capacitance.

[0273] In the third and fourth embodiments, hollow regions can be formed in the semiconductor substrate 322.

[0274] <005TH EMBODIMENT>

[0275] (Configuration example of image capturing apparatus according to one embodiment)

[0276] Figure 36 ​​FIG. 1 is a block diagram showing a configuration example of an image capturing device according to an embodiment of the present disclosure.

[0277] Figure 36 The image capturing device 1000 in FIG. 1 is a video camera, a digital still camera, or the like. The image capturing device 1000 includes a lens group 1001, a solid-state image capturing element 1002, a digital signal processing (DSP) circuit 1003, a frame memory 1004, a display unit 1005, a recording unit 1006, an operation unit 1007, and a power supply unit 1008. The DSP circuit 1003, the frame memory 1004, the display unit 1005, the recording unit 1006, the operation unit 1007, and the power supply unit 1008 are connected to each other via a bus 1009.

[0278] The lens group 1001 captures light (image light) that has entered from an object and forms an image on an image capturing surface of the solid-state image capturing element 1002. The solid-state image capturing element 1002 includes the CMOS image sensor described above. The solid-state image capturing element 1002 converts incident light of the number (in pixels) of the image formed on the image capturing surface by the lens group 1001 into an electric signal and supplies the electric signal to the DSP circuit 1003 as a pixel signal.

[0279] The DSP circuit 1003 performs predetermined image processing on the pixel signal supplied from the solid-state image capturing element 1002, supplies the processed image signal in units of frames to the frame memory 1004, and temporarily stores the image signal in the frame memory 1004.

[0280] The display unit 1005 includes, for example, a flat panel display device such as a liquid crystal panel or an organic electroluminescence (EL) panel, and displays an image on the basis of the pixel signal in units of frames temporarily stored in the frame memory 1004.

[0281] The recording unit 1006 includes, for example, a digital versatile disc (DVD), a flash memory, or the like, reads out the pixel signal in units of frames temporarily stored in the frame memory 1004, and records the pixel signal.

[0282] The operation unit 1007 issues an operation instruction on various functions of the image capturing device 1000 under the operation of a user. The power supply unit 1008 appropriately supplies power to the DSP circuit 1003, the frame memory 1004, the display unit 1005, the recording unit 1006, and the operation unit 1007.

[0283] An electronic device to which the present technology is applied can be a device that uses a CMOS image sensor in an image capturing unit (photoelectric conversion unit). In addition to the image capturing device 1000, the present technology can be applied to a portable terminal device having an image capturing function and a copier that uses a CMOS image sensor in an image reading unit.

[0284] (Usage examples of CMOS image sensor)

[0285] Figure 37 A schematic diagram showing the above usage examples of CMOS image sensor.

[0286] For example, as described above, the above CMOS image sensor can be used in various situations, such as for sensing visible light, infrared light, ultraviolet light, X-ray light.

[0287] - A device provided for capturing images for viewing, such as a digital camera, and a mobile device having a camera function.

[0288] - A device provided for transportation, such as a vehicle-mounted sensor that takes pictures of the front, rear, surroundings, and interior of a vehicle for safe driving such as automatic stopping and for recognizing the state of a driver, a monitoring camera that monitors a vehicle and a road while driving, and a distance measuring sensor that measures the distance between vehicles.

[0289] - A device provided for a household appliance such as a television, a refrigerator, an air conditioner, for taking pictures of the user's posture to operate the household appliance according to the posture.

[0290] - A device provided for medical and health care, such as an endoscope that performs angiography by receiving infrared light and a device.

[0291] - A device provided for security, such as a monitoring camera for preventing crime and a camera for personnel authentication.

[0292] - A device provided for cosmetic use, such as a skin measurement device that captures an image of the skin and a microscope that captures an image of the scalp.

[0293] - A device provided for sports, such as a sports camcorder and a wearable camera for sports applications.

[0294] - A device provided for agriculture, such as a camera for monitoring the state of a field and crops.

[0295] The effects described in this specification are illustrative and are not limited. There are other effects.

[0296] Further, the embodiments of the present disclosure are not intended to be limited to the above-described embodiments, and various modifications are possible without departing from the scope of the present disclosure.

[0297] The present disclosure can also be applied to a charge-coupled device (CCD) image sensor, not limited to a CMOS image sensor.

[0298] The present disclosure can also be configured as follows. (1)

[0300] A solid-state image capturing element in which at least a portion of a region between a floating diffusion wiring connected to a floating diffusion node and a wiring other than the floating diffusion wiring is a hollow region. (2)

[0302] The solid-state image capturing element according to (1), in which the floating diffusion wiring and the hollow region are in contact with each other. (3)

[0304] The solid-state image capturing element according to (1), in which the floating diffusion wiring and the hollow region are not in contact with each other. (4)

[0306] The solid-state image capturing element according to any one of (1) to (3), in which the hollow region is a region other than a region between the floating diffusion wiring and a TRG wiring connected to a transfer transistor in the region between the floating diffusion wiring and the wiring other than the floating diffusion wiring. (5)

[0308] The solid-state image capturing element according to any one of (1) to (4), in which at least a portion of a periphery of a vertical signal line is a hollow region. (6)

[0310] The solid-state image capturing element according to any one of (1) to (5), in which the floating diffusion wiring is one of a plurality of floating diffusion wirings connected to a plurality of floating diffusion nodes from a ground. (7)

[0312] The solid-state image capturing element according to (1), in which a number of the hollow regions is plural. (8)

[0314] The solid-state image capturing element according to (1) or (7), in which an insulating film is formed in a region other than the hollow region in the region between the floating diffusion wiring and the wiring other than the floating diffusion wiring. (9)

[0316] The solid-state image capturing element according to (8) above, wherein a material of the insulating film formed around the upper portion of the hollow region and a material of the insulating film formed around the lower portion of the hollow region are different. (10)

[0318] The solid-state image capturing element according to (9) above, wherein a size of the lower portion of the hollow region is larger than a size of the upper portion. (11)

[0320] The solid-state image capturing element according to (10) above, wherein the number of the hollow regions is plural, and the lower portions of the plural hollow regions are connected together, and the upper portions thereof are connected together. (12)

[0322] The solid-state image capturing element according to one of (1) and (7) to (11) above, wherein at least a portion of a region between the floating diffusion wiring and the semiconductor substrate in contact with the floating diffusion wiring is a hollow region. (13)

[0324] The solid-state image capturing element according to one of (1) and (7) to (11) above, comprising:

[0325] a first semiconductor substrate on which the floating diffusion wiring, the wiring other than the floating diffusion wiring, and a wiring layer in which the hollow region is formed are stacked;

[0326] a second semiconductor substrate bonded to the first semiconductor substrate; and

[0327] a connection portion that electrically connects the first semiconductor substrate to the second semiconductor substrate, wherein a hollow region is formed around the connection portion of the wiring layer. (14)

[0329] The solid-state image capturing element according to (13) above, wherein the hollow region formed around the connection portion of the wiring layer penetrates the first semiconductor substrate. (15)

[0331] An electronic apparatus comprising:

[0332] a solid-state image capturing element, wherein at least a portion of a region between a floating diffusion wiring connected to a floating diffusion node and a wiring other than the floating diffusion wiring is a hollow region. (16)

[0334] A solid-state image capturing element comprising:

[0335] a first semiconductor substrate;

[0336] a second semiconductor substrate bonded to the first semiconductor substrate; and

[0337] a connection portion electrically connecting the first semiconductor substrate to the second semiconductor substrate, wherein a hollow region is formed around the connection portion of the wiring layer stacked on the first semiconductor substrate.

[0338] [List of Reference Signs]

[0339] 50 CMOS image sensor, 53 vertical signal line, 92 transfer transistor, 93 FD, 132 FD wiring, 133 wiring, 134 TRG wiring, 135, 201 to 206, 221, 241 hollow region, 301, 302 FD, 320 CMOS image sensor, 321, 322 semiconductor substrate, 351, 352 wiring layer, 353 insulating film, 361 FD wiring, 364A to 364C hollow region, 421 insulating film, 432 hollow region, 452 TSV, 1000 image capturing apparatus, 1002 solid-state image capturing element.

Claims

1. A semiconductor device comprising: a first silicon layer; a second silicon layer bonded to the first silicon layer; a first wiring layer stacked on the first silicon layer; and a second wiring layer stacked on the second silicon layer, wherein a first wiring in the first wiring layer is connected to a connection portion, and a second wiring in the second wiring layer is connected to the connection portion, the first wiring layer and the second wiring layer are configured to electrically connect the first silicon layer to the second silicon layer through the connection portion, wherein a first hollow region surrounds the connection portion in the first wiring layer, and an insulating film is located between the first silicon layer and the first hollow region. The insulating film also surrounds the first hollow region.

2. The semiconductor device according to claim 1, wherein 3. The semiconductor device according to claim 2, wherein a second hollow region is formed in the first wiring layer, and the insulating film is also located between the first hollow region and the second hollow region. The first silicon layer includes a floating diffusion node.

4. The semiconductor device according to any one of Claims 1 to 3, wherein 5. The semiconductor device according to claim 4, wherein the first wiring layer further includes: a third hollow region, a fourth hollow region, and a third wiring connected to the floating diffusion node, and the third wiring is located between the third hollow region and the fourth hollow region in a first direction. The third wiring does not contact each of the first hollow region, the third hollow region, and the fourth hollow region.

6. The semiconductor device according to claim 5, wherein 7. The semiconductor device according to claim 5, wherein the first wiring layer further includes a transfer transistor, and the transfer transistor is located between the third hollow region and the first silicon layer in a second direction perpendicular to the first direction.

8. The semiconductor device according to claim 5, wherein the third wiring contacts the third hollow region and the fourth hollow region.

9. The semiconductor device according to claim 5, wherein the third hollow region includes a plurality of hollow regions aligned in the first direction.

10. The semiconductor device according to claim 5, wherein the fourth hollow region includes a plurality of hollow regions aligned in the first direction. ​

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