A manufacturing method of a U-gate trench type SiC MOSFET

Abstract

The application provides a manufacturing method of U-shaped gate trench type SiC MOSFET, comprising the following steps: forming a drift layer on a silicon carbide substrate, forming a barrier layer on the drift layer, etching the barrier layer, ion implantation, and forming a conductive area; re-forming the barrier layer, etching the barrier layer, ion implantation, and forming a masking layer; restoring the area above the masking layer to the same impurity concentration as the drift layer through impurity compensation; etching to form a gate area, oxidizing the gate area, and forming a gate insulating layer; depositing a gate; re-forming the barrier layer, etching the barrier layer, ion implantation, and respectively forming a pinch-off area, a source area, a source metal layer, and a gate metal layer; removing all the barrier layers, and depositing a drain metal layer on the silicon carbide substrate, so as to reduce the on-resistance and improve the gate oxide reliability.

Description

TECHNICAL FIELD

[0001] The application relates to a manufacturing method of a U-shaped gate trench type SiC MOSFET. BACKGROUND

[0002] SiC devices are widely concerned and researched due to the superior physical properties of silicon carbide (SiC) materials. High-temperature and high-power electronic devices have high input impedance, fast switching speed, high working frequency, high temperature resistance and high voltage resistance, and are widely used in switching power supplies, high-frequency heating, automobile electronics and power amplifiers.

[0003] However, due to the particularly high critical breakdown field strength and poor gate oxide quality of SiC, in the U-shaped gate type SiC MOSFET, the gate oxide is at the bottom end of the U-shaped gate, the electric field is concentrated at the minimum angle, the electric field strength is extremely large, and therefore the problem of excessively large electric field strength at the bottom end of the U-shaped gate needs to be solved. Meanwhile, the reduction of on-resistance is the eternal pursuit of power MOSFETs, and each method for reducing on-resistance should be valued. SUMMARY

[0004] The technical problem to be solved by the application is to provide a manufacturing method of a U-shaped gate trench type SiC MOSFET, which reduces the on-resistance and improves the gate oxide reliability.

[0005] The application is implemented as follows: a manufacturing method of a U-shaped gate trench type SiC MOSFET, comprising the following steps:

[0006] Step 1: forming a drift layer on a silicon carbide substrate, forming a barrier layer on the drift layer, etching the barrier layer to form a conductive region through hole, and performing ion implantation on the drift layer through the through hole to form a conductive region;

[0007] Step 2: re-forming the barrier layer, etching the barrier layer to form a mask layer through hole, and performing ion implantation on the drift layer through the mask layer through hole to form a mask layer;

[0008] Step 3: performing ion implantation through the mask layer through hole, and restoring the region above the mask layer to the same impurity concentration as the drift layer by impurity compensation;

[0009] Step 4: etching to form a gate region, oxidizing the gate region to form a gate insulating layer;

[0010] Step 5: depositing a gate;

[0011] Step 6: re-forming the barrier layer on the drift layer, etching the barrier layer to form a pinch-off region through hole, and performing ion implantation on the drift layer through the pinch-off region through hole to form a pinch-off region;

[0012] Step 7: Re-form a barrier layer on the drift layer, and etch the barrier layer to form source region vias. Perform ion implantation on the drift layer through the source region vias to form the source region.

[0013] Step 8: Re-form a barrier layer on the drift layer, and etch the barrier layer to form a source region metal via. Deposit the source region through the source region metal via to form a source metal layer.

[0014] Step 9: Reform the barrier layer and etch the gate metal deposition area into the barrier layer to deposit the gate metal layer;

[0015] Step 10: Remove all barrier layers and deposit a drain metal layer on the silicon carbide substrate.

[0016] Furthermore, the gate insulating layer is U-shaped.

[0017] Furthermore, the pinch-off region is p-type doped, and the doping concentration of the pinch-off region is less than the doping concentration of the source region but higher than the doping concentration of the drift layer.

[0018] The advantages of this invention are:

[0019] 1. The U-shaped masking layer under the gate of the U-shaped gate trench SiC MOSFET device is located at the sharpest point of the gate oxide angle, i.e. the point where the gate oxide electric field strength is the highest. This masking layer can effectively reduce the electric field strength at the trench corner and improve the gate oxide reliability.

[0020] Second, on both sides of the masking layer, there are n-type heavily doped conductive regions. These conductive regions can form low-resistance conductive channels after the MOS transistor is turned on, which can effectively reduce the on-resistance of the MOS.

[0021] Third, the conductive channel of this device is a high-concentration n-type conductive region, and its conductive channel is relatively narrow, so the lateral dimension can be further reduced, thereby reducing the cell area. Attached Figure Description

[0022] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0023] Figure 1 This invention provides a manufacturing process for a U-shaped gate trench SiC MOSFET. Figure 1 .

[0024] Figure 2 This invention provides a manufacturing process for a U-shaped gate trench SiC MOSFET. Figure 2 .

[0025] Figure 3 This invention provides a manufacturing process for a U-shaped gate trench SiC MOSFET. Figure 3 .

[0026] Figure 4 This invention provides a manufacturing process for a U-shaped gate trench SiC MOSFET. Figure 4 .

[0027] Figure 5 This invention provides a manufacturing process for a U-shaped gate trench SiC MOSFET. Figure 5 .

[0028] Figure 6 This invention provides a manufacturing process for a U-shaped gate trench SiC MOSFET. Figure 6 .

[0029] Figure 7 This invention provides a manufacturing process for a U-shaped gate trench SiC MOSFET. Figure 7 .

[0030] Figure 8 This invention provides a manufacturing process for a U-shaped gate trench SiC MOSFET. Figure 8 .

[0031] Figure 9 This invention provides a manufacturing process for a U-shaped gate trench SiC MOSFET. Figure 9 .

[0032] Figure 10 This invention provides a manufacturing process for a U-shaped gate trench SiC MOSFET. Figure 10 .

[0033] Figure 11 This is a schematic diagram of the structure of a U-shaped gate trench SiC MOSFET according to the present invention. Detailed Implementation

[0034] like Figures 1 to 10 As shown, the present invention discloses a method for manufacturing a U-shaped gate trench SiC MOSFET, comprising the following steps:

[0035] Step 1: A drift layer 2 is formed on a silicon carbide substrate 1, a barrier layer 9 is formed on the drift layer 2, and a conductive via is formed by etching the barrier layer 9. Ions are implanted into the drift layer 2 through the via to form a conductive region 22.

[0036] Step 2: Reform the barrier layer 9, and etch the barrier layer to form a masking layer via. Perform ion implantation on the drift layer through the masking layer via to form a masking layer 21.

[0037] Step 3: Ion implantation is performed through the vias of the masking layer 21 to restore the region above the masking layer to the same impurity concentration as the drift layer through impurity compensation;

[0038] Step 4: Etch to form the gate region, oxidize the gate region, and form a gate insulating layer 23, wherein the gate insulating layer 23 is U-shaped;

[0039] Step 5: Deposit gate 3;

[0040] Step 6: Re-form the barrier layer 9 on the drift layer 2, and etch the barrier layer to form a pinch-off region via. Perform ion implantation on the drift layer through the pinch-off region via to form a pinch-off region 5. The pinch-off region 5 is p-type doped. The doping concentration of the pinch-off region 5 is less than the doping concentration of the source region 4 and higher than the doping concentration of the drift layer 2.

[0041] Step 7: Re-form the barrier layer 9 on the drift layer 2, and etch the barrier layer to form source region vias. Perform ion implantation on the drift layer 2 through the source region vias to form the source region 4.

[0042] Step 8: Re-form the barrier layer 9 on the drift layer 2, and etch the barrier layer to form a source region metal via. Deposit the source region through the source region metal via to form the source metal layer 6.

[0043] Step 9: Reform the barrier layer 9 and etch the gate metal deposition area on the barrier layer 9 to deposit the gate metal layer 7;

[0044] Step 10: Remove all barrier layers 9 and deposit drain metal layer 8 on silicon carbide substrate 1.

[0045] like Figure 11 As shown, the U-shaped gate trench SiC MOSFET manufactured by the above manufacturing method includes:

[0046] A silicon carbide substrate 1,

[0047] A drift layer 2 is disposed on the upper side of the silicon carbide substrate 1. The drift layer 2 is provided with a masking layer 21, a conductive region 22 and a gate insulating layer 23. The bottom of the conductive region 22 and the bottom of the masking layer 21 are both connected to the drift layer 2. The side of the masking layer 21 is connected to the conductive region 22. The side of the conductive region 22 is connected to the drift layer 2. The drift layer 2 is provided with a U-shaped groove 24. The bottom of the U-shaped groove 24 is connected to the top of the masking layer 21. The gate insulating layer 23 is disposed on the U-shaped groove 24.

[0048] A gate 3, the gate 3 being connected to the gate insulating layer 23;

[0049] A source region 4 is provided, the bottom of which is connected to the conductive region 22 and the drift layer 2 respectively, and one side of the source region 4 is connected to the gate insulating layer 23, which is U-shaped;

[0050] A pinch-off region 5 is provided, the bottom of which is connected to the drift layer 2, and one side of which is connected to the source region 4. The pinch-off region 5 is p-type doped, and the doping concentration of the pinch-off region 5 is less than that of the source region 4 and higher than that of the drift layer 3.

[0051] A source metal layer 6 is provided, which is connected to the top of the source region 4 and the top of the pinch-off region 5.

[0052] A gate metal layer 7 is connected to the gate 3;

[0053] And a drain metal layer 8, which is connected to the underside of the silicon carbide substrate 1.

[0054] At the lower end of the gate insulating layer 23 (typically an oxide layer, SiO2), there is a P+ masking layer 21 in the minimum angle region. This masking layer 21 reduces the electric field strength at the lower end of the gate dielectric and improves the reliability of the gate insulating layer 23.

[0055] Conductive regions 22 are provided on the left and right sides of the masking layer 21. The conductive regions 22 are in contact with the pinch-off region 5. When the pinch-off region 5 is inverted by the gate control, a low-resistance conductive path is directly formed. The source region 4 is also heavily doped with n-type, realizing ohmic contact between the source region 4 and the source metal layer 6.

[0056] The masking layer 21 surrounds the bottom end of the gate insulating layer 23 where the electric field is highest, effectively reducing the electric field strength of the gate oxide and improving gate oxide reliability. A heavily doped n-type conductive region is created in a narrow area below the pinch-off region 5. This conductive region forms a low-resistance conductive path, effectively reducing the on-resistance of the MOS.

[0057] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A method for manufacturing a U-shaped gate trench SiC MOSFET, characterized in that, Includes the following steps: Step 1: Form a drift layer on a silicon carbide substrate, form a barrier layer on the drift layer, and etch a conductive via into the barrier layer. Then, implant ions into the drift layer through the via to form a conductive region. Step 2: Reform the barrier layer and etch the barrier layer to form a masking layer via. Then, perform ion implantation on the drift layer through the masking layer via to form a masking layer. Step 3: Ion implantation is performed through the vias in the masking layer to restore the region above the masking layer to the same impurity concentration as the drift layer through impurity compensation; Step 4: Etch to form the gate region, oxidize the gate region, and form the gate insulating layer; Step 5: Deposit the gate; Step 6: Re-form a barrier layer on the drift layer, and etch the barrier layer to form a pinch-off region via. Perform ion implantation on the drift layer through the pinch-off region via to form the pinch-off region. Step 7: Re-form a barrier layer on the drift layer, and etch the barrier layer to form source region vias. Perform ion implantation on the drift layer through the source region vias to form the source region. Step 8: Re-form a barrier layer on the drift layer, and etch the barrier layer to form a source region metal via. Deposit the source region through the source region metal via to form a source metal layer. Step 9: Reform the barrier layer and etch the gate metal deposition area into the barrier layer to deposit the gate metal layer; Step 10: Remove all barrier layers and deposit a drain metal layer on the silicon carbide substrate; The drift layer is disposed on the upper side of the silicon carbide substrate; the drift layer has a masking layer, a conductive region, and a gate insulating layer, the bottom of the conductive region and the bottom of the masking layer are both connected to the drift layer, the side of the masking layer is connected to the conductive region, the side of the conductive region is connected to the drift layer, the drift layer has a U-shaped groove, the bottom of the U-shaped groove is connected to the top of the masking layer, the gate insulating layer is disposed on the U-shaped groove; the gate is connected to the gate insulating layer; one side and the lower side of the source region are both connected to the pinch-off region, the other side of the source region is connected to the gate insulating layer, the gate insulating layer is U-shaped; the bottom of the pinch-off region is connected to the drift layer and the conductive region, and the source metal layer is connected to the source region and the pinch-off region respectively.

2. The method for manufacturing a U-shaped gate trench SiC MOSFET as described in claim 1, characterized in that, The pinch-off region is p-type doped, and the doping concentration of the pinch-off region is less than that of the source region but higher than that of the drift layer.

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