A method for manufacturing a P-type SiC LDMOS power device

Abstract

This invention provides a method for manufacturing a P-type SiC LDMOS power device. The method involves preparing a silicon carbide substrate with an epitaxial layer; forming a barrier layer on the epitaxial layer and etching the barrier layer to form vias; performing ion implantation through the vias to form an isolation region on the epitaxial layer; forming a voltage-bearing region, a source ohmic contact region, and a drain ohmic contact region by reforming the barrier layer, etching, and ion implantation; removing all barrier layers and performing oxidation or deposition to form an insulating layer; forming a barrier layer on the insulating layer and etching the barrier layer and the insulating layer to form vias, followed by deposition of a source metal layer and a drain metal layer; reforming the barrier layer and etching the barrier layer and the insulating layer to form vias, and depositing a gate metal layer; removing the barrier layer to complete the manufacturing process. This method reduces the hole concentration in the voltage-bearing region when the device operates under reverse breakdown voltage conditions, thereby reducing the lateral dimensions of the device without changing the device's breakdown voltage.

Description

Technical Field

[0001] This invention relates to a method for manufacturing a P-type SiC LDMOS power device. Background Technology

[0002] Silicon carbide (SiC) materials have attracted widespread attention and research due to their superior physical properties. Their high-temperature, high-power electronic devices possess advantages such as high input impedance, fast switching speed, high operating frequency, and resistance to high temperatures and pressures, leading to their widespread application in switching power supplies, high-frequency heating, automotive electronics, and power amplifiers.

[0003] However, the development of SiC MOSFETs is still limited to the field of discrete devices, with relatively little research in the integrated circuit field, especially for power integrated circuits with voltage withstand capabilities. In power integrated circuits, p-type LDMOS is an important power supply device, but related research has not yet been conducted. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a manufacturing method for a P-type SiC LDMOS power device, which reduces the hole concentration in the withstand voltage region when the device is operating under reverse withstand voltage conditions, and reduces the lateral dimension of the device without changing the withstand voltage of the device.

[0005] This invention is achieved as follows: a method for manufacturing a P-type SiC LDMOS power device, comprising the following steps:

[0006] Step 1: Prepare a silicon carbide substrate with an epitaxial layer;

[0007] Step 2: Form a barrier layer on the epitaxial layer and etch the barrier layer to form vias. Perform ion implantation on the epitaxial layer through the vias to form an isolation region.

[0008] Step 3: Reform the barrier layer and etch the barrier layer to form vias. Perform ion implantation on the epitaxial layer through the vias to form a pressure-bearing region.

[0009] Step 4: Reform the barrier layer and etch the barrier layer to form vias. Perform ion implantation on the epitaxial layer and the pressure bearing region through the vias to form the source ohmic contact region and the drain ohmic contact region.

[0010] Step 5: Remove all barrier layers and oxidize or deposit to form an insulating layer;

[0011] Step 6: Form a barrier layer on the insulating layer, and etch the barrier layer and the insulating layer to form a via, then deposit the source metal layer and the drain metal layer.

[0012] Step 7: Reform the barrier layer, and etch the barrier layer and insulating layer to form vias, and deposit the gate metal layer;

[0013] Step 8: Remove the barrier layer to complete the manufacturing process.

[0014] Furthermore, between steps 7 and 8, step a is included: reforming the barrier layer, etching the barrier layer to form through holes, depositing drain metal to form protrusions, and forming a parallel plate capacitor with the protrusions and the isolation and pressure bearing areas.

[0015] Furthermore, the silicon carbide substrate and the epitaxial layer are both N-type, while the isolation region, the pressure bearing region, the drain ohmic contact region, and the source ohmic contact region are all P-type.

[0016] The advantages of this invention are:

[0017] I. The power device of the present invention, a method for manufacturing a P-type SiC LDMOS power device, is p-type conductive and is suitable for power devices in integrated circuits;

[0018] II. The power device of the manufacturing method of P-type SiC LDMOS power device of the present invention reduces the hole concentration in the withstand voltage region when the device is operating under reverse withstand voltage without reducing the withstand voltage level, and reduces the lateral dimension of the device without changing the withstand voltage.

[0019] In summary, this device reduces its size and increases its power density through minor adjustments to the drain structure, which is significant for reducing the size of integrated circuits. Attached Figure Description

[0020] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0021] Figure 1 This invention provides a process flow for manufacturing a P-type SiC LDMOS power device. Figure 1 .

[0022] Figure 2 This invention provides a process flow for manufacturing a P-type SiC LDMOS power device. Figure 2 .

[0023] Figure 3 This invention provides a process flow for manufacturing a P-type SiC LDMOS power device. Figure 3 .

[0024] Figure 4 This invention provides a process flow for manufacturing a P-type SiC LDMOS power device. Figure 4 .

[0025] Figure 5 This invention provides a process flow for manufacturing a P-type SiC LDMOS power device. Figure 5 .

[0026] Figure 6 This invention provides a process flow for manufacturing a P-type SiC LDMOS power device. Figure 6 .

[0027] Figure 7 This invention provides a process flow for manufacturing a P-type SiC LDMOS power device. Figure 7 .

[0028] Figure 8 This invention provides a process flow for manufacturing a P-type SiC LDMOS power device. Figure 8 .

[0029] Figure 9 This invention provides a process flow for manufacturing a P-type SiC LDMOS power device. Figure 9 .

[0030] Figure 10 This is a schematic diagram of the structure of a P-type SiC LDMOS power device according to the present invention. Detailed Implementation

[0031] like Figures 1 to 9 As shown, the present invention discloses a method for manufacturing a P-type SiC LDMOS power device, comprising the following steps:

[0032] Step 1: Prepare a silicon carbide substrate 1 with an epitaxial layer 2;

[0033] Step 2: Form a barrier layer 9 on the epitaxial layer 2, and etch the barrier layer 9 to form a via. Perform ion implantation on the epitaxial layer 2 through the via to form an isolation region 3.

[0034] Step 3: Reform the barrier layer 9 and etch the barrier layer 9 to form a via. Ion implantation is performed on the epitaxial layer through the via to form the pressure bearing region 4.

[0035] Step 4: Reform the barrier layer 9 and etch the barrier layer to form vias. Ion implant the epitaxial layer 2 and the pressure bearing region 3 through the vias to form the source ohmic contact region 21 and the drain ohmic contact region 31.

[0036] Step 5: Remove all barrier layers 9, and oxidize or deposit to form an insulating layer 8;

[0037] Step 6: Form a barrier layer 9 on the insulating layer 8, and etch the barrier layer 9 and the insulating layer 8 to form a via, and then deposit the source metal layer 6 and the drain metal layer 5.

[0038] Step 7: Reform the barrier layer 9, and etch the barrier layer 9 and the insulating layer 8 to form vias, and deposit the gate metal layer 7;

[0039] Step a: Reform the barrier layer 9, etch the barrier layer 9 to form a through hole, deposit drain metal to form a protrusion 51, and form a parallel plate capacitor of the protrusion 51 and the isolation region 3 and the pressure bearing region 4.

[0040] Step 8: Remove the barrier layer 9 to complete manufacturing;

[0041] The silicon carbide substrate 1 and the epitaxial layer 2 are both N-type, while the isolation region 3, the pressure bearing region 4, the drain ohmic contact region 31, and the source ohmic contact region 21 are all P-type.

[0042] like Figure 10 As shown, the power device obtained by the above manufacturing method includes:

[0043] A silicon carbide substrate 1;

[0044] An epitaxial layer 2 is connected to the upper side of the silicon carbide substrate 1, and a source ohmic contact region 21 is provided on the epitaxial layer 2;

[0045] An isolation region 3 is provided, the bottom of which is connected to the upper side of the silicon carbide substrate 1, and one side of which is connected to the epitaxial layer 2. A drain ohmic contact region 31 is provided on the isolation region 3.

[0046] A pressure-bearing area 4, the bottom and one side of the pressure-bearing area 4 are connected to the epitaxial layer 2, and the other side of the pressure-bearing area 4 is connected to the isolation area 3;

[0047] A drain metal layer 5 is connected to the drain ohmic contact region 31;

[0048] A source metal layer 6 is provided, which is connected to the source region ohmic contact region 21.

[0049] A gate metal layer 7 is connected to the epitaxial layer 2;

[0050] An insulating layer 8 is provided between the drain metal layer 5, the source metal layer 6 and the gate metal layer 7. The silicon carbide substrate 1 and the epitaxial layer 2 are both N-type. The isolation region 3, the pressure bearing region 4, the drain ohmic contact region 31 and the source ohmic contact region 21 are all P-type.

[0051] The drain metal layer 5 has a protrusion 51, one side of which is connected to the insulating layer 8. The protrusion 51 is located above the isolation zone 3 and the pressure-bearing zone 4 of a set length.

[0052] The protrusion 51 of the drain metal layer 5, the insulating layer 8, the isolation region 3 below, and the small portion of the pressure-bearing region 4 form a parallel plate capacitor, which has the effect of induced charge.

[0053] When the drain metal layer 5 is subjected to a large voltage, the drain metal layer 5 is at a high level. Electrons are induced in the isolation region 3 and a small part of the voltage-bearing region 4, which further reduces the hole concentration in these two regions, thereby reducing the equivalent doping concentration in these two regions and improving the voltage withstand capability. Therefore, the original voltage withstand characteristics of the device can be achieved in a smaller size, realizing the miniaturization of the device.

[0054] When the drain metal layer 5 is at a low level, there is no potential difference between the upper and lower plates of the equivalent capacitor, which has no effect on the conduction characteristics of the device.

[0055] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A method for manufacturing a P-type SiC LDMOS power device, characterized in that, Includes the following steps: Step 1: Prepare a silicon carbide substrate with an epitaxial layer; Step 2: Form a barrier layer on the epitaxial layer and etch the barrier layer to form vias. Perform ion implantation on the epitaxial layer through the vias to form an isolation region. Step 3: Reform the barrier layer and etch the barrier layer to form vias. Perform ion implantation on the epitaxial layer through the vias to form a pressure-bearing region. Step 4: Reform the barrier layer and etch the barrier layer to form vias. Perform ion implantation on the epitaxial layer and the pressure bearing region through the vias to form the source ohmic contact region and the drain ohmic contact region. Step 5: Remove all barrier layers and oxidize or deposit to form an insulating layer; Step 6: Form a barrier layer on the insulating layer, and etch the barrier layer and the insulating layer to form a via. Then deposit the source metal layer and the drain metal layer. The thickness of the source metal layer and the drain metal layer is greater than the thickness of the insulating layer. Step 7: Reform the barrier layer and etch the barrier layer and insulating layer to form vias. The vias expose the surface of the epitaxial layer between the pressure bearing region and the source ohmic contact region. Deposit the gate metal layer on the epitaxial layer. Step 8: Remove the barrier layer to complete manufacturing; The epitaxial layer is connected to the upper side of the silicon carbide substrate, and a source ohmic contact region is provided on the epitaxial layer; the bottom of the isolation region is connected to the upper side of the silicon carbide substrate, one side of the isolation region is connected to the epitaxial layer, and a drain ohmic contact region is provided on the isolation region; the bottom and one side of the pressure bearing region are connected to the epitaxial layer, and the other side of the pressure bearing region is connected to the isolation region; the drain metal layer is connected to the drain ohmic contact region; the source metal layer is connected to the source ohmic contact region. Between steps 7 and 8, step a is further included: reforming the barrier layer and etching the barrier layer to form a through hole, exposing the surface of the insulating layer, depositing drain metal connected to the drain metal layer in the through hole, and forming a protrusion, the protrusion being located above the isolation region and the pressure bearing region, forming a parallel plate capacitor of the protrusion and the isolation region and the pressure bearing region.

2. The method for manufacturing a P-type SiC LDMOS power device as described in claim 1, characterized in that, The silicon carbide substrate and epitaxial layer are both N-type, while the isolation region, pressure bearing region, drain ohmic contact region and source ohmic contact region are all P-type.

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