An LDMOS transistor structure and a corresponding manufacturing method

Abstract

The application relates to the technical field of LDMOS, and discloses an LDMOS transistor structure and a corresponding manufacturing method, which comprise a device body, the device body comprises a substrate layer and an N-type drift region located above the substrate layer, at least two second gates are arranged at a predetermined distance interval above the N-type drift region; when the device body is in an off state, a voltage is applied to the at least two second gates so as to increase the breakdown voltage at the corresponding positions; when the device body is in an on state, a voltage is applied to the at least two second gates so as to reduce the on-resistance; the application realizes a breakthrough in the contradiction between the breakdown voltage and the on-resistance through the above technical scheme, improves the reliability of a power semiconductor chip and an electric power intelligent device, and ensures the safe and stable operation of a power grid.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of LDMOS, in particular to an LDMOS transistor structure and a corresponding manufacturing method. BACKGROUND

[0002] Compared with the power circuit composed of discrete devices, the power integrated circuit has the advantages of high integration, strong stability and low manufacturing cost, and has developed rapidly in recent years. The power integrated circuit has become the inevitable choice of power circuit. The power integrated circuit mainly adopts special process based on BCD (BiCMOS / CMOS / DMOS), and the most critical lateral double diffusion metal oxide semiconductor field effect transistor (LDMOS) device as a power switch plays a key role in the power integrated circuit. LDMOS devices account for a large proportion, and the power consumption is much larger than other analog and digital devices in the chip, accounting for a large part of the loss of the entire power integrated circuit. The performance of its breakdown voltage and on-resistance is directly related to important indicators such as conversion efficiency, switching frequency and stable running time of power integrated chip. At the same time, the performance of LDMOS device is also an important standard to judge the level of BCD process technology. However, for DMOS power devices, high breakdown voltage and low on-resistance are contradictory in design and process manufacturing.

[0003] Specifically, the performance of a general LDMOS device is mainly limited by its on-resistance. Under the condition that the device meets a certain withstand voltage, the on-resistance of the device should be reduced as much as possible. However, reducing the on-resistance of the device requires reducing the length of the drift region and increasing the doping concentration of the drift region, which in turn affects the breakdown voltage of the device. Therefore, high breakdown voltage and low on-resistance are contradictory in design and process manufacturing. SUMMARY

[0004] The present application aims to overcome the problem of the existing LDMOS device in the design and process manufacturing of high breakdown voltage and low on-resistance, and provides an LDMOS transistor structure and a corresponding manufacturing method.

[0005] In order to achieve the above object, the present application provides an LDMOS transistor structure, comprising: a device body, the device body comprising a substrate layer and a P-well region and an N-type drift region located on the surface of the substrate layer, the surface of the P-well region being provided with a first gate, and the surface of the N-type drift region being provided with a drain, characterized in that the surface of the N-type drift region between the first gate and the drain is provided with at least two second gates arranged at intervals; wherein the at least two second gates arranged at intervals are used to apply a voltage to the at least two second gates when the device body is in an off state, so as to increase the breakdown voltage of the device body, and to apply a voltage to the at least two second gates when the device body is in an on state, so as to reduce the on-resistance of the device body.

[0006] As an implementable manner, the first gate comprises a first gate oxide layer and a first gate electrode, the second gate comprises a second gate oxide layer and a second gate electrode, the first gate oxide layer is arranged on the surface of the P-well region, the first gate electrode is arranged on the surface of the first gate oxide layer, the second gate oxide layer is arranged on the surface of the N-type drift region, and the second gate electrode is arranged on the surface of the second gate oxide layer; the thickness of the second gate oxide layer is greater than the thickness of the first gate oxide layer.

[0007] As an implementable manner, the surface of the P-well region is further provided with a source, the source is located on the side of the first gate away from the second gate, the source comprises a source N+ region, a source P+ region and a source electrode, the source N+ region and the source P+ region are located on the surface of the P-well region, and the source electrode is located on the surface of the source N+ region and the source P+ region; the drain comprises a drain N+ region and a drain electrode, the drain N+ region is located on the surface of the N-type drift region, and the drain electrode is located on the surface of the drain N+ region.

[0008] As an implementable manner, the substrate layer further comprises an N buried layer; or, a silicon dioxide layer is further arranged between the substrate layer and the P-well region and the N-type drift region.

[0009] As an implementable manner, the at least two second gates are arranged at non-equal intervals.

[0010] Correspondingly, the present application further provides an LDMOS transistor manufacturing method, comprising the following steps:

[0011] providing a substrate layer, epitaxially growing N-type doped silicon on the surface of the substrate layer to form an N-type epitaxial layer;

[0012] performing ion implantation on the N-type epitaxial layer to form a P-well region and an N-type drift region;

[0013] forming a first gate on the surface of the P-well region and at least two second gates in spaced arrangement on the surface of the N-type drift region, wherein the at least two second gates are arranged in such a way that when the subsequently formed device body is in an off state, applying a voltage to the at least two second gates can increase the breakdown voltage of the junction region between the P-well region and the N-type drift region, and when the subsequently formed device body is in an on state, applying a voltage to the at least two second gates can reduce the on-resistance of the device body;

[0014] forming a source N+ region and a source P+ region in the P-well region by ion implantation, and forming a drain N+ region in the N-type drift region by ion implantation, forming a source electrode on the surface of the source N+ region and the source P+ region, and forming a drain electrode on the surface of the drain N+ region, wherein the at least two second gates are located between the first gate and the drain electrode;

[0015] finally, performing a back-end process to complete the process manufacturing and obtain the device body.

[0016] As an implementation manner, the N-type epitaxial layer is ion implanted to form a P-well region and an N-type drift region; a first gate is formed on the surface of the P-well region and at least two second gates in spaced arrangement are formed on the surface of the N-type drift region; the P-well region is ion implanted to form a source N+ region and a source P+ region, and the N-type drift region is ion implanted to form a drain N+ region; a source electrode is formed on the surface of the source N+ region and the source P+ region, and a drain electrode is formed on the surface of the drain N+ region.

[0017] The N-type epitaxial layer is subjected to photolithography, ion implantation and diffusion treatment to form a P-well region, and the region of the N-type epitaxial layer other than the P-well region is an N-type drift region; a first gate is formed on the surface of the P-well region and at least two second gates in spaced arrangement are formed on the surface of the N-type drift region through thermal oxidation, deposition, photolithography and etching treatment; a source N+ region and a source P+ region are formed in the P-well region and a drain N+ region is formed in the N-type drift region by photolithography and ion implantation, and a source electrode is formed on the surface of the source N+ region and the source P+ region by depositing a metal electrode, and a drain electrode is formed on the surface of the drain N+ region by depositing a metal electrode.

[0018] As an implementation manner, the step of forming a first gate on the surface of the P-well region and at least two second gates in spaced arrangement on the surface of the N-type drift region specifically includes:

[0019] Forming a first oxide layer and at least two second oxide layers arranged in intervals on the surface of the P-well region, etching the first oxide layer to be removed, then forming a first oxide layer on the surface of the P-well region as a first gate oxide layer, and then forming a second oxide layer on the surface of the second oxide layer to obtain a second gate oxide layer containing two second oxide layer surfaces, wherein the thickness of the second gate oxide layer is greater than the thickness of the first gate oxide layer.

[0020] Forming a first gate electrode on the surface of the first gate oxide layer and a second gate electrode on the surface of each second gate oxide layer to obtain a first gate containing the first gate oxide layer and the first gate electrode, and at least two second gates arranged in intervals containing the second gate oxide layer and the second gate electrode.

[0021] As an implementable manner, the step of forming the N-type epitaxial layer includes: providing a substrate layer, performing ion implantation in the substrate layer to form an N buried layer, and epitaxially growing N-type doped silicon on the surface of the substrate layer to form an N-type epitaxial layer; or providing a substrate layer, depositing a silicon dioxide layer on the surface of the substrate layer, epitaxially growing N-type doped silicon on the surface of the silicon dioxide layer to form an N-type epitaxial layer.

[0022] As an implementable manner, when the second gate has i, the first gate and the first second gate are arranged from left to right, the interval distance between the first second gate and the i-th second gate is △i, and the interval distance between the i-1-th second gate and the i-th second gate is △i+1, wherein the distance values of △1, …, △i, △i+1 increase from left to right, so that when the device body is in an off state and a voltage is applied to the plurality of second gates, the junction region of the P-well region and the N-type drift region is not broken down.

[0023] The beneficial effects of the present application: based on the traditional LDMOS transistor structure, a series of second gates arranged at a predetermined distance are added, on the one hand, when the device body is in the off state, a voltage is applied to the second gate, the depletion of the N-type drift region is increased, so that the entire device can withstand higher voltage, and the breakdown voltage is increased; on the other hand, when the device body is in the on state, a voltage is applied to the second gate, more electrons can be attracted on the surface of the drift region to form a high-concentration electron accumulation layer, thereby modulating the conductivity of the drift region and reducing the on-resistance; moreover, each gate is equivalent to one more electric field peak, which can reduce the electric field peaks on both sides, thereby increasing the breakdown voltage, the breakdown voltage is equal to the integral of the electric field in the lateral direction, the electric field on both sides is reduced, the overall electric field can be increased, the breakdown voltage is increased, and the effect is better; the breakthrough of the contradiction between the breakdown voltage and the on-resistance is realized, the reliability of the power semiconductor chip and the power intelligent device is improved, and the safe and stable operation of the power grid is ensured. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 It is a schematic diagram of a traditional LDMOS transistor structure;

[0025] Figure 2 It is a schematic diagram of the structure of the second gate oxide layer in the LDMOS transistor structure of the embodiment of the present application when the thickness of the second gate oxide layer is equal to the thickness of the first gate oxide layer;

[0026] Figure 3 It is a schematic diagram of the structure of the second gate oxide layer in the LDMOS transistor structure of the embodiment of the present application when the thickness of the second gate oxide layer is greater than the thickness of the first gate oxide layer;

[0027] Figure 4 It is a schematic diagram of the structure of the LDMOS transistor structure of the embodiment of the present application after adding an N buried layer;

[0028] Figure 5 It is a schematic diagram of the structure of the LDMOS transistor structure of the embodiment of the present application after adding a silicon dioxide layer;

[0029] Figure 6 It is a schematic diagram of the structure of the LDMOS transistor structure of the embodiment of the present application in the manufacturing process. DETAILED DESCRIPTION

[0030] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of the present application.

[0031] The embodiment provides a technical scheme: a kind of LDMOS transistor structure, comprising: device body, the device body includes substrate layer and P well area and N type drift region located on the surface of the substrate layer, the surface of the P well area is equipped with first gate, the surface of the N type drift region is equipped with drain, it is characterized in that, at least two second gates are arranged at intervals in the surface of the N type drift region between the first gate and the drain;Wherein, at least two second gates arranged at intervals are used to when the device body is in off state, at least two second gates are applied voltage to thereby increase the breakdown voltage of the device body, when the device body is in on state, at least two second gates are applied voltage to thereby reduce the on resistance of the device body.

[0032] The first gate includes a first gate oxide layer and a first gate electrode, and the second gate includes a second gate oxide layer and a second gate electrode, the first gate oxide layer is arranged on the surface of the P well area, the first gate electrode is arranged on the surface of the first gate oxide layer, the second gate oxide layer is arranged on the surface of the N type drift region, and the second gate electrode is arranged on the surface of the second gate oxide layer;In the embodiment, the thickness of the second gate oxide layer of the finally formed second gate can not be limited;But in one embodiment, as shown in Figure 2 The thickness of the second gate oxide layer is equal to the thickness of the first gate oxide layer, so that when the device body is in on state, the voltage applied to the second gate can be equal to the voltage applied to the first gate, wherein the second gate oxide layer and the first gate oxide layer can be formed at the same time.

[0033] Further, the surface of the P well area is also provided with a source, and the source is located on the side of the first gate away from the second gate, the source includes a source N+ region, a source P+ region and a source electrode, the source N+ region and the source P+ region are located in the P well area, and the source electrode is located on the surface of the source N+ region and the source P+ region, the drain includes a drain N+ region and a drain electrode, the drain N+ region is located in the N type drift region, and the drain electrode is located on the surface of the drain N+ region.

[0034] Specifically, as shown in Figure 1The shown is a traditional LDMOS transistor structure, the device body includes a substrate layer 100, an N-type drift region 220 and a P-well region 210 located on the surface of the substrate layer 100, a source N+ region 211, a source P+ region 212 located on the surface of the P-well region 210, a source electrode 310 located on the surface of the source N+ region 211 and the source P+ region 212, a first gate oxide layer 320 located on the surface of the P-well region 210, a first gate electrode 330 located on the surface of the first gate oxide layer 320, a drain N+ region 221 located on the surface of the N-type drift region 220, and a drain electrode 340 located on the surface of the drain N+ region 221, wherein the first gate oxide layer 320 and the first gate electrode 330 constitute a first gate.

[0035] In the embodiment, the breakdown voltage of the device body is increased, mainly by increasing the breakdown voltage of the junction region of the P-well region and the N-type drift region, and the junction region of the N-type drift region and the drain, because in general the electric field of these two regions is stronger than other places and is easy to be broken down, and the junction region of the P-well region and the N-type drift region is more prone to be broken down and the electric field is stronger.

[0036] That is, in normal circumstances, the place most prone to be broken down is the junction of the P-well region and the N-type drift region, and in order to increase the breakdown voltage of the junction region of the P-well region and the N-type drift region and the junction region of the N-type drift region and the drain, the embodiment is to set at least two second gates as shown in Figure 1 based on the traditional LDMOS transistor structure as shown in Figure 2 at least two second gates spaced apart at a predetermined distance, specifically, as shown in Figure 2 at least two second gates 350 spaced apart at a predetermined distance are arranged above the N-type drift region 220, wherein by arranging at least two second gates spaced apart at a predetermined distance, when the device body is in an off state, applying voltage to the at least two second gates can increase the depletion of the N-type drift region, so that the entire device can withstand higher voltage, thereby increasing the breakdown voltage, and when the device body is in an on state, applying voltage to the at least two second gates can form a high-concentration electron accumulation layer in the N-type drift region, thereby modulating the conductivity of the N-type drift region and reducing the on-resistance of the device body.

[0037] In the embodiment, the second gates arranged at intervals are arranged to form a field peak corresponding to each second gate when a voltage is applied to the plurality of second gates, and when the field peaks increase, the electric field of the junction region of the P-well region and the N-type drift region and the junction region of the N-type drift region and the drain can be lowered, and because the electric field of the junction region of the P-well region and the N-type drift region is stronger, more second gates can be arranged near the P-well region than near the drain side, and the peak of each second gate can flatten the entire electric field distribution, thereby increasing the breakdown voltage of the entire device; that is, to ensure that the device is not broken down, more second gates can be arranged on the side of the N-type drift region near the P-well region, thereby increasing the breakdown voltage of the junction region of the P-well region and the N-type drift region, and in addition, the rightmost second gate needs to be a certain distance away from the drain, because the electric field at the drain is weaker than the electric field at the junction region of the P-well region and the N-type drift region, and the second gate near the drain does not need to be too close to the drain to lower the electric field, otherwise, if there are too many or too close second gates near the drain, the electric field will be enhanced, thereby causing the rightmost second gate near the drain and the drain to be easily broken down.

[0038] The second gates arranged at intervals can be non-equidistantly arranged, for example, when there are i second gates, the first second gate to the i-th second gate are arranged from left to right, the interval distance between the first gate and the first second gate is Δ1, the interval distance between the i-1-th second gate and the i-th second gate is Δi, and the interval distance between the i-th second gate and the drain is Δi+1, wherein the distance values of Δ1, …, Δi, Δi+1 increase from left to right, so that when a voltage is applied to the plurality of second gates when the device body is in an off state, the junction region of the P-well region and the N-type drift region and the junction region of the N-type drift region and the drain will not be broken down.

[0039] For example, as shown in FIGS. 3A and 3B, when the number of second gates is 5, the first second gate 351, the second second gate 352, the third second gate, the fourth second gate, and the fifth second gate 355 can be arranged from left to right in a non-equidistant manner. Figure 2 and Figure 3 As can be seen, the interval distance between the first gate and the fifth second gate gradually increases from left to right, and the purpose of this arrangement is to ensure that the junction region of the P-well region and the N-type drift region and the junction region of the N-type drift region and the drain will not be broken down.

[0040] However, in other embodiments, the number and spacing of the second gates can be determined according to different devices and application scenarios. For example, at least two second gates may not all be arranged with unequal spacing. But no matter how the distance values ​​are set, the distance values ​​Δ1, Δ2, ..., Δi, Δi+1 must ensure that when the device body is in the off state and a voltage is applied to multiple second gates, the boundary region between the P-well region and the N-type drift region is not broken down, and other regions, such as the region between the i-th second gate closest to the drain and the drain, will not be broken down. This requires... To ensure that more second gates are provided on the side closest to the first gate, and that there is a sufficient distance between the i-th second gate closest to the drain and the drain, that is, to ensure that the distance value Δi+1 is large enough, or to simultaneously ensure that there is a sufficient distance between the (i-1)-th second gate closest to the drain and the i-th second gate, and between the i-th second gate and the drain, that is, to ensure that the distance values ​​Δi and Δi+1 are large enough together, etc., so that when the device body is in the off state, the device will not be broken down by applying voltage to multiple second gates.

[0041] Furthermore, in one embodiment, such as Figure 3 As shown, the thickness of the second gate oxide layer 360 is greater than the thickness of the first gate oxide layer 320 to prevent the second gate oxide layer from being broken down when a voltage is applied in the off or on state; this also makes the voltage applied to the second gate greater than the voltage applied to the first gate when the device body is in the on state, thereby further reducing the on-resistance of the device body.

[0042] Specifically, when the device body is in the off state, in order to further prevent the second gate and the drain near the second gate from being broken down and to ensure the safety of the drain, such as... Figure 3As shown, the thickness of the second gate oxide layer 360 can be greater than the thickness of the first gate oxide layer 320, because the voltage applied to the second gate will change with the thickness of the second gate oxide layer, if the thickness of the second gate oxide layer is thicker, it will result in that the applied voltage can be greater, that is, when the thickness of the second gate oxide layer is thicker than the first gate oxide layer, the voltage applied to the second gate oxide layer is greater than the voltage applied to the first gate oxide layer, which is to prevent the second gate from being broken down, thereby preventing the drain closer to the second gate from being broken down, and ultimately improving the breakdown voltage of the entire device. At this time, since the thickness of the second gate oxide layer 360 can be greater than the thickness of the first gate oxide layer 320, the voltage applied to at least two second gates also needs to be greater than the voltage applied to the first gate when the device body is in an open state. At this time, since the voltage applied to at least two second gates is greater, the on-resistance of the device body is further reduced.

[0043] It should be noted that the specific voltage applied to the first gate and the second gate in the present embodiment is different for different devices, and can be determined according to the thickness of the first gate oxide layer, the second gate oxide layer, the length of the N-type drift region and the like. However, when the device body is in an open state, the applied voltage is greater than 0V, and when the thickness of the second gate oxide layer is equal to the thickness of the first gate oxide layer, the voltage applied to at least two second gates and the voltage applied to the first gate can be equal. When the thickness of the second gate oxide layer is greater than the thickness of the first gate oxide layer, the voltage applied to at least two second gates is greater than the voltage applied to the first gate. When the device body is in an off state, the first gate can not be applied with voltage at this time, but the voltage applied to at least two second gates needs to be less than 0V. For example, for a certain device, +5V is applied to the first gate when it is turned on, and +10V is applied to the second gate. When it is turned off, the first gate is not applied with voltage, and -5V is applied to the second gate.

[0044] Further, as shown in Figure 4 The substrate layer further comprises an N buried layer 10, specifically, the substrate layer is further provided with an N buried layer 10 at a predetermined depth, wherein the N buried layer 10 can form a reverse bias junction with the substrate layer, introduce a new electric field peak, and greatly improve the blocking performance of the device body in the longitudinal voltage.

[0045] Further, as shown in Figure 5 The substrate layer and the P-well region and the N-type drift region are further provided with a silicon dioxide layer 20, wherein the silicon dioxide layer 20 can realize isolation between the device body, has small parasitic capacitance, and reduces the latch-up effect.

[0046] The embodiment adds a series of second gates arranged at a predetermined distance on the basis of the traditional LDMOS transistor structure, on the one hand, when the device body is in the off state, a voltage is applied to the second gate to increase the depletion of the N-type drift region, so that the entire device can withstand higher voltage and the breakdown voltage is increased; on the other hand, when the device body is in the on state, a voltage is applied to the second gate to attract more electrons on the surface of the drift region to form a high-concentration electron accumulation layer, thereby modulating the conductivity of the drift region and reducing the on-resistance; moreover, with each additional second gate, it is equivalent to one more electric field peak, which can reduce the electric field peaks on both sides of the junction between the P-well and the N-drift region and the junction between the N-drift region and the drain, and in these two regions, the peak of the junction between the P-well region and the N-type drift region is larger, which is the main breakdown part, so more second gates can be arranged on the side close to the P-well region to increase the breakdown voltage, and the breakdown voltage is equal to the integral of the electric field in the lateral direction, the electric field on both sides is reduced, the overall electric field can be increased, the breakdown voltage is increased, and the effect is better.

[0047] The embodiment realizes breakthrough of the contradiction between the breakdown voltage and the on-resistance through the above technical solutions, improves the reliability of the power semiconductor chip and the power intelligent device, and ensures the safe and stable operation of the power grid.

[0048] Based on the same concept, the embodiment of the present application also provides a LDMOS transistor manufacturing method, comprising the following steps:

[0049] A substrate layer is provided, and N-type doped silicon is epitaxially formed on the surface of the substrate layer to form an N-type epitaxial layer; as shown in (a) of Figure 6 (a) of the figure shows the substrate layer 100 and the formed N-type epitaxial layer 200;

[0050] The N-type epitaxial layer is ion implanted to form a P-well region and an N-type drift region; as shown in (b) of Figure 6 (b) of the figure shows the formed P-well region 210 and N-type drift region 220;

[0051] A first gate is formed on the surface of the P-well region and at least two second gates are arranged at intervals on the surface of the N-type drift region, wherein the at least two second gates arranged at intervals enable, when the subsequently formed device body is in the off state, a voltage applied to the at least two second gates to increase the breakdown voltage of the junction region between the P-well region and the N-type drift region, and when the subsequently formed device body is in the on state, a voltage applied to the at least two second gates to reduce the on-resistance of the device body; as shown in (c) of Figure 6 (c) of the figure shows the formed second gate oxide layer, second gate electrode 350, first gate oxide layer 320 and first gate electrode 330;

[0052] ion implantation is performed on the P-well region to form a source N+ region and a source P+ region and ion implantation is performed on the N-type drift region to form a drain N+ region, a source electrode is formed on the surface of the source N+ region and the source P+ region, and a drain electrode is formed on the surface of the drain N+ region, wherein at least two second gates arranged at intervals are located between the first gate and the drain electrode; as Figure 6 (d) in (b) and (c) shows the formed source N+ region 211 and source P+ region 212, the source electrode 310, the drain N+ region 221, and the drain electrode 340;

[0053] Finally, a back-end process is performed to complete the process manufacturing to obtain a device body; wherein the back-end process belongs to the prior art, and will not be described in detail in the present embodiment.

[0054] The first gate comprises a first gate oxide layer and a first gate electrode, the second gate comprises a second gate oxide layer and a second gate electrode, the first gate oxide layer is located on the surface of the P-well region, the first gate electrode is located on the surface of the first gate oxide layer, the second gate oxide layer is located on the surface of the N-type drift region, the second gate electrode is located on the surface of the second gate oxide layer, the source N+ region, the source N+ region, and the source electrode constitute a source electrode, the drain N+ region and the drain electrode constitute a drain electrode, and at least two second gates arranged at intervals are located between the first gate and the drain electrode.

[0055] The step of forming a first gate on the surface of the P-well region and forming at least two second gates arranged at intervals on the surface of the N-type drift region specifically comprises:

[0056] A first oxide layer and at least two second oxide layers arranged at intervals are formed on the surface of the P-well region, the first oxide layer is etched and removed, a first oxide layer is then formed on the surface of the P-well region as a first gate oxide layer, and a second oxide layer is then formed on the surface of the second oxide layer to obtain a second gate oxide layer comprising two second oxide layer surfaces; wherein the thickness of the second gate oxide layer is greater than the thickness of the first gate oxide layer, so that when the device body is in an off state, the voltage applied to the second gate is greater than the voltage applied to the first gate, thereby preventing the drain electrode from being broken down;

[0057] A first gate electrode is formed on the surface of the first gate oxide layer, and a second gate electrode is formed on the surface of each second gate oxide layer to obtain at least two second gates arranged at intervals comprising the second gate oxide layer and the second gate electrode.

[0058] Further, the first oxide layer and the at least two second oxide layers are formed simultaneously on the surface of the P-well region; and after the first oxide layer is etched and removed, a first gate oxide layer is formed on the surface of the P-well region, and a second gate oxide layer is formed on the surface of the second oxide layer to form a second gate oxide layer including two second oxide layers.

[0059] In the embodiment, the step of providing a substrate layer and epitaxially growing N-type doped silicon on the surface of the substrate layer to form an N-type epitaxial layer includes the following steps: providing a substrate layer, ion implantation at a predetermined depth of the substrate layer to form an N-type buried layer, and epitaxially growing N-type doped silicon on the surface of the substrate layer to form an N-type epitaxial layer.

[0060] In the embodiment, the step of providing a substrate layer and epitaxially growing N-type doped silicon on the surface of the substrate layer to form an N-type epitaxial layer includes the following steps: providing a substrate layer, depositing a silicon dioxide layer on the surface of the substrate layer, and epitaxially growing N-type doped silicon on the surface of the silicon dioxide layer to form an N-type epitaxial layer.

[0061] The step of ion implantation on the N-type epitaxial layer to form a P-well region and an N-type drift region includes the following steps: photoetching, ion implantation and diffusion treatment on the N-type epitaxial layer to form a P-well region, and the N-type epitaxial layer except the P-well region is an N-type drift region; wherein the photoetching, ion implantation and diffusion treatment are prior art, and will not be described in detail in the embodiment.

[0062] The step of forming a first gate on the surface of the P-well region and at least two second gates on the surface of the N-type drift region includes the following steps: forming a first gate on the surface of the P-well region and at least two second gates on the surface of the N-type drift region by thermal oxidation, deposition, photoetching and etching treatment; wherein the thermal oxidation, deposition, photoetching and etching treatment are prior art, and will not be described in detail in the embodiment.

[0063] The step of ion implantation on the P-well region to form a source N+ region and a source P+ region, ion implantation on the N-type drift region to form a drain N+ region, forming a source electrode on the surface of the source N+ region and the source P+ region, and forming a drain electrode on the surface of the drain N+ region includes the following steps: forming a source N+ region and a source P+ region in the P-well region and a drain N+ region in the N-type drift region by photoetching and ion implantation, and then depositing a metal electrode on the surface of the source N+ region and the source P+ region to form a source electrode and depositing a metal electrode on the surface of the drain N+ region to form a drain electrode; wherein the metal electrode can be NiPt, and the photoetching and ion implantation are prior art, and will not be described in detail in the embodiment.

[0064] Although the present application has been disclosed with reference to the preferred embodiments, it is not intended to limit the present application, and any person skilled in the art can make possible changes and modifications to the technical solutions of the present application using the disclosed methods and technical contents without departing from the spirit and scope of the present application. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application without departing from the technical solutions of the present application shall fall within the protection scope of the technical solutions of the present application.

Claims

1. An LDMOS transistor structure comprising: The device body comprises a substrate layer and a P well region and an N type drift region on the surface of the substrate layer, the surface of the P well region is provided with a first gate, and the surface of the N type drift region is provided with a drain, characterized in that the surface of the N type drift region between the first gate and the drain is provided with at least two second gates arranged at intervals, the at least two second gates are arranged in sequence along the direction from the first gate to the drain, and the intervals between the first gate and the first second gate, the second gates and the i-th second gate and the drain are sequentially increased, wherein the at least two second gates arranged at intervals are used to apply a voltage to the at least two second gates when the device body is in an off state, so as to increase the breakdown voltage of the device body, and apply a voltage to the at least two second gates when the device body is in an on state, so as to reduce the on resistance of the device body, and the substrate layer further comprises an N buried layer; or the substrate layer and the P well region and the N type drift region are further provided with a silicon dioxide layer.

2. The LDMOS transistor structure of claim 1, wherein, The first gate comprises a first gate oxide layer and a first gate electrode, the second gate comprises a second gate oxide layer and a second gate electrode, the first gate oxide layer is arranged on the surface of the P well region, the first gate electrode is arranged on the surface of the first gate oxide layer, the second gate oxide layer is arranged on the surface of the N type drift region, and the second gate electrode is arranged on the surface of the second gate oxide layer; wherein the thickness of the second gate oxide layer is greater than the thickness of the first gate oxide layer.

3. The LDMOS transistor structure of claim 1, wherein, The surface of the P well region is further provided with a source, the source is located on the side of the first gate away from the second gate, the source comprises a source N+ region, a source P+ region and a source electrode, the source N+ region and the source P+ region are located on the surface of the P well region, the source electrode is located on the surface of the source N+ region and the source P+ region, the drain comprises a drain N+ region and a drain electrode, the drain N+ region is located on the surface of the N type drift region, and the drain electrode is located on the surface of the drain N+ region.

4. The LDMOS transistor structure of claim 1, wherein, The at least two second gates are arranged at non-equidistant intervals.

5. A method of fabricating an LDMOS transistor, characterized by, The method comprises the following steps: providing a substrate layer, epitaxially growing N type doped silicon on the surface of the substrate layer to form an N type epitaxial layer; performing ion implantation on the N type epitaxial layer to form a P well region and an N type drift region; forming a first gate on the surface of the P well region and at least two second gates arranged at intervals on the surface of the N type drift region, wherein the at least two second gates arranged at intervals enable the breakdown voltage of the junction region between the P well region and the N type drift region to be increased by applying a voltage to the at least two second gates when the subsequently formed device body is in an off state, and the on resistance of the device body to be reduced by applying a voltage to the at least two second gates when the subsequently formed device body is in an on state; The P well region is ion implanted to form a source N+ region and a source P+ region, the N type drift region is ion implanted to form a drain N+ region, a source electrode is formed on the surface of the source N+ region and the source P+ region, and a drain electrode is formed on the surface of the drain N+ region, the drain electrode and the drain N+ region forming a drain, wherein at least two second gates are arranged at intervals between the first gate and the drain electrode, when the second gates are i in number, the first gate and the first second gate are arranged from left to right, the interval distance between the first gate and the first second gate is △1, the interval distance between the i-1th second gate and the i th second gate is △i, and the interval distance between the i th second gate and the drain is △i+1, wherein the distance values of △1, …, △i, and △i+1 increase from left to right, so that the junction region of the P well region and the N type drift region is not broken down when the device body is in an off state and a voltage is applied to the plurality of second gates; Finally, the device body is obtained after a back-end process is performed.

6. The method of claim 5, wherein the LDMOS transistor is formed by: The N type epitaxial layer is ion implanted to form a P well region and an N type drift region; a first gate is formed on the surface of the P well region, and at least two second gates are formed on the surface of the N type drift region at intervals; the P well region is ion implanted to form a source N+ region and a source P+ region, and the N type drift region is ion implanted to form a drain N+ region; a source electrode is formed on the surface of the source N+ region and the source P+ region, and a drain electrode is formed on the surface of the drain N+ region; the steps specifically include the following steps. The N type epitaxial layer is ion implanted to form a P well region, and the region of the N type epitaxial layer other than the P well region is an N type drift region; a first gate is formed on the surface of the P well region by heat oxidation, deposition, photolithography, and etching, and at least two second gates are formed on the surface of the N type drift region at intervals; a source N+ region and a source P+ region are formed in the P well region by photolithography and ion implantation, and a drain N+ region is formed in the N type drift region; a metal electrode is deposited on the surface of the source N+ region and the source P+ region to form a source electrode, and a metal electrode is deposited on the surface of the drain N+ region to form a drain electrode.

7. The method of claim 5, wherein the LDMOS transistor is formed by the steps of: The steps of forming a first gate on the surface of the P well region and forming at least two second gates on the surface of the N type drift region at intervals specifically include the following steps. A first oxide layer and at least two second oxide layers arranged at intervals are formed on the surface of the P well region, the first oxide layer is etched and removed, a first oxide layer is then formed on the surface of the P well region as a first gate oxide layer, and a second oxide layer is further formed on the surface of the second oxide layer to obtain a second gate oxide layer comprising two second oxide layer surfaces; wherein the thickness of the second gate oxide layer is greater than the thickness of the first gate oxide layer. A first gate electrode is formed on the surface of the first gate oxide layer, and a second gate electrode is formed on the surface of each second gate oxide layer, to obtain at least two second gates comprising the second gate oxide layer and the second gate electrode, which are arranged in an interval.

8. The method of claim 6, wherein the LDMOS transistor is formed by: The step of providing a substrate layer and epitaxially growing N-type doped silicon on the surface of the substrate layer to form an N-type epitaxial layer specifically comprises: providing a substrate layer, performing ion implantation in the substrate layer to form an N-type buried layer, and epitaxially growing N-type doped silicon on the surface of the substrate layer to form an N-type epitaxial layer; or providing a substrate layer, depositing a silicon dioxide layer on the surface of the substrate layer, and epitaxially growing N-type doped silicon on the surface of the silicon dioxide layer to form an N-type epitaxial layer.

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