A modeling method of LDMOS parasitic capacitance for different voltage applications

Abstract

This invention discloses a method for modeling the parasitic capacitance of LDMOS under different voltage applications, comprising the following steps: Step S1, based on the existing SPICE models of LDMOS under different application voltages, extract the gate-drain parasitic capacitance (Cgd) of LDMOS under different application voltages; Step S2, based on the analysis of the LDMOS device structure and the gate-drain parasitic capacitance Cgd, divide the gate-drain parasitic capacitance (Cgd) into channel capacitance (cgdc) and overlay capacitance (cgdov), and construct the corresponding mathematical fitting formula; Step S3, based on the mathematical fitting formula of channel capacitance (cgdc) and overlay capacitance (cgdov), obtain the fitting formula of gate-drain parasitic capacitance (Cgd), and refit the data obtained in Step S1 to update the coefficients of the fitting formula of gate-drain parasitic capacitance (Cgd), thereby establishing a new SPICE model.

Description

Technical Field

[0001] This invention relates to a method for modeling parasitic capacitance of LDMOS, and more particularly to a method for modeling parasitic capacitance of LDMOS for different voltage applications. Background Technology

[0002] Figure 1a This is an existing LDMOS (Laterally Diffused Metal Oxide Semiconductor) structure, primarily used in radio frequency power amplification. 1 represents the field oxide region or shallow trench isolation region (STI). 1. Isolation; 2. N-type drift region (Ndrift), defined by a separate mask; 3. P-well; 4. Gate oxide; 5. Polysilicon gate, with the polysilicon field plate spanning the shallow channel isolation region (STI). The polysilicon lead-out electrode forms the gate of the LDMOS; 6. Drain N-type heavily doped region N+, whose lead-out electrode forms the drain D of the LDMOS; 7. Source N-type heavily doped region N+, whose lead-out electrode forms the source S of the LDMOS; 8. P-type heavily doped region P+, whose lead-out electrode forms the body B of the LDMOS; 9. P-type substrate (Psub); 10. N+ buried layer (NBL); 11. P-type epitaxial layer (Pepi), generally referring to the P-type region surrounded by an N-type isolation ring, typically connected to the lowest local potential.

[0003] To simulate the impact of gate voltage on circuit performance in LDMOS devices, the industry has added parasitic capacitances that vary with the external gate bias voltage to the gate-drain and gate-body terminals, respectively, based on a common sub-circuit model. These parasitic capacitances are Cgd (gate-drain capacitance) and Cgb (gate-body capacitance), forming a completely new sub-circuit. Figure 1b As shown, D, G, S, and B are the drain, gate, source, and body terminals of the LDMOS, R1 is the drain equivalent resistance, and R2 is the source equivalent resistance.

[0004] The super-integrated silicon gate process BCD (Bipolar-CMOS-DMOS) platform typically develops LDMOS devices for various voltage applications, including 16V, 20V, 30V, 40V, 50V, 60V, 80V, 100V, and 120V, to meet customers' multi-voltage needs. Facing multiple voltage applications, modeling requires adding corresponding testkey circuits. Multiple models need to be built based on device testing at different voltages; creating a separate model for each voltage is time-consuming and labor-intensive.

[0005] Furthermore, despite offering so many LDMOS models applicable to different voltages, it is difficult to provide LDMOS models for the entire voltage range to meet the diverse needs of customers. For example, if a customer needs a 70V LDMOS, we cannot provide a model without the corresponding test key circuit. Summary of the Invention

[0006] To overcome the shortcomings of the existing technology, the purpose of this invention is to provide a method for modeling the parasitic capacitance of LDMOS for different voltage applications, so as to realize an LDMOS model that can be applied to different voltages.

[0007] To achieve the above and other objectives, this invention proposes a method for modeling the parasitic capacitance of LDMOS for different voltage applications, comprising the following steps:

[0008] Step S1: Based on the existing SPICE models of LDMOS under different application voltages, extract the gate-drain parasitic capacitance (Cgd) of LDMOS under different application voltages.

[0009] Step S2: Based on the analysis of the LDMOS device structure and the gate-drain parasitic capacitance Cgd, the gate-drain parasitic capacitance (Cgd) is divided into channel capacitance (cgdc) and overlay capacitance (cgdov), and the corresponding mathematical fitting formula is constructed.

[0010] Step S3: Based on the mathematical fitting formulas of channel capacitance (cgdc) and overlay capacitance (cgdov), the fitting formula of gate-drain parasitic capacitance (Cgd) is obtained, and the data obtained in step S1 is refitted to update the coefficients of the fitting formula of gate-drain parasitic capacitance (Cgd), thereby establishing a new SPICE model.

[0011] Optionally, the channel capacitance (cgdc) is constructed based on the existing SPICE model fitting formula and is used to characterize the parasitic capacitance between the channel end and the gate.

[0012] Optionally, the overlay capacitance (cgdov) is constructed using a linear fitting formula to characterize the parasitic capacitance between the N-type drift region and the polycrystalline silicon field plate.

[0013] Optionally, the construction of the overlay capacitor (cgdov) includes:

[0014] Obtain coverage capacitance data under different application voltages;

[0015] A mathematical fitting trend line is formed based on the acquired coverage capacitance data, thereby obtaining a linear fitting formula;

[0016] Taking into account the dimensions of the parameters, the mathematical fitting formula for the coverage capacitance (cgdov) is obtained.

[0017] Optionally, in step S3, the mathematical fitting formula for the overlay capacitance (cgdov) is added to the mathematical fitting formula for the channel capacitance (cgdc) constructed based on the existing SPICE model fitting formula as the fitting formula for the gate-drain parasitic capacitance (Cgd).

[0018] Optionally, in step S2, the mathematical fitting formula for the channel capacitance (cgdc) constructed based on the existing SPICE model fitting formula is as follows:

[0019] Cgdc=rnwc*w*count*(lc / (lc-rnlc)*(cvar1_n+cvar2_n*(1+tanh(v(g,d1)+cvar3_n) / cvar4_n)))

[0020] Where cvar1_n is the first n-type capacitance coefficient, cvar2_n is the second n-type capacitance coefficient, cvar3_n is the third n-type capacitance coefficient, cvar4_n is the fourth n-type capacitance coefficient, rnwc is the n-type width coefficient, w is the device width, count is the number of repetitions, lc is the effective length of the device, tanh is the hyperbolic tangent function, and v(g,d1) is the gate-drain voltage.

[0021] Optionally, in step S2, the mathematical fitting formula for the constructed covering capacitance cgdov is:

[0022] cgdov=(cgdov1*(pf+pa)-cgdov2)*1e-16

[0023] Where cgdov1 is the first coverage capacitance coefficient, cgdov2 is the second coverage capacitance coefficient, pf is the length of the PF region, and pa is the length of the PA region.

[0024] Optionally, in step S3, the fitting formula for the new gate-drain parasitic capacitance (Cgd) is obtained as follows:

[0025] Cgd=rnwc*w*count*(lc / (lc-rnlc)*(cvar1_n+cvar2_n*(1+tanh(v(g,d1)+cvar3_n) / cvar4_n)))+(cgdov1*(pf+pa)-cgdov2)*1E-16.

[0026] Optionally, in step S3, the coefficients of the updated gate-drain parasitic capacitance (Cgd) fitting formula include the first n-type capacitance coefficient cvar1_n, the second n-type capacitance coefficient cvar2_n, the third n-type capacitance coefficient cvar3_n, the fourth n-type capacitance coefficient cvar4_n, and the n-type width coefficient rnwc.

[0027] Optionally, the original fitting formula and coefficients are retained for the gate parasitic capacitance (Cgb) in the new SPICE model.

[0028] Compared with existing technologies, the present invention provides a method for modeling LDMOS parasitic capacitance for different voltage applications. This method divides the gate-drain parasitic capacitance (Cgd) of an LDMOS device into channel capacitance (cgdc) and overlay capacitance (cgdov), and constructs corresponding mathematical fitting formulas. Then, it adds the mathematical fitting formula for the overlay capacitance (cgdov) to the mathematical fitting formula for the channel capacitance (cgdc) constructed based on existing SPICE model fitting formulas, using this as the fitting formula for the gate-drain parasitic capacitance (Cgd). The model is then refitted to update the coefficients of the gate-drain parasitic capacitance (Cgd) fitting formula, thereby achieving an LDMOS model applicable to different voltages. Attached Figure Description

[0029] Figure 1a This is a schematic diagram of the existing LDMOS structure;

[0030] Figure 1b for Figure 1a The equivalent circuit structure diagram of LDMOS;

[0031] Figure 1c The graph shows the gate capacitance Cgg and gate-source voltage Vgs of an LDMOS transistor.

[0032] Figure 2 This is a schematic diagram illustrating the structure of an LDMOS device.

[0033] Figure 3 The graph shows the variation trend of Cgd for LDMOS devices at different voltages;

[0034] Figure 4 This is a flowchart of a method for modeling the parasitic capacitance of LDMOS for different voltage applications according to the present invention;

[0035] Figure 5 This is a graph showing the mathematical fitting trend relationship between cgdov and pf+pa in an embodiment of the present invention.

[0036] Figure 6a This is a curve showing the capacitor voltage fitting of the 60V withstand voltage device in an embodiment of the present invention;

[0037] Figure 6b This is a curve showing the capacitor voltage fitting of the 80V withstand voltage device in an embodiment of the present invention.

[0038] Figure 6c This is a curve showing the capacitor voltage fitting of a 100V withstand voltage device in an embodiment of the present invention. Detailed Implementation

[0039] The following describes the embodiments of the present invention through specific examples and in conjunction with the accompanying drawings. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific examples, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0040] Figure 2 The diagram shown is a schematic representation of the structure of an LDMOS device. Figure 2 As shown, the gate-drain parasitic capacitance Cgd consists of two parts: the channel capacitance between the channel end and the gate, and the covering capacitance between the N-type drift region (Ndrift)2 and the polysilicon (Poly) 5 field plate. The channel capacitance between the channel end and the gate is represented by cgdc, and the covering capacitance between the N-type drift region (Ndrift)2 and the polysilicon (Poly) 5 field plate is represented by cgdov. Cgd = cgdc + cgdov.

[0041] like Figure 2 As shown, the coverage area between the N-type drift region (Ndrift) 2 and the polysilicon (Poly) 5 field electrode is divided into two parts: PF and PA. PF is the overlapping area of ​​the gate polysilicon (Poly) 5, the shallow channel isolation region (STI) 1, and the N-type drift region (Ndrift) 2. PA is the overlapping area of ​​the shallow channel isolation region (STI) 1 and the N-type drift region (Ndrift) 2.

[0042] from Figure 3 As we can see, for devices with different voltages in LDMOS, the Cgd curve shows the same trend, only with a relative shift. This is because the area between PF+PA and the drift region is equivalent to a capacitor composed of two parallel plates, so increasing PF+PA is equivalent to increasing the length of the capacitor plates. Therefore, cgdov can be simplified as a variable capacitor that varies with the length of PF+PA.

[0043] Based on this, the present invention provides a method for modeling the parasitic capacitance of LDMOS for different voltage applications, such as... Figure 4 As shown, a method for modeling the parasitic capacitance of LDMOS for different voltage applications includes the following steps:

[0044] Step S1: Based on the existing SPICE models of LDMOS with different application voltages, extract the gate-drain parasitic capacitance Cgd of LDMOS under different application voltages.

[0045] Step S2: Based on the analysis of the LDMOS device structure and the gate-drain parasitic capacitance Cgd, the gate-drain parasitic capacitance Cgd is divided into two parts: channel capacitance cgdc and overlay capacitance cgdov, and the corresponding mathematical fitting formula is constructed.

[0046] The channel capacitance cgdc is constructed according to the existing SPICE model fitting formula and is used to characterize the parasitic capacitance between the channel end and the gate. Its mathematical fitting formula is as follows:

[0047] Cgdc=rnwc*w*count*(lc / (lc-rnlc)*(cvar1_n+cvar2_n*(1+tanh(v(g,d1)+cvar3_n) / cvar4_n)))(Formula 1)

[0048] Where cvar1_n is the first n-type capacitance coefficient, cvar2_n is the second n-type capacitance coefficient, cvar3_n is the third n-type capacitance coefficient, cvar4_n is the fourth n-type capacitance coefficient, rnwc is the n-type width coefficient, w is the device width, count is the number of repetitions, lc is the effective length of the device, tanh is the hyperbolic tangent function, and v(g,d1) is the gate-drain voltage.

[0049] The overlay capacitance cgdov was constructed using a linear fitting formula to characterize the parasitic capacitance between the N-type drift region (Ndrift)2 and the polysilicon (Poly) 5 field plate.

[0050] Specifically, to obtain the linear fitting formula for the coverage capacitance cgdov, it is necessary to first obtain the coverage capacitance data. LDMOS transistors with withstand voltages of 60V, 80V, and 100V are selected as the original data, with a width-to-length ratio of 20 / 0.5µm. The corresponding power field (PF) lengths are 1µm, 1.5µm, and 2µm, respectively, and the corresponding power field (PA) lengths are 2.5µm, 3.5µm, and 4.5µm, respectively. The coverage capacitance at 60V withstand voltage is set to 0 under certain gate-source and gate-drain voltages. Under the same conditions, the increment of Cgd is the increment of the coverage capacitance cdgov. The calculated coverage capacitances for 80V and 100V LDMOS transistors are 5 and 10, respectively, as shown in Table 1.

[0051] Table 1. Correspondence between cgdov and device parameters, and PF+PA.

[0052] Voltage W L PF PA PF+PA cgdov 60V 20 0.5 1 1.5 2.5 0 80V 20 0.5 1.5 2 3.5 5 100V 20 0.5 2 2.5 4.5 10

[0053] Using cgdov as the y-axis and the length pf+pa of PF+PA as the x-axis, fit the above data as follows: Figure 5 As shown, the linear fitting formula is obtained as follows:

[0054] y = 5x - 12.5

[0055] Taking into account the dimensions of the parameters, the fitting formula for the coverage capacitance cgdov is shown in Equation 2.

[0056] cgdov=(cgdov1*(pf+pa)-cgdov2)*1e-16 (Formula 2)

[0057] Among them, the first coverage capacitance coefficient cgdov1 = 5, and the second coverage capacitance coefficient cgdov2 = 12.5.

[0058] Step S3: Based on the mathematical fitting formulas of the channel capacitance cgdc and the overlay capacitance cgdov, the fitting formula of the gate-drain parasitic capacitance Cgd is obtained. The data obtained in Step 1 is refitted to update the coefficients of the fitting formula of the gate-drain parasitic capacitance Cgd, and a new SPICE model is established.

[0059] Specifically, the above formula 1 is added to the mathematical fitting formula of the channel capacitance cgdc constructed based on the existing SPICE model fitting formula as the fitting formula for the gate-drain parasitic capacitance Cgd. The data obtained in step S1 is then refitted to update the coefficients of the cgdc fitting formula: the first n-type capacitance coefficient cvar1_n, the second n-type capacitance coefficient cvar2_n, the third n-type capacitance coefficient cvar3_n, the fourth n-type capacitance coefficient cvar4_n, and the n-type width coefficient rnwc, thus establishing a new SPICE model.

[0060] In this embodiment, the fitting formula for the new gate-drain parasitic capacitance Cgd is:

[0061] Cgd=rnwc*w*count*(lc / (lc-rnlc)*(cvar1_n+cvar2_n*(1+tanh(v(g,d1)+cvar3_n) / cvar4_n)))+(cgdov1*(pf+pa)-cgdov2)*1E-16 (Formula 3)

[0062] Where w is the device width, count is the number of repetitions, lc is the effective device length, tanh is the hyperbolic tangent function, v(g,d1) is the gate-drain voltage, pf is the PF region length, and pa is the PA region length.

[0063] After fitting, the new CGDC coefficients are cvar1_n = 2.833544E-3, cvar2_n = 3.69903E-2, cvar3_n = -1.228685, cvar4_n = 1.415433, and rnwc = 1.49E-8.

[0064] It should be noted that for the gate parasitic capacitance Cgb in the model, the original fitting formula and coefficients are retained, and the fitting formula for Cgb is:

[0065] Cgb=rpwc*w*count*(lc / (lc-rplc)*(cvar1_p+cvar2_p*(1+tanh(v(s,g)+cvar3_p) / c var4_p))) (Formula 4)

[0066] Among them, the first p-type capacitance coefficient cvar1_p = 0.886697, the second p-type capacitance coefficient cvar2_p = 0.173778, the third p-type capacitance coefficient cvar3_p = -1.986959, the fourth n-type capacitance coefficient cvar4_p = 0.781666, and the p-type width coefficient rpwc = 1.78E-9.

[0067] Figures 6a-6c This is a comparison curve of the gate capacitance Cgg of LDMOS devices with different withstand voltages (60V, 80V, 100V) obtained by using the model of this invention and existing models when the gate-source voltage Vgs changes (-5.5V to 5.5V). The unit is Farads (F). snld60, snld80, and snld100 represent devices with withstand voltages of 60V, 80V, and 100V, respectively. The corresponding gate-drain voltage Vds is -=0V, the temperature is T=25 degrees, and the width / length / repetition number W / L / M=100 / 0.5 / 10.

[0068] The new model file is shown in the following Spice subcircuit description statement:

[0069]

[0070]

[0071] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can make modifications and changes to the above embodiments without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the claims.

Claims

1. A method for modeling the parasitic capacitance of LDMOS for different voltage applications, comprising the following steps: Step S1: Based on the existing SPICE models of LDMOS with different application voltages, extract the gate-drain parasitic capacitance Cgd of LDMOS under different application voltages. Step S2: Based on the analysis of the LDMOS device structure and the gate-drain parasitic capacitance Cgd, the gate-drain parasitic capacitance Cgd is divided into the channel capacitance cgdc and the overlay capacitance cgdov, and the corresponding mathematical fitting formula is constructed. in, The mathematical fitting formula for the channel capacitance cgdc, constructed based on the existing SPICE model fitting formula, is as follows: Cgdc=rnwc*w*count*(lc / (lc-rnlc)*(cvar1_n+cvar2_n*(1+tanh(v(g,d1)+cvar3_n) / cvar4_n))), Where cvar1_n is the first n-type capacitance coefficient, cvar2_n is the second n-type capacitance coefficient, cvar3_n is the third n-type capacitance coefficient, cvar4_n is the fourth n-type capacitance coefficient, rnwc is the n-type width coefficient, w is the device width, count is the number of repetitions, lc is the effective length of the device, tanh is the hyperbolic tangent function, and v(g,d1) is the gate-drain voltage; The mathematical fitting formula for the constructed covering capacitance cgdov is as follows: cgdov=(cgdov1*(pf+pa)-cgdov2)*1E-16 Where cgdov1 is the first coverage capacitance coefficient, cgdov2 is the second coverage capacitance coefficient, pf is the length of the PF region, and pa is the length of the PA region; Step S3: Based on the mathematical fitting formula of the channel capacitance cgdc and the cover capacitance cgdov, the fitting formula of the gate-drain parasitic capacitance Cgd is obtained, and the data obtained in step S1 is refitted to update the coefficients of the fitting formula of the gate-drain parasitic capacitance Cgd, thereby establishing a new SPICE model. The fitting formula for the new gate-drain parasitic capacitance Cgd is as follows: Cgd=rnwc*w*count*(lc / (lc-rnlc)*(cvar1_n+cvar2_n*(1+tanh(v(g,d1)+cvar3_n) / cvar4_n)))+(cgdov1*(pf+pa)-cgdov2)*1E-16.

2. The LDMOS parasitic capacitance modeling method for different voltage applications as described in claim 1, characterized in that, The channel capacitance cgdc is constructed based on the existing SPICE model fitting formula and is used to characterize the parasitic capacitance between the channel end and the gate.

3. The LDMOS parasitic capacitance modeling method for different voltage applications as described in claim 2, characterized in that, The overlay capacitance cgdov is constructed using a linear fitting formula and is used to characterize the parasitic capacitance between the N-type drift region and the polycrystalline silicon field plate.

4. The LDMOS parasitic capacitance modeling method for different voltage applications as described in claim 3, characterized in that, The construction of the overlay capacitor cgdov includes: Obtain coverage capacitance data under different application voltages; A mathematical fitting trend line is formed based on the acquired coverage capacitance data, thereby obtaining a linear fitting formula; Taking into account the dimensions of the parameters, the mathematical fitting formula for the covering capacitance cgdov is obtained.

5. The LDMOS parasitic capacitance modeling method for different voltage applications as described in claim 1, characterized in that, In step S3, the coefficients of the updated gate-drain parasitic capacitance Cgd fitting formula include the first n-type capacitance coefficient cvar1_n, the second n-type capacitance coefficient cvar2_n, the third n-type capacitance coefficient cvar3_n, the fourth n-type capacitance coefficient cvar4_n, and the n-type width coefficient rnwc.

6. The LDMOS parasitic capacitance modeling method for different voltage applications as described in claim 5, characterized in that, For the gate parasitic capacitance Cgb in the new SPICE model, its original fitting formula and coefficients are retained.

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