A dynamic random access memory cache is provided as a second type of memory

Abstract

Various embodiments are provided for providing a dynamic random access memory ("DRAM") cache as a second type of memory in a computing system by a processor. One or more free bits of the DRAM, a data compression operation, or a combination thereof can be used to clear a selected amount of bytes in a memory row. Cache directory and data can be stored in the memory row. The DRAM cache is configured as a cache of the second type of memory.

Description

TECHNICAL FIELD

[0001] The present invention relates generally to computing systems, and more particularly, to various embodiments of using one or more computing processors to provide dynamic random access memory ("DRAM") as a cache of a second type of memory. BACKGROUND

[0002] In today's society, computer systems are common. Computer systems can be found in the workplace, at home, or at school. Computer systems can include data storage systems or disk storage systems to process and store data. In recent years, both software technology and hardware technology have experienced phenomenal advances. With new technologies, more and more functions are added, and greater convenience is provided for the use of these computer systems. The amount of information to be processed today has greatly increased. Therefore, processing, storing, and / or retrieving various amounts of information are key issues to be addressed. SUMMARY

[0003] Various embodiments are shown for providing dynamic random access memory ("DRAM") cache by a processor as a second type of memory in a computing system. A selected amount of bytes of memory in a memory row can be purged using one or more free bits of the DRAM, a data compression operation, or a combination thereof. Cache directory and data can be stored in the memory row. The DRAM cache is configured as a cache of the second type of memory. BRIEF DESCRIPTION OF DRAWINGS

[0004] In order that the advantages of the invention will be readily understood, a more particular description of the invention, briefly described above, will be rendered by reference to specific embodiments illustrated in the appended drawings. Understanding that these drawings depict only typical embodiments of the invention and are not therefore to be considered to be limiting of its scope, the invention will be described and explained with additional specificity and detail by the use of the accompanying drawings, in which:

[0005] Figure 1 is a block diagram that depicts an exemplary cloud computing node that can be employed in accordance with embodiments of the present invention;

[0006] Figure 2 is an additional block diagram that depicts an exemplary cloud computing environment that can be employed in accordance with embodiments of the present invention;

[0007] Figure 3 is an additional block diagram that depicts an abstraction model layer that can be employed in accordance with embodiments of the present invention;

[0008] Figures 4A-4C is an additional block diagram that depicts the operation of a basic system of dynamic random access memory ("DRAM") cache as a second type of memory in which aspects of the present invention can be implemented;

[0009] Figures 5A-5B is a block diagram depicting a DRAM cache one-to-two ("1-to-2") way and one-to-four ("1-to-4") way set associative cache in accordance with aspects of the present application;

[0010] Figure 6 is an additional block diagram depicting the operation of various options for a dynamic random access memory ("DRAM") cache as a second type of memory that can implement aspects of the present application;

[0011] Figure 7 is an additional block diagram depicting a first order performance estimate in accordance with aspects of the present application; and

[0012] Figure 8 is a flowchart depicting an exemplary method of providing a dynamic random access memory ("DRAM") cache as a second type of memory in a computing system that can implement aspects of the present application. DETAILED DESCRIPTION

[0013] A computing environment can include a main storage device (also referred to as main memory) as well as secondary storage devices. The main storage device is considered to be fast access storage device as compared to secondary storage devices such as memory of a storage class. Further, the addressing of the main storage device is considered to be simpler than addressing storage class memory. Storage class memory is an external storage space beyond the traditional main storage device that provides faster access than direct access storage devices. The storage class memory can be implemented as a group of solid state devices connected to the computing system via a number of input / output (I / O) adapters that are used to map the technology of the I / O devices to the memory bus of the central processing unit(s).

[0014] Additionally, memory devices are used in a wide variety of applications including computer systems. Computer systems containing microprocessors or similar devices and other electronic devices typically include system memory, which is often implemented using dynamic random access memory (DRAM). Thus, it is desirable to use DRAM as a cache for a second type of memory. The second type of memory can be slower, higher capacity, and / or inexpensive DRAM. The second type of memory can also be some other type of memory such as non-volatile memory ("NVM") flash, phase change material ("PCM"), and other emerging memories. In one aspect, the emerging memories have high capacity but are typically slower (latency, bandwidth) than DRAM. Thus, the present application uses DRAM as a cache to mitigate the lower performance of the second ("second") type of memory. Thus, the present application uses DRAM as a cache for the second type of memory addresses the challenge / issue that a cache needs a directory (e.g., tag array), but the current state of the art directory size limits the cache size due to the directory challenge.

[0015] Using DRAM as a cache for the second type of memory has an additional challenge / problem, where adding a directory requires significant resource consumption, design, and engineering effort, while impacting both processor and memory design and scheduling. Thus, the use of the present invention eliminates this second challenge / problem, as the present invention eliminates the need for additional bits in the DRAM for a directory. Idle bits, such as idle bits in Double Data Rate 5 Synchronous ("DDR5") DRAM, are in high demand, are thus typically reserved for other purposes, and the present invention eliminates the need for these idle bits. Also, according to the present invention, there is no need to change the processor "nesting" - the nesting is all the logic between the core and the memory.

[0016] Thus, the present invention provides a DRAM cache as a second type of memory in a computing system. One or more idle bits of the DRAM, a data compression operation, or a combination thereof can be used to clear a selected amount of bytes of memory in a memory row. The cache directory and data can be stored in the memory row. The DRAM cache is configured as a cache for the second type of memory.

[0017] In one aspect, the present invention can release at least 4 bytes of space in a 128 byte memory row using a data compression operation. In another embodiment, if idle bits are available in the DRAM, such as in a DDR5 DRAM, then data compression can not be necessary. The cache directory and data can be placed in the same memory row. Additionally, the entire DRAM and / or a selected amount of the DRAM can become a cache for the SCM / slow DRAM, with an average bandwidth / delay similar to that of the DRAM, and a capacity similar to that of the SCM / slow DRAM. The current state of the art of computer system caching uses a concept called "N-way" associativity, where each memory row can flexibly exist in one of N locations in the cache, where N is a positive integer (e.g., 1, 2, 3, etc.). A larger N means greater flexibility in finding the location of a memory row in the cache. Thus, a highly associative cache has greater flexibility in finding the location of a memory row, but is more complex to implement. A direct mapped cache means that a memory row can only be in one location in the cache, thus less flexible in finding the location of a memory row in the cache, but easier to implement.

[0018] In one aspect, the present invention, depending on the data compressibility, is either a direct-mapped (1-way) DRAM cache or a 2-way set-associative cache due to compression, can be implemented with each of the 1 or 2 cache lines containing 128 bytes. The present invention uses 128 byte size cache lines, same as the state of the art processor caches. Cache lines are exchanged between the cache and the main memory in the same cache line granularity of 128 bytes. In one aspect of the present invention, since the present invention is an all hardware solution, the computing system software support for implementing the cache is not necessary. Thus, the present invention provides an advantage over the current state of the art solutions which 1) use a page-based approach which requires significant software development, 2) have performance loss since even when a single byte in a page needs to be accessed, the computing system has to move the entire data page (64KB) between the DRAM and the SCM / Slow DRAM. In contrast, the present invention moves only 128 bytes, thus reducing the memory bus bandwidth consumption. Due to the hardware solution, the DRAM cache is transparent to any software, e.g., hypervisor, operating system, without relying on any software group.

[0019] In another aspect, the present invention provides a DRAM (storage class memory; assuming the system DRAM and the second type of memory are on separate memory channels (e.g., Open Coherent Accelerator Processor Interface “OCAPI”)) that can be configured as a cache of the SCM, and / or a memory buffer attached to both the DRAM and the SCM. In one aspect, the DRAM cache of the SCM can be performed at similar cost and capacity as the second type of memory (e.g., a 4 terabyte “TB” DRAM cache backed by a 32 TB SCM (where the latency and bandwidth are on average closer to the 32 TB DRAM)).

[0020] The present invention does not require changes to the DRAM or SCM organization, e.g., 1) compatible with any DRAM design based on DDR4, DDR5, HBM, and any SCM, 2) no additional bits needed for the cache directory (e.g., eliminating SRAM arrays, TLBs, etc.), 3) no impact or dependency on the virtual memory subsystem, page tables, page size, 4) the unit of transfer and cache granularity is equal to 128 bytes, which can be equal to the memory transfer unit and L3 line size, 5) unaware of the location of the memory buffer chip of the implemented processor or DRAM cache (with minor area impact), 6) transparent to the existing ECC, and / or 6) operates below the coherence domain, e.g., the DRAM and SCM appear similar to regular DRAM.

[0021] When the cache is a "hit," the DRAM cache can add 1 and / or 2 processor cycles to the DRAM (e.g., regular / normal DRAM) read time, which means that the memory row is present in the cache. When the memory row is not in the DRAM cache, there is a "miss," and the delay to access the memory row is the delay of the SCM delay. The SCM delay depends on the memory technology used, and for SLC flash technology and / or OpenCAPI type of memory device technology, the SCM delay can be 3 to 5 microseconds ("us"), or when the SCM is NAND flash, the SCM delay can be 1-3 microseconds, and when the SCM is PCM, the SCM delay can be 1 microsecond. When the SCM is a slow DRAM technology, the SCM delay can equal two times ("2x") of the regular / normal DRAM.

[0022] It is to be appreciated that, although the present disclosure includes detailed descriptions of cloud computing, implementation of the teachings recited herein are not limited to a cloud computing environment. Rather, embodiments of the present application are capable of being implemented in conjunction with any other type of computing environment now known or later developed.

[0023] Cloud computing is a model of service delivery for enabling convenient, on-demand network access to a shared pool of configurable computing resources (e.g. networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) that can be rapidly provisioned and released with minimal management effort or interaction with a provider of the service. This cloud model can include at least five characteristics, at least three service models, and at least four deployment models.

[0024] Features include the following:

[0025] On-demand self-service: cloud consumers can unilaterally provision computing capabilities, such as server time and network storage, as needed automatically without requiring human interaction with the service's provider.

[0026] Broad network access: capabilities are available over a network and accessed through standard mechanisms that promote use by heterogeneous thin or thick client platforms (e.g., mobile phones, laptops, and PDAs).

[0027] Resource pooling: the provider's computing resources are pooled to serve multiple consumers using a multi-tenant model, with different physical and virtual resources dynamically assigned and reassigned according to demand. There is a sense of location independence in that the consumer generally has no control or knowledge over the exact location of the provided resources but can be able to specify location at a higher level of abstraction (e.g., country, state, or datacenter).

[0028] Fast elasticity: in some cases, capabilities can be rapidly and elastically provisioned, in some cases automatically, which allows for rapid scaling of capabilities, in some cases to large quantities in a short time frame. For consumers, the capacity available for provision often appears to be unlimited and can be purchased in any quantity at any time.

[0029] Measured service: cloud systems automatically control and optimize resource use by leveraging utilization of capacity, often on a transient basis, with users perhaps consuming more of resources at one time than at another based on their requirements or demands. Cloud systems can, in some cases, have mechanisms for limiting any single consumer from using the whole available service capacity. This allows cloud systems to make use of the resources of each of the consumers.

[0030] Service models are as follows:

[0031] Software as a Service (SaaS): the capability provided to the consumer is to use the provider's applications running on a cloud infrastructure. The applications are accessible from various client devices through either a thin client interface, such as a web browser (e.g., web-based e-mail) or a program interface. The consumer does not manage or control the underlying cloud infrastructure including network, servers, operating systems, storage, or even individual application capabilities, with the possible exception of limited user-specific application configuration settings.

[0032] Platform as a Service (PaaS): the capability provided to the consumer is to deploy onto the cloud infrastructure consumer-created or acquired applications created using programming languages and tools supported by the provider. The consumer does not manage or control the underlying cloud infrastructure including networks, servers, operating systems, or storage, but has control over the deployed applications and possibly application hosting environment configurations.

[0033] Infrastructure as a Service (laaS): the capability provided to the consumer is to provision processing, storage, networks, and other fundamental computing resources where the consumer is able to deploy and run arbitrary software, which can include operating systems and applications. The consumer does not manage or control the underlying cloud infrastructure but has control over operating systems, storage, deployed applications, and possibly limited control of select networking components (e.g., host firewalls).

[0034] Deployment models are as follows:

[0035] Private cloud: the cloud infrastructure is operated solely for the organization. It can be managed by the organization or a third party and can exist on-premises or off-premises.

[0036] Community cloud: the cloud infrastructure is shared by several organizations and supports mission-oriented business objectives by providing a common configuration for a group of consumers. It can be managed by the organizations or a third party and can exist on-premises or off-premises.

[0037] Public cloud: the cloud infrastructure is made available to the general public or a large industry group and is owned by an organization selling cloud services.

[0038] Hybrid cloud: the cloud infrastructure is a composition of two or more clouds (private, community, or public) that remain unique entities but are bound together by standardized or proprietary technology that enables data and application portability.

[0039] A cloud computing environment is service-oriented, focusing on stateless, low-coupling, modularity, and semantic interoperability. At the core of cloud computing is an infrastructure comprising a network of interconnected nodes.

[0040] Referring now to the drawing Figure 1 , a schematic diagram of an example of a cloud computing node is shown. Cloud computing node 10 is only one example of a suitable cloud computing node and is not intended to suggest any limitation as to the scope of use or functionality of embodiments of the present application described herein. Regardless, cloud computing node 10 is capable of being implemented and / or performing any of the functionality set forth above in the flow diagrams.

[0041] Within cloud computing node 10 there is a computer system / server 12, which is operational with numerous other general purpose or special purpose computing system environments or configurations. Examples of well- known computing systems, environments, and / or configurations that can be suitable for use with computer system / server 12 include, but are not limited to, personal computer systems, server computer systems, thin clients, thick clients, hand-held or laptop devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of the above systems or devices, and the like.

[0042] Computer system / server 12 can be described in the general context of computer system-executable instructions, such as program modules being executed by a computer system. Generally, program modules can include routines, programs, objects, components, logic, data structures, and so on that perform particular tasks or implement particular abstract data types. Computer system / server 12 can be practiced in distributed cloud computing environments with remote processing devices that are linked through a communications network. In a distributed cloud computing environment, program modules can be located in both local and remote computer system storage media including memory storage devices.

[0043] As Figure 1 shown, computer system / server 12 in cloud computing node 10 is shown in the form of a general-purpose computing device. The components of computer system / server 12 can include, but are not limited to, one or more processors or processing units 16, a system memory 28, and a bus 18 that couples various system components including system memory 28 to processor 16.

[0044] Bus 18 represents one or more of several types of bus structures, including a storage bus or

[0045] Computer system / server 12 typically includes a variety of computer system readable media. Such media might include computer system readable media in the form of volatile and non-volatile media, removable and non-removable media.

[0046] System memory 28 can include computer system readable media in the form of volatile memory, such as random access memory (RAM) 30 and / or cache memory 32. Computer system / server 12 can further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, a storage system 34 can be provided for reading from and writing to non-removable, non-volatile magnetic media (not shown and typically called a "hard drive"). Although not specifically shown, a magnetic disk drive can also be provided for reading from and writing to a removable, non-volatile magnetic disk (e.g., a "floppy disk"), and an optical disk drive can be provided for reading from or writing to a removable, non-volatile optical disk (such as a CD-ROM, DVD-ROM or other optical media). Each of these disk drives and their associated computer system readable media can also be connected to bus 18 by one or more data media interfaces. As will be further depicted and described below, system memory 28 can include at least one program product having a set (e.g., at least one) of program modules that are configured to carry out the functions of embodiments of the application.

[0047] Program / utility 40 having a set (at least one) of program modules 42 can be stored in system memory 28 by way of example, and not limitation, as well as an operating system, one or more application programs, other program modules, and program data. Each of the operating system, one or more application programs, other program modules, and program data or some combination thereof, can include an implementation of a networking environment. Program modules 42 generally carry out the functions and / or methodologies of embodiments of the application as described herein.

[0048] Computer system / server 12 can also communicate with one or more external devices 14, such as a keyboard, indicating device, display 24, etc.; one or more devices that enable users to interact with computer system / server 12; and / or devices that enable computer system / server 12 to communicate with one or more other computing devices (e.g., network interface cards, modems, etc.). This communication can occur via input / output (I / O) interface 22. However, computer system / server 12 can communicate with one or more networks, such as local area networks (LANs), general-purpose wide area networks (WANs), and / or public networks (e.g., the Internet), via network adapter 20. As shown, network adapter 20 communicates with other components of computer system / server 12 via bus 18. It should be understood that, although not shown, other hardware and / or software components can be used in conjunction with computer system / server 12, examples including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archive storage systems.

[0049] Now for reference Figure 2 The diagram illustrates an illustrative cloud computing environment 50. As shown, the cloud computing environment 50 includes one or more cloud computing nodes 10 to which local computing devices used by cloud consumers can communicate, such as personal digital assistants (PDAs) or cellular phones 54A, desktop computers 54B, laptop computers 54C, and / or automotive computer systems 54N. The nodes 10 can communicate with each other. They can be physically or virtually grouped (not shown) within one or more networks, such as private clouds, community clouds, public clouds, or hybrid clouds, or combinations thereof, as described above. This allows the cloud computing environment 50 to provide infrastructure, platform, and / or software as a service, without requiring cloud consumers to maintain resources on their local computing devices. It should be understood that... Figure 2 The types of computing devices 54A-N shown are for illustrative purposes only, and computing node 10 and cloud computing environment 50 can communicate with any type of computing device over any type of network and / or network-addressable connection (e.g., using a web browser).

[0050] Now for reference Figure 3 This demonstrates a cloud computing environment of 50 ( Figure 2 This provides a set of functional abstractions. It should be understood beforehand that... Figure 3 The components, layers, and functions shown are for illustrative purposes only, and embodiments of the invention are not limited thereto. As depicted, the following layers and corresponding functions are provided:

[0051] The device layer 55 includes physical and / or virtual devices embedded with and / or independent of electronics, sensors, actuators, and other objects to perform various tasks in the cloud computing environment 50. Each device in the device layer 55 incorporates networking capability into other functional abstraction layers, such that information obtained from the device can be provided to the device, and / or information from other abstraction layers can be provided to the device. In one embodiment, the various devices, including the device layer 55, can incorporate into a network of entities collectively referred to as the "Internet of Things" (IoT). As those skilled in the art will appreciate, such a network of entities allows for the intercommunication, collection, and propagation of data for a variety of purposes.

[0052] As shown, the device layer 55 includes sensors 52, actuators 53, a "learning" thermostat 56 with integrated processing, sensors, and networking electronics, a camera 57, controllable household outlets / sockets 58, and controllable electrical switches 59, as shown. Other possible devices can include, but are not limited to, various additional sensor devices, networking devices, electronic devices such as remote control devices, additional actuator devices, so-called "smart" appliances such as refrigerators or washing / drying machines, and a wide variety of other possible interconnected objects.

[0053] The hardware and software layer 60 includes hardware and software components. Examples of hardware components include: mainframes 61; RISC (Reduced Instruction Set Computer) architecture based servers 62; servers 63; blade servers 64; storage devices 65; and networks and networking components 66. In some embodiments, software components include network application server software 67 and database software 68.

[0054] The virtualization layer 70 provides an abstraction layer from which the following examples of virtual entities can be provided: virtual servers 71; virtual storage 72; virtual networks 73, including virtual private networks; virtual applications and operating systems 74; and virtual clients 75.

[0055] In one example, management layer 80 can provide the functions described below. Resource provisioning 81 provides dynamic procurement of computing resources and other resources that are utilized to perform tasks within the cloud computing environment. Metering and Pricing 82 provide cost tracking as resources are utilized within the cloud computing environment, and billing or invoicing for consumption of these resources. In one example, these resources can include application software licenses. Security provides identity verification for cloud consumers and tasks, as well as protection for data and other resources. User portal 83 provides access to the cloud computing environment for consumers and system administrators. Service level management 84 provides cloud computing resource allocation and management such that required service levels are met. Service Level Agreement (SLA) planning and fulfillment 85 provide pre-arrangement for, and procurement of, cloud computing resources for which a future requirement is anticipated in accordance with an SLA.

[0056] Workloads layer 90 provides examples of functionality that can be utilized by the cloud computing environment. Examples of workloads and functionality that can be provided from this layer include: mapping and navigation 91; software development and lifecycle management 92; virtual classroom education delivery 93; data analytics processing 94; transaction processing 95; and, in the context of the illustrated embodiments of the present application, various workloads and functionality 96 for providing dynamic random access memory ("DRAM") caching in a computing environment. Additionally, the workloads and functionality 96 for providing dynamic random access memory ("DRAM") caching in a computing environment can include operations such as data analytics (including data collection and processing from various environmental sensors) and / or analytics operations. Those of ordinary skill in the art will appreciate that the workloads and functionality 96 for providing dynamic random access memory ("DRAM") caching in a computing environment can also work in conjunction with other portions of the various abstraction layers, such as those in hardware and software 60, virtualization 70, management 80, and other workloads 90 (such as data analytics processing 94) to achieve the various purposes of the illustrated embodiments of the present application.

[0057] As previously noted, the present application provides a novel solution for providing DRAM as a cache of a second type of memory. In operation, existing DRAM can be accessed and utilized. The SCM or slow DRAM can be an OCAPI or attached memory bus. The SCM / slow DRAM size can be an integer multiple of the DRAM size (e.g., a minimum 2x size, such as a 1 terabyte ("TB") DRAM and a 16 TB SCM / slow DRAM. The storage unit in this DRAM cache is a 128 byte size block of data, hereinafter referred to as a "line".

[0058] The higher SCM address bits can become tags in the cache (e.g., the address tag size bits can equal log2(SCM size / DRAM size), equal 4 bits, and / or can equal a maximum 8 bit tag for any future expansion (e.g., a 256 capacity ratio of SCM to DRAM).

[0059] Additionally, 128 byte memory lines can be compressed, where each memory line can be compressed to 124 bytes or less (e.g., using a small and fast compressor). In one aspect, all or a portion of the memory lines will be compressed to a selected / desired result of the original size (e.g., 124 / 128 = 97%). Once the memory line is compressed, its corresponding address tag can be stored in the 4 byte space released in the cache line due to compression (e.g., tag size is the maximum 8 bits indicated previously). The compressed cache line also contains valid and modified bits (2 bits) and / or a compressed and cached ID (CID) field (e.g., 20 or 21 bits long). The CID field in the cache line indicates when the memory line is stored in compressed form in the DRAM cache. The CID is a predetermined bit pattern recognized by the memory controller in identifying whether the cache line is compressed. When a memory line cannot be compressed, there is no CID bit pattern. Thus, in one aspect of the invention, uncompressed memory lines are stored in the SCM and not in the DRAM cache.

[0060] If the memory line is compressed to 60 bytes or less, two compressed memory lines can be stored in one 128 byte size cache line (e.g., 2-way set associative DRAM cache). In this case, each compressed line includes 4 bytes of control information (tag, CID, valid, modified) plus 60 bytes of compressed data, thus 64 bytes in total. Thus, two compressed memory lines can be stored in the location of one 128 byte cache line. Control bits can be added in the released space to indicate whether the cache line is a 1-way or 2-way set associative DRAM cache (e.g., fast / small memory 520 (e.g., fast / small type 1 memory)).

[0061] It should be noted that the CID can be a 20 bit arbitrary constant set at power up, e.g., CID = 0xEDB3A. The selected CID value is written to the SystemCID register and from that time on, this value is used to recognize compressed cache lines.

[0062] When the CID value stored in the cache line is equal to the SystemCID register, it indicates that the 128 byte line is in compressed format, thus the memory line contains control information, e.g., cache tag, valid and / or modified bits.

[0063] When the CID value stored in the cache line does not equal the SystemCID register, it indicates that the 128 byte line contains raw data in uncompressed form. The SystemCID register value never changes, but it can be subjected to a logical operation (e.g., XOR operation) with the hash of the memory address when stored in the cache line. In another aspect, the SystemCID register contents can be updated periodically, but the cache line in DRAM must be updated accordingly.

[0064] For a read hit, the following operations can be performed. A memory line can be requested from the DRAM that is used as a cache for a second type of memory (e.g., SCM). The CID field in the cache line can be compared to the SystemCID register. If the two values are equal, then the line is compressed. The valid bit for the line is checked. If the line is valid, the address tag stored in the cache line is compared to the address requested by the processor. If the requested line is found in the DRAM cache (e.g., cache read hit), the data can be decompressed and passed to the processor.

[0065] For a read miss, the following operations can be performed. The CID field in the cache line can be compared to the SystemCID register. If the two values match, then the line is compressed. The valid bit is checked. If the line is valid, the address tag stored in the cache line is compared to the address requested by the processor. If the requested address does not match the stored tag, then the line is not found in the DRAM cache (e.g., cache miss). After a miss, the 128 byte miss memory line is fetched / retrieved from the SCM and passed to the processor. If the 128 byte memory line passed to the processor compresses to 124 bytes or less, then the existing line in the DRAM cache can be replaced and written back to the SCM if necessary. The new address tag and control fields can be written to the DRAM cache line (e.g., newly written memory line in the DRAM cache). The CID field can be written to indicate that the memory line is cached and compressed. If the 128 byte memory block does not compress, then the existing DRAM cache line is not replaced.

[0066] For a write hit, the following can be performed. A memory line can be first read from the DRAM cache. The CID field of the line can be compared to the SystemCID register. The stored address tag can be compared to the address requested by the processor. Assuming the requested memory line is located / found in the DRAM, the written line can be compressed. If the store line is 124 bytes or less, the existing store line can be overwritten (no write back needed). If the memory line is not compressed, the DRAM line can be set to invalid and the memory line can be written to the SCM. Optionally, the implied line can be brought from the SCM to the DRAM.

[0067] For a write miss, the following can be performed. A memory line can be first read from the DRAM cache. The CID field of the line can be compared to the SystemCID register. The address tags can be compared. Assuming the requested memory line is not located in / or found in the DRAM, the written block can be compressed. If 124 bytes or less, the existing line can be replaced (and if the modified bit is valid, the old line is written back to the SCM). If the store line is not compressed, the store line can be written to the SCM and the old store line is not replaced.

[0068] Figures 4A-4C The operation of the base system 400 for a dynamic random access memory (“DRAM”) cache as a second type of memory is described. That is, the block diagram of the base system 400 depicts a processor 410, a fast / small memory 420 (e.g., a fast / small first type of memory, such as a DRAM cache), and a slow / large memory 430 (e.g., a slow / large second type of memory, such as an SCM). That is, the fast / small memory 420 is used as a DRAM cache for the slow / large memory 430 (e.g., a slow / large second type of memory). In one aspect, Figures 1-3 One or more of the components, modules, services, applications, and / or functions described in Figures 4A-4C may be used in

[0069] Turning now to Figure 4A In a first step, the operation of the base system 400 uses the DRAM cache to store a 128 byte slow memory line (@address b0, b1, b2, b3, b4) by reading a 128 byte slow memory line (@address b0, b1, b2, b3, b4). In a second step, on the processor 410, the 128 byte slow memory line (@address b0, b1, b2, b3, b4) can be compressed to 124 bytes (or less), freeing 4 bytes.

[0070] In a third step, higher address bits bO, b1, referred to as "tags," are written into the 4-byte free space. At this point, the tags (e.g., higher address bits bO, b1) and the data are stored in the same 128-byte line. In a fourth step, the 128-byte line (from processor 410) can be written to the memory line (@address b2, b3, b4 of fast / small memory 420. It should be noted that there are no changes required in the memory organization, nor are there additional bits or computer components (e.g., hardware lines) required.

[0071] Turning now to Figure 4B When processor 410 needs to read from memory line (@address bO, b1, b2, b3, b4), in a first action step, the top / higher address bits bO, b1 can be stripped from the memory line @address bO, b1, b2, b3, b4, and then the processor requests a read from the memory line @address b2, b3, b4 of fast / small memory 420. In a second action step, if the tag (e.g., higher address bits bO, b1) read from the memory line @address b2, b3, b4 of fast / small memory 420 matches the requested address, then there is a cache hit. The cData (e.g., cache data) of 124B or less can be decompressed and passed to processor 410 (e.g., processor core). Alternatively, in a third action step, if the tag (e.g., higher address bits bO, b1) read from the memory line @address b2, b3, b4 of fast / small memory 420 does not match the requested address, then there is a cache miss.

[0072] From Figure 4B the third action step of a cache miss (e.g., if the tag (e.g., higher address bits bO, b1) read from the memory line @address b2, b3, b4 of fast / small memory 420 does not match the requested address, then there is a cache miss), in a fourth action step as shown in Figure 4C the missed address of memory line @address bO, b1, b2, b3, b4 must be sent to slow / large memory 430 (e.g., slow / large second type memory).

[0073] Turning now to Figures 5A-5B , Figure 5A depicts a one-to-two ("1-to-2") way set associative DRAM cache 500 and a one-to-four ("1-to-4") way set associative DRAM cache (e.g., fast / small memory 520 of Figures 4A-4C In one aspect, Figures 1-4A -Figure 4C One or more of the components, modules, services, applications, and / or functions described in the Figures 5A-5B may be used in For brevity, repeated description of similar elements, components, modules, services, applications, and / or functions employed in other embodiments described herein is omitted.

[0074] As Figure 5A depicted, if 128 byte rows are each compressed to less than 60 bytes, two memory rows can be placed / stored in the space of one memory row of the fast / small memory 420 (e.g., fast / small type 1 memory). That is, if the total of two memory rows compressed is 120B or less, they can be placed in the same memory row. In other words, the two memory rows at memory row @address b0, b1, b2, b3, b4 and memory row @address a0, a1, b2, b3, b4 are in the same physical memory row @address b2, b3, b4. Thus, a 2-way associativity cache is desirable as it generally increases cache hit rate.

[0075] Turning now to Figure 5B , an alternate "second chance" location can be dynamically selected for each memory row, further adding (e.g., doubling) the associativity from a 2-way associativity cache to a 4-way associativity cache. If the first location (e.g., first memory row) is a cache miss, a second location (e.g., second memory row) can be searched. The second location means two reads (e.g., read first location then read second location), which will increase read latency (1.5 microseconds on average). However, if cache miss penalty is high, searching the second location in the fast / small memory 420 (e.g., fast / small type 1 memory) can be preferable as the increased associativity reduces misses to the slow / large memory 430 (e.g., slow / large type 2 memory). Figures 4A-4C

[0076] It should be noted that the fast / small memory 420 can be referred to as a 1-to-4 way associativity cache as in the worst case, two rows will not each compress to 60B and each location will store one row (e.g., 2-way). In the best case scenario, two locations (e.g., first and second locations of the fast / small memory 420) can store 2 rows. In the average scenario (e.g., middle), one location can have 2 rows and the other location can have 1 row (3-way).

[0077] Figure 6is an additional block diagram depicting operations of various options for a dynamic random access memory ("DRAM") cache as a second type of memory that can implement aspects of the application. In one aspect, Figures 1-5A Figure 5B One or more of the components, modules, services, applications, and / or functions described in Figure 6 are used in Repetitive description of like elements, components, modules, services, applications, and / or functions employed in other embodiments described herein is omitted for sake of brevity.

[0078] As depicted in system 610, the system 610 can include a processor connected to a memory buffer ("MB") via a bus. Each of the DRAM and SCM MBs can be associated with the MB. The SCM MB can be associated with the SCM. In this configuration, the cache logic can be entirely contained in the MB. The DRAM capacity can be a substantial portion of the SCM to increase cache hit rates.

[0079] As depicted in system 620, the system 640 can include a processor connected to a memory buffer ("MB") via a first bus and to a SCM MB via a second bus. The DRAM can be associated with the MB. The SCM can be associated with the MB.

[0080] In this configuration, the cache logic can be entirely handled by the processor with the memory buffer and memory controller being entirely unaware of cache activity. The DRAM (e.g., server DRAM) can be a DRAM cache of the SCM that can have a selected amount of storage capacity (e.g., up to a size of several megabytes). The DRAM (e.g., server DRAM) can occupy a selected number of memory ports (e.g., a majority of the memory ports) and be optimized for performance (e.g., optimized bandwidth and minimized latency).

[0081] The SCM can also occupy fewer memory ports and be optimized for storage capacity. As a result, the hybrid memory system performance is similar to a server DRAM with the cost capacity of the SCM (e.g., less than 50% of the cost of the all-DRAM system).

[0082] Turning now to Figure 7 Table 700 describes first order performance estimates. In one aspect, Figures 1-6 One or more of the components, modules, services, applications, and / or functions described in Figure 7 are used in Repetitive description of like elements, components, modules, services, applications, and / or functions employed in other embodiments described herein is omitted for sake of brevity.

[0083] As depicted, table 700 depicts first order performance estimates for a base system (DRAM only), slow DRAM, DRAM cache, and slow DRAM (e.g., 90% cache hit rate on DRAM cache), SCM, and DRAM cache and SCM (e.g., 90% cache hit rate on DRAM cache). The first order performance estimates include average latency relative to DRAM, relative CPI, and details. Cycles per instruction (CPI) is a figure of merit that describes processor performance. The lower the CPI, the higher the performance. Simulation results show that memory latency is responsible for 20% of the CPI (e.g., 10-30% on average depending on the processor workload). As depicted, column 710 of table 700 shows how to calculate the average CPI. For example, slow DRAM has a 2.0x latency of DRAM. Since slow DRAM accounts for 20% of the CPI and it has a 2x latency of DRAM, the average CPI calculated in the second row of 710 is 1.2. However, if slow SRAM is combined with DRAM cache, the average latency would be 1.2, a reduction from 2.0 of the slow DRAM solution, and thus the calculation of the 3rd row in 710 shows that the DRAM cache and slow DRAM solution (e.g., DRAM cache + slow DRAM solution) has an average CPI of 1.04, which is less than the average CPI of 1.2 of the slow DRAM solution.

[0084] Turning now to Figure 8 , a method 800 is depicted for providing a dynamic random access memory ("DRAM") cache as a second type of memory in a computing environment, in which various aspects of the illustrated embodiments can be implemented. The functionality 800 can be implemented as a method performed as instructions on a machine, where the instructions are included on at least one computer readable medium or non-transitory machine readable storage medium. The functionality 800 can begin in block 802.

[0085] As shown in block 804, a selected amount of bytes of memory in a memory line can be freed (e.g., purged, replaced, and / or edited) using one or more free bits of the DRAM, a data compression operation, or a combination thereof. The cache directory and data can be placed (and stored) in a memory line (e.g., in the same memory line), as in block 806. As in block 808, the DRAM cache is implemented / configured as a cache of the second type of memory (e.g., a direct mapped DRAM cache or a one-to-many set associative cache). The functionality 800 can end in block 810.

[0086] In one aspect, in conjunction with Figure 8The operations of the functions 800 can include, as at least one of the steps of and / or as part of at least one step of, each of the following. The operations of the functions 800 can configure a DRAM cache as a cache of a storage class memory ("SCM") or a slow DRAM solution, and / or configure the DRAM cache as a direct-mapped DRAM cache or a set-associative cache.

[0087] The operations of the functions 800 can configure the DRAM cache as a single-way or double-way set-associative cache in which two memory rows are placed in the same location, and / or configure the DRAM cache as a pair of four-way set-associative caches in which two memory rows are placed in a first same location and two alternate memory rows are placed in a second same location.

[0088] The operations of the functions 800 can compress data in a selected amount of bytes in a memory row to make room for both a cache directory and data. The operations of the functions 800 can add tags and metadata in a freed-up segment of data in the memory row.

[0089] The operations of the functions 800 can compress a memory row equal to or less than 124 bytes and free up at least four bytes, store tags and data in the memory row, and / or write the memory row to a first type of memory and a second type of memory.

[0090] The present application can be a system, a method, and / or a computer program product. The computer program product can include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present application.

[0091] The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium can be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.

[0092] Computer readable program instructions described herein can be downloaded to respective computing / processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and / or a wireless network. The network can comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer readable program instructions from the network and forwards the computer readable program instructions to storage media within the respective computing / processing device for execution by a processor.

[0093] Computer readable program instructions for carrying out operations of the present application can be assembly instructions, instruction-set-architecture (ISA) instructions, machine- related instructions, microcode, firmware instructions, state-setting data, or source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) can execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present application.

[0094] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable data processing apparatus, or other device implement the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0095] These computer-readable program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / actions specified in one or more blocks of a flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, programmable data processing apparatus, and / or other devices to operate in a particular manner, such that the computer-readable storage medium in which the instructions are stored includes an article of writing comprising instructions for implementing aspects of the functions / actions specified in one or more blocks of a flowchart and / or block diagram.

[0096] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer-implemented process, such that the instructions, which execute on the computer, other programmable apparatus or other device, perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0097] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions comprising one or more executable instructions for implementing a specified logical function. In some alternative embodiments, the functions mentioned in the blocks may occur in a different order than those mentioned in the figures. For example, two blocks shown consecutively may actually be executed substantially simultaneously, or these blocks may sometimes be executed in reverse order, depending on the functions involved. It will also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

Claims

1. A method performed by a processor for providing a dynamic random access memory (DRAM) cache as a second type of memory in a computing environment, comprising: cleaning a selected amount of bytes in a memory line using one or more free bits of the DRAM, a data compression operation, or a combination thereof, wherein the data compression operation compresses a memory line equal to or less than 124 bytes and frees at least four bytes, and the data compression operation includes compressing one memory line; and storing both a cache directory and data in the memory line, wherein the memory line is written to a first type of memory and a second type of memory, and wherein the DRAM cache is configured as a cache of the second type of memory, wherein uncompressed memory lines are written in the first type of memory without being stored in the second type of memory.

2. The method of claim 1, further comprising configuring the DRAM cache as a cache of a storage class memory (SCM) or a slow DRAM solution.

3. The method of claim 1, further comprising configuring the DRAM cache as a direct mapped cache or a set associative cache.

4. The method of claim 1, further comprising: configuring the DRAM cache as a two-way set associative cache, wherein two memory lines are placed in similar locations; or configuring the DRAM cache as a four-way set associative cache, wherein two memory lines are placed in a first similar location and two replacement memory lines are placed in a second similar location.

5. The method of claim 1, further comprising compressing data in the selected amount of bytes in the memory line to place both the cache directory and data.

6. The method of claim 1, further comprising adding tags and metadata in a data segment cleaned in the memory line.

7. A system for providing a dynamic random access memory (DRAM) cache as a second type of memory in a computing environment, comprising: one or more computers with executable instructions that when executed cause the system to: clean a selected amount of bytes in a memory line using one or more free bits of the DRAM, a data compression operation, or a combination thereof, wherein the data compression operation compresses a memory line equal to or less than 124 bytes and frees at least four bytes, and the data compression operation includes compressing one memory line; store both a cache directory and data in the memory line, wherein the memory line is written to a first type of memory and a second type of memory, and wherein the DRAM cache is configured as a cache of the second type of memory, wherein uncompressed memory lines are written in the first type of memory without being stored in the second type of memory.

8. The system of claim 7, wherein, the executable instructions configure the DRAM cache as a cache of a storage class memory (SCM) or a slow DRAM solution.

9. The system of claim 7, wherein the executable instructions configure the DRAM cache as a direct-mapped DRAM cache or a set-associative cache.

10. The system of claim 7, wherein the executable instructions further: configure the DRAM cache as a two-way set-associative cache, wherein two memory lines are placed in similar locations; or configure DRAM cache as a four-way set-associative cache, wherein two memory lines are placed in a first similar location and two alternate memory lines are placed in a second similar location.

11. The system of claim 7, wherein the executable instructions compress data in the selected amount of bytes in the memory line to place both the cache directory and data.

12. The system of claim 7, wherein the executable instructions add tags and metadata in a section of the memory line that is cleared of data.

13. A computer program product for providing a dynamic random access memory (DRAM) cache as a second type of memory in a computing environment by a processor, the computer program product comprising a non-transitory computer-readable storage medium having computer-readable program code portions stored therein, the computer-readable program code portions comprising: an executable portion that clears a selected amount of bytes in a memory line using one or more free bits of the DRAM, a data compression operation, or a combination thereof, wherein the data compression operation compresses a memory line equal to or less than 124 bytes and frees at least four bytes, and the data compression operation includes compressing one memory line; and an executable portion that stores both a cache directory and data in the executable portion in the memory line, wherein the memory line is written to a first type of memory and a second type of memory, and wherein the DRAM cache is configured as a cache of the second type of memory, wherein uncompressed memory lines are written to the first type of memory without being stored in the second type of memory.

14. The computer program product of claim 13, further comprising an executable portion that configures the DRAM cache as a cache of a storage class memory (SCM) or a slow DRAM solution.

15. The computer program product of claim 13, further comprising an executable portion that configures the DRAM cache as a direct-mapped DRAM cache or a set-associative cache.

16. The computer program product of claim 13, further comprising an executable portion that: configures DRAM cache as a two-way set-associative cache, wherein two memory lines are placed in similar locations; configures DRAM cache as a four-way set-associative cache, wherein two memory lines are placed in a first similar location and two alternate memory lines are placed in a second similar location; or compresses data in the selected amount of bytes in the memory line to place both the cache directory and data.

17. The computer program product of claim 13, further comprising adding tags and metadata to executable portions in the section of data being flushed in the memory row.

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