Resistive random access memory cell integrated with vertical field effect transistor

Abstract

A one-transistor two-resistor (1T2R) resistive random access memory (ReRAM) structure and a method for forming the structure includes forming a vertical field effect transistor (VFET) including an epitaxial region (810) located above a channel region (502) and below a dielectric cap (708). The epitaxial region (810) includes two opposing protruding regions of triangular shape bounded by <111> planes that extend horizontally beyond the channel region (502). A ReRAM stack is deposited conformally on the VFET. The ReRAM stack includes an oxide layer (1910) located directly above the epitaxial region (810), a top electrode layer (1912) directly above the oxide layer (1910), and a metal fill (1920) above the top electrode layer (1912). Each of the two opposing protruding regions of the epitaxial region (810) acts as a bottom electrode of the ReRAM stack.

Description

Technical Field

[0001] This invention relates generally to the field of magnetic storage devices, and more specifically to the integration of resistive random access memory (ReRAM) devices with vertical field-effect transistors (VFETs). Background Technology

[0002] ReRAM is one of the most promising technologies for non-volatile memory devices. Due to its low power consumption, high-speed operation, high-density CMOS-compatible integration, and high cycle endurance, ReRAM technology is becoming the mainstream choice for high-density memory arrays and new in-memory computing systems.

[0003] The basic ReRAM mechanism is based on the formation and breakage of nanoscale conductive filaments, typically formed between two electrodes, which results in repeatable resistance switching between high-resistance and low-resistance states. A drawback of the ReRAM mechanism is its reliance on randomness and the uncontrolled placement of the conductive filaments. Therefore, improved designs and techniques for forming ReRAM devices are desired. Summary of the Invention

[0004] This invention addresses the shortcomings of the prior art and provides additional advantages by providing a method for forming a semiconductor device. The method includes: forming a vertical field-effect transistor (VFET), the VFET including an epitaxial region above a channel region and below a dielectric cap. The epitaxial region includes two opposing triangular protrusions extending horizontally beyond the channel region. A resistive random access memory (RAM) stack is conformally deposited on the VFET, the RAM stack including an oxide layer directly above the epitaxial region, a top electrode layer directly above the oxide layer, and a metal filler above the top electrode layer. Each of the two opposing protrusions of the epitaxial region serves as a bottom electrode of the resistive RAM stack.

[0005] Another aspect of the present invention provides a method for forming a semiconductor device, the method comprising: forming a doped source on a substrate; forming a dummy gate on the doped source, the dummy gate being disposed between a first spacer disposed on the doped source and a second spacer disposed on the dummy gate; forming a trench in the dummy gate, the first spacer, and the second spacer to expose the doped source, and growing an epitaxial layer within the trench, away from the doped source, to form a channel region extending from the doped source and through the dummy gate; the top of the channel region being recessed to form a dielectric cap; growing an epitaxial region on a portion of the channel region to form a source / drain region above the dummy gate and below the dielectric cap, the epitaxial region including two opposing triangular protrusions extending horizontally beyond the channel region; replacing the dummy gate with a gate stack comprising a metal gate material surrounding the channel region; and etching the metal gate material to expose the epitaxial region. A first interstage dielectric layer is formed to separate the epitaxial region from the metal gate material, and an oxide layer and a top electrode are conformally deposited over the first interstage dielectric layer, the outer surface of the epitaxial region, and the sidewalls of the dielectric cap.

[0006] Another aspect of the present invention provides a semiconductor device comprising: a vertical field-effect transistor (VFET) including an epitaxial region located above a channel region and below a dielectric cap, the epitaxial region including two opposing triangular protrusions extending horizontally beyond the channel region; and a resistive random access memory (RAM) structure on each side of the epitaxial region and the dielectric cap. The resistive RAM structure includes an oxide layer directly above the outer surface of the epitaxial region and the sidewall of the dielectric cap, a top electrode layer directly above the oxide layer, and a metal filler above the top electrode layer. Each of the two protrusions of the epitaxial region serves as a bottom electrode of the resistive RAM structure. Attached Figure Description

[0007] The following detailed description, given by way of example and not intended to limit the invention thereto, will be best understood in conjunction with the accompanying drawings:

[0008] Figure 1 This is a cross-sectional view of a semiconductor device during an intermediate step in a method for manufacturing a vertical field-effect transistor (VFET) according to an embodiment of the present disclosure.

[0009] Figure 1A yes Figure 1 Top view.

[0010] Figure 2 This is a cross-sectional view of a semiconductor device according to an embodiment of the present disclosure, showing a trench formed through a dielectric capping layer, a second spacer, and a dummy gate.

[0011] Figure 2A yes Figure 2 Top view.

[0012] Figure 3 This is a cross-sectional view of a semiconductor device after etching through a first spacer to expose the doped source and form a self-aligned junction, according to an embodiment of the present disclosure.

[0013] Figure 3A yes Figure 3 Top view.

[0014] Figure 4 This is a cross-sectional view of a semiconductor device after the interior of the oxidized dummy gate sidewall, according to an embodiment of the present disclosure.

[0015] Figure 4A yes Figure 4 Top view.

[0016] Figure 5 This is a cross-sectional view of a semiconductor device after an epitaxial layer has been grown from a doped source to form an epitaxial channel region, according to an embodiment of the present disclosure.

[0017] Figure 5A yes Figure 5 Top view.

[0018] Figure 6 This is a cross-sectional view of a semiconductor device after a planarization process, according to an embodiment of the present disclosure.

[0019] Figure 6A yes Figure 6 Top view.

[0020] Figure 7 This is a cross-sectional view of a semiconductor device after the channel region has been partially recessed, filled with dielectric material to form a dielectric cap, and the dielectric material has been planarized, according to an embodiment of the present disclosure.

[0021] Figure 7A yes Figure 7 Top view.

[0022] Figure 8 This is a cross-sectional view of a semiconductor device after the dielectric capping layer has been removed and an epitaxial region has been formed on the channel region to form the source / drain region, according to an embodiment of the present disclosure.

[0023] Figure 8A yes Figure 8 Top view.

[0024] Figure 9 This is a cross-sectional view of a semiconductor device after spacers have been deposited on an epitaxial region according to an embodiment of the present disclosure.

[0025] Figure 9A yes Figure 9 Top view.

[0026] Figure 10 This is a cross-sectional view of a semiconductor device after removing the portion of the second spacer and the dummy gate, according to an embodiment of the present disclosure.

[0027] Figure 10A yes Figure 10 Top view.

[0028] Figure 11 This is a cross-sectional view of a semiconductor device after the remaining portion of the dummy gate below the spacer has been removed to expose a thin oxide layer, according to an embodiment of the present disclosure.

[0029] Figure 11A yes Figure 11 Top view.

[0030] Figure 12 This is a cross-sectional view of a semiconductor device after the thin oxide layer has been removed and the gate dielectric material and work function metal have been conformally deposited, according to an embodiment of the present disclosure.

[0031] Figure 12A yes Figure 12 Top view.

[0032] Figure 13 This is a cross-sectional view of a semiconductor device after etching the gate dielectric material and work function metal according to an embodiment of the present disclosure.

[0033] Figure 13A yes Figure 13 Top view.

[0034] Figure 14 This is a cross-sectional view of a semiconductor device after being filled with a metal gate material and planarized on the metal gate material, according to an embodiment of the present disclosure.

[0035] Figure 14A yes Figure 14 Top view.

[0036] Figure 15 This is a cross-sectional view of a semiconductor device after the metal gate material has been partially recessed, according to an embodiment of the present disclosure.

[0037] Figure 15A yes Figure 15 Top view.

[0038] Figure 16 This is a cross-sectional view of a semiconductor device after a first interstage dielectric layer has been deposited on a metal gate material and a planarization process has been performed, according to an embodiment of the present disclosure.

[0039] Figure 16A yes Figure 16 Top view.

[0040] Figure 17 This is a cross-sectional view of a semiconductor device after the first interstage dielectric layer has been partially recessed, according to an embodiment of the present disclosure.

[0041] Figure 17A yes Figure 17 Top view.

[0042] Figure 18 This is a cross-sectional view of the semiconductor device 100 after the spacers have been removed, according to an embodiment of the present disclosure.

[0043] Figure 18A yes Figure 18 Top view.

[0044] Figure 19 This is a cross-sectional view of a semiconductor device after forming a resistive random access memory stack according to an embodiment of the present disclosure.

[0045] Figure 19A yes Figure 19 Top view.

[0046] Figure 20 This is a cross-sectional view of a semiconductor device 100 after gate lithography and etching, according to an embodiment of the present disclosure.

[0047] Figure 20A yes Figure 20 Top view.

[0048] Figure 21 This is a cross-sectional view of a semiconductor device after further etching of the first interstage dielectric layer according to an embodiment of the present disclosure.

[0049] Figure 21A yes Figure 21 Top view.

[0050] Figure 22 This is a cross-sectional view of a semiconductor device after the deposition of a second interstage dielectric layer, according to an embodiment of the present disclosure.

[0051] Figure 22A yes Figure 22 Top view.

[0052] Figure 23 This is a cross-sectional view of a semiconductor device after the formation of source / drain contacts, gate contacts, and ReRAM contacts, according to embodiments of the present disclosure.

[0053] Figure 23A yes Figure 23 Top view.

[0054] The accompanying drawings are not necessarily drawn to scale. They are schematic representations only and are not intended to describe specific parameters of the invention. The drawings are intended to illustrate typical embodiments of the invention only. In the drawings, the same reference numerals denote the same elements. Detailed Implementation

[0055] Detailed embodiments of the claimed structures and methods are disclosed herein; however, it should be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods, and they may be implemented in different forms. The invention can be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Details of well-known features and techniques may be omitted in the description to avoid unnecessarily obscuring the presented embodiments.

[0056] For the purposes described below, terms such as “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and their derivatives shall refer to the disclosed structures and methods as oriented as shown in the accompanying drawings. Terms such as “above,” “cover,” “top,” “on top,” “positioned on,” or “positioned on top of” mean that a first element, such as a first structure, is present on a second element, such as a second structure, wherein an intermediate element, such as an interface structure, may be present between the first and second elements. The term “direct contact” means that the first element, such as a first structure, and the second element, such as a second structure, are connected at the interface of the two elements without any intermediate conductive, insulating, or semiconductor layer.

[0057] It should be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the scope of the inventive concept, the first element discussed below may be referred to as the second element.

[0058] To avoid obscuring the presentation of embodiments of the present invention, some processing steps or operations known in the art may have been combined for presentation and illustrative purposes in the following detailed description, and may not have been described in detail in some cases. In other cases, some processing steps or operations known in the art may not be described at all. It should be understood that the following description focuses more on the distinguishing features or elements of the various embodiments of the present invention.

[0059] A typical ReRAM structure includes a top electrode, a bottom electrode, and an oxide layer between the two electrodes. In oxide ReRAM, electroformed conductive filaments are required. This process relies on preventing randomness in controlling the position of the conductive filaments in the oxide ReRAM. This results in higher voltages being generated as the ReRAM cells scale and the device becomes more variable.

[0060] Embodiments of the present invention generally relate to the field of magnetic storage devices, and more specifically to the integration of resistive random access memory (ReRAM) devices with vertical field-effect transistors (VFETs). The proposed embodiments provide a method and related structures for fabricating a single-transistor-two-resistor (1T2R) ReRAM structure that reduces the randomness of electroforming conductive filaments while improving device scalability. Specifically, the proposed embodiments provide a 1T2R non-volatile memory cell for a vertically stacked structure for a field-programmable gate array (FPGA), wherein a portion of the top source / drain region of the VFET is used as the bottom electrode of the ReRAM structure, and two oxide ReRAMs are integrated with a vertical field-effect transistor. One way to form a single-transistor-two-resistor ReRAM structure includes: forming a VFET device comprising a faceted epitaxial region having a protruding external portion; forming a ReRAM stack directly above the epitaxial region, the ReRAM stack comprising an oxide layer above an electrode layer and a metal filler above the electrode layer, the oxide layer being in direct contact with the protruding external portion of the faceted epitaxial region that serves as the bottom electrode of an adjacent ReRAM element. Reference is made below. Figures 1-23A The accompanying drawings describe in detail an embodiment that can form a transistor-two-resistor ReRAM structure.

[0061] Now for reference Figure 1 A cross-sectional view of a semiconductor device 100 during an intermediate step in a method for manufacturing a vertical field-effect transistor (VFET) according to an embodiment of the present disclosure is shown. In this embodiment, Figure 1A This is a top view of semiconductor device 100.

[0062] At this point in the manufacturing process, the semiconductor device 100 includes a dummy gate 120 and a dielectric capping layer 140 disposed on a semiconductor substrate 102 (hereinafter “substrate”). The substrate 102 includes, for example, a bulk semiconductor substrate. The substrate 102 includes one or more semiconductor materials. Non-limiting examples of suitable semiconductor materials for the substrate 102 may include silicon (Si), strained Si, silicon carbide (SiC), germanium (Ge), silicon-germanium (SiGe), silicon-germanium-carbon (SiGeC), Si alloys, Ge alloys, III-V materials (e.g., gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), or aluminum arsenide (AlAs)), II-VI materials (e.g., cadmium selenide (CdSe), cadmium sulfide (CdS), cadmium telluride (CdTe), zinc oxide (ZnO), zinc selenide (ZnSe), zinc sulfide (ZnS), or zinc telluride (ZnTe)) or any combination thereof. In an embodiment, the substrate 102 may include germanium.

[0063] A doped source 108 is disposed on a substrate 102 above an anti-doped layer 104. The doped source 108 and the anti-doped layer 104 are formed by incorporating a dopant into the substrate 102 or by epitaxial growth on the substrate 102. According to an embodiment, the doped source 108 is heavily doped with a dopant, which may be a p-type dopant (e.g., boron or gallium) or an n-type dopant (e.g., phosphorus or arsenic). The anti-doped layer 104 includes a dopant that is different from / opposite to the dopant in the doped source 108. For example, when the doped source 108 includes a p-type dopant, the anti-doped layer 104 includes an n-type dopant, and when the doped source 108 includes an n-type dopant, the anti-doped layer 104 includes a p-type dopant. The doped source 108 is heavily doped, comprising approximately 10... 19 atoms / cm 3 To about 10 22 atoms / cm 3 The dopant concentration varies between these ranges. The thickness of the anti-doped layer can range from about 5 nm to about 50 nm or from about 10 nm to about 20 nm. The thickness of the doped source 108 can range from about 50 nm to about 250 nm or from about 100 nm to about 200 nm.

[0064] A dummy gate 120 is disposed on a doped source 108 between a first spacer 116 and a second spacer 118. The first spacer 116 is deposited on the doped source 108, the dummy gate 120 is deposited on the first spacer 116, and the second spacer 118 is deposited on the dummy gate 120. The first spacer 116 and the second spacer 118 may comprise an insulating material, such as silicon dioxide, silicon nitride, SiOCN, or SiBCN. Other non-limiting examples of materials for the first spacer 116 and the second spacer 118 include dielectric oxides (e.g., silicon oxide), dielectric nitrides (e.g., silicon nitride), dielectric oxynitrides, or any combination thereof. The materials forming the first spacer 116 and the second spacer 118 are deposited using standard deposition processes, including, for example, chemical vapor deposition (CVD) or physical vapor deposition (PVD). The first spacer 116 and the second spacer 118 may each have a thickness varying between approximately 3 nm and approximately 15 nm, or between approximately 5 nm and approximately 10 nm.

[0065] The dummy gate 120 includes a sacrificial gate material, such as amorphous silicon (aSi) or polysilicon. The sacrificial gate material can be deposited using a deposition process, including but not limited to PVD, CVD, plasma-enhanced chemical vapor deposition (PECVD), inductively coupled plasma chemical vapor deposition (ICPCVD), or any combination thereof. The sacrificial gate material forming the dummy gate 120 has a thickness varying between approximately 8 nm and approximately 100 nm, or between approximately 10 nm and approximately 30 nm.

[0066] A dielectric capping layer 140 is deposited on a second spacer 118 above a dummy gate 120. Non-limiting examples of materials used for the dielectric capping layer 140 include silicon dioxide, tetraethyl orthosilicate (TEOS) oxide, high aspect ratio plasma (HARP) oxide, high temperature oxide (HTO), high density plasma (HDP) oxide, oxides formed by atomic layer deposition (ALD) processes (e.g., silicon oxide), or any combination thereof. The dielectric capping layer 140 has a thickness ranging from about 30 nm to about 200 nm or from about 50 nm to about 100 nm.

[0067] Now for reference Figure 2 The diagram shows a cross-sectional view of a semiconductor device 100 according to an embodiment of the present disclosure, illustrating a trench 204 formed through a dielectric capping layer 140, a second spacer 118, and a dummy gate 120 to expose a first spacer 116. In this embodiment, Figure 2A This is a top view of semiconductor device 100.

[0068] Trench 204 extends from the top surface of dielectric capping layer 140 to the top surface of first spacer 116, thereby exposing first spacer 116. Trench 204 is formed by performing an etching process that selectively (substantially does not remove) the material forming first spacer 116. The etching process can be, for example, reactive ion etching (RIE). As known to those skilled in the art, multiple etching processes can be performed to form trench 204. For example, a first etching process is performed to selectively remove a portion of dielectric capping layer 140 relative to the material of second spacer 118. A second etching process is then performed to selectively remove the portion of second spacer 118 located below the portion of trench 204 formed by the first etching process relative to the material of dummy gate 120. A third etching process is then performed to selectively remove a portion of dummy gate 120 relative to the material of first spacer 116, which is located below the portion of trench 204 formed by the second etching process. As shown, the resulting trench 204 extends downward through the top surface of dielectric capping layer 140 to the top surface of the exposed portion of first spacer 116. The width of trench 204 can vary from about 3 nm to about 20 nm or from about 5 nm to about 10 nm. The depth of trench 204 can vary from about 50 nm to about 300 nm or from about 100 nm to about 200 nm.

[0069] See now Figure 3 The image shows a cross-sectional view of a semiconductor device 100 after etching through a first spacer 116 to expose the doped source 108 and form a self-aligned junction, according to an embodiment of the present disclosure. In this embodiment, Figure 3AThis is a top view of semiconductor device 100.

[0070] The first spacer 116 can be etched using a process that selectively (without removing substantially) the doped source 108 material. The first spacer 116 can be etched, for example, by reactive ion etching. The exposed portion of the first spacer 116 is removed by the etching process to expose a portion of the underlying source contact layer. As will be described in detail below, this creates a self-aligned junction (not shown) because the source extension can be epitaxially grown from the doped source 108 to the top surface of the first spacer 116.

[0071] Now for reference Figure 4 This image shows a cross-sectional view of a semiconductor device 100 following the inner portion of the sidewall of the oxidized dummy gate 120, according to an embodiment of the present disclosure. In this embodiment, Figure 4A This is a top view of the semiconductor device 100. Oxidation can be performed by a plasma oxidation process or other oxidation processes that form a thin oxide layer 410. In some embodiments, a portion of the first spacer 116 or the doped source 108 may also be oxidized. In this embodiment, the following is performed... Figure 5-5A Prior to the epitaxial growth described herein, any oxides formed in these regions are removed.

[0072] Now for reference Figure 5 This image shows a cross-sectional view of a semiconductor device 100 after an epitaxial layer has been grown from a doped source 108 to form an epitaxial channel region 502 (hereinafter referred to as the "channel region"), according to an embodiment of the present disclosure. In this embodiment, Figure 5A This is a top view of semiconductor device 100. As known to those skilled in the art, the epitaxial growth of channel region 502 includes epitaxial semiconductor material, and the epitaxial growth and / or deposition processes are selective for formation on the semiconductor surface and do not deposit material on other surfaces such as thin oxide layer 410, first spacer 116, or second spacer 118. The epitaxial growth of channel region 502 extends over dielectric capping layer 140, as shown in the figure.

[0073] The trench region 502 can be grown using suitable epitaxial growth processes, including, for example, chemical vapor deposition (CVD) (liquid phase (LP) or reduced pressure chemical vapor deposition (RPCVD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), metal-organic chemical vapor deposition (MOCVD), or other suitable processes.

[0074] The source of the epitaxial channel material can be, for example, silicon, germanium, or a combination thereof. The gas source for depositing the epitaxial semiconductor material can include a silicon-containing gas source, a germanium-containing gas source, or a combination thereof. For example, an epitaxial silicon layer can be deposited from a silicon gas source selected from the group consisting of silane, disilane, propane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, and combinations thereof. An epitaxial germanium layer can be deposited from a germanium gas source selected from the group consisting of germanane, digerane, halogerane, dichlorogerane, trichlorogerane, tetrachlorogerane, and combinations thereof. Such combinations of gas sources can be used to form epitaxial silicon-germanium alloy layers. Carrier gases such as hydrogen, nitrogen, helium, and argon can be used.

[0075] Now for reference Figure 6 This diagram shows a cross-sectional view of a semiconductor device 100 after a planarization process, according to an embodiment of the present disclosure. In this embodiment, Figure 6A This is a top view of semiconductor device 100. The planarization process performed on semiconductor device 100 can be a chemical mechanical planarization (CMP) process. Planarization removes excess epitaxial growth above the dielectric capping layer 140.

[0076] See now Figure 7 The diagram shows a cross-sectional view of a semiconductor device 100 after a channel region 502 has been partially recessed, filled with a dielectric material to form a dielectric cap 708, and the dielectric material has been planarized, according to an embodiment of the present disclosure. In this embodiment, Figure 7A This is a top view of the semiconductor device 100. The channel region 502 is partially recessed to a level still within the dielectric capping layer 140 and above the second spacer 118. The channel region 502 is recessed using, for example, reactive ion etching or wet etching processes.

[0077] A recess (not shown) formed above the channel region 502 is filled with dielectric material to form a dielectric cap 708 above the channel region 502. The formation of the dielectric cap 708 allows the spacer 920 ( Figure 9 The deposition of the dielectric cap 708 and the subsequent self-alignment of the gate structure are described. The dielectric material forming the dielectric cap 708 can be a dielectric oxide (e.g., silicon oxide), a dielectric nitride (e.g., silicon nitride), a dielectric oxynitride, or any combination thereof. The dielectric material forming the dielectric cap 708 is deposited using a standard deposition process such as CVD or PVD. After deposition, excess dielectric material is planarized by, for example, CMP.

[0078] Now for reference Figure 8 This illustration shows a cross-sectional view of a semiconductor device 100 after the dielectric capping layer 140 has been removed and an epitaxial region 810 has been formed on the channel region 502 to form a source / drain region, according to an embodiment of the present disclosure. Figure 8AThis is a top view of semiconductor device 100.

[0079] Epitaxial region 810 is disposed between dielectric cap 708 and channel region 502. As known to those skilled in the art, a portion of channel region 502 above the second spacer 118 may be recessed along the sidewall prior to the formation of epitaxial region 810. Epitaxial region 810 forms the source / drain region of semiconductor device 100 (i.e., VFET device). Epitaxial growth of epitaxial region 810 can be performed as described above. Figure 5-5A As described in the text.

[0080] It should be noted that the rhombic facet effect observed in epitaxial region 810 is a result of differential semiconductor growth along different crystal planes. Faceted epitaxial growth eventually slows down to a very low growth rate and "terminates" at the set of crystal planes with the slowest growth rate (i.e., <111> The resulting semiconductor structure is oriented at a plane, and thus has a surface oriented in such a crystal plane having the slowest semiconductor growth rate. As shown in the figure, the epitaxial region 810 includes two (opposite) protruding regions or triangular-shaped portions (by...). <111> The geometry (defined by a planar boundary) extends horizontally beyond the channel region 502. As described below, this geometry can enhance hole / electron mobility toward the protruding region, which can be advantageous for ReRAM performance. Various processing parameters, including growth temperature, growth pressure, and process gas flow rate, can be easily adjusted to regulate the relative growth rate along different sets of crystal planes, thereby controlling the surface orientation of the resulting semiconductor structure.

[0081] Now for reference Figure 9 This image shows a cross-sectional view of a semiconductor device 100 after the deposition of spacers 920 on the epitaxial region 810, according to an embodiment of the present disclosure. In this embodiment, Figure 9A This is a top view of semiconductor device 100.

[0082] Spacer 920 protects the epitaxial region 810 during subsequent processing steps. Spacer 920 is also disposed on the sidewall of dielectric cap 708. Spacer 920 comprises an insulating material, such as a dielectric oxide (e.g., silicon oxide), a dielectric nitride (e.g., silicon nitride), a dielectric oxynitride, or any combination thereof. The spacer 920 material is deposited using a standard deposition process such as CVD or PVD. The spacer material can be etched using a dry etching process (e.g., RIE process) such that it covers the epitaxial region 810 and is removed from the surfaces of dielectric cap 708 and the second spacer 118. Spacer 920 has a width varying from about 5 nm to about 50 nm or from about 15 nm to about 30 nm.

[0083] Now for reference Figure 10This diagram shows a cross-sectional view of a semiconductor device 100 after removing a portion of the second spacer 118 and the dummy gate 120, according to an embodiment of the present disclosure. In this embodiment, Figure 10A This is a top view of semiconductor device 100. The second spacer 118 and the dummy gate 120 are recessed into a removal portion extending horizontally beyond spacer 920. An etching process selectively (which will substantially not remove) is performed on the first spacer 116. The etching process can be a dry etching process, such as a RIE process.

[0084] Now for reference Figure 11 This image shows a cross-sectional view of a semiconductor device 100 after removing the remaining portion of the dummy gate 120 below the spacer 920 to expose the thin oxide layer 410, according to an embodiment of the present disclosure. In this embodiment, Figure 11A This is a top view of semiconductor device 100. The remaining portion of the dummy gate 120 can be removed by a wet etching process, such as a process involving thermal ammonia etching.

[0085] See now Figure 12 The diagram shows a cross-sectional view of a semiconductor device 100 after the thin oxide layer 410 has been removed and the gate dielectric material 1214 and work function metal 1218 have been conformally deposited, according to an embodiment of the present disclosure. In this embodiment, Figure 12A This is a top view of semiconductor device 100. Gate dielectric material 1214 and work function metal 1218 form a portion of the gate stack that replaces the dummy gate 120. Gate dielectric material 1214 and work function metal 1218 are disposed on the remaining portion of the first spacer 116, channel region 502, spacer 920, and second spacer 118 below the epitaxial region 810.

[0086] The gate dielectric material 1214 may be a dielectric material having a dielectric constant greater than 3.9, 7.0, or 10.0. Non-limiting examples of suitable materials for the gate dielectric material 1214 include oxides, nitrides, oxynitrides, silicates (e.g., metal silicates), aluminates, titanates, nitrides, or any combination thereof. Examples of high-k materials (having a dielectric constant greater than 7.0) include, but are not limited to, metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. High-k materials may also include dopants such as lanthanum and aluminum. The gate dielectric material 1214 may be formed by suitable deposition processes, including, for example, CVD, PVD, PECVD, ALD, evaporation, chemical solution deposition, or other similar processes. The thickness of the gate dielectric material 1214 can vary depending on the deposition process and the composition and amount of the high-k dielectric material used.

[0087] The work function metal 1218 may be disposed above the gate dielectric material 1214. The type of work function metal 1218 depends on the type of transistor. Non-limiting examples of suitable work function metal 1218 include p-type work function metal materials and n-type work function metal materials. P-type work function materials include components such as ruthenium, palladium, molybdenum, cobalt, nickel, and conductive metal oxides or any combination thereof. N-type metal materials include compositions such as hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, and aluminum carbide), aluminides, or any combination thereof. The work function metal 1218 may be deposited by suitable deposition processes, such as CVD, PECVD, PVD, plating, thermal or electron beam evaporation, and sputtering.

[0088] See now Figure 13 This image shows a cross-sectional view of a semiconductor device 100 after etching the gate dielectric material 1214 and the work function metal 1218, according to an embodiment of the present disclosure. In this embodiment, Figure 13A This is a top view of semiconductor device 100. Gate dielectric material 1214 and work function metal 1218 are recessed into the horizontally extending removal portion beyond spacer 920. An etching process is performed on the first spacer 116 that is selective (and will not be substantially removed). The etching process can be, for example, anisotropic etching.

[0089] Now for reference Figure 14 This image shows a cross-sectional view of a semiconductor device 100 after being filled with a metal gate material 1420 and planarized on the metal gate material 1420, according to an embodiment of the present disclosure. In this embodiment, Figure 14A This is a top view of semiconductor device 100. The metal gate material 1420 is a conductive gate metal deposited on the gate dielectric material 1214 and the work function metal 1218 to form a gate stack. Non-limiting examples of suitable conductive metals include aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof. The conductive metal forming the metal gate material 1420 can be deposited by a suitable deposition process, such as CVD, PECVD, PVD, electroplating, thermal or electron beam evaporation and sputtering. A planarization process (e.g., CMP) is performed to polish the surface of the metal gate material 1420.

[0090] Now for reference Figure 15 This image shows a cross-sectional view of a semiconductor device 100 after the metal gate material 1420 has been partially recessed, according to an embodiment of the present disclosure. Figure 15A This is a top view of the semiconductor device 100. The metal gate material 1420 is partially recessed by an etching process such as reactive ion etching.

[0091] See now Figure 16 This image shows a cross-sectional view of a semiconductor device 100 after a first interlayer dielectric (ILD) layer 1610 has been deposited on a metal gate material 1420 and a planarization process has been performed, according to an embodiment of the present disclosure. In this embodiment, Figure 16A This is a top view of the semiconductor device 100. The first ILD layer 1610 may be formed of, for example, a low-k dielectric material (k < 4.0), including but not limited to silicon oxide, spin-coated glass, flowable oxide, high-density plasma oxide, borophosphosilicate glass (BPSG), or any combination thereof. The first ILD layer 1610 is deposited by a deposition process, including but not limited to CVD, PVD, PECVD, ALD, evaporation, chemical solution deposition, or similar processes.

[0092] See now Figure 17 This shows a cross-sectional view of a semiconductor device 100 after the first ILD layer 1610 has been partially recessed, according to an embodiment of the present disclosure. In this embodiment, Figure 17A This is a top view of semiconductor device 100. The first ILD layer 1610 is partially recessed by any suitable etching process (e.g., reactive ion etching). The recess of the first ILD layer 1610 exposes the spacer 920 in preparation for its removal.

[0093] See now Figure 18 This diagram shows a cross-sectional view of the semiconductor device 100 after the spacer 920 has been removed, according to an embodiment of the present disclosure. In this embodiment, Figure 18A This is a top view of semiconductor device 100. As shown, spacer 920 can be removed by any suitable etching process. Removal of spacer 920 exposes epitaxial region 810 and dielectric cap 708.

[0094] Now for reference Figure 19 This illustration shows a cross-sectional view of a semiconductor device 100 after forming a resistive random access memory (ReRAM) stack, according to an embodiment of the present disclosure. In this embodiment, Figure 19A This is a top view of the semiconductor device 100. In this embodiment, the simplified ReRAM stack includes an oxide layer 1910, an electrode layer 1912 above the oxide layer 1090, and a metal filler 1920 above the electrode layer 1912. The oxide layer 1910 is conformally deposited along the exposed top surface of the first ILD layer 1610 and the epitaxial region 810 (source / drain region) and the exposed sidewalls of the dielectric cap 708.

[0095] The oxide layer 1910 can be deposited conformally using known deposition techniques such as ALD. The oxide layer 1910 can be made of a metal oxide material or a high-k material. Non-limiting examples of suitable materials for the oxide layer 1910 may include titanium oxide, tantalum oxide, and hafnium oxide. The oxide layer 1910 serves as the dielectric layer of the ReRAM structure, separating the epitaxial region 810 from the electrode layer 1912.

[0096] Electrode layer 1912 is conformally deposited on top of oxide layer 1910. Electrode layer 1912 can be deposited using known deposition techniques such as ALD. Electrode layer 1912 can be made of materials such as titanium nitride and aluminum-doped titanium nitride. It should be noted that in this embodiment, electrode layer 1912 serves as the top electrode of the ReRAM structure, while epitaxial region 810 serves two functions. Specifically, epitaxial region 810 serves as the top source / drain region of the VFET device, while the doped source 108 serves as the bottom source / drain region of the VFET device. Furthermore, epitaxial region 810 also serves as the bottom electrode of the ReRAM structure.

[0097] Once the electrode layer 1912 is conformally deposited over the oxide layer 1910, a metal filler 1920 is deposited over the electrode layer 1912. After the metal filler 1920 is deposited, the semiconductor device 100 undergoes a CMP process to obtain the smooth and flat surface shown in the figure. The metal filler 1920 may be made of a suitable low-resistivity metal (e.g., tungsten or copper). The metal filler 1920 acts as an electrical conductor between the electrode layer 1912 and the contacts subsequently formed on the top surface of the metal filler 1920.

[0098] See now Figure 20 This diagram shows a cross-sectional view of a semiconductor device 100 after gate lithography and etching, according to an embodiment of the present disclosure. In this embodiment, Figure 20A This is a top view of semiconductor device 100.

[0099] A mask (not shown) may be disposed on the metal filler 1920 and subsequently patterned. It is understood that the gate photolithography and etching processes are performed simultaneously with the etching of the ReRAM stack (e.g., oxide layer 1910, electrode layer 1912, and metal filler 1920). As known to those skilled in the art, patterns are transferred into the metal filler 1920 and the metal gate material 1420, portions of the metal filler 1920 and the metal gate material 1420 are removed, and a portion of the first spacer 116 is exposed, as shown in the figures. In some embodiments, a combination of RIE processes may be performed to remove portions of the ReRAM stack, the first ILD layer 1610, and the metal gate material 1420.

[0100] It should be noted that during the photolithography and patterning of the metal gate material 1420 and the ReRAM stack, the ReRAM stack is further recessed to expose portions of the first ILD layer 1610 instead of portions of the metal gate material 1420, as shown in Figure 21A This can be observed in [the text]. For example, [the text abruptly ends here]. Figure 21 and 21A As shown, during the preparation of (gate) contact patterning, only the relative portions of the first ILD layer 1610 are exposed.

[0101] See now Figure 22 This diagram shows a cross-sectional view of a semiconductor device 100 after the formation of the second ILD layer 2210, according to an embodiment of the present disclosure. In this embodiment, Figure 22A This is a top view of the semiconductor device 100. Similar to the dielectric material forming the first ILD layer 1610, a dielectric material is deposited to fill the depressions in the semiconductor device 100. The deposited dielectric material forms a second ILD layer 2210, which comprises a similar material and is formed in a manner similar to the first ILD layer 1610.

[0102] Now for reference Figure 23 This diagram shows a cross-sectional view of a semiconductor device 100 after the formation of source / drain contacts 2310, gate contacts 2312, and ReRAM contacts 2314, according to an embodiment of the present disclosure. In this embodiment, Figure 22A This is a top view of semiconductor device 100. Source / drain contacts 2310 extend through the second ILD layer 2210 and the first spacer 116 to reach a doped source 108 and are formed within a trench (not shown). The process for forming the source / drain contacts is standard and well known in the art. Typically, the process involves filling the trench with a conductive material or a combination of conductive materials to form the source / drain contacts 2310. The conductive material filling the source / drain contacts 2310 includes conductive metals, such as aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof. The conductive material can be deposited by a suitable deposition process, such as CVD, PECVD, PVD, electroplating, thermal or electron beam evaporation, or sputtering. A planarization process (e.g., CMP) is performed to remove any conductive material from the surface of the second ILD layer 2210.

[0103] Gate contact 2312 ( Figure 23A(As shown) Extending from the surface of the second ILD layer 2210 through the first ILD layer 1610 to the metal gate material 1420. The process for forming the gate contact 2312 is standard and well known in the art. This process generally involves using a suitable etching process to form trenches (not shown) in the second ILD layer 2210 and the first ILD layer 1610 to the metal gate material 1420, and filling the trenches with a conductive material or a combination of conductive materials to form the gate contact 2312. The conductive material forming the gate contact 2312 may be a conductive metal, such as aluminum (Al), molybdenum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof, deposited by a suitable deposition process (e.g., CVD, PECVD, PVD, electroplating, thermal or electron beam evaporation or sputtering). A planarization process (e.g., CMP) is performed to remove any conductive material from the surface of the second ILD layer 2210.

[0104] ReRAM contact 2314 may subsequently be formed over and in direct contact with metal filler 1920. The ReRAM contact may be made of a conductive metal including, for example, aluminum (Al), platinum (Pt), gold (Au), tungsten (W), titanium (Ti), or any combination thereof.

[0105] Therefore, the final semiconductor device 100 includes a vertical field-effect transistor, wherein a ReRAM element or structure is located on each side of the epitaxial region 810 separated by the dielectric cap 708. As shown, the ReRAM structures located on opposite sides of the dielectric cap 708 and the epitaxial region 810 both include angled regions projecting outward toward a metal filler 1920 defined by a triangle formed by the epitaxial region 810, the oxide layer 1910, and the electrode layer 1912. As described above, this angled region is a result of faceted epitaxial growth of the epitaxial region 810. More specifically, the epitaxial region 810 includes a rhomboid faceting effect result of differential growth along different crystal planes, which causes the two opposing protruding regions of the epitaxial region 810 to be angled outward toward the metal filler 1920. <111> The ReRAM structure uses a planar boundary. The prominent angled regions enhance the electroforming of the current-conducting filaments. Therefore, the randomness of the electroforming of the current-conducting filaments is reduced in the proposed ReRAM structure. Furthermore, integrating the VFET with the ReRAM structure saves space and allows for the fabrication of more VFETs on the same coverage area.

[0106] Therefore, embodiments of this disclosure provide a semiconductor device and a method of manufacturing the same, comprising two ReRAM elements vertically integrated on opposite sides of a VFET device on top. Specifically, in the proposed embodiment, each memory cell in the final semiconductor device comprises two resistive memory elements and a selector (1T-2R) that allows for a reduced footprint. The bottom electrode of the resistive memory element is the top source / drain region of a vertical field-effect transistor. The proposed semiconductor device also includes a channel region made of a single-crystal semiconductor material that further enhances device performance.

[0107] Various embodiments of the invention have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements to technologies found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A method for forming a vertical field-effect transistor, comprising: Forming a channel region extending from the doping source on the substrate; A dielectric cap is formed above the channel area; A metal gate material is formed on and around the channel region between the first spacer and the second spacer; A first interstage dielectric layer is formed adjacent to the second spacer; A top source / drain region is formed, the top source / drain region including an epitaxial region located above the channel region, the epitaxial region including two opposing triangular protrusions extending outward from the channel region, wherein a dielectric cap is located above the top surface of the epitaxial region; An oxide layer is conformally deposited on the top surface of the first interstage dielectric layer, the top surface of the second spacer, the top surface of each protruding region of the epitaxial region, and the sidewall of the dielectric cap. A top electrode layer is conformally deposited on the oxide layer; and A metal filler is deposited over the top electrode layer to form a resistive random access memory element on each side of the epitaxial region, wherein each of the two opposing protruding regions of the epitaxial region of the top source / drain region serves as the bottom electrode of the resistive random access memory element on each side of the epitaxial region.

2. The method according to claim 1, wherein, The epitaxial region includes a rhomboid faceting effect resulting from differential growth along different crystal planes, which causes the two opposing protruding regions of the epitaxial region to be formed by... <111> Surface definition.

3. The method according to claim 1, further comprising: Resistive random access memory elements on each side of the epitaxial region are vertically integrated on opposite sides of the top portion of the vertical field-effect transistor to form a transistor-two-resistor (1T2R) resistive random access memory structure.

4. The method according to claim 1, further comprising: An anti-doped layer is formed between the substrate and the doping source, wherein the doping source includes a first dopant and the anti-doped layer includes a second dopant different from the first dopant.

5. The method of claim 1, further comprising: Simultaneously, the oxide layer, top electrode layer, metal filler, first interstage dielectric layer, and metal gate material are etched to expose the top portion of the first spacer located above the doped source; as well as The oxide layer, top electrode layer, and metal filler are etched to expose a portion of the first interstage dielectric layer, wherein a recess is formed above the first spacer and the first interstage dielectric layer.

6. The method of claim 5, further comprising: A second interstage dielectric layer is deposited above the first spacer, adjacent to the resistive random access memory element and the first interstage dielectric layer, to prepare for the formation of contacts.

7. The method of claim 1, further comprising: Forming source / drain contacts that contact the doped source; Forming gate contacts that contact the metal gate material; as well as Two resistive random access memory contacts are formed to contact the top portion of the metal filler.

8. A method for forming a vertical field-effect transistor, comprising: A doping source is formed on the substrate; A dummy gate is formed on the doped source, and the dummy gate is arranged between a first spacer disposed on the doped source and a second spacer disposed on the dummy gate; Trenches are formed in the dummy gate, the first spacer, and the second spacer to expose the doping source; An epitaxial layer is grown in the trench away from the doped source to form a channel region extending from the doped source and through the dummy gate. The top portion of the channel region is recessed to form a dielectric cap; An epitaxial region is epitaxially grown on a portion of the channel region to form a source / drain region above the dummy gate and below the dielectric cap, the epitaxial region including two opposing triangular protrusions extending outward from the channel region; The dummy gate is replaced by a gate stack, the gate stack comprising a metal gate material surrounding the channel region; Etch the metal gate material to expose the epitaxial region; A first-level interstage dielectric layer is formed to separate the epitaxial region from the metal gate material; as well as An oxide layer is conformally deposited on the top surface of the first interstage dielectric layer, the top surface of the second spacer, the top surface of each protruding region of the epitaxial region, and the sidewall of the dielectric cap; A top electrode layer is conformally deposited on the oxide layer; A metal filler is deposited over the top electrode layer to form a resistive random access memory element on each side of the epitaxial region, wherein each of the two protruding regions of the epitaxial region of the source / drain region serves as the bottom electrode of the resistive random access memory element on each side of the epitaxial region.

9. The method of claim 8, further comprising: Resistive random access memory elements on each side of the epitaxial region are vertically integrated on opposite sides of the top portion of the vertical field-effect transistor to form a transistor-two-resistor (1T2R) resistive random access memory structure.

10. The method according to claim 8, wherein, The epitaxial region includes a rhomboid faceting effect resulting from differential growth along different crystal planes, which causes the two opposing protruding regions of the epitaxial region to be formed by... <111> Surface definition.

11. The method of claim 8, further comprising: An anti-doped layer is formed between the substrate and the doping source, wherein the doping source includes a first dopant and the anti-doped layer includes a second dopant different from the first dopant.

12. The method of claim 8, further comprising: Simultaneously, the oxide layer, the top electrode layer, the first interstage dielectric layer, and the metal gate material are etched to expose the top portion of the first spacer located above the doped source; as well as The oxide layer and the top electrode layer are etched to expose a portion of the first interstage dielectric layer, wherein a recess is formed above the first spacer and the first interstage dielectric layer.

13. The method of claim 12, further comprising: A second interstage dielectric layer is deposited above the first spacer, adjacent to the resistive random access memory element and the first interstage dielectric layer, to prepare for the formation of contacts.

14. The method of claim 8, further comprising: Forming source / drain contacts that contact the doped source; Forming gate contacts that contact the metal gate material; as well as Two resistive random access memory contacts are formed to contact the top portion of the metal filler.

15. A vertical field-effect transistor, comprising: The channel region extends from the doping source on the substrate; A metal gate material is disposed between the first spacer and the second spacer on and around the channel region; The first interlayer dielectric layer is adjacent to the second spacer. The top source / drain region includes an epitaxial region located above the channel region, the epitaxial region including two opposing triangular protrusions extending outward from the channel region; as well as Dielectric cap, located above the epitaxial region; An oxide layer is conformally deposited on the top surface of the first interphase dielectric layer, the top surface of the second spacer, the top surface of each protruding region of the epitaxial region, and the sidewall of the dielectric cap; The top electrode layer is conformally deposited on the oxide layer; and A metal filler, deposited above the top electrode layer, is used to form resistive random access memory elements on each side of the epitaxial region, wherein each protruding region of the epitaxial region of the top source / drain region serves as the bottom electrode of the resistive random access memory element on each side of the epitaxial region.

16. The vertical field-effect transistor of claim 15, wherein, The epitaxial region includes a rhomboid faceting effect resulting from differential growth along different crystal planes, which causes the two opposing protruding regions of the epitaxial region to be formed by... <111> Plane definition.

17. The vertical field-effect transistor according to claim 15, wherein, The resistive random access memory elements on each side of the epitaxial region are vertically integrated on opposite sides of the top portion of the vertical field-effect transistor to form a resistive random access memory structure of a transistor-two-resistor (1T2R).

18. The vertical field-effect transistor of claim 15, further comprising: An anti-doping layer is provided between the substrate and the doping source, wherein the doping source includes a first dopant and the anti-doping layer includes a second dopant different from the first dopant.

19. The vertical field-effect transistor of claim 15, further comprising: A second interstage dielectric layer is used for contact formation, the second interstage dielectric layer being formed above the first spacer and adjacent to the resistive random access memory element and the first interstage dielectric layer.

20. The vertical field-effect transistor of claim 15, further comprising: Source / drain contacts that are in contact with the doped source; Gate contacts that contact the metal gate material; as well as Two resistive random access memory contacts that contact the top portion of the metal filler.

Images