Three-dimensional memory devices including discrete charge storage elements and methods of forming the same

Abstract

An alternating stack of insulating layers and spacer material layers can be formed over a substrate. The spacer material layers can be formed as electrically conductive layers, or can be subsequently replaced with electrically conductive layers. Memory openings can be formed through the alternating stack, and annular lateral recesses are formed at levels of the insulating layers. Metal portions are formed in the annular lateral recesses, and a semiconductor material layer is deposited over the metal portions. Metal-semiconductor alloy portions are formed by performing an anneal process, and are subsequently removed by performing a selective etch process. Remaining portions of the semiconductor material layer include a vertical stack of semiconductor material portions, which can optionally be partially or fully converted to silicon nitride material portions. The semiconductor material portions and / or the silicon nitride material portions can be used as discrete charge storage elements.

Description

[0001] Related applications

[0002] This application claims priority to the following patent applications: U.S. Non-Provisional Patent Application No. 16 / 849,600, filed April 15, 2020; and U.S. Non-Provisional Patent Application No. 16 / 849,664, filed April 15, 2020, the entire contents of which are incorporated herein by reference for all purposes. Technical Field

[0003] This disclosure relates in general to the field of semiconductor devices, and more specifically to a three-dimensional memory device including discrete charge storage elements and a method for manufacturing the same. Background Technology

[0004] Each cell has a three-dimensional vertical NAND string with one bit, as disclosed in the article “Novel UltraHigh Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell” by T. Endoh et al., IEDM Proc. (2001) 33-36. Summary of the Invention

[0005] According to one aspect of this disclosure, a method for forming a three-dimensional memory device is provided, the method comprising: forming an alternating stack of insulating layers and spacer material layers over a substrate, wherein the spacer material layers are formed as conductive layers or subsequently replaced by conductive layers; forming a memory opening through the alternating stack; forming an annular lateral recess at a layer level of the insulating layer by laterally recessing the sidewalls of the insulating layer relative to the sidewalls of the spacer material layers surrounding the memory opening; forming a vertical stack of discrete metal portions in the annular lateral recess; forming a semiconductor material layer on the vertical stack of the metal portions; forming a vertical stack of metal-semiconductor alloy portions by reacting the vertical stack of the metal portions with portions of the semiconductor material layer positioned at a layer level of the insulating layer; selectively removing the vertical stack of the metal-semiconductor alloy portions relative to unreacted portions of the semiconductor material layer, wherein the unreacted portions of the semiconductor material layer remain at a layer level of the spacer material layer and include the vertical stack of discrete semiconductor material portions; and forming a tunneling dielectric layer and a vertical semiconductor channel in the memory opening.

[0006] According to another aspect of this disclosure, a three-dimensional memory device is provided, comprising: an alternating stack of insulating and conductive layers positioned above a substrate; a memory opening extending vertically through the alternating stack, wherein the memory opening has lateral protrusions extending outward at each level of the insulating layer; and a memory opening filling structure positioned within the memory opening and comprising, from the outside to the inside: a barrier dielectric layer; a charge storage structure comprising a vertical stack of discrete semiconductor material portions and at least one silicon nitride material portion in contact with the vertical stack; a tunneling dielectric layer in contact with the charge storage structure; and a vertical semiconductor channel.

[0007] According to another aspect of this disclosure, a three-dimensional memory device is provided, comprising: an alternating stack of insulating and conductive layers located above a substrate; a memory opening extending vertically through the alternating stack, wherein the memory opening has a laterally projecting portion extending outward at a layer level of the insulating layer; and a memory opening filling structure positioned within the memory opening and comprising, from the outside to the inside, a barrier dielectric layer, a vertically stacked discrete charge storage material portions, a tunneling dielectric layer, and a vertical semiconductor channel, wherein each charge storage material portion includes a tubular portion positioned at a layer level of a corresponding electrical material layer, an upper flange portion extending laterally outward from an upper end of an outer sidewall of the tubular portion, and a lower flange portion extending laterally outward from a lower end of an outer sidewall of the tubular portion.

[0008] According to another aspect of this disclosure, a method for forming a three-dimensional memory device is provided, the method comprising: forming an alternating stack of an insulating layer and spacer material layers over a substrate, wherein the spacer material layers are formed as conductive layers or subsequently replaced by conductive layers; forming a memory opening through the alternating stack; forming an annular lateral recess at a layer level of the insulating layer by laterally recessing the sidewalls of the insulating layer relative to the sidewalls of the spacer material layers surrounding the memory opening; forming a vertical stack of discrete metal portions in the annular lateral recess; forming a semiconductor material layer on the vertical stack of the metal portions; removing the vertical stack of discrete metal portions and portions of the semiconductor material layer adjacent to the vertical stack of discrete metal portions, wherein the remaining portion of the semiconductor material layer comprises the vertical stack of semiconductor material portions, and each semiconductor material portion comprises a tubular portion, an upper flange portion extending laterally outward from an upper end of an outer sidewall of the tubular portion, and a lower flange portion extending laterally outward from a lower end of an outer sidewall of the tubular portion; and forming a tunneling dielectric layer and a vertical semiconductor channel in the memory opening.

[0009] According to another aspect of this disclosure, a three-dimensional memory device is provided, comprising: an alternating stack of insulating and conductive layers positioned above a substrate; a memory opening extending vertically through the alternating stack, wherein the memory opening has a lateral protrusion extending outward at a layer level of the insulating layer; and a memory opening filling structure positioned within the memory opening and comprising, from the outside to the inside, a barrier dielectric layer, a vertically stacked charge storage material portion, a tunneling dielectric layer and a vertical semiconductor channel, and a vertically stacked discrete annular insulating material portion positioned at a layer level of the insulating layer between the barrier dielectric layer and the tunneling dielectric layer. Attached Figure Description

[0010] Figure 1 This is a schematic vertical cross-sectional view of an exemplary structure after the formation of at least one peripheral device and semiconductor material layer according to an embodiment of the present disclosure.

[0011] Figure 2 This is a schematic vertical cross-sectional view of an exemplary structure following the formation of an alternating stack of insulating and sacrificial material layers according to an embodiment of this disclosure.

[0012] Figure 3 This is a schematic vertical cross-sectional view of an exemplary structure following the formation of a stepped platform and a backward stepped dielectric material portion, according to an embodiment of this disclosure.

[0013] Figure 4A This is a schematic vertical cross-sectional view of an exemplary structure after the formation of the memory opening and the support opening, according to an embodiment of the present disclosure.

[0014] Figure 4B yes Figure 4A A top view of an exemplary structure. Vertical plane A-A' is... Figure 4A The plane of the cross section.

[0015] Figures 5A to 5P This is a schematic vertical cross-sectional view of the sequence of memory openings within an exemplary structure during the formation of a first exemplary memory opening filling structure, according to an embodiment of the present disclosure.

[0016] Figure 5Q and Figure 5R This is a schematic vertical cross-sectional view of the sequence of memory openings during an alternative configuration of forming a first exemplary memory opening filling structure, according to an embodiment of the present disclosure.

[0017] Figures 6A to 6J This is a schematic vertical cross-sectional view of the sequence of memory openings within an exemplary structure during the formation of a second exemplary memory opening filling structure, according to an embodiment of the present disclosure.

[0018] Figure 6K and Figure 6L This is a schematic vertical cross-sectional view of the sequence of memory openings during an alternative configuration of forming a second exemplary memory opening filling structure, according to an embodiment of the present disclosure.

[0019] Figures 7A to 7N This is a schematic vertical cross-sectional view of the sequence of memory openings within an exemplary structure during the formation of a third exemplary memory opening filling structure, according to an embodiment of the present disclosure.

[0020] Figure 7O and Figure 7P This is a schematic vertical cross-sectional view of the sequence of memory openings during an alternative configuration of forming a third exemplary memory opening filling structure, according to an embodiment of the present disclosure.

[0021] Figures 8A to 8F This is a schematic vertical cross-sectional view of the sequence of memory openings within an exemplary structure during the formation of a fourth exemplary memory opening filling structure, according to an embodiment of the present disclosure.

[0022] Figure 8G and Figure 8H This is a schematic vertical cross-sectional view of the sequence of memory openings during an alternative configuration of forming a fourth exemplary memory opening filling structure, according to an embodiment of the present disclosure.

[0023] Figures 9A to 9F This is a schematic vertical cross-sectional view of the sequence of memory openings within an exemplary structure during the formation of a fifth exemplary memory opening filling structure, according to an embodiment of the present disclosure.

[0024] Figure 9G and Figure 9H This is a schematic vertical cross-sectional view of the sequence of memory openings during an alternative configuration of forming a fifth exemplary memory opening filling structure, according to an embodiment of the present disclosure.

[0025] Figures 10A to 10M This is a schematic vertical cross-sectional view of the sequence of memory openings within an exemplary structure during the formation of a sixth exemplary memory opening filling structure, according to an embodiment of the present disclosure.

[0026] Figure 10N and Figure 10O This is a schematic vertical cross-sectional view of the sequence of memory openings during an alternative configuration of forming a sixth exemplary memory opening filling structure, according to an embodiment of this disclosure.

[0027] Figures 11A to 11GThis is a schematic vertical cross-sectional view of the sequence of memory openings within an exemplary structure during the formation of a seventh exemplary memory opening filling structure, according to an embodiment of the present disclosure.

[0028] Figure 11H and Figure 11I This is a schematic vertical cross-sectional view of the sequence of memory openings during an alternative configuration of forming a seventh exemplary memory opening filling structure, according to an embodiment of this disclosure.

[0029] Figures 12A to 12G This is a schematic vertical cross-sectional view of the sequence of memory openings within an exemplary structure during the formation of an eighth exemplary memory opening filling structure, according to an embodiment of the present disclosure.

[0030] Figure 12H and Figure 12I This is a schematic vertical cross-sectional view of the sequence of memory openings during an alternative configuration of forming an eighth exemplary memory opening filling structure, according to an embodiment of the present disclosure.

[0031] Figure 13 This is a schematic vertical cross-sectional view of an exemplary structure after the formation of the memory stack structure and the support pillar structure according to an embodiment of the present disclosure.

[0032] Figure 14A This is a schematic vertical cross-sectional view of an exemplary structure after the formation of the back side groove, according to an embodiment of the present disclosure.

[0033] Figure 14B yes Figure 14A A partial perspective top view of an exemplary structure. Vertical plane A-A' is... Figure 14A A schematic vertical cross-sectional view of the plane.

[0034] Figure 15 This is a schematic vertical cross-sectional view of an exemplary structure after the formation of the back recess according to an embodiment of the present disclosure.

[0035] Figure 16A This is a schematic vertical cross-sectional view of an exemplary structure after a conductive layer has been formed in the back recess according to an embodiment of the present disclosure.

[0036] Figure 16B yes Figure 16A A partial perspective top view of an exemplary structure. Vertical plane A-A' is... Figure 16A A schematic vertical cross-sectional view of the plane.

[0037] Figure 17 This is a schematic vertical cross-sectional view of an exemplary structure after the formation of insulating spacers and back-side contact structures according to an embodiment of the present disclosure.

[0038] Figure 18A This is a schematic vertical cross-sectional view of an exemplary structure after the formation of the additional contact via structure according to an embodiment of the present disclosure.

[0039] Figure 18B yes Figure 18A A top view of an exemplary structure. Vertical plane A-A' is... Figure 18A A schematic vertical cross-sectional view of the plane.

[0040] Figure 19A In the case where, according to the embodiments of this disclosure, either the first exemplary memory opening filling structure or the second exemplary memory opening filling structure exists in the memory opening... Figure 18A and Figure 18B An enlarged view of the memory opening in an exemplary structure.

[0041] Figure 19B In the case where an alternative configuration of the first exemplary memory opening filling structure or the second exemplary memory opening filling structure exists in the memory opening according to the embodiments of this disclosure. Figure 18A and Figure 18B An enlarged view of the memory opening in an exemplary structure.

[0042] Figure 20A This refers to the implementation of the present disclosure in the case where a third exemplary memory opening filling structure exists in a memory opening. Figure 18A and Figure 18B An enlarged view of the memory opening in an exemplary structure.

[0043] Figure 20B This refers to the case where an alternative configuration of the third exemplary memory opening filling structure exists in the memory opening, according to an embodiment of this disclosure. Figure 18A and Figure 18B An enlarged view of the memory opening in an exemplary structure.

[0044] Figure 21A This is according to an embodiment of the present disclosure in the case where a fourth exemplary memory opening filling structure exists in a memory opening. Figure 18A and Figure 18B An enlarged view of the memory opening in an exemplary structure.

[0045] Figure 21B This refers to the case where an alternative configuration of the fourth exemplary memory opening filling structure exists in the memory opening, according to an embodiment of this disclosure. Figure 18A and Figure 18B An enlarged view of the memory opening in an exemplary structure.

[0046] Figure 22AThis refers to the implementation of the present disclosure in the case where the fifth exemplary memory opening filling structure exists in the memory opening. Figure 18A and Figure 18B An enlarged view of the memory opening in an exemplary structure.

[0047] Figure 22B This refers to the case where an alternative configuration of the fifth exemplary memory opening filling structure exists in the memory opening, according to an embodiment of this disclosure. Figure 18A and Figure 18B An enlarged view of the memory opening in an exemplary structure.

[0048] Figure 23A This is according to an embodiment of the present disclosure, in the case where the sixth exemplary memory opening filling structure exists in the memory opening. Figure 18A and Figure 18B An enlarged view of the memory opening in an exemplary structure.

[0049] Figure 23B This refers to the case where an alternative configuration of the sixth exemplary memory opening filling structure exists in the memory opening, according to an embodiment of this disclosure. Figure 18A and Figure 18B An enlarged view of the memory opening in an exemplary structure.

[0050] Figure 24A This refers to the implementation of the present disclosure in the case where the seventh exemplary memory opening filling structure exists in the memory opening. Figure 18A and Figure 18B An enlarged view of the memory opening in an exemplary structure.

[0051] Figure 24B This refers to the case where an alternative configuration of the seventh exemplary memory opening filling structure exists in the memory opening, according to an embodiment of this disclosure. Figure 18A and Figure 18B An enlarged view of the memory opening in an exemplary structure.

[0052] Figure 25A This refers to the implementation of the present disclosure in the case where the eighth exemplary memory opening filling structure exists in the memory opening. Figure 18A and Figure 18B An enlarged view of the memory opening in an exemplary structure.

[0053] Figure 25B This refers to the case where an alternative configuration of the eighth exemplary memory opening filling structure exists in the memory opening, according to an embodiment of this disclosure. Figure 18A and Figure 18B An enlarged view of the memory opening in an exemplary structure. Detailed Implementation

[0054] As discussed above, this disclosure relates to a three-dimensional memory device including discrete charge storage elements and a method for manufacturing the same, various aspects of which are described below. Embodiments of this disclosure can be used to form various structures, including multi-level memory structures, with non-limiting examples including semiconductor devices such as three-dimensional monolithic memory array devices comprising multiple NAND memory strings.

[0055] The accompanying drawings are not to scale. Where a single instance of an element is shown, multiple instances of the element may be repeated unless explicitly described or otherwise clearly indicated that no repetition of an element exists. Numbers such as “first,” “second,” and “third” are used only to identify similar elements and may be used differently throughout the specification and claims of this disclosure. The term “at least one” element refers to all possibilities, including the possibility of a single element and the possibility of multiple elements.

[0056] The same reference numerals denote the same or similar elements. Unless otherwise stated, elements with the same reference numerals are assumed to have the same composition and the same function. Unless otherwise specified, “contact” between elements means direct contact between elements that provide a shared edge or surface. If two or more elements are not in direct contact with each other, the two elements are “separated” from each other. As used herein, a first element positioned “on” a second element may be positioned on the outer side of the surface of the second element or on the inner side of the second element. As used herein, if there is physical contact between the surfaces of the first element and the second element, the first element is positioned “directly” on the second element. As used herein, if there is a conductive path made of at least one conductive material between the first element and the second element, the first element is “electrically connected” to the second element. As used herein, a “prototype” structure or a “process” structure refers to a transient structure in which the shape or composition of at least one of its components is subsequently modified.

[0057] As used herein, a “layer” refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have a extent smaller than that of the underlying or overlying structure. Additionally, a layer may be a region of uniform or non-uniform continuous structure whose thickness is less than that of the continuous structure. For example, a layer may be positioned between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, or may have one or more layers on, above, and / or below it.

[0058] As used herein, the first and second surfaces are “vertically coincident” if the second surface is above or below the first surface and if there is a vertical or substantially vertical plane that includes both the first and second surfaces. A substantially vertical plane is a plane that extends in a straight line along an angle less than 5 degrees from the vertical direction. The vertical or substantially vertical plane is straight along the vertical or substantially vertical direction and may or may not include curvature along a direction perpendicular to the vertical or substantially vertical direction.

[0059] A monolithic three-dimensional memory array is a memory array in which multiple memory stages are formed on a single substrate, such as a semiconductor wafer, without having an intermediate substrate. The term "monolithic" refers to the fact that the layers of each stage of the array are deposited directly on the layers of each lower stage of the array. In contrast, two-dimensional arrays can be formed separately and then packaged together to form a non-monolithic memory device. For example, as described in U.S. Patent 5,915,167 entitled "Three-dimensional Structure Memory," a non-monolithic stacked memory is constructed by forming memory stages on separate substrates and vertically stacking the memory stages. The substrate may be thinned or removed from the memory stages prior to bonding, but since the memory stages are initially formed on separate substrates, such a memory is not a true monolithic three-dimensional memory array. Various three-dimensional memory devices disclosed herein include monolithic three-dimensional NAND string memory devices and can be fabricated using the various embodiments described herein.

[0060] See Figure 1 This illustration shows an exemplary structure according to embodiments of the present disclosure, which can be used, for example, to fabricate a device structure containing a vertical NAND memory device. The exemplary structure includes a substrate (9, 10), which may be a semiconductor substrate. The substrate may include a lower substrate semiconductor layer 9 and optionally an upper substrate semiconductor layer 10. The lower substrate semiconductor layer 9 may be a semiconductor wafer or a layer of semiconductor material, and may include at least one elemental semiconductor material (e.g., a single-crystal silicon wafer or layer), at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. The substrate may have a main surface 7, which may be, for example, the topmost surface of the lower substrate semiconductor layer 9. The main surface 7 may be a semiconductor surface. In one embodiment, the main surface 7 may be a single-crystal semiconductor surface, such as a single-crystal semiconductor surface.

[0061] As used in this article, "semiconductor material" refers to a material with a conductivity of 1.0 × 10⁻⁶ m / s. -5 S / m to 1.0×10 5Materials with electrical conductivity in the range of S / m. As used herein, "semiconductor material" refers to a material having an electrical conductivity in the absence of electrical dopants in the presence of S / m. -5 Materials with electrical conductivity ranging from S / m to 1.0 S / m can be produced by appropriate doping with electrodopersive agents, exhibiting conductivity ranging from 1.0 S / m to 1.0 × 10⁻⁶. 5 Doped materials with electrical conductivity in the range of S / m. As used herein, “electrical dopant” refers to a p-type dopant that adds holes to the valence band of the band structure, or an n-type dopant that adds electrons to the conduction band of the band structure. As used herein, “conductive material” refers to a material with conductivity greater than 1.0 × 10⁻⁶ S / m. 5 Materials with a conductivity of S / m. As used herein, "insulating material" or "dielectric material" refers to a material with a conductivity of less than 1.0 × 10⁻⁶ S / m. -5 Materials with an electrical conductivity of S / m. As used herein, "heavily doped semiconductor material" refers to a material doped with an electrically conductive agent at a sufficiently high atomic concentration to become a conductive material (i.e., having a conductivity greater than 1.0 × 10⁻⁶) when formed into a crystalline material or converted into a crystalline material by an annealing process (e.g., starting from an initial amorphous state). 5 Semiconductor materials with a conductivity of S / m. "Doped semiconductor materials" can be heavily doped semiconductor materials, or can include those exhibiting a conductivity of 1.0 × 10⁻⁶ S / m. -5 S / m to 1.0×10 5 Semiconductor materials with electrical dopant concentrations (i.e., p-type and / or n-type dopant) in the range of S / m. "Intrinsic semiconductor material" refers to a semiconductor material undoped with electrical dopants. Therefore, a semiconductor material can be semiconductor or conductive, and can be intrinsic or doped. Doped semiconductor materials can be semiconductor or conductive, depending on the atomic concentration of the electrical dopant therein. As used herein, "metallic material" refers to a conductive material comprising at least one metallic element. All conductivity measurements were performed under standard conditions.

[0062] At least one semiconductor device 700 of the peripheral circuit may be formed on a portion of the lower substrate semiconductor layer 9. The at least one semiconductor device may include, for example, a field-effect transistor. For example, at least one shallow trench isolation structure 720 may be formed by etching a portion of the lower substrate semiconductor layer 9 and depositing a dielectric material therein. A gate dielectric layer, at least one gate conductor layer, and a gate cap dielectric layer may be formed over the lower substrate semiconductor layer 9 and may subsequently be patterned to form at least one gate structure (750, 752, 754, 758), each of which may include a gate dielectric 750, a gate electrode (752, 754), and a gate cap dielectric 758. The gate electrodes (752, 754) may include a stack of a first gate electrode portion 752 and a second gate electrode portion 754. At least one gate spacer 756 may be formed around the at least one gate structure (750, 752, 754, 758) by depositing and anisotropically etching a dielectric pad. An active region 730 can be formed in the upper portion of the lower substrate semiconductor layer 9, for example, by introducing an electrical dopant using the at least one gate structure (750, 752, 754, 758) as a mask structure. Additional masks may be used as needed. The active region 730 may include the source and drain regions of a field-effect transistor. Optionally, a first dielectric pad 761 and a second dielectric pad 762 may be formed. Each of the first and second dielectric pads (761, 762) may include a silicon oxide layer, a silicon nitride layer, and / or a dielectric metal oxide layer. As used herein, silicon oxide includes silicon dioxide and non-stoichiometric silicon oxide having more or less two oxygen atoms per silicon atom. Silicon dioxide is preferred. In an exemplary example, the first dielectric pad 761 may be a silicon oxide layer, and the second dielectric pad 762 may be a silicon nitride layer. At least one semiconductor device of the peripheral circuitry may include driver circuitry for a subsequently formed memory device, which may include at least one NAND device.

[0063] A dielectric material such as silicon oxide can be deposited over the at least one semiconductor device and can subsequently be planarized to form a planarized dielectric layer 770. In one embodiment, the planarized top surface of the planarized dielectric layer 770 may be coplanar with the top surface of the dielectric liner (761, 762). Subsequently, the planarized dielectric layer 770 and the dielectric liner (761, 762) can be removed from a certain area to physically expose the top surface of the underlying substrate semiconductor layer 9. As used herein, a surface is “physically exposed” if it is in physical contact with a vacuum or a gaseous material such as air.

[0064] An optional upper substrate semiconductor layer 10 (if present) may be formed on the top surface of the lower substrate semiconductor layer 9 by depositing a single-crystal semiconductor material (e.g., by selective epitaxy) before or after the formation of the at least one semiconductor device 700. The deposited semiconductor material may be the same as or different from the semiconductor material of the lower substrate semiconductor layer 9. The deposited semiconductor material may be any material that can be used for the lower substrate semiconductor layer 9, as described above. The single-crystal semiconductor material of the upper substrate semiconductor layer 10 may be epitaxially aligned with the single-crystal structure of the lower substrate semiconductor layer 9. The portion of the deposited semiconductor material positioned above the top surface of the planarized dielectric layer 770 may be removed, for example, by chemical mechanical planarization (CMP). In this case, the upper substrate semiconductor layer 10 may have a top surface coplanar with the top surface of the planarized dielectric layer 770.

[0065] At least one region of a semiconductor device 700 is referred to herein as peripheral device region 200. The region subsequently forming a memory array is referred to herein as memory array region 100. A stair region 300 for a stepped platform for the subsequent formation of a conductive layer may be provided between memory array region 100 and peripheral device region 200.

[0066] In one alternative embodiment, the peripheral device region 200 may be positioned below the memory array region 100 in a CMOS array configuration. In another alternative embodiment, the peripheral device region 200 may be positioned on a separate substrate, which is then bonded to the memory array region 100.

[0067] refer to Figure 2 An alternating stack of multiple insulating layers 32 and spacer material layers (which may be sacrificial material layers 42) is formed above the top surface of the substrate (9,10). As used herein, a “material layer” means a layer comprising material throughout its entirety. As used herein, an alternating stack of multiple first elements and second elements means a structure in which instances of first elements and instances of second elements alternate. Each instance of a first element that is not an end element of an alternating stack of elements is adjacent to two instances of a second element on both sides, and each instance of a second element that is not an end element of an alternating stack of elements is adjacent to two instances of a first element at both ends. The first elements may have the same thickness therebetween or may have different thicknesses. The second elements may have the same thickness therebetween or may have different thicknesses. The alternating stack of multiple insulating layers 32 and spacer material layers may begin with the bottommost insulating layer 32 or the bottommost spacer material layer and may end with the topmost insulating layer 32 or the topmost spacer material layer. In one embodiment, instances of first elements and instances of second elements may form cells that are periodically repeated within the alternating stack of elements.

[0068] Typically, the spacer material layer can be formed as a conductive layer, or can be subsequently replaced by a conductive layer. In the case where the spacer material layer is subsequently replaced by a conductive layer, the spacer material layer is formed as a sacrificial material layer 42. Alternatively, if the spacer material layer is formed as a conductive layer, it is not necessary to replace the spacer material layer with another material layer. Although this disclosure is described with the embodiment of the spacer material layer being formed as a sacrificial material layer 42 that is subsequently replaced by a conductive layer, embodiments in which the sacrificial material layer is formed as a conductive layer are explicitly contemplated herein. In such cases, the step of replacing the sacrificial material layer 42 with a conductive layer is omitted.

[0069] The alternating stacking of multiple insulating layers 32 and spacer material layers (such as sacrificial material layer 42) is referred to herein as an alternating stack (32, 42). Insulating materials that can be used for insulating layer 32 include, but are not limited to, silicon oxide (including doped or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicon glass (OSG), spin-coated dielectric materials, dielectric metal oxides (e.g., alumina, hafnium oxide, etc.) and their silicates, commonly referred to as high dielectric constant (high k) dielectric oxides, dielectric metal oxynitrides and their silicates, and organic insulating materials. In one embodiment, the insulating material of insulating layer 32 may be silicon oxide.

[0070] The spacer material of the sacrificial material layer 42 includes a sacrificial material that can be selectively removed from the insulating material of the insulating layer 32. As used herein, the removal of the first material is "selective" for the second material if the removal process removes the first material at a rate at least twice that of the removal rate of the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material relative to the second material.

[0071] The sacrificial material layer 42 may comprise an insulating material, a semiconductor material, or a conductive material. The spacer material of the sacrificial material layer 42 may subsequently be replaced with a conductive electrode, which may serve as a control gate electrode for, for example, a vertical NAND device. Non-limiting examples of spacer materials include silicon nitride, amorphous semiconductor materials (such as amorphous silicon), and polycrystalline semiconductor materials (such as polycrystalline silicon). In one embodiment, the sacrificial material layer 42 may be a spacer material layer comprising silicon nitride or a semiconductor material, the semiconductor material comprising at least one of silicon and germanium.

[0072] In one embodiment, the insulating layer 32 may comprise silicon oxide, and the sacrificial material layer may comprise a silicon nitride sacrificial material layer. The insulating material of the insulating layer 32 may be deposited, for example, by plasma-enhanced chemical vapor deposition (PECVD). For example, if silicon oxide is used for the insulating layer 32, tetraethyl orthosilicate (TEOS) may be used as a precursor material for the PECVD process. Spacer materials may be formed for the sacrificial material layer 42, for example, by thermal CVD or atomic layer deposition (ALD).

[0073] The sacrificial material layer 42 can be appropriately patterned so that conductive material portions subsequently formed by replacing the sacrificial material layer 42 can be used as conductive electrodes, such as the control gate electrode of a subsequently formed monolithic three-dimensional NAND string memory device. The sacrificial material layer 42 may include portions having a strip shape extending substantially parallel to the main surface 7 of the substrate.

[0074] The thickness of the insulating layer 32 and the sacrificial material layer 42 can range from 20 nm to 50 nm, but smaller and larger thicknesses can be used for each insulating layer 32 and each sacrificial material layer 42. The number of repetitions of the pairs of insulating layers 32 and sacrificial material layers (e.g., control gate electrodes or sacrificial material layers) 42 can range from 2 to 1,024, and is typically in the range of 8 to 256, but more repetitions are also possible. The top gate electrode and the bottom gate electrode in the stack can be used as select gate electrodes. In one embodiment, each sacrificial material layer 42 in the alternating stack (32, 42) can have a substantially uniform thickness within each respective sacrificial material layer 42.

[0075] Optionally, an insulating cap layer 70 may be formed over the alternating stacks (32, 42). The insulating cap layer 70 comprises a dielectric material different from the material of the sacrificial material layer 42. In one embodiment, the insulating cap layer 70 may comprise a dielectric material that can be used for the insulating layer 32 as described above. The insulating cap layer 70 may have a greater thickness than each insulating layer 32. The insulating cap layer 70 may be deposited, for example, by chemical vapor deposition. In one embodiment, the insulating cap layer 70 may be a silicon oxide layer.

[0076] refer to Figure 3 A stepped surface is formed at the peripheral region of the alternating stacks (32, 42), which is referred to herein as a plateau region. As used herein, a “stepped surface” means a set of surfaces comprising at least two horizontal surfaces and at least two vertical surfaces, such that each horizontal surface is adjacent to a first vertical surface extending upward from a first edge of the horizontal surface and to a second vertical surface extending downward from a second edge of the horizontal surface. A stepped cavity is formed within this volume by removing portions of the alternating stacks (32, 42) from the volume by forming the stepped surface. A “stepped cavity” means a cavity having a stepped surface.

[0077] A platform region is formed in a staircase region 300, located between a memory array region 100 and a peripheral device region 200, which contains at least one semiconductor device for peripheral circuitry. The stepped cavity may have various stepped surfaces such that the horizontal cross-sectional shape of the stepped cavity gradually varies according to the vertical distance from the top surface of the substrate (9, 10). In one embodiment, the stepped cavity can be formed by repeatedly performing a set of processing steps. This set of processing steps may include, for example, a first type of etching process and a second type of etching process, the first type of etching process vertically increasing the cavity depth by one or more levels, and the second type of etching process laterally extending the area to be vertically etched in subsequent first-type etching processes. As used herein, a “level” comprising alternating multiple structures is defined as the relative position of a pair of first and second material layers within the structure.

[0078] Each sacrificial material layer 42 within the alternating stacks (32,42), except for the topmost sacrificial material layer 42, extends laterally further than any overlying sacrificial material layer 42 within the alternating stacks (32,42) in the plateau region. The plateau region comprises stepped surfaces of the alternating stacks (32,42) that extend continuously from the bottom layer within the alternating stacks (32,42) to the top layer within the alternating stacks (32,42).

[0079] Each vertical step of the stepped surface may have one or more pairs of insulating layers 32 and sacrificial material layers 42. In one embodiment, each vertical step may have a single pair of insulating layers 32 and sacrificial material layers 42. In another embodiment, multiple “columns” of steps may be formed along a first horizontal direction hd1, such that each vertical step has multiple pairs of insulating layers 32 and sacrificial material layers 42, and the number of columns may be at least the number of such multiple pairs. Each column of the steps may be vertically offset from each other, such that each sacrificial material layer 42 has a physically exposed top surface in the corresponding column of the steps. In an exemplary example, two columns of steps are formed for each block of the memory stack structure to be subsequently formed, such that one column of steps provides a physically exposed top surface for odd-numbered sacrificial material layers 42 (e.g., counted from the bottom) and the other column of steps provides a physically exposed top surface for even-numbered sacrificial material layers (e.g., counted from the bottom). Configurations of three, four, or more vertically offset columns of stairs with corresponding sets of physically exposed sacrificial material layers 42 may also be adopted. Each sacrificial material layer 42 has a greater lateral extent in at least one direction than any covering sacrificial material layer 42, such that each physically exposed surface of any sacrificial material layer 42 has no overhangs. In one embodiment, the vertical steps within each column of stairs may be arranged along a first horizontal direction hd1, and the columns of stairs may be arranged along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. In one embodiment, the first horizontal direction hd1 may be perpendicular to the boundary between the memory array region 100 and the stair region 300.

[0080] A backward-stepped dielectric portion 65 (i.e., an insulating filler portion) can be formed in a stepped cavity by depositing a dielectric material therein. For example, a dielectric material such as silicon oxide can be deposited in the stepped cavity. Excess portions of the deposited dielectric material can be removed, for example, from above the top surface of the insulating cap layer 70 by chemical mechanical planarization (CMP). The remaining portion of the deposited dielectric material filling the stepped cavity constitutes the backward-stepped dielectric portion 65. As used herein, a "backward-stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that monotonically increases according to the vertical distance from the substrate to the top surface on which the element is situated. If silicon oxide is used for the backward-stepped dielectric portion 65, the silicon oxide of the backward-stepped dielectric portion 65 may be doped with or undoped with dopants such as B, P, and / or F.

[0081] Optionally, the drain electrode is selected from a hierarchical isolation structure 72 ( Figure 4AThe drain selection level isolation structure 72 can be formed by a subset of an insulating cap layer 70 and a sacrificial material layer 42 positioned at the drain selection level. The drain selection level isolation structure 72 can be formed, for example, by forming a drain selection level isolation trench and filling the trench with a dielectric material such as silicon oxide. Excess dielectric material can be removed from above the top surface of the insulating cap layer 70.

[0082] refer to Figure 4A and Figure 4B A photolithographic material stack (not shown), including at least a photoresist layer, can be formed over an insulating cap layer 70 and a backward stepped dielectric portion 65, and can be photolithographically patterned to form openings therein. The openings include a first set of openings formed over the memory array region 100 and a second set of openings formed over the staircase region 300. The pattern in the photolithographic material stack can be transferred through the insulating cap layer 70 or the backward stepped dielectric portion 65 by at least one anisotropic etching using the patterned photolithographic material stack as an etching mask, and through alternating stacks (32, 42). A portion of the alternating stacks (32, 42) below the openings in the patterned photolithographic material stack is etched to form a memory opening 49 and a support opening 19. As used herein, a “memory opening” refers to a structure in which memory elements, such as a memory stack structure, are subsequently formed. As used herein, a “support opening” refers to a structure in which a support structure (such as a support pillar structure) that mechanically supports other elements is subsequently formed. The memory opening 49 extends through the integral formation of the alternating stacks (32, 42) in the insulating cap layer 70 and the memory array region 100. The support opening 19 extends through the backward stepped dielectric material portion 65 and the portion of the alternating stacks (32, 42) located below the stepped surface in the stair region 300.

[0083] Memory opening 49 extends through the entirety of the alternating stack (32,42). Support opening 19 extends through a subset of layers within the alternating stack (32,42). The chemical properties of the anisotropic etching process used to etch the material through the alternating stack (32,42) can be alternated to optimize the etching of the material in the alternating stack (32,42). The anisotropic etching can be, for example, a series of reactive ion etchings. The sidewalls of memory opening 49 and support opening 19 can be substantially vertical or can be tapered. The patterned photolithographic material stack can then be removed, for example, by ashing.

[0084] The memory opening 49 and the support opening 19 can extend from the top surface of the alternating stack (32, 42) to at least a horizontal plane including the topmost surface of the upper substrate semiconductor layer 10. In one embodiment, after the top surface of the upper substrate semiconductor layer 10 is physically exposed at the bottom of each memory opening 49 and each support opening 19, over-etching of the upper substrate semiconductor layer 10 may optionally be performed. Over-etching may be performed before or after the removal of the photolithographic material stack. In other words, the recessed surface of the upper substrate semiconductor layer 10 may be vertically offset from the unrecessed top surface of the upper substrate semiconductor layer 10 by a recess depth. The recess depth may range, for example, from 1 nm to 50 nm, although smaller and larger depths may also be used. Over-etching is optional and may be omitted. If over-etching is not performed, the bottom surfaces of the memory opening 49 and the support opening 19 may be coplanar with the topmost surface of the upper substrate semiconductor layer 10.

[0085] Each of the memory opening 49 and the support opening 19 may include a sidewall (or multiple sidewalls) extending substantially perpendicular to the topmost surface of the substrate. A two-dimensional array of memory openings 49 may be formed in the memory array region 100. A two-dimensional array of support openings 19 may be formed in the staircase region 300. The lower substrate semiconductor layer 9 and the upper substrate semiconductor layer 10 together constitute the substrate (9, 10), which may be a semiconductor substrate. Alternatively, the upper substrate semiconductor layer 10 may be omitted, and the memory opening 49 and the support opening 19 may extend to the top surface of the lower substrate semiconductor layer 9.

[0086] Figures 5A to 5P The structural changes of the memory opening 49 during the formation of the first exemplary memory opening filling structure are shown. The same structural changes occur simultaneously in each of the other memory openings 49 and each support opening 19.

[0087] refer to Figure 5A , showed Figure 4A and Figure 4B The memory opening 49 in the exemplary device structure extends through the insulating cap layer 70, the alternating stacks (32, 42), and optionally into the upper portion of the upper substrate semiconductor layer 10. In this processing step, each support opening 19 may extend through the backward stepped dielectric material portion 65, a subset of the alternating stacks (32, 42), and optionally through the upper portion of the upper substrate semiconductor layer 10. The recess depth of the bottom surface of each memory opening relative to the top surface of the upper substrate semiconductor layer 10 may range from 0 nm to 30 nm, but a greater recess depth may also be used. Optionally, the sacrificial material layer 42 may be partially laterally recessed, for example, by isotropic etching to form a lateral recess (not shown).

[0088] refer to Figure 5BOptional pedestal channel portions (e.g., epitaxial pedestals) 11 may be selectively epitaxially formed at the bottom portions of each memory opening 49 and each support opening 19. Each pedestal channel portion 11 includes a single-crystal semiconductor material epitaxially aligned with the single-crystal semiconductor material of the upper substrate semiconductor layer 10. In one embodiment, the top surface of each pedestal channel portion 11 may be formed above a horizontal plane including the top surface of the bottommost sacrificial material layer 42. In this case, a source-select gate electrode can then be formed by replacing the bottommost sacrificial material layer 42 with a conductive material layer. The pedestal channel portion 11 may be a portion of a transistor channel extending between the source region subsequently formed in the substrate (9, 10) and the drain region subsequently formed in the upper portion of the memory opening 49. Memory cavity 49' ( Figure 5D The doping exists in the unfilled portion of the memory opening 49 above the base channel portion 11. In one embodiment, the base channel portion 11 may comprise monocrystalline silicon. In one embodiment, the base channel portion 11 may have doping of a first conductivity type, which is the same as the conductivity type of the upper substrate semiconductor layer 10 that the base channel portion contacts. If the upper substrate semiconductor layer 10 is not present, the base channel portion 11 may be formed directly on the lower substrate semiconductor layer 9, and the base channel portion may have doping of the first conductivity type.

[0089] refer to Figure 5C An annular lateral recess 149 may be formed at a level of the insulating layer 32 that is not masked by the base channel portion 11. Additional annular lateral recesses may be formed at a level of the insulating cap layer 70 surrounding the memory opening 49. The annular lateral recess 149 may be formed by laterally recessing the sidewalls of the insulating layer 32 relative to the sidewalls of the spacer material layer (such as the sacrificial material layer 42) surrounding the memory opening 49. An isotropic etching process that selectively etches the material of the insulating layer 32 relative to the material of the spacer material layer may be performed to laterally recess the physically exposed sidewalls of the insulating layer 32 relative to the sidewalls of the spacer material layer (such as the sacrificial material layer). In one embodiment, the physically exposed surface of the insulating cap layer 70 may be isotropically recessed while forming the annular lateral recess 149. In an exemplary example, insulating layer 32 comprises silicon oxide, spacer material layer 42 comprises silicon nitride or semiconductor material (such as polysilicon), and isotropic etching process includes wet etching process using dilute hydrofluoric acid.

[0090] The duration of the isotropic etching process can be selected so that the lateral recess distance of the annular lateral recess 149 can be in the range of 5 nm to 100 nm, such as 10 nm to 50 nm, but smaller and larger lateral recess distances are also possible. The lateral recess distance refers to the lateral distance between the recessed sidewall of the insulating layer 32 and the sidewall of an adjacent covering spacer material layer (such as an adjacent covering sacrificial material layer 42) or the sidewall of an adjacent lower spacer material layer. Each annular lateral recess 149 can have an annular cylindrical volume and is part of the memory opening 49. Therefore, the memory opening 49 comprises a vertical stack of annular lateral recesses 149 disposed at the layer level of the insulating layer 32.

[0091] refer to Figure 5D The barrier dielectric layer 52 can be conformally deposited on the physically exposed surfaces of the insulating layer 32 and spacer material layers (such as sacrificial material layer 42). The barrier dielectric layer 52 can be deposited on the sidewalls of the insulating layer 32, the cover of the insulating layer 32 or the annular horizontal surface below a corresponding annular lateral recess in the annular lateral recess 149, the sidewalls of the sacrificial material layer 42, the bottom surface of the memory opening 49 (if no pedestal channel portion is used, it can be the top surface of the pedestal channel portion 11 or the top surface of the upper substrate semiconductor layer 10), and the physically exposed surfaces of the insulating cap layer 70.

[0092] The barrier dielectric layer 52 may comprise a single dielectric material layer or a stack of multiple dielectric material layers. In one embodiment, the barrier dielectric layer may comprise a dielectric metal oxide layer, which is substantially composed of a dielectric metal oxide. As used herein, a dielectric metal oxide refers to a dielectric material comprising at least one metal element and at least oxygen. The dielectric metal oxide may be substantially composed of at least one metal element and oxygen, or may be substantially composed of at least one metal element, oxygen, and at least one non-metal element such as nitrogen. In one embodiment, the barrier dielectric layer 52 may comprise a dielectric metal oxide having a dielectric constant greater than 7.9 (i.e., having a dielectric constant greater than that of silicon nitride).

[0093] Non-limiting examples of dielectric metal oxides include aluminum oxide (Al₂O₃), hafnium oxide (HfO₂), lanthanum oxide (LaO₂), yttrium oxide (Y₂O₃), tantalum oxide (Ta₂O₅), their silicates, their nitrogen-doped compounds, their alloys, and stacks thereof. The dielectric metal oxide layer can be deposited, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), liquid-source atomized chemical deposition, or combinations thereof. The thickness of the dielectric metal oxide layer can range from 1 nm to 20 nm, but smaller and larger thicknesses are also possible. Subsequently, the dielectric metal oxide layer can be used as a dielectric material portion that blocks the leakage of stored charge to the control gate electrode. In one embodiment, the barrier dielectric layer 52 comprises aluminum oxide. In one embodiment, the barrier dielectric layer 52 may comprise multiple dielectric metal oxide layers with different material compositions.

[0094] Alternatively or otherwise, the barrier dielectric layer 52 may include a dielectric semiconductor compound, such as silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof. In one embodiment, the barrier dielectric layer 52 may include silicon oxide. In this case, the dielectric semiconductor compound of the barrier dielectric layer 52 may be formed by conformal deposition methods such as low-pressure chemical vapor deposition, atomic layer deposition, or combinations thereof. The thickness of the dielectric semiconductor compound may range from 1 nm to 20 nm, but smaller and larger thicknesses are also possible.

[0095] The barrier dielectric layer 52 has a laterally wavy vertical cross-sectional profile and includes a laterally protruding portion that extends laterally into an annular lateral recess 149. The laterally protruding portion of the barrier dielectric layer 52 can be positioned at the level of the insulating layer 32. The outer sidewall of the laterally protruding portion of the barrier dielectric layer 52 contacts the sidewall of the insulating layer 32, and the annular horizontal surface of the laterally protruding portion of the barrier dielectric layer 52 contacts the annular horizontal surface of a spacer material layer (such as sacrificial material layer 42).

[0096] refer to Figure 5EThe metal layer 66L can be deposited conformally on the inner sidewall of the barrier dielectric layer. The metal layer 66L can contain any metal capable of forming a metal-semiconductor alloy (such as a metal silicide). In one embodiment, the metal layer 66L can contain at least one transition metal capable of forming a metal silicide. For example, the metal layer 66L can contain tungsten, titanium, cobalt, molybdenum, platinum, nickel, and / or any other transition metal that forms a metal silicide upon reaction with silicon. The metal layer 66L can be deposited using conformal deposition methods such as chemical vapor deposition or atomic layer deposition. The thickness of the metal layer 66L can range from 2 nm to 20 nm, such as 4 nm to 10 nm, but smaller and larger thicknesses are also possible. The thickness of the metal layer 66L can be less than, equal to, or greater than half the thickness of each insulating layer 32. Therefore, after the metal layer 66L is formed, the annular lateral recess 149 may or may not have an unfilled volume.

[0097] refer to Figure 5F An optional patterned film 47 can be deposited anisotropically to cover the topmost lateral protrusions of the insulating cap layer 70 and the metal layer 66L above the topmost spacer material layer (such as the topmost sacrificial material layer 42). The patterned film 47 is deposited with high orientation and therefore has a significantly greater thickness above the insulating cap layer 70 than at the bottom horizontal surface of the memory opening 49 (which may be the top surface of the substrate channel portion 11). The patterned film 47 may be a film containing amorphous carbon as a primary component. For example, Applied Materials Inc. TM Advanced Patterning Film TM It can be used for patterned film 47. Alternatively, patterned film 47 can be omitted.

[0098] The portion of the metal layer 66L positioned outside the annular lateral recess 149 can be anisotropically etched by performing an anisotropic etching process. The anisotropic etching process can employ etching chemistry that selectively etches the material of the metal layer 66L relative to the patterned film 47 (if present), the material of the spacer material layer 42, the material of the barrier dielectric layer 52, and / or the material of the substrate channel portion 11. The anisotropic etching process can employ reactive ion etching. The remaining portion of the metal layer 66L comprises a vertical stack of discrete metal portions 66. The discrete metal portions 66 can be formed in a corresponding annular lateral recess 149 of the memory opening 49. Therefore, the vertical stack of discrete metal portions 66 can be formed in the annular lateral recess 149. The vertical stack of discrete metal portions 66 is formed directly on the portion of the inner sidewall of the barrier dielectric layer 52 positioned at the level of the insulating layer 32.

[0099] If the thickness of the metal layer 66L is less than half the thickness of each insulating layer 32, the discrete metal portion 66 may have a C-shaped (e.g., clamshell-shaped) vertical cross-sectional profile having a vertical portion connecting the two horizontal portions; or if the thickness of the metal layer 66L is greater than half the thickness of each insulating layer 32, the discrete metal portion may have a rectangular vertical cross-sectional profile. In one embodiment, the discrete metal portion 66 may comprise and / or consist substantially of tungsten, titanium, cobalt, molybdenum, platinum, nickel, and / or any other transition metal that forms a metal silicide upon reaction with silicon.

[0100] refer to Figure 5G The patterned film 47 (if present) can subsequently be removed, for example, by ashing. If the patterned film 47 is omitted, the discrete metal portion 66 at the layer level of the insulating cap layer 70 also does not exist, because it will be... Figure 5F The anisotropic etching process shown is removed during the process.

[0101] refer to Figure 5H The semiconductor material layer 54L can be conformally deposited on the physically exposed surfaces of the vertically stacked metal portions 66 and on the physically exposed surfaces of the barrier dielectric layer 52. The semiconductor material layer 54L comprises a semiconductor material that can form a metal-semiconductor alloy with the material of the metal portions 66. For example, the semiconductor material layer 54L may comprise silicon and / or germanium. In one embodiment, the semiconductor material layer 54L may comprise amorphous silicon, polycrystalline silicon, germanium, and / or a silicon-germanium alloy. The thickness of the semiconductor material layer 54L can be selected such that the entire vertical stack of discrete metal portions 66 can react with the semiconductor material of the semiconductor material layer 54L during a subsequent annealing process. In one embodiment, the semiconductor material layer 54L may have a thickness in the range of 2 nm to 20 nm, such as 4 nm to 10 nm, but smaller and larger thicknesses are also possible.

[0102] refer to Figure 5I An anisotropic etching process can be performed to remove the horizontal portion of the semiconductor material layer 54L and the metal layer 66L (if present) covering the insulating cap layer 70, as well as to remove the horizontal portion of the semiconductor material layer 54L positioned at the bottom of the memory opening 49 (such as the horizontal portion of the semiconductor material layer 54L positioned above the base channel portion 11).

[0103] refer to Figure 5JA thermal annealing process is performed at an elevated temperature, which induces the formation of a metal-semiconductor alloy between the material of the metal portion 66 and the material of the semiconductor layer 54L. The elevated temperature can range from 400 degrees Celsius to 1,000 degrees Celsius, but lower or higher temperatures can be used depending on the composition of the metal-semiconductor alloy. In this case, it is not necessary to form a low-resistivity phase metal-semiconductor alloy required for typical semiconductor applications. Even a high-resistivity intermediate phase metal-semiconductor alloy formed at a relatively low temperature is sufficient, as long as this metal-semiconductor alloy can be selectively removed relative to the unreacted portion of the semiconductor layer 54L in a subsequent selective etching process. Generally, the thickness of the metal layer 66L and the semiconductor layer 54L can be selected to ensure that the entire volume of the metal portion 66 reacts with the semiconductor layer 54L to form the metal-semiconductor alloy portion 67. The vertical stacking of the metal-semiconductor alloy portions 67 can be formed by reacting the vertical stacking of the metal portions 66 with portions of the semiconductor layer 54L positioned at the level of the insulating layer 32. Unreacted portions of semiconductor material layer 54L are retained at each level of sacrificial material layer 42 located on the top surface of base channel portion 11. This group of unreacted portions of semiconductor material layer 54L in memory opening 49 comprises a vertical stack of semiconductor material portions 54S.

[0104] refer to Figure 5K A selective isotropic etching process can be performed, which selectively etches the material of the metal-semiconductor alloy portion 67 relative to the material of the semiconductor material portion 54S. The vertical stack of the metal-semiconductor alloy portion 67 is selectively removed relative to the unreacted portion of the semiconductor material layer 54L (i.e., the vertical stack of the semiconductor material portions 54S). The vertical stack of the semiconductor material portions 54S remains at the level of spacer material layers (such as sacrificial material layer 42). In one embodiment, each semiconductor portion 54S may have a tubular shape. As used herein, a "tubular" element refers to an element having an inner cylindrical sidewall, an outer cylindrical sidewall, and a substantially uniform thickness between the inner and outer sidewalls. The vertical stack of the semiconductor material portions 54S can subsequently be used as a vertical stack of charge storage elements, which can be used as floating gates of NAND strings. After the vertical stack of the metal-semiconductor alloy portions 67 is removed, portions of the inner sidewalls of the barrier dielectric layer 52 are physically exposed.

[0105] refer to Figure 5LThe tunneling dielectric layer 56 can be deposited using conformal deposition processes such as chemical vapor deposition. The tunneling dielectric layer 56 comprises a dielectric material through which charge tunneling can be performed under appropriate electrical bias conditions. The tunneling dielectric layer 56 can be formed directly on a portion of the inner sidewall of the barrier dielectric layer 52 that is physically exposed and positioned at the level of the insulating layer 32. The tunneling dielectric layer 56 can be formed directly on a vertical stack of discrete cylindrical semiconductor material portions 54S. Charge tunneling can be performed by hot carrier injection or by Fowler-Nordheim tunneling-induced charge transfer, depending on the operating mode of the monolithic three-dimensional NAND string memory device to be formed. The tunneling dielectric layer 56 can comprise silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (such as aluminum oxide and hafnium oxide), dielectric metal oxynitrides, dielectric metal silicates, alloys thereof, and / or combinations thereof. In one embodiment, the tunneling dielectric layer 56 may comprise a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, typically referred to as an ONO stack. In one embodiment, the tunneling dielectric layer 56 may comprise a substantially carbon-free silicon oxide layer or a substantially carbon-free silicon oxynitride layer. The thickness of the tunneling dielectric layer 56 may range from 2 nm to 20 nm, but smaller and larger thicknesses are also possible.

[0106] An optional first semiconductor channel layer 601 can then be deposited on the tunneling dielectric layer 56 using a conformal deposition process. The first semiconductor channel layer 601 comprises a semiconductor material, such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the first semiconductor channel layer 601 comprises amorphous silicon or polycrystalline silicon. The first semiconductor channel layer 601 can be formed using a conformal deposition method such as low-pressure chemical vapor deposition (LPCVD). The thickness of the first semiconductor channel layer 601 can range from 2 nm to 10 nm, but smaller and larger thicknesses are also possible.

[0107] refer to Figure 5M An optional patterned film 77 can be deposited anisotropically to cover the top portion of the insulating cap layer 70 and the first semiconductor channel layer 601 above the topmost spacer material layer (such as the topmost sacrificial material layer 42). The patterned film 77 is deposited with high orientation and therefore has a significantly greater thickness above the insulating cap layer 70 than at the bottom horizontal surface of the memory opening 49 (which may be the top surface of the base channel portion 11). The patterned film 77 may be a film containing amorphous carbon as a primary component. For example, Applied Materials Inc. TM Advanced Patterning Film TMIt can be used for patterned film 77. Alternatively, patterned film 77 can be omitted.

[0108] An anisotropic etching process can be performed to remove the horizontal bottom portion of the first semiconductor channel layer 601, tunneling dielectric layer 56, and barrier dielectric layer 52 located above the base channel portion 11 at the bottom of each memory opening 49 (or, in the absence of a base channel portion, above the upper substrate semiconductor layer 10). The central portion of the top surface of the base channel portion 11 can be vertically recessed using an anisotropic etching process. In the absence of the base channel portion 11 in the memory opening 49, a portion of the horizontal surface of the upper substrate semiconductor layer 10 can be vertically recessed below the memory opening 49. If present, the patterned film 77 can subsequently be removed, for example, by ashing.

[0109] The surface of the base channel portion 11 (or the surface of the upper substrate semiconductor layer 10 without the base channel portion 11) is physically exposed beneath the opening through the first semiconductor channel layer 601, the tunneling dielectric layer 56, and the barrier dielectric layer 52. Optionally, the physically exposed semiconductor surface at the bottom of each memory cavity 49' may be vertically recessed such that the recessed semiconductor surface beneath the memory cavity 49' is vertically offset by a recess distance from the top surface of the base channel portion 11 (or the upper substrate semiconductor layer 10 without the base channel portion 11). The vertical stack of semiconductor material portions 54S serves as a discrete charge storage element with a floating gate. A set of barrier dielectric layers 52, the vertical stack of semiconductor material portions 54S, and the tunneling dielectric layer 56 in the memory opening 49 constitute the memory film 50. In one embodiment, the first semiconductor channel layer 601, the tunneling dielectric layer 56, and the barrier dielectric layer 52 may have vertically overlapping sidewalls.

[0110] refer to Figure 5NThe second semiconductor channel layer 602 may be deposited directly on the semiconductor surface of the base channel portion 11, or, if the base channel portion 11 is omitted, on the upper substrate semiconductor layer 10, and directly on the first semiconductor channel layer 601 (if present). The second semiconductor channel layer 602 comprises a semiconductor material, such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the second semiconductor channel layer 602 comprises amorphous silicon or polycrystalline silicon. The second semiconductor channel layer 602 may be formed by a conformal deposition method such as low-pressure chemical vapor deposition (LPCVD). The thickness of the second semiconductor channel layer 602 may range from 2 nm to 10 nm, but smaller and larger thicknesses are also possible. The second semiconductor channel layer 602 may partially fill the memory cavity 49' in each memory opening, or may completely fill the cavity in each memory opening.

[0111] The materials of the first semiconductor channel layer 601 and the second semiconductor channel layer 602 are collectively referred to as the semiconductor channel material. In other words, the semiconductor channel material is the collection of all semiconductor materials in the first semiconductor channel layer 601 and the second semiconductor channel layer 602. The combination of the barrier dielectric layer 52, the tunneling dielectric layer 56, the first semiconductor channel layer 601, and the second semiconductor channel layer 602 can completely fill the volume of the annular lateral recess provided at the layer level of the insulating layer 32.

[0112] refer to Figure 5O In cases where the memory cavity 49' in each memory opening is not completely filled by the second semiconductor channel layer 602, a dielectric core layer can be deposited in the memory cavity 49' to fill any remaining portion of the memory cavity 49' in each memory opening. The dielectric core layer comprises a dielectric material, such as silicon oxide or organosilicon glass. The dielectric core layer can be deposited by conformal deposition methods (such as low-pressure chemical vapor deposition (LPCVD)) or by self-planarization deposition processes (such as spin coating). For example, the horizontal portion of the dielectric core layer can be removed by recess etching above the top surface of the second semiconductor channel layer 602. Furthermore, the material of the dielectric core layer can be selectively vertically recessed relative to the semiconductor material of the second semiconductor channel layer 602 into each memory opening 49, recessed downward to a depth between a first horizontal plane including the top surface of the insulating cap layer 70 and a second horizontal plane including the bottom surface of the insulating cap layer 70. Each remaining portion of the dielectric core layer constitutes a dielectric core 62.

[0113] refer to Figure 5PA doped semiconductor material with a second conductivity type can be deposited in each recessed region above the dielectric core 62. The second conductivity type is the opposite of the first conductivity type. For example, if the first conductivity type is p-type, then the second conductivity type is n-type, and vice versa. The dopant concentration of the doped semiconductor material can range from 5.0 × 10¹⁸ / cm³ to 2.0 × 10²¹ / cm³, but smaller and larger dopant concentrations are also possible. The doped semiconductor material can be, for example, doped polysilicon.

[0114] Excess portions of the deposited semiconductor material can be removed from the top surface of the insulating cap layer 70, for example, by chemical mechanical planarization (CMP) or recess etching. Each remaining portion of the doped semiconductor material having a second conductivity type includes a doped semiconductor region having a pn junction at the interface with the vertical semiconductor channel 60. In one embodiment, the doped semiconductor region serves as the drain region 63 of the vertical NAND string. The horizontal portion of the second semiconductor channel layer 602 positioned above the top surface of the insulating cap layer 70 can be simultaneously removed by a planarization process. Each remaining portion of the second semiconductor channel layer 602 can be entirely positioned within the memory opening 49 or entirely positioned within the support opening 19.

[0115] Each remaining portion of the doped semiconductor material having a second conductivity type constitutes a drain region 63. Each adjacent pair of the optional first semiconductor channel layer 601 and the second semiconductor channel layer 602 can collectively form a vertical semiconductor channel 60 through which current can flow when a vertical NAND device including the vertical semiconductor channel 60 is turned on. A tunneling dielectric layer 56 is surrounded by a vertical stack of semiconductor material portions 54S and laterally surrounds a portion of the vertical semiconductor channel 60. Each adjacent group of the tunneling dielectric layer 56, the vertical stack of semiconductor material portions 54S, and the barrier dielectric layer 52 collectively constitutes a memory film 50 comprising a vertical stack of memory elements capable of storing corresponding data bits with a macroscopic retention time. As used herein, macroscopic retention time refers to a retention time suitable for operation of a memory device as a permanent memory device, such as a retention time exceeding 24 hours.

[0116] Each combination of the memory film 50 and the vertical semiconductor channel 60 within the memory opening 49 constitutes a memory stack structure 55. The memory stack structure 55 is a combination of the semiconductor channel 60, the tunneling dielectric layer 56, a plurality of vertically stacked memory elements including discrete (i.e., vertically separated) semiconductor material portions 54S, and the barrier dielectric layer 52. Each combination of the base channel portion 11 (if present), the memory stack structure 55, the dielectric core 62, and the drain region 63 within the memory opening 49 is referred to herein as a memory opening-filled structure 58. Each combination of the base channel portion 11 (if present), the memory film 50, the vertical semiconductor channel 60, the dielectric core 62, and the drain region 63 within each support opening 19 fills the corresponding support opening 19 and constitutes a support pillar structure.

[0117] Figure 5Q and Figure 5R An alternative configuration of the first exemplary memory aperture-filled structure is shown. (Reference) Figure 5Q By filling the annular transverse recess 149 with a dielectric filling material, it is possible to... Figure 5K An alternative configuration of the first exemplary memory aperture-filled structure is obtained from the illustrated structure. Specifically, after removing the vertical stack of the metal-semiconductor alloy portion 67, a dielectric filler material, such as undoped or doped silicate glass, can be deposited in the remaining volume of the annular lateral recess 149. In one embodiment, the dielectric filler material may have a higher etch rate than the material blocking the dielectric layer 52. For example, the dielectric filler material may comprise borosilicate glass, which provides an etch rate in dilute hydrofluoric acid that is 100 to 10,000 times higher than that of undoped silicate glass.

[0118] By etching back the dielectric filler material, a portion of the dielectric filler material can be removed from the outside of the annular lateral recess 149. An isotropic or anisotropic etching process can be used. The chemical properties of the etching process used to etch the dielectric filler material can be selective relative to the material of the semiconductor material portion 54S and the material of the barrier dielectric layer 52. The remaining portion of the annular lateral recess 149 filled with dielectric filler material comprises a vertical stack of annular insulating material portions 57. When an anisotropic etching process is used to pattern the annular insulating material portions 57, the inner sidewalls of the annular insulating material portions 57 can be vertically aligned with the inner sidewalls of the semiconductor material portions 54S.

[0119] refer to Figure 5R It can be executed Figures 5L to 5PThe processing steps are to provide an alternative configuration of the second exemplary memory opening-filling structure 58. In this case, the tunneling dielectric layer 56 can be formed directly on the vertical stack of the annular insulating material portions 57. The memory film 50 may include a barrier dielectric layer 52, a vertical stack of semiconductor material portions 54S, a vertical stack of annular insulating material portions 57 (which may contact the vertical stack of semiconductor material portions 54S), and a tunneling dielectric layer 56.

[0120] Figures 6A to 6J This is a schematic vertical cross-sectional view of the sequence of memory openings within an exemplary structure during the formation of a second exemplary memory opening filling structure according to an embodiment of the present disclosure. Instead of the first exemplary memory opening filling structure, a second exemplary memory opening filling structure may be formed within each memory opening 49.

[0121] refer to Figure 6A This illustrates a memory opening 49 during the formation of a second exemplary memory opening-fill structure, wherein the metal layer self-segregates into the annular lateral recess 149 during annealing. Specifically, by conformally depositing a metal layer 166L on the inner sidewall of the barrier dielectric layer 52, it is possible to... Figure 5D The structure shown is obtained Figure 6A The structure is shown. The metal layer 166L may contain any metal that can spontaneously separate into the annular transverse recess 149 during a subsequent annealing process. For example, the metal layer 166L may contain cobalt and / or consist substantially of cobalt.

[0122] refer to Figure 6B A thermal annealing process is performed at an elevated temperature to induce thermal migration of the metal layer 166L into the annular lateral recess 149. During the thermal annealing process, the metal layer 166L self-separates into the vertical stack of discrete metal portions 166 to reduce the total surface area. The elevated temperature of the thermal annealing process can range from 300 degrees Celsius to 1,000 degrees Celsius, but lower or higher temperatures can be used depending on the composition of the metal layer 166L. The thickness of the metal layer 166L deposited at the processing step of FIG. 6 can be selected such that the discrete metal portions 166 are confined within a corresponding annular lateral recess in the annular lateral recess 149 and do not directly contact each other (i.e., are vertically separated from each other). The inner sidewalls of the barrier dielectric layer 52 can be physically exposed at each level of the spacer material layer (such as the sacrificial material layer 42).

[0123] refer to Figure 6C It can be executed Figure 5HThe processing steps are to form a semiconductor material layer 54L. The semiconductor material layer 54L can be conformally deposited on the physically exposed surfaces of the barrier dielectric layer 52 and the discrete metal portion 166, each of which can have a ring configuration.

[0124] refer to Figure 6D A thermal annealing process is performed at elevated temperatures, which induces the formation of a metal-semiconductor alloy between the material of the metal portion 166 and the material of the semiconductor material layer 54L. The elevated temperatures can range from 400 degrees Celsius to 1,000 degrees Celsius, but lower or higher temperatures may be used depending on the composition of the metal-semiconductor alloy. Generally, the thicknesses of the metal layer 166L and the semiconductor material layer 54L can be selected to ensure that the entire volume of the metal portion 166 reacts with the semiconductor material layer 54L to form the metal-semiconductor alloy portion 167. The vertical stacking of the metal-semiconductor alloy portions 167 can be formed by reacting the vertical stacking of the metal portions 166 with portions of the semiconductor material layer 54L positioned at the levels of the insulating layer 32. Unreacted portions of the semiconductor material layer 54L are retained at each level of the sacrificial material layer 42 positioned on the top surface of the base channel portion 11. This group of unreacted portions of the semiconductor material layer 54L in the memory opening 49 includes the vertical stacking of the semiconductor material portions 54S.

[0125] refer to Figure 6E A selective isotropic etching process can be performed, which selectively etches the material of the metal-semiconductor alloy portion 167 relative to the material of the semiconductor material portion 54S. The vertical stack of the metal-semiconductor alloy portions 167 is selectively removed relative to the unreacted portion of the semiconductor material layer 54L (i.e., the vertical stack of the semiconductor material portions 54S). The vertical stack of the semiconductor material portions 54S remains at the level of spacer material layers (such as sacrificial material layer 42). In one embodiment, each semiconductor portion 54S may have a tubular shape. The vertical stack of the semiconductor material portions 54S can subsequently be used as a vertical stack of charge storage elements, which can be used as a floating gate of a NAND string. After the vertical stack of the metal-semiconductor alloy portions 167 is removed, portions of the inner sidewalls of the barrier dielectric layer 52 are physically exposed.

[0126] refer to Figure 6F It can be executed Figure 5L The processing steps are to form a tunneling dielectric layer 56 and a first semiconductor channel layer 601.

[0127] refer to Figure 6G It can be executed Figure 5MThe processing steps involve depositing an optional patterned film 77 and anisotropically etching the horizontal bottom portion of the first semiconductor channel layer 601, tunneling dielectric layer 56, and barrier dielectric layer 52 above the base channel portion 11 located at the bottom of each memory opening 49 (or above the upper substrate semiconductor layer 10 if the base channel portion is absent). The central portion of the top surface of the base channel portion 11 can be vertically recessed by an anisotropic etching process. If the base channel portion 11 is absent in the memory opening 49, a portion of the horizontal surface of the upper substrate semiconductor layer 10 can be vertically recessed below the memory opening 49. The patterned film 77 (if present) can then be removed, for example, by ashing.

[0128] refer to Figure 6H It can be executed Figure 5N The processing steps are to form the second semiconductor channel layer 602. The materials of the first semiconductor channel layer 601 and the second semiconductor channel layer 602 are collectively referred to as the semiconductor channel material. The combination of the barrier dielectric layer 52, the tunneling dielectric layer 56, the first semiconductor channel layer 601, and the second semiconductor channel layer 602 can completely fill the volume of the annular lateral recess provided at the layer level of the insulating layer 32.

[0129] refer to Figure 6I It can be executed Figure 5O The processing steps are to form a dielectric core 62 in each memory opening 49.

[0130] refer to Figure 6J It can be executed Figure 5P The processing steps involve forming a doped semiconductor portion, such as a drain region 63, at the upper portion of each memory opening 49. Each adjacent pair of the first semiconductor channel layer 601 (if present) and the second semiconductor channel layer 602 can collectively form a vertical semiconductor channel 60 through which current can flow when the vertical NAND device including the vertical semiconductor channel 60 is turned on. A tunneling dielectric layer 56 is surrounded by a vertical stack of semiconductor material portions 54S and laterally surrounds a portion of the vertical semiconductor channel 60. Each adjacent group of the tunneling dielectric layer 56, the vertical stack of semiconductor material portions 54S, and the barrier dielectric layer 52 collectively constitutes a memory film 50 comprising a vertical stack of memory elements capable of storing corresponding data bits with macroscopic retention times.

[0131] Each combination of the memory film 50 and the vertical semiconductor channel 60 within the memory opening 49 constitutes a memory stack structure 55. The memory stack structure 55 is a combination of the semiconductor channel 60, the tunneling dielectric layer 56, a plurality of vertically stacked memory elements including semiconductor material portions 54S, and the barrier dielectric layer 52. Each combination of the base channel portion 11 (if present), the memory stack structure 55, the dielectric core 62, and the drain region 63 within the memory opening 49 is referred to herein as a memory opening-filling structure 58. Each combination of the base channel portion 11 (if present), the memory film 50, the vertical semiconductor channel 60, the dielectric core 62, and the drain region 63 within each support opening 19 fills the corresponding support opening 19 and constitutes a support pillar structure.

[0132] Figure 6K and Figure 6L An alternative configuration of the second exemplary memory aperture-filled structure is shown. (Reference) Figure 6K By filling the annular transverse recess 149 with a dielectric filling material, it is possible to... Figure 6E An alternative configuration of the first exemplary memory aperture-filled structure is obtained from the illustrated structure. Specifically, after removing the vertical stack of the metal-semiconductor alloy portion 67, a dielectric filler material, such as undoped or doped silicate glass, can be deposited in the remaining volume of the annular lateral recess 149. In one embodiment, the dielectric filler material may have a higher etch rate than the material blocking the dielectric layer 52. For example, the dielectric filler material may comprise borosilicate glass, which provides an etch rate in dilute hydrofluoric acid that is 100 to 10,000 times higher than that of undoped silicate glass.

[0133] By etching back the dielectric filler material, a portion of the dielectric filler material can be removed from the outside of the annular lateral recess 149. An isotropic or anisotropic etching process can be used. The chemical properties of the etching process used to etch the dielectric filler material can be selective relative to the material of the semiconductor material portion 54S and the material of the barrier dielectric layer 52. The remaining portion of the annular lateral recess 149 filled with dielectric filler material comprises a vertical stack of annular insulating material portions 57. When an anisotropic etching process is used to pattern the annular insulating material portions 57, the inner sidewalls of the annular insulating material portions 57 can be vertically aligned with the inner sidewalls of the semiconductor material portions 54S.

[0134] refer to Figure 6L It can be executed Figures 6F to 6JThe processing steps are to provide an alternative configuration of the second exemplary memory opening-filling structure 58. In this case, the tunneling dielectric layer 56 can be formed directly on the vertical stack of the annular insulating material portions 57. The memory film 50 may include a barrier dielectric layer 52, a vertical stack of semiconductor material portions 54S, a vertical stack of annular insulating material portions 57 (which may contact the vertical stack of semiconductor material portions 54S), and a tunneling dielectric layer 56.

[0135] Figures 7A to 7N This is a schematic vertical cross-sectional view of the sequence of memory openings within an exemplary structure during the formation of a third exemplary memory opening-fill structure according to an embodiment of the present disclosure. The third exemplary memory opening-fill structure includes a hybrid charge storage structure comprising a continuous charge storage dielectric layer and a discrete floating gate. Instead of the first or second exemplary memory opening-fill structure described above, a third exemplary memory opening-fill structure may be formed within each memory opening 49.

[0136] refer to Figure 7A This shows the memory opening 49 after an annular lateral recess 149 is formed at the level of the insulating layer 32. Figure 7A The exemplary structure can be compared with Figure 5C The exemplary structure shown is the same.

[0137] refer to Figure 7B It can be executed Figure 5D The process involves forming a barrier dielectric layer 52. Subsequently, a continuous charge storage dielectric layer, such as a silicon nitride layer 53, can be deposited on the physically exposed surface of the barrier dielectric layer 52 using a conformal deposition process (such as chemical vapor deposition or atomic layer deposition). The silicon nitride layer 53 may have a thickness ranging from 1 nm to 8 nm, such as 2 nm to 6 nm, but smaller and larger thicknesses are also possible. The silicon nitride layer 53 extends vertically through the alternating stacked layers (32, 42) and contacts the outer sidewalls of each discrete tubular semiconductor material portion 54S within the vertical stack of the discrete tubular semiconductor material portions 54S. The silicon nitride layer 53 may contact the inner sidewalls of the barrier dielectric layer 52.

[0138] refer to Figure 7C It can be executed Figure 5E The processing steps are to directly form a metal layer 66L on the silicon nitride layer 53.

[0139] refer to Figure 7D It can be executed arbitrarily. Figure 5FThe processing steps involve anisotropically depositing an optional patterned film 47 and anisotropically etching the unmasked portions of the metal layer 66L. The remaining portion of the metal layer 66L after the anisotropic etching process comprises a vertically stacked discrete metal portions 66. Alternatively, if the metal layer 66L contains cobalt, it can be processed as described above regarding... Figure 6B The annealing process separates the metal parts into discrete metal portions 66.

[0140] refer to Figure 7E The patterned film 47 (if present) can then be removed, for example, by ashing.

[0141] refer to Figure 7F It can be executed Figure 5H The processing steps involve conformally depositing a semiconductor material layer 54L.

[0142] refer to Figure 7G It can be executed Figure 5I The processing steps involve anisotropically etching the horizontal portion of the semiconductor material layer 54L and the metal layer 66L covering the insulating cap layer 70, and removing the horizontal portion of the semiconductor material layer 54L positioned at the bottom of the memory opening 49 (such as the horizontal portion of the semiconductor material layer 54L positioned above the base channel portion 11).

[0143] refer to Figure 7H Executable Figure 5J The processing steps are as follows. Specifically, a thermal annealing process is performed at an elevated temperature, which induces the formation of a metal-semiconductor alloy between the material of the metal portion 66 and the material of the semiconductor material layer 54L. Generally, the thickness of the metal layer 66L and the thickness of the semiconductor material layer 54L can be selected to ensure that the entire volume of the metal portion 66 reacts with the semiconductor material layer 54L to form the metal-semiconductor alloy portion 67. The vertical stacking of the metal-semiconductor alloy portion 67 can be formed by reacting the vertical stacking of the metal portions 66 with portions of the semiconductor material layer 54L positioned at the level of the insulating layer 32. Unreacted portions of the semiconductor material layer 54L are retained at each level of the sacrificial material layer 42 positioned on the top surface of the base channel portion 11. This group of unreacted portions of the semiconductor material layer 54L in the memory opening 49 includes the vertical stacking of the semiconductor material portions 54S.

[0144] refer to Figure 7I Executable Figure 5KThe processing steps include: Specifically, a selective isotropic etching process can be performed, which selectively etches the material of the metal-semiconductor alloy portion 67 relative to the material of the semiconductor material portion 54S. The vertical stack of the metal-semiconductor alloy portion 67 is selectively removed relative to the unreacted portion of the semiconductor material layer 54L (i.e., the vertical stack of the semiconductor material portions 54S). The vertical stack of the semiconductor material portions 54S remains at the level of spacer material layers (such as sacrificial material layer 42). In one embodiment, each semiconductor portion 54S may have a tubular shape. The vertical stack of the semiconductor material portions 54S can subsequently be used as a vertical stack of charge storage elements, which can be used as a floating gate of a NAND string. After the vertical stack of the metal-semiconductor alloy portion 67 is removed, portions of the inner sidewalls of the silicon nitride layer 53 are physically exposed.

[0145] refer to Figure 7J It can be executed Figure 5L The processing steps are to form a tunneling dielectric layer 56 and an optional first semiconductor channel layer 601.

[0146] refer to Figure 7K It can be executed arbitrarily. Figure 5M The processing steps involve anisotropically depositing a patterned film 77 on the topmost portion of the insulating cap layer 70 and the first semiconductor channel layer 601 above the topmost spacer material layer (such as the topmost sacrificial material layer 42). Anisotropic etching processes can be performed to remove the horizontal bottom portions of the first semiconductor channel layer 601, tunneling dielectric layer 56, silicon nitride layer 53, and barrier dielectric layer 52 located above the pedestal channel portion 11 at the bottom of each memory opening 49 (or, in the absence of a pedestal channel portion, above the upper substrate semiconductor layer 10). The central portion of the top surface of the pedestal channel portion 11 can be vertically recessed by anisotropic etching processes. In the absence of a pedestal channel portion 11 in the memory opening 49, a portion of the horizontal surface of the upper substrate semiconductor layer 10 can be vertically recessed below the memory opening 49. The patterned film 77 can then be removed, for example, by ashing.

[0147] The surface of the base channel portion 11 (or the surface of the upper substrate semiconductor layer 10 without the base channel portion 11) is physically exposed beneath the opening through the first semiconductor channel layer 601, the tunneling dielectric layer 56, and the barrier dielectric layer 52. Optionally, the physically exposed semiconductor surface at the bottom of each memory cavity 49' may be vertically recessed such that the recessed semiconductor surface beneath the memory cavity 49' is vertically offset by a recess distance from the top surface of the base channel portion 11 (or the upper substrate semiconductor layer 10 without the base channel portion 11). The vertical stack of semiconductor material portions 54S serves as a discrete charge storage element with a floating gate. A continuous silicon nitride layer 53 serves as an additional charge storage material portion, extending continuously through each of the alternately stacked (32, 42) layers positioned above a horizontal plane including the top surface of the base channel portion 11. The vertically stacked combination of silicon nitride layer 53 and semiconductor material portion 54S constitutes a composite charge storage structure, which includes charge storage elements at each level of spacer material layer (such as sacrificial material layer 42). A set of barrier dielectric layers 52, silicon nitride layer 53, vertically stacked semiconductor material portion 54S, and tunneling dielectric layer 56 in memory opening 49 constitute memory film 50. In one embodiment, the first semiconductor channel layer 601, tunneling dielectric layer 56, silicon nitride layer 53, and barrier dielectric layer 52 may have vertically overlapping sidewalls.

[0148] refer to Figure 7L It can be executed Figure 5N The processing steps involve depositing the second semiconductor channel layer 602 directly onto the semiconductor surface of the base channel portion 11 or onto the upper substrate semiconductor layer 10 (if the base channel portion 11 is omitted), and directly onto the first semiconductor channel layer 601. The combination of the barrier dielectric layer 52, silicon nitride layer 53, tunneling dielectric layer 56, first semiconductor channel layer 601, and second semiconductor channel layer 602 can completely fill the volume of the annular lateral recess provided at the layer level of the insulating layer 32.

[0149] refer to Figure 7M The 5O processing steps can be performed in the dielectric core 62 in each memory opening 49.

[0150] refer to Figure 7N It can be executed Figure 5PThe processing steps form doped semiconductor material portions, such as drain region 63. Each adjacent pair of the first semiconductor channel layer 601 and the second semiconductor channel layer 602 can collectively form a vertical semiconductor channel 60 through which current can flow when a vertical NAND device including the vertical semiconductor channel 60 is turned on. Each combination of the memory film 50 within the memory opening 49 and the vertical semiconductor channel 60 constitutes a memory stack structure 55. The memory stack structure 55 is a combination of semiconductor channel 60, tunneling dielectric layer 56, a vertical stack including semiconductor material portions 54S, a plurality of memory elements positioned at the level of spacer material layer 42 of silicon nitride layer 53, and barrier dielectric layer 52. Each combination of base channel portion 11 (if present), memory stack structure 55, dielectric core 62, and drain region 63 within the memory opening 49 is referred to herein as memory opening fill structure 58. Each combination of the base channel portion 11 (if present), memory film 50, vertical semiconductor channel 60, dielectric core 62 and drain region 63 within each support opening 19 fills the corresponding support opening 19 and constitutes a support pillar structure.

[0151] In one embodiment, the tunneling dielectric layer 56 has a transversely wavy vertical cross-sectional profile and includes a transversely protruding portion positioned at the level of the insulating layer 32, which contacts the horizontal annular surface of the barrier dielectric layer 52 and the upper or lower portion of the vertically stacked adjacent discrete tubular semiconductor material portions 54S of the spacer material layer (such as the sacrificial material layer 42).

[0152] Figure 7O and Figure 7P An alternative configuration of the third exemplary memory aperture-filled structure is shown. (Reference) Figure 7O By filling the annular transverse recess 149 with a dielectric filling material, it is possible to... Figure 7I An alternative configuration of the third exemplary memory aperture-filled structure is obtained from the illustrated structure. Specifically, after removing the vertical stack of the metal-semiconductor alloy portion 67, a dielectric filler material, such as undoped or doped silicate glass, can be deposited in the remaining volume of the annular lateral recess 149. In one embodiment, the dielectric filler material may have a higher etch rate than the material blocking the dielectric layer 52. For example, the dielectric filler material may comprise borosilicate glass, which provides an etch rate in dilute hydrofluoric acid that is 100 to 10,000 times higher than that of undoped silicate glass.

[0153] By etching back the dielectric filler material, a portion of the dielectric filler material can be removed from the outside of the annular lateral recess 149. An isotropic or anisotropic etching process can be used. The chemical properties of the etching process used to etch the dielectric filler material can be selective relative to the material of the semiconductor material portion 54S and the material of the barrier dielectric layer 52. The remaining portion of the annular lateral recess 149 filled with dielectric filler material comprises a vertical stack of annular insulating material portions 57. When an anisotropic etching process is used to pattern the annular insulating material portions 57, the inner sidewalls of the annular insulating material portions 57 can be vertically aligned with the inner sidewalls of the semiconductor material portions 54S.

[0154] refer to Figure 7P It can be executed Figures 7J to 7N The processing steps are used to provide an alternative configuration of the third exemplary memory opening-filling structure 58. In this case, the tunneling dielectric layer 56 can be formed directly on the vertical stack of the annular insulating material portions 57. The memory film 50 may include a barrier dielectric layer 52, a silicon nitride layer 53, a vertical stack of semiconductor material portions 54S, a vertical stack of annular insulating material portions 57 (which may contact the vertical stack of semiconductor material portions 54S), and a tunneling dielectric layer 56.

[0155] Figure 7P The memory aperture filling structure comprises a vertical stack of annular insulating material portions 57 positioned at each level of an insulating layer 32 between a barrier dielectric layer 52 and a tunneling dielectric layer 56. The tunneling dielectric layer 56 includes a straight outer wall that contacts each annular insulating material portion 57 within the vertical stack of the annular insulating material portions 57 and contacts the vertical stack of discrete tubular semiconductor material portions 54S.

[0156] exist Figure 7N The third exemplary memory opening filling structure 58 and Figure 7P In an alternative implementation, all surfaces of the vertically stacked discrete tubular semiconductor material portions 54S are in contact with the surface of the silicon nitride pad 53 or the surface of the tunneling dielectric layer 56.

[0157] The combination of a vertically stacked silicon nitride layer 53 and discrete tubular semiconductor material portions 54S constitutes a charge storage structure (53, 54S). Generally, the charge storage structure (53, 54S) includes a vertically stacked discrete tubular semiconductor material portions 54S and at least one continuous silicon nitride material portion in contact with the vertically stacked discrete tubular semiconductor material portions 54S. In one embodiment, the at least one silicon nitride material portion includes a silicon nitride layer 53 that extends vertically through the alternating stacked layers (32, 42) and contacts the outer wall of each discrete tubular semiconductor material portion 54S within the vertically stacked discrete tubular semiconductor material portions 54S. Figure 7N In one embodiment shown, at the level of insulating layer 32, silicon nitride layer 53 contacts the inner sidewall of barrier dielectric layer 52 and the outer sidewall of tunneling dielectric layer 56. In one embodiment, all surfaces of the vertically stacked discrete tubular semiconductor material portions 54S may contact the surface of silicon nitride pad 53 or the surface of tunneling dielectric layer 56.

[0158] Figures 8A to 8F This is a schematic vertical cross-sectional view of the sequence of memory openings within an exemplary structure during the formation of a fourth exemplary memory opening filling structure including discrete charge storage dielectric portions, according to an embodiment of the present disclosure. Instead of the first, second, or third exemplary memory opening filling structures described above, a fourth exemplary memory opening filling structure may be formed within each memory opening 49.

[0159] refer to Figure 8A The structure for forming the fourth exemplary memory aperture-filling structure can be achieved by vertically stacking the semiconductor nitride material portions 54S from... Figure 5K Structure Figure 6E structure or Figure 7I The structure is obtained from the above. The vertical stacking of semiconductor material portions 54S is at least partially converted into a vertical stacking of silicon nitride material portions 54N, which may be a vertical stacking of discrete tubular silicon nitride material portions 54N. In one embodiment, if the vertical stacking of semiconductor material portions 54S is completely converted into a vertical stacking of silicon nitride material portions 54N, each silicon nitride material portion 54N may have a gradient silicon-to-nitrogen ratio, wherein the silicon-to-nitrogen ratio of the inner portion facing the memory opening 49 is lower than the silicon-to-nitrogen ratio of the outer portion facing the spacer material layer 42. In one embodiment, the thickness of each silicon nitride material portion 54N may be in the range of 3 nm to 30 nm, such as 5 nm to 15 nm, but smaller and larger thicknesses are also possible.

[0160] refer to Figure 8B It can be executed Figure 5L The processing steps are to form a barrier dielectric layer 52 and an optional first semiconductor channel layer 601.

[0161] refer to Figure 8C It can be executed Figure 5MThe processing steps include optionally depositing a patterned film 77, and anisotropically etching the horizontal bottom portion of the first semiconductor channel layer 601 (if present), the tunneling dielectric layer 56, and the barrier dielectric layer 52 located above the pedestal channel portion 11 at the bottom of each memory opening 49 (or above the upper substrate semiconductor layer 10 if the pedestal channel portion is absent). The central portion of the top surface of the pedestal channel portion 11 can be vertically recessed by an anisotropic etching process. In the absence of the pedestal channel portion 11 in the memory opening 49, a portion of the horizontal surface of the upper substrate semiconductor layer 10 can be vertically recessed below the memory opening 49. The patterned film 77 can then be removed, for example, by ashing.

[0162] refer to Figure 8D It can be executed Figure 5N The processing steps are to form the second semiconductor channel layer 602. The materials of the first semiconductor channel layer 601 and the second semiconductor channel layer 602 are collectively referred to as the semiconductor channel material. The combination of the barrier dielectric layer 52, the tunneling dielectric layer 56, the first semiconductor channel layer 601, and the second semiconductor channel layer 602 can completely fill the volume of the annular lateral recess provided at the layer level of the insulating layer 32.

[0163] refer to Figure 8E It can be executed Figure 5O The processing steps are to form a dielectric core 62 in each memory opening 49.

[0164] refer to Figure 8F It can be executed Figure 5P The processing steps involve forming a doped semiconductor portion, such as a drain region 63, at the upper portion of each memory opening 49. Each adjacent pair of the first semiconductor channel layer 601 and the second semiconductor channel layer 602 can collectively form a vertical semiconductor channel 60 through which current can flow when the vertical NAND device including the vertical semiconductor channel 60 is turned on. A tunneling dielectric layer 56 is surrounded by a vertical stack of silicon nitride material portions 54N and laterally surrounds a portion of the vertical semiconductor channel 60. Each adjacent group of the tunneling dielectric layer 56, the vertical stack of silicon nitride material portions 54N, and the barrier dielectric layer 52 collectively constitutes a memory film 50 comprising a vertical stack of memory elements capable of storing corresponding data bits with macroscopic retention times.

[0165] Each combination of the memory film 50 and the vertical semiconductor channel 60 within the memory opening 49 constitutes a memory stack structure 55. The memory stack structure 55 is a combination of the semiconductor channel 60, the tunneling dielectric layer 56, a plurality of vertically stacked memory elements including silicon nitride material portions 54N, and the barrier dielectric layer 52. Each combination of the base channel portion 11 (if present), the memory stack structure 55, the dielectric core 62, and the drain region 63 within the memory opening 49 is referred to herein as a memory opening-filled structure 58. Each combination of the base channel portion 11 (if present), the memory film 50, the vertical semiconductor channel 60, the dielectric core 62, and the drain region 63 within each support opening 19 fills the corresponding support opening 19 and constitutes a support pillar structure.

[0166] Figure 8G and Figure 8H An alternative configuration of the fourth exemplary memory aperture-filled structure is shown. (Reference) Figure 8G By filling the annular transverse recess 149 with a dielectric filling material, it is possible to... Figure 8A The illustrated structure provides an alternative configuration to the fourth exemplary memory aperture-filled structure. Specifically, after removing the vertical stack of the metal-semiconductor alloy portion 67, a dielectric filler material, such as undoped or doped silicate glass, can be deposited in the remaining volume of the annular lateral recess 149. In one embodiment, the dielectric filler material may have a higher etch rate than the material blocking the dielectric layer 52. For example, the dielectric filler material may comprise borosilicate glass, which provides an etch rate in dilute hydrofluoric acid that is 100 to 10,000 times higher than that of undoped silicate glass.

[0167] By etching back the dielectric filler material, a portion of the dielectric filler material can be removed from the outside of the annular lateral recess 149. An isotropic or anisotropic etching process can be used. The chemical properties of the etching process used to etch the dielectric filler material can be selective relative to the material of the silicon nitride material portion 54N and the material of the barrier dielectric layer 52. The remaining portion of the annular lateral recess 149 filled with dielectric filler material comprises a vertical stack of annular insulating material portions 57. When an anisotropic etching process is used to pattern the annular insulating material portions 57, the inner sidewalls of the annular insulating material portions 57 can vertically coincide with the inner sidewalls of the silicon nitride material portions 54N.

[0168] refer to Figure 8H It can be executed Figures 8B to 8FThe processing steps are to provide an alternative configuration to the first exemplary memory opening-filling structure 58. In this case, the tunneling dielectric layer 56 can be formed directly on the vertical stack of the annular insulating material portions 57. The memory film 50 may include a barrier dielectric layer 52, a vertical stack of silicon nitride material portions 54N, a vertical stack of annular insulating material portions 57 (which may contact the vertical stack of silicon nitride material portions 54N), and a tunneling dielectric layer 56.

[0169] Figures 9A to 9F This is a schematic vertical cross-sectional view of the sequence of memory openings within an exemplary structure during the formation of a fifth exemplary memory opening-fill structure according to an embodiment of the present disclosure. The fifth exemplary memory opening-fill structure includes a hybrid charge storage structure comprising discrete dielectric charge storage portions and a floating gate. Instead of the first, second, third, or fourth exemplary memory opening-fill structures described above, a fifth exemplary memory opening-fill structure may be formed within each memory opening 49.

[0170] refer to Figure 9A The structure for forming the fifth exemplary memory aperture-filling structure can be achieved by vertically stacking partially nitrided semiconductor material portions 54S. Figure 5K Structure Figure 6E structure or Figure 7I The structure is obtained from the vertical stacking of the composite charge storage structures (54S, 54N). The vertical stacking of the composite charge storage structures (54S, 54N) can be formed by converting the surface portion of the vertically stacked discrete tubular semiconductor material portions 54S into silicon nitride material portions 54N. Each composite charge storage structure in the composite charge storage structures (54S, 54N) includes a corresponding semiconductor material portion 54S and a corresponding silicon nitride material portion 54N, the corresponding semiconductor material portion 54S being the remainder of a corresponding discrete tubular semiconductor material portion 54S, the corresponding silicon nitride material portion 54N being formed by nitriding the surface portion of the corresponding discrete tubular semiconductor material portion 54S. In one embodiment, each silicon nitride material portion 54N includes an interface region located near the corresponding semiconductor material portion in the semiconductor material portion 54S, and the interface region has a gradually decreasing silicon-to-nitrogen ratio from portion 54N toward portion 54S. The thickness of each 54S semiconductor material portion can range from 1 nm to 30 nm, such as 2 nm to 20 nm, but smaller and larger thicknesses are also possible. The thickness of each 54N silicon nitride material portion can range from 1 nm to 30 nm, such as 2 nm to 20 nm, but smaller and larger thicknesses are also possible. The thickness of each composite charge storage structure (54S, 54N) can range from 3 nm to 30 nm, such as 5 nm to 15 nm, but smaller and larger thicknesses are also possible.

[0171] refer to Figure 9B It can be executed Figure 5L The processing steps are to form a barrier dielectric layer 52 and optionally a first semiconductor channel layer 601.

[0172] refer to Figure 9C It can be executed Figure 5M The processing steps include depositing a patterned film 77 and anisotropically etching the horizontal bottom portion of the first semiconductor channel layer 601, tunneling dielectric layer 56, and barrier dielectric layer 52 located above the base channel portion 11 at the bottom of each memory opening 49 (or, in the absence of a base channel portion, above the upper substrate semiconductor layer 10). The central portion of the top surface of the base channel portion 11 can be vertically recessed by an anisotropic etching process. In the absence of a base channel portion 11 in the memory opening 49, a portion of the horizontal surface of the upper substrate semiconductor layer 10 can be vertically recessed below the memory opening 49. The patterned film 77 can then be removed, for example, by ashing.

[0173] refer to Figure 9D It can be executed Figure 5N The processing steps are used to form the second semiconductor channel layer 602. The materials of the first semiconductor channel layer 601 and the second semiconductor channel layer 602 are collectively referred to as the semiconductor channel material. The combination of the barrier dielectric layer 52, the tunneling dielectric layer 56, the first semiconductor channel layer 601, and the second semiconductor channel layer 602 can completely fill the volume of the annular lateral recess provided at the layer level of the insulating layer 32.

[0174] refer to Figure 9E It can be executed Figure 5O The processing steps are to form a dielectric core 62 in each memory opening 49.

[0175] refer to Figure 9F It can be executed Figure 5P The processing steps involve forming a doped semiconductor portion, such as a drain region 63, at the upper portion of each memory opening 49. Each adjacent pair of the first semiconductor channel layer 601 and the second semiconductor channel layer 602 can collectively form a vertical semiconductor channel 60 through which current can flow when the vertical NAND device including the vertical semiconductor channel 60 is turned on. A tunneling dielectric layer 56 is surrounded by a vertical stack of composite charge storage structures (54S, 54N) and laterally surrounds a portion of the vertical semiconductor channel 60. Each adjacent group of the tunneling dielectric layer 56, the vertical stack of composite charge storage structures (54S, 54N), and the barrier dielectric layer 52 collectively constitutes a memory film 50 comprising a vertical stack of memory elements capable of storing corresponding data bits with macroscopic retention times.

[0176] Each combination of the memory film 50 and the vertical semiconductor channel 60 within the memory opening 49 constitutes a memory stack structure 55. The memory stack structure 55 is a combination of the semiconductor channel 60, the tunneling dielectric layer 56, a plurality of vertically stacked memory elements including a composite charge storage structure (54S, 54N), and the barrier dielectric layer 52. Each combination of the base channel portion 11 (if present), the memory stack structure 55, the dielectric core 62, and the drain region 63 within the memory opening 49 is referred to herein as a memory opening-filling structure 58. Each combination of the base channel portion 11 (if present), the memory film 50, the vertical semiconductor channel 60, the dielectric core 62, and the drain region 63 within each support opening 19 fills the corresponding support opening 19 and constitutes a support pillar structure.

[0177] Figure 9G and Figure 9H An alternative configuration of the fourth exemplary memory aperture-filled structure is shown. (Reference) Figure 9G By filling the annular transverse recess 149 with a dielectric filling material, it is possible to... Figure 9A The illustrated structure provides an alternative configuration to the fourth exemplary memory aperture-filled structure. Specifically, after removing the vertical stack of the metal-semiconductor alloy portion 67, a dielectric filler material, such as undoped or doped silicate glass, can be deposited in the remaining volume of the annular lateral recess 149. In one embodiment, the dielectric filler material may have a higher etch rate than the material blocking the dielectric layer 52. For example, the dielectric filler material may comprise borosilicate glass, which provides an etch rate in dilute hydrofluoric acid that is 100 to 10,000 times higher than that of undoped silicate glass.

[0178] By etching back the dielectric filler material, a portion of the dielectric filler material can be removed from the outside of the annular lateral recess 149. An isotropic or anisotropic etching process can be used. The chemical properties of the etching process used to etch the dielectric filler material can be selective relative to the materials of the composite charge storage structure (54S, 54N) and the barrier dielectric layer 52. The remaining portion of the annular lateral recess 149 filled with dielectric filler material comprises a vertical stack of annular insulating material portions 57. When an anisotropic etching process is used to pattern the annular insulating material portions 57, the inner sidewalls of the annular insulating material portions 57 can be vertically aligned with the inner sidewalls of the composite charge storage structure (54S, 54N).

[0179] refer to Figure 9H It can be executed Figures 9B to 9FThe processing steps are to provide an alternative configuration of the first exemplary memory opening-filling structure 58. In this case, the tunneling dielectric layer 56 can be formed directly on the vertical stack of the annular insulating material portions 57. The memory film 50 may include a barrier dielectric layer 52, a vertical stack of composite charge storage structures (54S, 54N), a vertical stack of annular insulating material portions 57 (which may contact the vertical stack of composite charge storage structures (54S, 54N), and a tunneling dielectric layer 56.

[0180] Figures 10A to 10M This is a schematic vertical cross-sectional view of the sequence of memory openings within an exemplary structure during the formation of a sixth exemplary memory opening-filling structure including a floating gate with a flanged portion, according to an embodiment of the present disclosure. Instead of the first, second, third, fourth, or fifth exemplary memory opening-filling structures described above, a sixth exemplary memory opening-filling structure may be formed within each memory opening 49.

[0181] refer to Figure 10A The diagram illustrates a structure for forming a sixth exemplary memory opening-filling structure, which can be used with... Figure 5D The structures are the same.

[0182] refer to Figure 10B The metal layer 66L can be deposited conformally on the inner sidewall of the barrier dielectric layer. The metal layer 66L can contain any metal capable of forming a metal-semiconductor alloy (such as a metal silicide). In one embodiment, the metal layer 66L can contain at least one transition metal capable of forming a metal silicide. For example, the metal layer 66L can contain tungsten, titanium, cobalt, molybdenum, platinum, nickel, and / or any other transition metal that forms a metal silicide upon reaction with silicon. The metal layer 66L can be deposited using conformal deposition methods such as chemical vapor deposition or atomic layer deposition. The thickness of the metal layer 66L can be greater than half the thickness of each insulating layer 32. In one embodiment, the metal layer fills the entire volume of each cavity in the annular lateral recess 149. In one embodiment, the thickness of the metal layer 66L above the sidewall of the spacer material layer (such as the sacrificial material layer 42) can range from 10 nm to 50 nm, such as 20 nm to 25 nm, but smaller and larger thicknesses are also possible.

[0183] refer to Figure 10COptionally, an anisotropic deposition process, such as physical vapor deposition (e.g., sputtering), can be performed to deposit additional portions of the metal on the horizontal surface of the metal layer 66L. The horizontal portions of the metal layer 66L can be thickened. Anisotropic metal deposition processes increase the thickness of the horizontal portions of the metal layer 66L, facilitating the removal of the horizontal portions of the semiconductor material layer in subsequent processing steps by forming metal-semiconductor alloy portions. Alternatively, this step can be omitted. Figure 10C The steps.

[0184] refer to Figure 10D An isotropic etching process, such as a wet etching process, can be performed to thin the metal layer 66L (i.e., to partially recess the metal layer 66L). Alternatively, if the metal layer 66L contains cobalt, the metal layer 66L can self-separate during the annealing process described above to form... Figure 10D The structure shown. The remaining portion of the metal layer 66L comprises a vertical stack of discrete metal portions 66.

[0185] Discrete metal portions 66 may be formed within a corresponding annular lateral recess 149 in the memory opening 49, but not completely fill the annular lateral recess. Each discrete metal portion 66 within the vertical stack of discrete metal portions 66 includes an inner sidewall that is laterally offset outward from a portion of the inner sidewall of the blocking dielectric layer 52 positioned at the level of a spacer material layer (such as sacrificial material layer 42).

[0186] Therefore, the vertical stack of discrete metal portions 66 can be formed in the annular transverse recess 149. The vertical stack of discrete metal portions 66 is formed directly on the portion of the inner wall of the barrier dielectric layer 52 that is positioned at the level of the insulating layer 32.

[0187] Discrete metal portions 66 may have a corresponding tubular shape. Each discrete metal portion 66 may have an inner sidewall laterally offset outward from the sidewall of the spacer material layer (such as sacrificial material layer 42). In one embodiment, discrete metal portions 66 may comprise and / or consist substantially of tungsten, titanium, cobalt, molybdenum, platinum, nickel, and / or any other transition metal that forms a metal silicide upon reaction with silicon. In one embodiment, discrete metal portions 66 may have a thickness in the range of 2 nm to 20 nm, such as 4 nm to 10 nm, but smaller and larger thicknesses are also possible. The horizontal remaining portion of metal layer 66L may exist above the top surface of the base channel portion 11 and above the top surface of the insulating cap layer 70.

[0188] refer to Figure 10EThe semiconductor material layer 54L can be conformally deposited on the physically exposed surfaces of the vertically stacked metal portions 66 and on the physically exposed surfaces of the barrier dielectric layer 52. The semiconductor material layer 54L comprises a semiconductor material that can form a metal-semiconductor alloy with the material of the metal portions 66. For example, the semiconductor material layer 54L may comprise silicon and / or germanium. In one embodiment, the semiconductor material layer 54L may comprise amorphous silicon, polycrystalline silicon, germanium, and / or a silicon-germanium alloy. The thickness of the semiconductor material layer 54L can be selected such that the entire vertical stack of discrete metal portions 66 can react with the semiconductor material of the semiconductor material layer 54L during a subsequent annealing process. In one embodiment, the semiconductor material layer 54L may have a thickness in the range of 2 nm to 20 nm, such as 4 nm to 10 nm, but smaller and larger thicknesses are also possible.

[0189] refer to Figure 10F A thermal annealing process is performed at an elevated temperature, which induces the formation of a metal-semiconductor alloy between the material of the metal portion 66 and the material of the semiconductor layer 54L. The elevated temperature can range from 400 degrees Celsius to 1,000 degrees Celsius, but lower or higher temperatures can be used depending on the composition of the metal-semiconductor alloy. In this case, it is not necessary to form a low-resistivity phase metal-semiconductor alloy required for typical semiconductor applications. Even a high-resistivity intermediate phase metal-semiconductor alloy formed at a relatively low temperature is sufficient, as long as this metal-semiconductor alloy can be selectively removed relative to the unreacted portion of the semiconductor layer 54L in a subsequent selective etching process. Generally, the thicknesses of the discrete metal portion 66 and the semiconductor layer 54L can be selected to ensure that the entire volume of the metal portion 66 reacts with the semiconductor layer 54L to form the metal-semiconductor alloy portion 67. The vertical stack of the metal-semiconductor alloy portions 67 can be formed by reacting the vertical stack of the metal portions 66 with portions of the semiconductor layer 54L positioned at the level of the insulating layer 32. Unreacted portions of semiconductor material layer 54L are retained at each level of sacrificial material layer 42 located on the top surface of base channel portion 11. This group of unreacted portions of semiconductor material layer 54L in memory opening 49 comprises a vertical stack of semiconductor material portions 54S.

[0190] In one embodiment, the metal-semiconductor alloy portion 67 may be laterally offset outward from a cylindrical vertical plane including the sidewall of a spacer material layer (such as sacrificial material layer 42) surrounding the memory opening 49, while portions of the semiconductor material portions 54S protrude into the recess 149. Specifically, each semiconductor material portion 54S includes a tubular portion 54T, an upper flange portion 54U extending laterally outward from the upper end of the outer sidewall of the tubular portion 54T into the recess 149, and a lower flange portion 54F extending laterally outward from the lower end of the outer sidewall of the tubular portion 54T into the recess 149.

[0191] refer to Figure 10G A selective isotropic etching process can be performed, which selectively etches the material of the metal-semiconductor alloy portion 67 relative to the material of the semiconductor material portion 54S. The vertical stack of the metal-semiconductor alloy portion 67 is selectively removed relative to the unreacted portion of the semiconductor material layer 54L (i.e., the vertical stack of the semiconductor material portions 54S). The vertical stack of the semiconductor material portions 54S is maintained at the level of the spacer material layer (such as the sacrificial material layer 42) and partially extends into the recess 149. In one embodiment, each semiconductor material portion 54S includes a tubular portion 54T, an upper flange portion 54U, and a lower flange portion 54F. The upper flange portion 54U and the lower flange portion 54F of each semiconductor material portion 54S are positioned in the recess 149 and provide an increased charge trapping volume in addition to the charge trapping volume provided by the tubular portion 54T. Therefore, the thickness of the spacer material layer (such as the sacrificial material layer 42) can be reduced relative to conventional NAND devices that do not include flange portions. The vertical stack of discrete semiconductor material portions 54S can subsequently be used as a vertical stack of charge storage elements, which can be used as a floating gate of a NAND string. After the vertical stack of the metal-semiconductor alloy portions 67 is removed, portions of the inner sidewalls of the barrier dielectric layer 52 are physically exposed. The vertical stack of discrete metal portions 66 and the portions of the semiconductor material layer 54L adjacent to the vertical stack of discrete metal portions 66 are removed in the form of the vertical stack of the metal-semiconductor alloy portions 67.

[0192] refer to Figure 10H As described in the preceding embodiments, conformal deposition processes such as chemical vapor deposition can be used to deposit the tunneling dielectric layer 56. The tunneling dielectric layer 56 can be formed directly on the portion of the inner sidewall of the barrier dielectric layer 52 that is physically exposed and positioned at the level of the insulating layer 32. The tunneling dielectric layer 56 can also be formed directly on the vertical stack of discrete cylindrical semiconductor material portions 54S. The combination of the barrier dielectric layer 52, the vertical stack of semiconductor material portions 54S, and the tunneling dielectric layer 56 constitutes the memory film 50.

[0193] refer to Figure 10I It can be executed Figure 5L The processing steps are to form an optional first semiconductor channel layer 601 on the tunneling dielectric layer 56.

[0194] refer to Figure 10J It can be executed arbitrarily. Figure 5M The processing steps involve depositing an optional patterned film 77. An anisotropic etching process can be performed to remove the horizontal bottom portion of the first semiconductor channel layer 601 (if present), the tunneling dielectric layer 56, and the barrier dielectric layer 52 located above the pedestal channel portion 11 at the bottom of each memory opening 49 (or above the upper substrate semiconductor layer 10 if the pedestal channel portion is absent). A set of barrier dielectric layers 52, vertically stacked semiconductor material portions 54S, and tunneling dielectric layers 56 in the memory openings 49 constitute the memory film 50. In one embodiment, the first semiconductor channel layer 601, tunneling dielectric layer 56, and barrier dielectric layer 52 may have vertically overlapping sidewalls. The patterned film 77 (if present) can then be removed, for example, by ashing.

[0195] refer to Figure 10K It can be executed Figure 5N The processing steps involve depositing a second semiconductor channel layer 602. The materials of the first semiconductor channel layer 601 and the second semiconductor channel layer 602 are collectively referred to as semiconductor channel material. In other words, semiconductor channel material is the collection of all semiconductor materials in the first semiconductor channel layer 601 and the second semiconductor channel layer 602. The combination of the flange portion of the semiconductor material portion 54S, the barrier dielectric layer 52, the tunneling dielectric layer 56, the first semiconductor channel layer 601, and the second semiconductor channel layer 602 can completely fill the volume of the annular lateral recess 149 provided at the layer level of the insulating layer 32.

[0196] refer to Figure 10L Executable Figure 5O The processing steps are to form dielectric core 62.

[0197] refer to Figure 10M It can be executed Figure 5PThe processing steps form doped semiconductor material portions, such as drain region 63. Each adjacent group of tunneling dielectric layer 56, vertically stacked semiconductor material portions 54S, and barrier dielectric layer 52 collectively constitutes memory film 50, which includes a vertically stacked memory element capable of storing corresponding data bits with macroscopic retention times. Each combination of memory film 50 and vertical semiconductor channel 60 within memory opening 49 constitutes memory stack structure 55. Memory stack structure 55 is a combination of semiconductor channel 60, tunneling dielectric layer 56, a plurality of vertically stacked memory elements including semiconductor material portions 54S, and barrier dielectric layer 52. Each combination of base channel portion 11 (if present), memory stack structure 55, dielectric core 62, and drain region 63 within memory opening 49 is referred to herein as memory opening filled structure 58. Each combination of the base channel portion 11 (if present), memory film 50, vertical semiconductor channel 60, dielectric core 62 and drain region 63 within each support opening 19 fills the corresponding support opening 19 and constitutes a support pillar structure.

[0198] Figure 10N and Figure 10O An alternative configuration of the first exemplary memory aperture-filled structure is shown. (Reference) Figure 10N By filling the annular transverse recess 149 with a dielectric filling material, it is possible to... Figure 10G An alternative configuration of the first exemplary memory aperture-filled structure is obtained from the illustrated structure. Specifically, after removing the vertical stack of the metal-semiconductor alloy portion 67, a dielectric filler material, such as undoped or doped silicate glass, can be deposited in the remaining volume of the annular lateral recess 149. In one embodiment, the dielectric filler material may have a higher etch rate than the material blocking the dielectric layer 52. For example, the dielectric filler material may comprise borosilicate glass, which provides an etch rate in dilute hydrofluoric acid that is 100 to 10,000 times higher than that of undoped silicate glass.

[0199] By etching back the dielectric filler material, a portion of the dielectric filler material can be removed from the outside of the annular lateral recess 149. An isotropic or anisotropic etching process can be used. The chemical properties of the etching process used to etch the dielectric filler material can be selective relative to the material of the semiconductor material portion 54S and the material of the barrier dielectric layer 52. The remaining portion of the annular lateral recess 149 filled with dielectric filler material comprises a vertical stack of annular insulating material portions 57. When an anisotropic etching process is used to pattern the annular insulating material portions 57, the inner sidewalls of the annular insulating material portions 57 can be vertically aligned with the inner sidewalls of the semiconductor material portions 54S.

[0200] refer to Figure 10O It can be executed Figures 10H to 10M The processing steps are to provide an alternative configuration of the second exemplary memory opening-filling structure 58. In this case, the tunneling dielectric layer 56 can be formed directly on the vertical stack of the annular insulating material portions 57. The memory film 50 may include a barrier dielectric layer 52, a vertical stack of semiconductor material portions 54S, a vertical stack of annular insulating material portions 57 (which may contact the vertical stack of semiconductor material portions 54S), and a tunneling dielectric layer 56.

[0201] Figures 11A to 11G This is a schematic vertical cross-sectional view of the sequence of memory openings within an exemplary structure during the formation of a seventh exemplary memory opening filling structure comprising a discrete dielectric charge storage element having a flange portion, according to an embodiment of the present disclosure. Instead of the first, second, third, fourth, fifth, or sixth exemplary memory opening filling structures described above, a seventh exemplary memory opening filling structure may be formed within each memory opening 49.

[0202] refer to Figure 11A The structure used to form the seventh exemplary memory aperture-filling structure can be formed by vertically stacking the semiconductor nitride material portions 54S from Figure 10G The structure is obtained from this. The vertical stacking of semiconductor material portions 54S is completely converted into a vertical stacking of silicon nitride material portions 54N. Each silicon nitride material portion 54N includes a tubular portion 54T, an upper flange portion 54U extending laterally outward from the upper end of the outer wall of the tubular portion 54T into the recess 149, and a lower flange portion 54F extending laterally outward from the lower end of the outer wall of the tubular portion 54T into the recess 149. In one embodiment, each silicon nitride material portion 54N has a gradient silicon-to-nitrogen ratio, as described above regarding Figure 8A In one embodiment, the thickness of the tubular portion 54T of each silicon nitride material portion 54N can be in the range of 3 nm to 30 nm, such as 5 nm to 15 nm, but smaller and larger thicknesses are also possible. In one embodiment, the tubular portion 54T, the upper flange portion 54U, and the lower flange portion 54F can have substantially the same thickness.

[0203] The vertical stack of silicon nitride material portions 54N is positioned at the level of spacer material layers (such as sacrificial material layer 42). In one embodiment, each silicon nitride material portion 54N includes a tubular portion 54T, an upper flange portion 54U, and a lower flange portion 54F. The upper flange portion 54U and lower flange portion 54F of each silicon nitride material portion 54N provide an increased charge trapping volume in addition to the charge trapping volume provided by the tubular portion 54T. Therefore, the thickness of the spacer material layer (such as sacrificial material layer 42) can be reduced relative to conventional NAND devices that do not include flange portions. The vertical stack of discrete silicon nitride material portions 54N can then be used as a vertical stack of charge storage elements, which can be used as floating gates of NAND strings. After the vertical stack of metal-semiconductor alloy portions 67 is removed, portions of the inner sidewalls of the barrier dielectric layer 52 are physically exposed.

[0204] refer to Figure 11B It can be executed Figure 10H The processing steps are to form a tunneling dielectric layer 56.

[0205] refer to Figure 11C It can be executed Figure 10I The processing steps are used to form the first semiconductor channel layer 601.

[0206] refer to Figure 11D It can be executed arbitrarily. Figure 10J The processing steps involve depositing an optional patterned film 77, and anisotropically etching the horizontal bottom portion of the first semiconductor channel layer 601 (if present), tunneling dielectric layer 56, and barrier dielectric layer 52 located above the pedestal channel portion 11 at the bottom of each memory opening 49 (or above the upper substrate semiconductor layer 10 if the pedestal channel portion is absent). The central portion of the top surface of the pedestal channel portion 11 can be vertically recessed by an anisotropic etching process. In the absence of the pedestal channel portion 11 in the memory opening 49, a portion of the horizontal surface of the upper substrate semiconductor layer 10 can be vertically recessed below the memory opening 49. The patterned film 77 (if present) can then be removed, for example, by ashing.

[0207] refer to Figure 11E It can be executed Figure 10K The processing steps are to form the second semiconductor channel layer 602. The materials of the first semiconductor channel layer 601 and the second semiconductor channel layer 602 are collectively referred to as the semiconductor channel material. The combination of the barrier dielectric layer 52, the tunneling dielectric layer 56, the first semiconductor channel layer 601, and the second semiconductor channel layer 602 can completely fill the volume of the annular lateral recess provided at the layer level of the insulating layer 32.

[0208] refer to Figure 11F It can be executed Figure 10L The processing steps are to form a dielectric core 62 in each memory opening 49.

[0209] refer to Figure 11G It can be executed Figure 10M The processing steps involve forming a doped semiconductor portion, such as a drain region 63, at the upper portion of each memory opening 49. Each adjacent pair of the first semiconductor channel layer 601 and the second semiconductor channel layer 602 can collectively form a vertical semiconductor channel 60 through which current can flow when the vertical NAND device including the vertical semiconductor channel 60 is turned on. A tunneling dielectric layer 56 is surrounded by a vertical stack of silicon nitride material portions 54N and laterally surrounds a portion of the vertical semiconductor channel 60. Each adjacent group of the tunneling dielectric layer 56, the vertical stack of silicon nitride material portions 54N, and the barrier dielectric layer 52 collectively constitutes a memory film 50 comprising a vertical stack of memory elements capable of storing corresponding data bits with macroscopic retention times.

[0210] Each combination of the memory film 50 and the vertical semiconductor channel 60 within the memory opening 49 constitutes a memory stack structure 55. The memory stack structure 55 is a combination of the semiconductor channel 60, the tunneling dielectric layer 56, a plurality of vertically stacked memory elements including silicon nitride material portions 54N, and the barrier dielectric layer 52. Each combination of the base channel portion 11 (if present), the memory stack structure 55, the dielectric core 62, and the drain region 63 within the memory opening 49 is referred to herein as a memory opening-filled structure 58. Each combination of the base channel portion 11 (if present), the memory film 50, the vertical semiconductor channel 60, the dielectric core 62, and the drain region 63 within each support opening 19 fills the corresponding support opening 19 and constitutes a support pillar structure.

[0211] Figure 11H and Figure 11I An alternative configuration of the fourth exemplary memory aperture-filled structure is shown. (Reference) Figure 11H By filling the annular transverse recess 149 with a dielectric filling material, it is possible to... Figure 10G The structure shown provides an alternative configuration for the seventh exemplary memory opening-filling structure. Figure 10N The processing steps can be used to form a vertical stack of annular insulating material portions 57 in the unfilled volume of the annular lateral recess of each memory opening 49.

[0212] refer to Figure 11I It can be executed Figures 10H to 10MThe processing steps are to provide an alternative configuration to the first exemplary memory opening-filling structure 58. In this case, the tunneling dielectric layer 56 can be formed directly on the vertical stack of the annular insulating material portions 57. The memory film 50 may include a barrier dielectric layer 52, a vertical stack of silicon nitride material portions 54N, a vertical stack of annular insulating material portions 57 (which may contact the vertical stack of silicon nitride material portions 54N), and a tunneling dielectric layer 56.

[0213] Figures 12A to 12G This is a schematic vertical cross-sectional view of the sequence of memory openings within an exemplary structure during the formation of an eighth exemplary memory opening-fill structure according to an embodiment of the present disclosure. The eighth exemplary memory opening-fill structure includes a hybrid discrete charge storage structure comprising a discrete dielectric charge storage portion and a floating gate having a flanged portion. Instead of the first, second, third, fourth, fifth, sixth, or seventh exemplary memory opening-fill structures described above, an eighth exemplary memory opening-fill structure may be formed within each memory opening 49.

[0214] refer to Figure 12A The structure for forming the eighth exemplary memory aperture-filling structure can be achieved by vertically stacking partially nitrided semiconductor material portions 54S. Figure 10G The structure is obtained in the memory cavity 49'. The surface portion of the semiconductor material portion 54S physically exposed to the memory cavity 49' is converted into a silicon nitride material portion 54N, while the lower portion of the contact barrier dielectric layer 52 of the semiconductor material portion 54S is retained as the semiconductor material portion 54S. Therefore, the vertical stack of silicon nitride material portions 54N is formed by a nitriding process, and the remaining vertical stack of semiconductor material portions 54S has a higher density than that in the memory cavity 49'. Figure 10G The vertically stacked semiconductor material portions 54S provided at the processing step have a small volume. The vertical stack of the composite charge storage structures (54S, 54N) can be formed by converting the surface portion of the vertically stacked discrete semiconductor material portions 54S into silicon nitride material portions 54N. In one embodiment, each silicon nitride material portion 54N includes an interface region located near a corresponding discrete semiconductor material portion 54S, and the interface region has a gradient silicon-to-nitrogen ratio, as described above. Each composite charge storage structure in the composite charge storage structures (54S, 54N) includes a corresponding semiconductor material portion 54S (which is as shown in... Figure 10G The processing steps provide the remaining portion of a corresponding discrete semiconductor material portion 54S and a corresponding silicon nitride material portion 54N, which is formed by nitriding the surface portion of the corresponding discrete semiconductor material portion 54S.

[0215] Each composite charge storage structure in the composite charge storage structure (54S, 54N) includes a tubular portion 54T, an upper flange portion 54U extending laterally outward from the upper end of the outer wall of the tubular portion 54T into the recess 149, and a lower flange portion 54F extending laterally outward from the lower end of the outer wall of the tubular portion 54T into the recess 149. Each semiconductor material portion 54S includes a corresponding tubular portion, a corresponding upper flange portion, and a corresponding lower flange portion. Each silicon nitride material portion 54N includes a corresponding tubular portion, a corresponding upper flange portion, and a corresponding lower flange portion. The thickness of the tubular portion of each semiconductor material portion 54S can be in the range of 1 nm to 30 nm, such as 2 nm to 20 nm, but smaller and larger thicknesses are also possible. The thickness of the tubular portion of each silicon nitride material portion 54N can be in the range of 1 nm to 30 nm, such as 2 nm to 20 nm, but smaller and larger thicknesses are also possible. The thickness of each tubular portion of the composite charge storage structure (54S, 54N) can range from 3 nm to 30 nm, such as 5 nm to 15 nm, but smaller and larger thicknesses are also possible. The thickness of the tubular portion of the composite charge storage structure (54S, 54N) can be formed between the inner cylindrical sidewall and the outer cylindrical sidewall of the corresponding composite charge storage structure (54S, 54N).

[0216] Vertically stacked composite charge storage structures (54S, 54N) are positioned at the level of spacer material layers (such as sacrificial material layer 42) and partially protrude into the recess 149. In one embodiment, each composite charge storage structure in the composite charge storage structures (54S, 54N) includes a tubular portion 54T, an upper flange portion 54U, and a lower flange portion 54F. The upper flange portion 54U and lower flange portion 54F of each composite charge storage structure (54S, 54N) provide an increased charge trapping volume in addition to the charge trapping volume provided by the tubular portion 54T. Therefore, the thickness of the spacer material layer (such as sacrificial material layer 42) can be reduced relative to conventional NAND devices that do not include flange portions. The vertical stack of composite charge storage structures (54S, 54N) can then be used as a vertical stack of charge storage elements, which can be used as a hybrid floating gate and charge trapping dielectric element for NAND strings. After the vertical stack of the metal-semiconductor alloy portion 67 is removed, a portion of the inner sidewall of the barrier dielectric layer 52 is physically exposed.

[0217] refer to Figure 12B It can be executed Figure 10H The processing steps are to form a tunneling dielectric layer 56.

[0218] refer to Figure 12C It can be executed Figure 10IThe processing steps are used to form an optional first semiconductor channel layer 601.

[0219] refer to Figure 12D It can be executed arbitrarily. Figure 10J The processing steps involve depositing an optional patterned film 77, and anisotropically etching the horizontal bottom portion of the first semiconductor channel layer 601 (if present), tunneling dielectric layer 56, and barrier dielectric layer 52 located above the base channel portion 11 at the bottom of each memory opening 49 (or above the upper substrate semiconductor layer 10 if the base channel portion is absent). The central portion of the top surface of the base channel portion 11 can be vertically recessed by an anisotropic etching process. In the absence of the base channel portion 11 in the memory opening 49, a portion of the horizontal surface of the upper substrate semiconductor layer 10 can be vertically recessed below the memory opening 49. The patterned film 77 can then be removed, for example, by ashing.

[0220] refer to Figure 12E It can be executed Figure 10K The processing steps are to form the second semiconductor channel layer 602. The materials of the first semiconductor channel layer 601 and the second semiconductor channel layer 602 are collectively referred to as the semiconductor channel material. The combination of the barrier dielectric layer 52, the tunneling dielectric layer 56, the first semiconductor channel layer 601, and the second semiconductor channel layer 602 can completely fill the volume of the annular lateral recess provided at the layer level of the insulating layer 32.

[0221] refer to Figure 12F It can be executed Figure 10L The processing steps are to form a dielectric core 62 in each memory opening 49.

[0222] refer to Figure 12G It can be executed Figure 10M The processing steps involve forming a doped semiconductor portion, such as a drain region 63, at the upper portion of each memory opening 49. Each adjacent pair of the first semiconductor channel layer 601 and the second semiconductor channel layer 602 can collectively form a vertical semiconductor channel 60 through which current can flow when the vertical NAND device including the vertical semiconductor channel 60 is turned on. A tunneling dielectric layer 56 is surrounded by a vertical stack of composite charge storage structures (54S, 54N) and laterally surrounds a portion of the vertical semiconductor channel 60. Each adjacent group of the tunneling dielectric layer 56, the vertical stack of composite charge storage structures (54S, 54N), and the barrier dielectric layer 52 collectively constitutes a memory film 50 comprising a vertical stack of memory elements capable of storing corresponding data bits with macroscopic retention times.

[0223] Each combination of the memory film 50 and the vertical semiconductor channel 60 within the memory opening 49 constitutes a memory stack structure 55. The memory stack structure 55 is a combination of the semiconductor channel 60, the tunneling dielectric layer 56, a plurality of vertically stacked memory elements including a composite charge storage structure (54S, 54N), and the barrier dielectric layer 52. Each combination of the base channel portion 11 (if present), the memory stack structure 55, the dielectric core 62, and the drain region 63 within the memory opening 49 is referred to herein as a memory opening-filling structure 58. Each combination of the base channel portion 11 (if present), the memory film 50, the vertical semiconductor channel 60, the dielectric core 62, and the drain region 63 within each support opening 19 fills the corresponding support opening 19 and constitutes a support pillar structure.

[0224] Figure 12H and Figure 12I An alternative configuration of the fourth exemplary memory aperture-filled structure is shown. (Reference) Figure 12H By filling the annular transverse recess 149 with a dielectric filling material, it is possible to... Figure 10G The structure shown provides an alternative configuration for the fourth exemplary memory opening-filling structure. Figure 10N The processing steps can be used to form a vertical stack of annular insulating material portions 57 in the unfilled volume of the annular lateral recess of each memory opening 49.

[0225] refer to Figure 12I It can be executed Figures 10H to 10M The processing steps are to provide an alternative configuration to the first exemplary memory opening-filling structure 58. In this case, the tunneling dielectric layer 56 can be formed directly on the vertical stack of the annular insulating material portions 57. The memory film 50 may include a barrier dielectric layer 52, a vertical stack of composite charge storage structures (54S, 54N), a vertical stack of the annular insulating material portions 57 (which are accessible to the vertical stack of the silicon nitride material portions 54N), and the tunneling dielectric layer 56.

[0226] refer to Figure 13 This illustrates an exemplary structure after a memory opening filling structure 58 and a support pillar structure 20 are formed within the memory opening 49 and support opening 19, respectively. It is possible to... Figure 4A and Figure 4B An instance of a memory opening filling structure 58 is formed within each memory opening 49 of the structure. It can be... Figure 4A and Figure 4B An example of a structure in which a support column structure 20 is formed within each support opening 19.

[0227] Each memory stack structure 55 includes a vertical semiconductor channel 60, which may include multiple semiconductor channel layers (601, 602) and a memory film 50. The memory film 50 may include a tunneling dielectric layer 56 laterally surrounding the vertical semiconductor channel 60, a vertical stack of charge storage regions (including charge storage layer 54) laterally surrounding the tunneling dielectric layer 56, and an optional barrier dielectric layer 52. Although this disclosure is described using the illustrated configuration for a memory stack structure, the methods of this disclosure can be applied to alternative memory stack structures including different layer stacks or structures for the memory film 50 and / or for the vertical semiconductor channel 60.

[0228] refer to Figure 14A and Figure 14B The contact-level dielectric layer 73 can be formed over the alternating stacks (32, 42) of the insulating layer 32 and the sacrificial material layer 42, and over the memory stack structure 55 and the support pillar structure 20. The contact-level dielectric layer 73 comprises a dielectric material different from that of the sacrificial material layer 42. For example, the contact-level dielectric layer 73 may comprise silicon oxide. The contact-level dielectric layer 73 can have a thickness ranging from 50 nm to 500 nm, but smaller and larger thicknesses are also possible.

[0229] A photoresist layer (not shown) may be applied to the contact-level dielectric layer 73 and photolithographically patterned to form openings in regions between clusters of the memory stack structure 55. The pattern in the photoresist layer may be transmitted through the contact-level dielectric layer 73, the alternating stacks (32, 42), and / or the backward stepped dielectric material portions 65 using anisotropic etching to form a back-side trench 79 that extends vertically from the top surface of the contact-level dielectric layer 73 to the top surface of the substrate (9, 10) and laterally through the memory array region 100 and the staircase region 300.

[0230] In one embodiment, the back-side trenches 79 may extend laterally along a first horizontal direction hd1 and may be laterally spaced from each other along a second horizontal direction hd2, which is perpendicular to the first horizontal direction hd1. Memory stack structures 55 may be arranged in rows extending along the first horizontal direction hd1. Drain select hierarchical isolation structures 72 may extend laterally along the first horizontal direction hd1. Each back-side trench 79 may have a uniform width that remains constant along the longitudinal direction (i.e., along the first horizontal direction hd1). Each drain select hierarchical isolation structure 72 may have a uniform vertical cross-sectional profile along a vertical plane perpendicular to the first horizontal direction hd1, which does not change with translation along the first horizontal direction hd1. Multi-row memory stack structures 55 may be located between adjacent pairs of back-side trenches 79 and drain select hierarchical isolation structures 72, or between adjacent pairs of drain select hierarchical isolation structures 72. In one embodiment, the back-side trenches 79 may include source contact openings, where source contact via structures may subsequently be formed. The photoresist layer can be removed, for example, by ashing.

[0231] A dopant of a second conductivity type can be implanted into the portion of the upper substrate semiconductor layer 10 located below the back-side trench 79 to form a source region 61. The atomic concentration of the second conductivity type dopant in the source region 61 can range from 5.0 × 10¹⁸ / cm³ to 2.0 × 10²¹ / cm³, but smaller and larger atomic concentrations are also possible. The surface portion of the upper substrate semiconductor layer 10 extending between each source region 61 and the adjacent memory opening fill structure 58 includes a horizontal semiconductor channel 59.

[0232] refer to Figure 15 An etchant can be introduced into the back trench 79, for example, using an etching process. This etchant selectively etches the spacer material of the sacrificial material layer 42 relative to the insulating material of the insulating layer 32. A back recess 43 is formed in the volume from which the sacrificial material layer 42 is removed. The spacer material of the sacrificial material layer 42 can be selectively removed from the insulating material of the insulating layer 32, the material of the backward stepped dielectric portion 65, the semiconductor material of the upper substrate semiconductor layer 10, and the outermost material of the memory film 50. In one embodiment, the sacrificial material layer 42 may comprise silicon nitride, and the materials of the insulating layer 32 and the backward stepped dielectric portion 65 may be selected from silicon oxide and dielectric metal oxide.

[0233] The etching process that selectively removes spacer material relative to the outermost layer of the insulating material and memory film 50 can be a wet etching process using a wet etching solution, or a vapor-phase (dry) etching process that introduces the etchant in a vapor phase into the back trench 79. For example, if the sacrificial material layer 42 comprises silicon nitride, the etching process can be a wet etching process that immerses the exemplary structure in a wet etching bath comprising phosphoric acid, which selectively etches silicon nitride against silicon oxide, silicon, and various other materials used in the art. When the back recess 43 is present within the volume previously occupied by the sacrificial material layer 42, the support pillar structure 20, the backward stepped dielectric portion 65, and the memory stack structure 55 provide structural support.

[0234] Each back-side recess 43 may be a laterally extending cavity, the lateral dimension of which is greater than the vertical extent of the cavity. In other words, the lateral dimension of each back-side recess 43 may be greater than the height of the back-side recess 43. Multiple back-side recesses 43 may be formed in the volume from which spacer material of the sacrificial material layer 42 is removed. The memory openings forming the memory stack structure 55 are referred to herein as front openings or front cavities, in contrast to the back-side recesses 43. In one embodiment, the memory array region 100 includes a single three-dimensional NAND string array having multiple device levels disposed above the substrate (9, 10). In this case, each back-side recess 43 may define space for receiving a corresponding word line of the single three-dimensional NAND string array.

[0235] Each of the plurality of back-side recesses 43 may extend substantially parallel to the top surface of the substrate (9, 10). The back-side recesses 43 may be defined perpendicularly by the top surface of the underlying insulating layer 32 and the bottom surface of the covering insulating layer 32. In one embodiment, each back-side recess 43 may always have a uniform height.

[0236] refer to Figure 16A and Figure 16BThe optional base channel portion 11 and the physically exposed surface portions of the upper substrate semiconductor layer 10 can be converted into dielectric material portions by thermal conversion and / or plasma conversion of the semiconductor material. For example, thermal conversion and / or plasma conversion can be used to convert the surface portions of each base channel portion 11 into tubular dielectric spacers 116 and each physically exposed surface portion of the upper substrate semiconductor layer 10 into planar dielectric portions (not shown). In one embodiment, each tubular dielectric spacer 116 may be topologically homeomorphic to a torus, i.e., generally annular. As used herein, an element is topologically homeomorphic to a torus if the shape of the element can be continuously stretched without destroying the hole or forming a new hole into the shape of the torus. The tubular dielectric spacer 116 comprises a dielectric material that includes the same semiconductor element as the base channel portion 11 and additionally comprises at least one nonmetallic element such as oxygen and / or nitrogen, such that the material of the tubular dielectric spacer 116 is a dielectric material. In one embodiment, the tubular dielectric spacer 116 may comprise a dielectric oxide, dielectric nitride, or dielectric oxide oxynitride of the semiconductor material of the base channel portion 11. Dopants in the drain region 63, source region 61, and semiconductor channel 60 may be activated during the annealing process that forms the planar dielectric portion and the tubular dielectric spacer 116. Alternatively, additional annealing processes may be performed to activate electrical dopants in the drain region 63, source region 61, and semiconductor channel 60.

[0237] A back-side barrier dielectric layer 44 may optionally be formed. The back-side barrier dielectric layer 44 (if present) comprises a dielectric material used as a control gate dielectric for a control gate subsequently formed in the back-side recess 43. The back-side barrier dielectric layer 44 is optional if a barrier dielectric layer 52 is present in each memory opening. The back-side barrier dielectric layer 44 is present even if the barrier dielectric layer 52 is omitted.

[0238] A back-side barrier dielectric layer 44 can be formed in the back-side recess 43 and on the sidewalls of the back-side trench 79. The back-side barrier dielectric layer 44 can be formed directly on the horizontal surface of the insulating layer 32 within the back-side recess 43 and on the sidewalls of the memory stack structure 55. If the back-side barrier dielectric layer 44 is formed, it is optional to form tubular dielectric spacers 116 and planar dielectric portions prior to forming the back-side barrier dielectric layer 44. In one embodiment, the back-side barrier dielectric layer 44 can be formed by a conformal deposition process such as atomic layer deposition (ALD) or low-pressure chemical vapor deposition (LPCVD). The back-side barrier dielectric layer 44 can be substantially composed of aluminum oxide. The thickness of the back-side barrier dielectric layer 44 can range from 1 nm to 15 nm, such as 2 nm to 6 nm, but smaller and larger thicknesses are also possible.

[0239] The dielectric material of the back-side barrier dielectric layer 44 may be a dielectric metal oxide (such as aluminum oxide), a dielectric oxide of at least one transition metal element, a dielectric oxide of at least one lanthanide element, or a dielectric oxide of a combination of aluminum, at least one transition metal element, and / or at least one lanthanide element. Alternatively or additionally, the back-side barrier dielectric layer 44 may include a silicon oxide layer. The back-side barrier dielectric layer 44 may be deposited by conformal deposition methods such as low-pressure chemical vapor deposition or atomic layer deposition. The back-side barrier dielectric layer 44 is formed on the sidewalls of the back-side trench 79, the horizontal surface and sidewalls of the insulating layer 32, the sidewall surfaces of the memory stack structure 55 physically exposed to the back-side recess 43, and the top surface of the planar dielectric portion. Back-side cavities exist within the unfilled portions of each back-side trench 79 containing the back-side barrier dielectric layer 44.

[0240] At least one metallic material may be deposited in the backside recess 43. For example, a combination of a metal barrier layer and a metal filler material may be deposited in the backside recess 43. The metal barrier layer comprises a conductive metallic material, which may serve as a diffusion barrier layer and / or adhesion promoter layer for the subsequently deposited metal filler material. The metal barrier layer may comprise conductive metal nitride materials such as TiN, TaN, WN, MoN, or stacks thereof, or may comprise conductive metal carbide materials such as TiC, TaC, WC, or stacks thereof. In one embodiment, the metal barrier layer may be deposited using conformal deposition processes such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the metal barrier layer may be in the range of 2 nm to 8 nm, such as 3 nm to 6 nm, but smaller and larger thicknesses are also possible. In one embodiment, the metal barrier layer may consist substantially of a conductive metal nitride such as TiN. The metal filler material may be deposited using a conformal deposition method, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. In one embodiment, the metal filler layer may consist substantially of at least one elemental metal. The at least one elemental metal of the metal filler layer may be selected from, for example, tungsten, molybdenum, cobalt, ruthenium, titanium, and tantalum. In one embodiment, the metal filler layer may consist substantially of a single elemental metal. In one embodiment, a fluorine-containing precursor gas such as WF6 may be used to deposit the metal filler layer. In one embodiment, the metal filler layer may be a tungsten layer including residual fluorine atoms as impurities. The metal filler layer is spaced from the insulating layer 32 and the memory stack structure 55 by a metal barrier layer that prevents fluorine atoms from diffusing through it.

[0241] Multiple conductive layers 46 may be formed in multiple back-side recesses 43, and a continuous conductive material layer (not shown) may be formed on the sidewalls of each back-side trench 79 and above the contact-level dielectric layer 73. Each conductive layer 46 includes a portion of a metal barrier layer 46A and a portion of a metal filler layer 46B located between a pair of vertically adjacent dielectric material layers, such as a pair of insulating layers 32. The continuous conductive material layer includes a continuous portion of the at least one conductive material positioned in the back-side trench 79 or above the contact-level dielectric layer 73.

[0242] Each sacrificial material layer 42 may be replaced by a conductive layer 46. Back-side cavities exist in the portions of each back-side trench 79 that are not filled with the back-side blocking dielectric layer 44 and the continuous conductive material layer. Tubular dielectric spacers 116 laterally surround the base channel portion 11. When forming the conductive layer 46, the bottommost conductive layer 46 laterally surrounds each tubular dielectric spacer 116.

[0243] The deposited metallic material of the continuous conductive material layer is etched back from the sidewalls of each back trench 79 and from the contact-level dielectric layer 73, for example, by isotropic wet etching, anisotropic dry etching, or a combination thereof. Each remaining portion of the deposited metallic material in the back recess 43 constitutes a conductive layer 46. Each conductive layer 46 may be a conductive line structure. Therefore, the sacrificial material layer 42 is replaced by the conductive layer 46.

[0244] Each conductive layer 46 can serve as a combination of multiple control gate electrodes located at the same level and word lines electrically interconnected (i.e., electrically short-circuited) with the multiple control gate electrodes located at the same level. The multiple control gate electrodes within each conductive layer 46 are control gate electrodes for vertical memory devices including the memory stack structure 55. In other words, each conductive layer 46 can serve as a word line serving as a common control gate electrode for multiple vertical memory devices.

[0245] In one embodiment, the removal of the continuous conductive material layer may be selective in terms of the material of the back-side barrier dielectric layer 44. In this case, a horizontal portion of the back-side barrier dielectric layer 44 may be present at the bottom of each back-side trench 79. In another embodiment, the removal of the continuous conductive material layer may not be selective in terms of the material of the back-side barrier dielectric layer 44, or the back-side barrier dielectric layer 44 may not be used. Planar dielectric portions may be removed during the removal of the continuous conductive material layer. Back-side cavities are present within each back-side trench 79.

[0246] refer to Figure 17An insulating material layer can be formed in the back trench 79 and over the contact-level dielectric layer 73 using a conformal deposition process. Exemplary conformal deposition processes include, but are not limited to, chemical vapor deposition and atomic layer deposition. The insulating material layer includes insulating materials such as silicon oxide, silicon nitride, dielectric metal oxide, organosilicon glass, or combinations thereof. In one embodiment, the insulating material layer may include silicon oxide. The insulating material layer can be formed, for example, by low-pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD). The thickness of the insulating material layer can range from 1.5 nm to 60 nm, but smaller and larger thicknesses are also possible.

[0247] If a back-side barrier dielectric layer 44 is present, the insulating material layer can be formed directly on the surface of the back-side barrier dielectric layer 44 and directly on the sidewall of the conductive layer 46. If a back-side barrier dielectric layer 44 is not used, the insulating material layer can be formed directly on the sidewall of the insulating layer 32 and directly on the sidewall of the conductive layer 46.

[0248] Anisotropic etching is performed to remove horizontal portions of the insulating material layer from above the contact-level dielectric layer 73 and at the bottom of each back-side trench 79. Each remaining portion of the insulating material layer constitutes an insulating spacer 74. A back-side cavity exists within the volume surrounded by each insulating spacer 74. The top surface of the upper substrate semiconductor layer 10 is physically exposed at the bottom of each back-side trench 79.

[0249] The upper portion of the upper substrate semiconductor layer 10, extending between the source region 61 and the plurality of base channel portions 11, constitutes a horizontal semiconductor channel 59 for a plurality of field-effect transistors. The horizontal semiconductor channel 59 is connected to a plurality of vertical semiconductor channels 60 via corresponding base channel portions 11. The horizontal semiconductor channel 59 contacts the source region 61 and the plurality of base channel portions 11. The bottommost conductive layer 46 provided when forming a conductive layer 46 within the alternating stack (32, 46) may include the selected gate electrode of the field-effect transistor. Each source region 61 is formed in the upper portion of the substrate (9, 10). Semiconductor channels (59, 11, 60) extend between each source region 61 and a corresponding set of drain regions 63. The semiconductor channels (59, 11, 60) include the vertical semiconductor channels 60 of the memory stack structure 55.

[0250] A back-side contact via structure 76 can be formed within each back-side cavity. Each contact via structure 76 can fill a corresponding back-side cavity. The contact via structure 76 can be formed by depositing at least one conductive material in the remaining unfilled volume (i.e., the back-side cavity) of the back-side trench 79. For example, the at least one conductive material may include a conductive pad 76A and a conductive filler portion 76B. The conductive pad 76A may include a conductive metal pad, such as TiN, TaN, WN, WC, TiC, TaC, MoN, alloys thereof, or stacks thereof. The thickness of the conductive pad 76A may range from 3 nm to 30 nm, but smaller and larger thicknesses are also possible. The conductive filler portion 76B may include a metal or metal alloy. For example, the conductive filler portion 76B may include W, Mo, Cu, Al, Co, Ru, Ni, alloys thereof, or stacks thereof.

[0251] In an alternative embodiment, the contact via structure 76 may be omitted, and the horizontal source line may contact the side of the bottom portion of the vertical semiconductor channel 60.

[0252] The contact-level dielectric layer 73, covering alternating stacks (32, 46), can be used as a stop layer to planarize the at least one conductive material. If a chemical mechanical planarization (CMP) process is employed, the contact-level dielectric layer 73 can be used as a CMP stop layer. Each remaining continuous portion of the at least one conductive material in the back-side trench 79 constitutes a back-side contact via structure 76.

[0253] The back-side contact via structure 76 extends through the alternating stack (32, 46) and contacts the top surface of the source region 61. If a back-side barrier dielectric layer 44 is used, the back-side contact via structure 76 can contact the sidewalls of the back-side barrier dielectric layer 44.

[0254] refer to Figure 18A and Figure 18B Additional contact via structures (88, 86, 8P) can be formed through the contact-level dielectric layer 73 and optionally through the backward-stepped dielectric portion 65. For example, a drain contact via structure 88 can be formed through the contact-level dielectric layer 73 on each drain region 63. A word line contact via structure 86 can be formed on the conductive layer 46 through the contact-level dielectric layer 73 and through the backward-stepped dielectric portion 65. A peripheral device contact via structure 8P can be formed directly on the corresponding node of the peripheral device through the backward-stepped dielectric portion 65.

[0255] Exemplary structures may include three-dimensional memory devices. In one embodiment, the three-dimensional memory device includes a single three-dimensional NAND memory device. The conductive layer 46 may include or be electrically connected to corresponding word lines of the single three-dimensional NAND memory device. The substrate (9, 10) may include a silicon substrate. A vertical NAND memory device may include a single three-dimensional NAND string array above the silicon substrate. The silicon substrate may contain an integrated circuit including driver circuitry (including a subset of at least one semiconductor device 700) for memory devices positioned thereon. Alternatively, the driver circuitry may be formed on a separate substrate and then bonded to the memory device. The conductive layer 46 may include a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate (9, 10), for example, between a pair of back-side trenches 79. The plurality of control gate electrodes includes at least a first control gate electrode positioned in a first device level and a second control gate electrode positioned in a second device level. An array of single-unit three-dimensional NAND strings may include: a plurality of semiconductor channels (59, 11, 60), wherein at least one end portion 60 of each of the plurality of semiconductor channels (59, 11, 60) extends substantially perpendicular to the top surface of the substrate (9, 10) and includes a corresponding vertical semiconductor channel among the vertical semiconductor channels 60; and a plurality of charge storage elements. Each charge storage element may be positioned adjacent to a corresponding semiconductor channel among the plurality of semiconductor channels (59, 11, 60).

[0256] Figure 19A In the case where, according to the embodiments of this disclosure, either the first exemplary memory opening filling structure or the second exemplary memory opening filling structure exists in the memory opening... Figure 18A and Figure 18B An enlarged view of the memory opening in the exemplary structure. In this case, each charge storage element may include a semiconductor material portion 54S, which may have a tubular configuration. The tunneling dielectric layer 56 is in direct contact with the barrier dielectric layer 52 at the level of the insulating layer 32.

[0257] Figure 19B In the case where an alternative configuration of the first exemplary memory opening filling structure or the second exemplary memory opening filling structure exists in the memory opening according to the embodiments of this disclosure. Figure 18A and Figure 18B An enlarged view of the memory opening in the exemplary structure. In this case, each charge storage element may include a semiconductor material portion 54S, which may have a tubular configuration. The tunneling dielectric layer 56 is in direct contact with the inner sidewall of the annular insulating material portion 57 at the level of the insulating layer 32.

[0258] Figure 20AThis refers to the implementation of the present disclosure in the case where a third exemplary memory opening filling structure exists in a memory opening. Figure 18A and Figure 18B An enlarged view of the memory opening in the exemplary structure. In this case, each charge storage element may include a combination of a semiconductor material portion 54S (which may have a tubular configuration) and a portion of silicon nitride layer 53 positioned at the level of the semiconductor material portion 54S. The tunneling dielectric layer 56 is in direct contact with the barrier dielectric layer 52 at the level of the insulating layer 32.

[0259] Figure 20B This refers to the case where an alternative configuration of the third exemplary memory opening filling structure exists in the memory opening, according to an embodiment of this disclosure. Figure 18A and Figure 18B An enlarged view of the memory opening in the exemplary structure. In this case, each charge storage element may include a combination of a semiconductor material portion 54S (which may have a tubular configuration) and a portion of silicon nitride layer 53 positioned at the level of the semiconductor material portion 54S. The tunneling dielectric layer 56 is in direct contact with the inner sidewall of the annular insulating material portion 57 at the level of the insulating layer 32.

[0260] Figure 21A This is according to an embodiment of the present disclosure in the case where a fourth exemplary memory opening filling structure exists in a memory opening. Figure 18A and Figure 18B An enlarged view of the memory opening in the exemplary structure. In this case, each charge storage element may include a discrete silicon nitride material portion 54N, which may have a tubular configuration. The tunneling dielectric layer 56 is in direct contact with the barrier dielectric layer 52 at the level of the insulating layer 32.

[0261] Figure 21B This refers to the case where an alternative configuration of the fourth exemplary memory opening filling structure exists in the memory opening, according to an embodiment of this disclosure. Figure 18A and Figure 18B An enlarged view of the memory opening in the exemplary structure. In this case, each charge storage element may include a silicon nitride material portion 54N, which may have a tubular configuration. The tunneling dielectric layer 56 is in direct contact with the inner sidewall of the annular insulating material portion 57 at the level of the insulating layer 32.

[0262] Figure 22A This refers to the implementation of the present disclosure in the case where the fifth exemplary memory opening filling structure exists in the memory opening. Figure 18A and Figure 18BAn enlarged view of the memory opening in the exemplary structure. In this case, each charge storage element may include a discrete composite charge storage structure (54S, 54N), which may have a tubular configuration. Each composite charge storage structure (54S, 54N) may include a stack of semiconductor material portion 54S and silicon nitride material portion 54N. The tunneling dielectric layer 56 is in direct contact with the barrier dielectric layer 52 at the level of the insulating layer 32.

[0263] Figure 22B This refers to the case where an alternative configuration of the fifth exemplary memory opening filling structure exists in the memory opening, according to an embodiment of this disclosure. Figure 18A and Figure 18B An enlarged view of the memory opening in the exemplary structure. In this case, each charge storage element may include a composite charge storage structure (54S, 54N), which may have a tubular configuration. Each composite charge storage structure (54S, 54N) may include a stack of semiconductor material portions 54S and silicon nitride material portions 54N. The tunneling dielectric layer 56 is in direct contact with the inner sidewall of the annular insulating material portion 57 at the level of the insulating layer 32.

[0264] Figure 23A This is according to an embodiment of the present disclosure, in the case where the sixth exemplary memory opening filling structure exists in the memory opening. Figure 18A and Figure 18B An enlarged view of the memory opening in the exemplary structure. In this case, each charge storage element may include a discrete semiconductor material portion 54S, which may have a tubular portion 54T, an upper flange portion 54U, and a lower flange portion 54F. The tunneling dielectric layer 56 is in direct contact with the barrier dielectric layer 52 at the level of the insulating layer 32.

[0265] Figure 23B This refers to the case where an alternative configuration of the sixth exemplary memory opening filling structure exists in the memory opening, according to an embodiment of this disclosure. Figure 18A and Figure 18B An enlarged view of the memory opening in an exemplary structure. In this case, each charge storage element may include a semiconductor material portion 54S, which may have a tubular portion 54T, an upper flange portion 54U, and a lower flange portion 54F. The tunneling dielectric layer 56 is in direct contact with the inner sidewall of the annular insulating material portion 57 at the level of the insulating layer 32.

[0266] Figure 24A This refers to the implementation of the present disclosure in the case where the seventh exemplary memory opening filling structure exists in the memory opening. Figure 18A and Figure 18BAn enlarged view of the memory opening in the exemplary structure. In this case, each charge storage element may include a discrete silicon nitride material portion 54N, which may have a tubular portion 54T, an upper flange portion 54U, and a lower flange portion 54F. The tunneling dielectric layer 56 is in direct contact with the barrier dielectric layer 52 at the level of the insulating layer 32.

[0267] Figure 24B This refers to the case where an alternative configuration of the seventh exemplary memory opening filling structure exists in the memory opening, according to an embodiment of this disclosure. Figure 18A and Figure 18B An enlarged view of the memory opening in an exemplary structure. In this case, each charge storage element may include a silicon nitride material portion 54N, which may have a tubular portion 54T, an upper flange portion 54U, and a lower flange portion 54F. The tunneling dielectric layer 56 is in direct contact with the inner sidewall of the annular insulating material portion 57 at the level of the insulating layer 32.

[0268] Figure 25A This refers to the implementation of the present disclosure in the case where the eighth exemplary memory opening filling structure exists in the memory opening. Figure 18A and Figure 18B An enlarged view of the memory opening in an exemplary structure. In this case, each charge storage element may include a discrete composite charge storage structure (54S, 54N) comprising a stack of semiconductor material portion 54S and silicon nitride material portion 54N. Each composite charge storage structure (54S, 54N) may have a tubular portion 54T, an upper flange portion 54U, and a lower flange portion 54F. The tunneling dielectric layer 56 is in direct contact with the barrier dielectric layer 52 at the level of the insulating layer 32.

[0269] Figure 25B This refers to the case where an alternative configuration of the eighth exemplary memory opening filling structure exists in the memory opening, according to an embodiment of this disclosure. Figure 18A and Figure 18B An enlarged view of the memory opening in an exemplary structure. In this case, each charge storage element may include a composite charge storage structure (54S, 54N) comprising a stack of semiconductor material portions 54S and silicon nitride material portions 54N. Each composite charge storage structure (54S, 54N) may have a tubular portion 54T, an upper flange portion 54U, and a lower flange portion 54F. The tunneling dielectric layer 56 is in direct contact with the inner sidewall of the annular insulating material portion 57 at the level of the insulating layer 32.

[0270] Referring to all the accompanying drawings and according to various embodiments of the present disclosure, a three-dimensional memory device is provided, comprising: an alternating stack of insulating layers 32 and conductive layers 46 positioned above a substrate (9, 10); a memory opening 49 extending vertically through the alternating stack (32, 46), wherein the memory opening 49 has lateral protrusions (such as annular lateral recesses 149) extending outward at each level of the insulating layers 32; and a memory opening filling structure 5. 8. The memory opening filling structure is positioned in the memory opening 49 and includes, from the outside to the inside: a barrier dielectric layer 52; a charge storage structure {(54S,54N) or (54S,52)}, the charge storage structure including a vertical stack of discrete semiconductor material portions 54S and at least one silicon nitride material portion (54N or 53) in contact with the vertical stack 54S; a tunneling dielectric layer 56 in contact with the charge storage structure {(54S,54N) or (54S,52)}; and a vertical semiconductor channel 60.

[0271] In one embodiment, at least one silicon nitride material portion 54N includes a vertical stack of discrete silicon nitride material portions 54N in contact with a corresponding discrete semiconductor material portion 54S within a vertical stack of discrete semiconductor material portions 54S.

[0272] In one embodiment, each discrete silicon nitride material portion 54N within the vertical stack of discrete silicon nitride material portions 54N is in contact with the tunneling dielectric layer 56; and each discrete semiconductor material portion 54S within the vertical stack of discrete semiconductor material portions 54S is not in contact with the tunneling dielectric layer 56, and is spaced apart from the tunneling dielectric layer 56 by the vertical stack of discrete silicon nitride material portions 54N.

[0273] In one embodiment, each silicon nitride material portion 54N includes a tubular portion 54T having a uniform thickness between an inner sidewall and an outer sidewall, an upper flange portion 54U extending outward from the upper periphery of the inner sidewall of the tubular portion 54T, and a lower flange portion 54F extending outward from the lower periphery of the inner sidewall of the tubular portion 54T.

[0274] In one embodiment, each silicon nitride material portion 54N includes an interface region located near a corresponding discrete semiconductor material portion 54S, and the interface region has a gradient silicon-to-nitrogen ratio.

[0275] In one embodiment, the at least one silicon nitride material portion includes a silicon nitride layer 53 that extends vertically through the alternating stacked layers (32, 46) and contacts the outer sidewall of each discrete semiconductor material portion 54S within the vertical stack of discrete semiconductor material portions 54S. In one embodiment, the silicon nitride layer 53 contacts the inner sidewall of the barrier dielectric layer 52 and the outer sidewall of the tunneling dielectric layer 56. In one embodiment, all surfaces of the vertical stack of discrete semiconductor material portions 54S contact the surface of the silicon nitride pad 53 or the surface of the tunneling dielectric layer 56.

[0276] In one embodiment, the tunneling dielectric layer 56 has a transversely wavy vertical cross-sectional profile and includes a transversely protruding portion positioned at the level of the insulating layer 32, which contacts the horizontal annular surface of the dielectric layer 52 and the upper or lower layer of the vertically stacked adjacent discrete semiconductor material portions 54S of the conductive layer 46.

[0277] In one embodiment, the memory aperture filling structure 58 includes a vertical stack of annular insulating material portions 57 positioned at each level of the insulating layer 32 between the barrier dielectric layer 52 and the tunneling dielectric layer 56; and the tunneling dielectric layer 56 includes a straight outer wall that contacts each annular insulating material portion 57 within the vertical stack of the annular insulating material portions 57 and contacts the vertical stack of discrete semiconductor material portions 54S.

[0278] According to another aspect of this disclosure, a three-dimensional memory device is provided, comprising: an alternating stack of insulating layers 32 and conductive layers 46 positioned above a substrate (9, 10); a memory opening 49 extending vertically through the alternating stack (32, 46), wherein the memory opening 49 has lateral protrusions (such as annular lateral recesses 149) extending outward at the level of the insulating layers 32; and a memory opening filling structure 58 positioned within the memory opening 49 and extending from... The structure, from the outside in, includes a barrier dielectric layer 52, a vertical stack of discrete charge storage material portions {54S,54N,(54S,54N)}, a tunneling dielectric layer 56, and a vertical semiconductor channel 60. Each charge storage material portion {54S,54N,(54S,54N)} includes a tubular portion 54T positioned at a level of a corresponding electrical material layer in the electrical material layer 46, an upper flange portion 54U extending laterally outward from the upper end of the outer sidewall of the tubular portion 54T, and a lower flange portion 54F extending laterally outward from the lower end of the outer sidewall of the tubular portion 54T.

[0279] In one embodiment, each charge storage material portion includes a corresponding semiconductor material portion 54S. In one embodiment, each charge storage material portion includes a corresponding silicon nitride material portion 54N. In one embodiment, each charge storage material portion includes a corresponding stack of semiconductor material portions 54S and silicon nitride material portions 54N. In one embodiment, the semiconductor material portion 54S of each charge storage material portion (54S, 54N) does not contact the tunneling dielectric layer 56 and is spaced apart from the tunneling dielectric layer 56 by a corresponding silicon nitride material portion in the silicon nitride material portion 54N.

[0280] In one embodiment, the upper flange portion 54U contacts the horizontal top surface of the barrier dielectric layer 52; and the lower flange portion 54F includes the horizontal bottom surface of the barrier dielectric layer 52.

[0281] In one embodiment, the barrier dielectric layer 52 has a laterally wavy vertical cross-sectional profile; the first tubular portion of the barrier dielectric layer 52 positioned at the level of the insulating layer 32 is laterally offset outward from the second tubular portion of the barrier dielectric layer 52 positioned at the level of the conductive layer 46; and the first tubular portion of the barrier dielectric layer 52 does not contact the vertically stacked charge storage material portion 54 (i.e., does not directly contact it).

[0282] In one embodiment, the vertical semiconductor channel 60 includes: a tubular portion extending vertically through a plurality of conductive material layers 46 within an alternating stack (32, 46); and a lateral protrusion extending outward from the tubular portion at a layer level of the insulating layer 32 (e.g., ...). Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A , Figure 24A and Figure 25A (As shown).

[0283] In one embodiment, the memory opening-fill structure 58 includes a vertical stack of annular insulating material portions 57 positioned at the level of an insulating layer 32 between the barrier dielectric layer 52 and the tunneling dielectric layer 56. The tunneling dielectric layer 56 includes straight outer walls that contact each annular insulating material portion 57 within the vertical stack of the annular insulating material portions 57 and also contact the vertical stack of charge storage material portions {54S, 54N, (54S, 54N)} (e.g., Figure 19B , Figure 20B , Figure 21B , Figure 22B , Figure 23B , Figure 24B and Figure 25B (As shown).

[0284] In one embodiment, the memory aperture filling structure 58 includes a doped semiconductor material portion (such as a drain region 63) that is on the vertical semiconductor channel 60 and forms a pn junction at the interface with the vertical semiconductor channel 60.

[0285] Various embodiments of this disclosure can be used to provide a vertical stack of discrete charge storage elements that provides reduced charge leakage and / or increased charge storage capacity across vertical levels by using flange portions for each charge storage element. Various embodiments of this disclosure can facilitate vertical scaling of devices in three-dimensional NAND memory devices or other vertical memory devices.

[0286] While specific preferred embodiments have been mentioned above, it will be understood that this disclosure is not limited thereto. Those skilled in the art will appreciate that various modifications can be made to the disclosed embodiments, and such modifications are intended to fall within the scope of this disclosure. Compatibility is assumed in all embodiments that are not alternatives to each other. Unless otherwise expressly stated, the words “comprising” or “including” contemplate that the words “substantially constitute…” or “consist of…” replace all embodiments in which the words “comprising” or “including” are used. While embodiments employing specific structures and / or configurations are shown in this disclosure, it should be understood that this disclosure can be practiced with any other functionally equivalent compatible structures and / or configurations, provided that such substitutions are not expressly prohibited or otherwise considered impossible by those skilled in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A method for forming a three-dimensional memory device, the method comprising: An alternating stack of insulating and spacer material layers is formed over a substrate, wherein the spacer material layers are formed as conductive layers or are subsequently replaced by conductive layers. Forming an opening through the alternating stacks of memory; An annular lateral recess is formed at the layer level of the insulating layer by making the sidewall of the insulating layer laterally recessed relative to the sidewall of the spacer material layer around the memory opening; A vertical stack of discrete metal parts is formed in the annular transverse recess; A semiconductor material layer is formed on the vertical stack of the metal portions; The vertical stack of metal-semiconductor alloy portions is formed by reacting the vertical stack of the metal portions with portions of the semiconductor material layer positioned at the level of the insulating layer. The vertical stack of metal-semiconductor alloy portions is selectively removed relative to the unreacted portions of the semiconductor material layer, wherein the unreacted portions of the semiconductor material layer are retained at the level of the spacer material layer and include the vertical stack of discrete semiconductor material portions; as well as A tunneling dielectric layer and a vertical semiconductor channel are formed in the memory opening.

2. The method of claim 1, wherein the tunneling dielectric layer is formed directly on the vertical stack of discrete semiconductor material portions.

3. The method of claim 1, further comprising converting the vertical stack of discrete semiconductor material portions into a vertical stack of discrete cylindrical silicon nitride material portions by performing a nitriding process prior to forming the tunneling dielectric layer.

4. The method of claim 1, further comprising forming a vertical stack of discrete composite charge storage structures by converting the surface portion of the vertically stacked discrete semiconductor material portions into silicon nitride material portions, wherein each discrete composite charge storage structure comprises a corresponding semiconductor material portion and a corresponding silicon nitride material portion, the corresponding semiconductor material portion being the remaining portion of a corresponding discrete semiconductor material portion, the corresponding silicon nitride material portion being formed by nitriding the surface portion of the corresponding discrete semiconductor material portion.

5. The method according to claim 1, further comprising: After forming the annular lateral recess, a barrier dielectric layer is formed on the sidewall of the memory opening; A metal layer is deposited conformally on the inner sidewall of the barrier dielectric layer; as well as The portion of the metal layer positioned outside the annular lateral recess is anisotropically etched, wherein the remaining portion of the metal layer comprises the vertical stack of discrete metal portions.

6. The method according to claim 1, further comprising: After forming the annular lateral recess, a barrier dielectric layer is formed on the sidewall of the memory opening; A metal layer is deposited conformally on the inner sidewall of the barrier dielectric layer; as well as The metal layer is induced to thermally migrate into the annular transverse recess by performing an annealing process, wherein during the annealing process, the metal layer separates from the vertical stack of discrete metal portions.

7. The method of claim 5 or 6, further comprising forming a silicon nitride layer on the barrier dielectric layer, wherein the vertical stack of discrete metal portions is formed on a portion of the inner sidewall of the silicon nitride layer positioned at the level of the insulating layer, and wherein, after the vertical stack of the metal-semiconductor alloy portions is removed, the tunneling dielectric layer is formed directly on the portion of the inner sidewall of the silicon nitride layer positioned at the level of the insulating layer.

8. The method according to claim 1, wherein: The vertical stack of discrete metal portions is formed directly on the portion of the inner wall of the barrier dielectric layer that is positioned at the level of the insulating layer. and After the vertical stack of the metal-semiconductor alloy portion is removed, the portion of the inner sidewall of the barrier dielectric layer is physically exposed.

9. The method of claim 8, wherein the tunneling dielectric layer is formed directly on the portion of the inner sidewall of the blocking dielectric layer located at the level of the insulating layer.

10. The method of claim 8, further comprising: The annular lateral recess is filled by depositing a dielectric filler material after removing the vertical stack of the metal-semiconductor alloy portion; as well as The dielectric filler material is removed from the outside of the annular lateral recess by anisotropic etching, wherein the remaining portion of the dielectric filler material filling the annular lateral recess comprises a vertical stack of annular insulating material portions, and the tunneling dielectric layer is formed directly on the vertical stack of annular insulating material portions.

11. A three-dimensional memory device, the three-dimensional memory device comprising: Alternating stacking of insulating and conductive layers, wherein the alternating stacking of insulating and conductive layers is positioned above the substrate; A memory opening that extends vertically through the alternating stack, wherein the memory opening has a lateral protrusion extending outward at the level of the insulating layer; and A memory opening-filling structure is positioned within a memory opening and, from the outside to the inside, includes a barrier dielectric layer, a vertically stacked discrete charge storage material portion, a tunneling dielectric layer, and a vertical semiconductor channel. The barrier dielectric layer extends vertically continuously through a plurality of conductive layers within the alternating stack and through a plurality of insulating layers within the alternating stack. The vertical semiconductor channel includes a tubular channel portion extending vertically through the plurality of conductive layers and a laterally projecting channel portion protruding outward from the tubular channel portion at a layer level of the insulating layer, such that the distal surface of the laterally projecting channel portion protrudes further outward from the tubular channel portion than the surface of the discrete charge storage material portion contacting the barrier dielectric layer. Each charge storage material portion includes a tubular portion positioned at a layer level of a corresponding conductive layer within the conductive layers, an upper flange portion extending laterally outward from the upper end of the outer sidewall of the tubular portion, and a lower flange portion extending laterally outward from the lower end of the outer sidewall of the tubular portion.

12. The three-dimensional memory device of claim 11, wherein each charge storage material portion comprises a corresponding semiconductor material portion.

13. The three-dimensional memory device of claim 11, wherein each charge storage material portion comprises a corresponding silicon nitride material portion.

14. The three-dimensional memory device of claim 11, wherein each charge storage material portion comprises a corresponding stack of semiconductor material portions and silicon nitride material portions.

15. The three-dimensional memory device of claim 14, wherein the semiconductor material portion of each charge storage material portion does not contact the tunneling dielectric layer, and is spaced apart from the tunneling dielectric layer by a corresponding silicon nitride material portion of the silicon nitride material portion.

16. The three-dimensional memory device according to claim 11, wherein: The barrier dielectric layer has a transversely wavy vertical cross-sectional profile. The first tubular portion of the barrier dielectric layer, positioned at the level of the insulating layer, is laterally offset outward from the second tubular portion of the barrier dielectric layer, positioned at the level of the conductive layer; and The first tubular portion of the barrier dielectric layer does not contact the vertically stacked portion of the charge storage material.

17. The three-dimensional memory device of claim 11, wherein the vertical semiconductor channel comprises: A tubular portion that extends vertically through multiple layers of conductive material within the alternating stack; and A lateral protrusion that protrudes outward from the tubular portion at the level of the insulating layer.

18. The three-dimensional memory device according to claim 11, wherein: The memory opening filling structure also includes a vertical stack of discrete annular silicon oxide insulating material portions located at the level of the insulating layer between the barrier dielectric layer and the tunneling dielectric layer; and The tunneling dielectric layer includes a straight outer wall that contacts each of the annular insulating material portions within the vertical stack of the annular insulating material portions, and contacts the vertical stack of the charge storage material portions.

19. The three-dimensional memory device of claim 11, wherein the memory opening filling structure further comprises a doped semiconductor drain region, the doped semiconductor drain region being above the vertical semiconductor channel and forming a pn junction at the interface with the vertical semiconductor channel.

20. The three-dimensional memory device of claim 11, wherein each charge storage material portion comprises a corresponding semiconductor material portion, a corresponding silicon nitride material portion, or a corresponding stack of semiconductor material portions and silicon nitride material portions.

21. The three-dimensional memory device of claim 11, wherein the blocking dielectric layer extends continuously vertically through each conductive layer within the alternating stack, except for the bottommost conductive layer within the alternating stack.

22. The three-dimensional memory device according to claim 11, wherein: In addition to the bottommost insulating layer within the alternating stack, each insulating layer within the alternating stack includes a corresponding cylindrical sidewall extending vertically from the horizontal top surface of the corresponding insulating layer to the horizontal bottom surface of the corresponding insulating layer; and The entirety of the corresponding cylindrical sidewall of each insulating layer is in direct contact with the corresponding cylindrical segment of the outer sidewall of the barrier dielectric layer.

23. The three-dimensional memory device of claim 11, further comprising a dielectric core laterally surrounded by the vertical semiconductor channel, wherein: The tunneling dielectric layer includes vertically extending surface sections that are further from the dielectric core in the lateral direction than the vertically stacked discrete charge storage material portions. Each vertically extending surface segment of the tunneling dielectric layer that is farther from the dielectric core in the lateral direction than the vertically stacked discrete charge storage material portion is in direct contact with the corresponding vertically extending surface segment of the blocking dielectric layer.

24. The three-dimensional memory device of claim 11, further comprising a dielectric core laterally surrounded by the vertical semiconductor channel, wherein: The vertical semiconductor channel includes a lateral protrusion at a layer level of the insulating layer; and Compared to the vertical stacking of discrete charge storage material portions away from the dielectric core, the distal sidewall of the lateral protrusion of the vertical semiconductor channel is farther from the dielectric core along the lateral direction.

25. The three-dimensional memory device of claim 24, wherein each of the lateral protrusions of the vertical semiconductor channel is located below a corresponding overlying discrete charge storage material portion within a vertical stack of discrete charge storage material portions, and has a region overlapping, along the vertical direction, with the corresponding overlying discrete charge storage material portion within the vertical stack of the discrete charge storage material portions, and is located above a corresponding lower discrete charge storage material portion within the vertical stack of the discrete charge storage material portions, and has a region overlapping, along the vertical direction, with the corresponding lower discrete charge storage material portion within the vertical stack of the discrete charge storage material portions.

26. The three-dimensional memory device of claim 11, wherein each charge storage material portion comprises: The outer wall of the upper flange portion has a top periphery that coincides with the outer periphery of the top surface of the upper flange portion. The outer wall of the lower flange portion has a bottom perimeter that coincides with the outer perimeter of the bottom surface of the lower flange portion; The entire outer wall of the upper flange portion is in contact with the corresponding first surface segment of the tunneling dielectric layer; as well as The entire outer wall of the lower flange portion is in contact with the corresponding second surface segment of the tunneling dielectric layer.

27. The three-dimensional memory device of claim 11, wherein the end region of the lateral protruding channel portion is thicker than the middle region of the lateral protruding channel portion, and wherein the end region of the lateral protruding channel portion is located further away from the tubular channel portion than the middle region of the lateral protruding channel portion.

28. The three-dimensional memory device of claim 11, wherein the tubular channel portion has a straight inner sidewall that extends vertically through a plurality of conductive material layers.

29. A three-dimensional memory device, the three-dimensional memory device comprising: Alternating stacking of insulating and conductive layers, wherein the alternating stacking of insulating and conductive layers is positioned above the substrate; A memory opening that extends vertically through the alternating stack, wherein the memory opening has a lateral protrusion extending outward at the level of the insulating layer; and A memory opening-filling structure, wherein the memory opening-filling structure is positioned in the memory opening and comprises, from the outside to the inside, a barrier dielectric layer extending vertically through a plurality of conductive layers within the alternating stack and through a plurality of insulating layers within the alternating stack, a vertical stack of charge storage material portions, a tunneling dielectric layer and a vertical semiconductor channel, and a vertical stack of discrete annular insulating material portions positioned at the level of the insulating layer between the barrier dielectric layer and the tunneling dielectric layer and having a material composition different from that of the vertical stack of charge storage material portions.

30. The three-dimensional memory device of claim 29, wherein the tunneling dielectric layer includes a straight outer sidewall that contacts each of the annular insulating material portions within the vertical stack of the annular insulating material portions and contacts the vertical stack of the charge storage material portions.

31. The three-dimensional memory device of claim 29, wherein the vertical stack of the discrete annular insulating material portions is in direct contact with the vertical stack of the charge storage material portions.

32. The three-dimensional memory device of claim 29, wherein the vertical stacking of the discrete annular insulating material portions provides a lateral spacing between the barrier dielectric layer and the tunneling dielectric layer, such that the tunneling dielectric layer does not directly contact the barrier dielectric layer below a horizontal plane including the top surface of the topmost conductive layer of the conductive layer.

33. The three-dimensional memory device of claim 29, wherein the vertical stack of the discrete ring insulating material portions comprises a material selected from undoped silicate glass or doped silicate glass.

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