Computing device comprising a magnetic Josephson junction with embedded magnetic field control elements

Abstract

The on-chip magnetic field control device is formed near the Josephson junction (JJ) structure. The on-chip magnetic field control device includes a wiring structure laterally adjacent to the JJ structure. In some embodiments, in addition to the wiring structure, the magnetic field control device also includes a conductive plate connected to the wiring structure and located below the JJ structure. A magnetic field is induced directly or indirectly into the JJ structure using a current passing through the wiring structure. The field strength can be modulated by the amount of current passing through the wiring structure. The magnetic field can be turned off as needed by stopping the current from flowing through the wiring structure.

Description

Background Art

[0001] The present invention relates to a computing device (i.e., neuromorphic or artificial intelligence (AI)), and more particularly to a computing device including an on-chip magnetic field control structure located near a Josephson junction (JJ) structure and a method of forming the same.

[0002] Devices containing magnetic JJs have been identified as promising for advanced low-power / high-performance neuromorphic applications. JJs consist of two layers of superconducting material separated by a non-superconducting barrier layer so thin that electrons can pass through it. JJs generally exhibit the Josephson effect of supercurrents, whereby current can flow indefinitely across the JJ in the absence of an applied voltage.

[0003] Devices containing magnetic JJs sometimes require an external magnetic field perpendicular to the device for their functionality. Toggle-type magnetoresistive random access memory (MRAM) has used dual lines oriented at 90° to adjust the functionality of MRAM devices. However, there are no known implementations of this in devices containing magnetic JJs. Therefore, there is a need for on-chip magnetic field control structures that can be integrated into devices containing JJs. Summary of the Invention

[0004] The on-chip magnetic field control device is formed to be close to (within 5nm to 500nm) a Josephson junction (JJ) structure. The on-chip magnetic field control device includes a wiring structure laterally adjacent to the JJ structure. In some embodiments, in addition to the wiring structure, the magnetic field control device also includes a conductive plate connected to the wiring structure and located below the JJ structure. A magnetic field is induced directly or indirectly into the JJ structure using a current passing through the wiring structure. The field strength can be modulated by the amount of current passing through the wiring structure. The magnetic field can be turned off as needed by stopping the current from flowing through the wiring structure.

[0005] In one aspect of the present invention, a computing device is provided that includes an on-chip magnetic field control structure located near a JJ structure. In one embodiment of the present invention, the computing device includes a conductive plate embedded in a surface of a semiconductor substrate. At least one JJ structure is located above the conductive plate. A first wiring structure is positioned laterally adjacent to the at least one JJ structure. In an embodiment of the present invention, one of the conductive plate or the first wiring structure is configured to induce a magnetic field into the at least one JJ structure when a current is applied to the at least one JJ structure.

[0006] In another embodiment of the present invention, a method for forming such a computing device is provided. In one embodiment of the present invention, the method includes forming a conductive plate in a semiconductor substrate. Next, a first dielectric material layer is formed on the physically exposed surface of the semiconductor substrate and the conductive plate, wherein the first dielectric material layer includes a through-hole opening that physically exposes the surface of the conductive plate. Then, a metal-containing layer is formed in each through-hole opening and on the topmost surface of the first dielectric material layer. Next, the metal-containing layer is patterned to provide first and second metal-containing wiring structures, wherein the first metal-containing wiring structure contacts the conductive plate and the second metal-containing wiring structure is spaced apart from the conductive plate. A JJ structure is then formed on each second metal-containing wiring structure. Next, a second dielectric material layer is formed laterally adjacent to and above each JJ structure. The second dielectric material layer includes a wiring contact structure and a JJ contact structure embedded therein. The wiring contact structure contacts the first metal-containing wiring structure, and the JJ contact structure contacts the JJ structure.

[0007] In another embodiment, the method includes forming a conductive plate in a semiconductor substrate. Next, forming at least one JJ structure on the conductive plate. A first dielectric material layer is then formed laterally adjacent to the at least one JJ structure, wherein the first dielectric material layer includes a wiring structure embedded therein that contacts the semiconductor substrate. Next, a second dielectric material layer is formed above the first dielectric material layer and above the at least one JJ structure. The second dielectric material layer includes a wiring contact structure and a JJ contact structure embedded therein. The wiring contact structure contacts the wiring structure, and the JJ contact structure contacts the JJ structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a cross-sectional view of an exemplary structure that may be employed in accordance with embodiments of the present invention, the exemplary structure including a conductive plate embedded in a semiconductor substrate.

[0009] Figure 2 After forming a first dielectric material layer on the physically exposed surface of the semiconductor substrate and the conductive plate Figure 1 A cross-sectional view of an exemplary structure of FIG.

[0010] Figure 3 yes Figure 2 A cross-sectional view of an exemplary structure after forming via openings through the first dielectric material layer, wherein each via opening physically exposes a surface of the conductive plate.

[0011] Figure 4 yes Figure 3 A cross-sectional view of the exemplary structure after forming a metal-containing layer in each via opening and on the topmost surface of the first dielectric material layer.

[0012] Figure 5 yes Figure 4 A cross-sectional view of an exemplary structure after patterning the metal-containing layer to provide a metal-containing wiring structure on the first dielectric material layer.

[0013] Figure 6 After forming a gap-fill dielectric material into the gaps between each metal-containing wiring structure Figure 5 A cross-sectional view of an exemplary structure of FIG.

[0014] Figure 7 After forming a precursor JJ material stack thereon Figure 6 A cross-sectional view of an exemplary structure of FIG.

[0015] Figure 8 After the precursor JJ material stack is converted into a JJ material stack Figure 7 A cross-sectional view of an exemplary structure of FIG.

[0016] Figure 9 After patterning the JJ material stack to form multiple JJ structures Figure 8 A cross-sectional view of an exemplary structure of a plurality of JJ structures, each of which is located on a surface of a metal wiring structure that does not directly contact a conductive plate.

[0017] Figure 10 This is after forming the dielectric spacers that encapsulate each JJ structure. Figure 9 A cross-sectional view of an exemplary structure of FIG.

[0018] Figure 11 After forming a second dielectric material layer laterally adjacent to and over each dielectric spacer-encapsulated JJ structure Figure 10 A cross-sectional view of an exemplary structure of FIG.

[0019] Figure 12 After forming a plurality of contact openings in the second dielectric material layer Figure 11 A cross-sectional view of an exemplary structure of FIG.

[0020] Figure 13 After forming a metal-containing contact structure in each contact opening Figure 12 A cross-sectional view of an exemplary structure of FIG.

[0021] Figure 14 is a cross-sectional view of another exemplary structure that may be employed in accordance with one embodiment of the present invention, the other exemplary structure including a conductive plate embedded in a semiconductor substrate.

[0022] Figure 15 After the JJ material stack is formed on the semiconductor substrate and the conductive plate Figure 14A cross-sectional view of an exemplary structure of FIG.

[0023] Figure 16 After patterning the JJ material stack to provide a JJ structure on the conductive plate Figure 15 A cross-sectional view of an exemplary structure of FIG.

[0024] Figure 17 After forming the dielectric spacer of the package JJ structure Figure 16 A cross-sectional view of an exemplary structure of FIG.

[0025] Figure 18 After forming a first dielectric material layer laterally adjacent to the JJ structure encapsulated by the dielectric spacer Figure 17 A cross-sectional view of an exemplary structure of FIG.

[0026] Figure 19 After forming the opening in the first dielectric material layer Figure 18 A cross-sectional view of an exemplary structure, wherein each opening physically exposes a surface of the semiconductor substrate.

[0027] Figure 20 After forming a metal-containing wiring structure in each opening Figure 19 A cross-sectional view of an exemplary structure of FIG.

[0028] Figure 21 After forming a second dielectric material layer on the first dielectric material layer Figure 20 sectional view of an exemplary structure in which the second dielectric material layer includes a plurality of contact structures embedded therein. DETAILED DESCRIPTION

[0029] Embodiments of the present invention will now be described in more detail with reference to the following discussion and accompanying drawings. It should be noted that the accompanying drawings are provided for illustrative purposes only and, therefore, are not drawn to scale. It should also be noted that identical and corresponding elements are designated by identical reference numerals.

[0030] In the following description, numerous specific details are set forth, such as specific structures, components, materials, dimensions, processing steps and techniques, in order to provide an understanding of the various embodiments of the present invention. However, one of ordinary skill in the art will appreciate that the various embodiments of the present invention can be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the present invention.

[0031] It will be understood that when an element as a layer, region, or substrate is referred to as being "on" or "over" another element, it can be directly on the other element or intervening elements may be present. Conversely, when an element is referred to as being "directly on" or "directly on" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "under" or "beneath" another element, it can be directly under or beneath the other element or there may be intervening elements present. Conversely, when an element is referred to as being "directly under" or "directly beneath" another element, there are no intervening elements present.

[0032] First reference Figure 1-13 , which shows a first method of the present invention, which can be used to provide a computing device that includes an on-chip magnetic control device located near a JJ structure. In an embodiment of the present invention, a conductive plate is embedded in a semiconductor substrate. A wiring structure is then formed above the conductive plate. In this embodiment, some wiring structures are in direct contact with the conductive plate, while other wiring structures are not in contact with the conductive plate. A JJ structure is then formed above each wiring structure that is not in contact with the conductive plate. Next, a contact structure is formed. Some contact structures contact the wiring structures that are in direct contact with the conductive plate, while other contact structures contact the JJ structure. Collectively, in this embodiment, the conductive plate and the wiring structure connected to the conductive plate serve as a magnetic control device located near each JJ structure.

[0033] In this embodiment, the conductive plate can generate a magnetic field by passing current through the wiring structure. The wiring structure itself can also generate a magnetic field, but such a magnetic field is negligible compared to the magnetic field generated by the conductive plate. The intensity of the magnetic field can be modulated by the amount of current passing through the wiring structure. Furthermore, the magnetic field can be turned off as needed by stopping the flow of current through the wiring structure.

[0034] First refer to Figure 1 , showing an exemplary structure that can be adopted according to an embodiment of the present invention. Figure 1 The exemplary structure includes a conductive plate 12 embedded in a semiconductor substrate 10. Notably, the conductive plate 12 is located in a trench formed in the semiconductor substrate 10 such that the semiconductor substrate 10 is laterally positioned adjacent to and below the conductive plate 12.

[0035] The semiconductor substrate 10 that can be used in embodiments of the present invention includes at least one semiconductor material having semiconductor properties. Examples of semiconductor materials that can provide the semiconductor substrate 10 include, for example, silicon (Si), germanium (Ge), silicon-germanium alloy (SiGe), silicon carbide (SiC), silicon-germanium carbide (SiGeC), III-V compound semiconductors, or II-VI compound semiconductors. III-V compound semiconductors are materials that include at least one element from Group III of the periodic table and at least one element from Group V of the periodic table. II-VI compound semiconductors are materials that include at least one element from Group II of the periodic table and at least one element from Group VI of the periodic table.

[0036] The semiconductor substrate 10 may be a single crystal semiconductor material. The semiconductor substrate 10 may have any known crystal orientation. For example, the crystal orientation of the semiconductor substrate 10 may be {100}, {110}, or {111}. Other crystal orientations other than those specifically mentioned may also be used in embodiments of the present invention.

[0037] In some embodiments, semiconductor substrate 10 is a bulk semiconductor substrate; that is, a substrate composed entirely of at least one semiconductor material. In other embodiments, semiconductor substrate 10 is a semiconductor-on-insulator (SOI) substrate, which includes a handle substrate, a buried insulator layer, and a top semiconductor material layer. In such embodiments, conductive plate 12 may be formed only within the top semiconductor material layer, or within the top semiconductor material layer and the buried insulator layer, or within the top semiconductor material layer, the buried insulator layer, and the handle substrate.

[0038] As described above, the conductive plate 12 is present in a groove formed in the semiconductor substrate 10. The groove can be formed by a patterning process. In one embodiment, the patterning process includes photolithography and etching. Photolithography includes forming a photoresist material on the material or material stack to be patterned (e.g., semiconductor substrate 10), exposing the photoresist material to a desired radiation pattern and developing the exposed photoresist using a conventional resist developer. The etching for transferring the pattern from the developed photoresist material to the semiconductor substrate 10 can include isotropic etching or anisotropic etching. In one embodiment, the patterning process adopts reactive ion etching (RIE). The developed resist is usually removed from the structure using a conventional resist stripping process such as ashing after the pattern transfer etching.

[0039] The trench can have a variety of shapes. In one example, the shape of the trench can be cylindrical. In some embodiments, the trench can have a depth of 100 nm to 500 nm measured from the topmost surface of semiconductor substrate 10 to the bottom wall of the trench; however, other trench depths are possible and can be used in embodiments of the present invention.

[0040] Although a single trench is described and illustrated herein, a plurality of spaced-apart trenches may be formed in the semiconductor substrate 10 , and thereafter a conductive plate 12 may be formed in each of the plurality of trenches.

[0041] Conductive plates 12 are then formed in each trench. Conductive plates 12 can be formed by a deposition process such as, for example, chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), sputtering, or electroplating. A planarization process such as chemical mechanical polishing (CMP) can be performed after depositing the conductive plate material.

[0042] In some embodiments, the conductive plate 12 may be made of a conductive metal-containing material. Examples of conductive metal-containing materials that may be used as the conductive plate 12 include, but are not limited to, copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TIN), or a copper-aluminum alloy. In some embodiments, the conductive plate 12 may be made of a superconductor. A superconductor is an element or metal alloy that significantly loses all electrical resistance when cooled below a certain threshold temperature. A superconductor can allow electric current to flow without any significant energy loss. Examples of superconductors that may be used as the conductive plate 12 include, but are not limited to, molybdenum (Mo), niobium (N), osmium (Os), rhenium (Re), rhodium (Rh), ruthenium (Ru), Nb-Ti alloy, or zirconium nitride (ZrN).

[0043] Conductive plate 12 has the same shape as the trench. In one example, conductive plate 12 is cylindrical. In some embodiments, conductive plate 12 may have a topmost surface coplanar with the topmost surface of semiconductor substrate 10. In other embodiments, conductive plate 12 has a topmost surface above or below the topmost surface of semiconductor substrate 10.

[0044] Now refer to Figure 2 , showing the semiconductor substrate 10 and the conductive plate 12 after forming a first dielectric material layer 14 on the physically exposed surfaces thereof. Figure 1 The first dielectric material layer 14 is covered Figure 1. The first dielectric material layer 14 may be composed of any dielectric material such as, for example, silicon dioxide, silicon nitride, or silicon oxynitride. In some embodiments, the first dielectric material layer 14 is composed entirely of a single dielectric material. In other embodiments, the first dielectric material layer 14 is composed of a stack of two or more dielectric materials. The first dielectric material layer 14 may be formed using a deposition process such as CVD or PECVD. The first dielectric material layer 14 may have a thickness of from 10 nm to 100 nm; although other thicknesses are possible and may be used as the thickness of the first dielectric material layer 14.

[0045] Now refer to Figure 3 , showing the via opening 16 after forming the via opening 16 through the first dielectric material layer 14 Figure 2 1 , wherein each through-hole opening 16 physically exposes the surface of the conductive plate 12. In the illustrated embodiment, a pair of through-hole openings 16 are shown as an example. Each through-hole opening 16 can be formed by photolithography and etching as defined above. After performing the pattern transfer etching, the resist used to pattern the first dielectric material layer 14 is stripped from the exemplary structure.

[0046] Now refer to Figure 4 , showing the metal-containing layer 18 after forming the metal-containing layer 18 in each via opening 16 and on the topmost surface of the first dielectric material layer 14 Figure 3 1. Metal-containing layer 18 may be composed of one of the conductive metal-containing materials mentioned above for conductive plate 12 or one of the superconductors. In one embodiment, metal-containing layer 18 is composed of a material that is compositionally the same as conductive plate 12. For example, both metal-containing layer 18 and conductive plate 12 may be composed of Cu. In another embodiment, metal-containing layer 16 is composed of a material that is compositionally different from conductive plate 12. For example, metal-containing layer 18 may be composed of Nb, and conductive plate 12 may be composed of Cu.

[0047] Metal-containing layer 18 may be formed by a deposition process including, for example, CVD, PECVD, sputtering, or electroplating. Metal-containing layer 18 has a thickness sufficient to fill each via opening 16 and extend above the topmost surface of first dielectric material layer 14.

[0048] Now refer to Figure 5 , showing the metal-containing layer 18 after patterning to provide a metal-containing wiring structure 18P on the first dielectric material layer 14 Figure 4As shown in the figure, some metal-containing wiring structures 18P include lower via portions 18V that directly contact the surface of the underlying conductive plate 12, while other metal-containing structures 18P do not include lower via portions 18V. The metal-containing wiring structures 18P that include lower via portions 18V can be referred to as first wiring structures or combined line-via wiring structures, while the metal-containing wiring structures 18P that do not include lower via portions 18V can be referred to as second wiring structures or line wiring structures.

[0049] The patterning of the metal-containing layer 18 includes photolithography and etching as defined above. Figure 5 As shown, there is a gap 19 between each metal-containing wiring structure 18P. Figure 5 As shown, each first wiring structure (18P / 18V) is positioned laterally adjacent to an area containing a second wiring structure 18P.

[0050] Now refer to Figure 6 , showing the gap filling dielectric material 20 after forming the gap 19 between each metal-containing wiring structure 18P. Figure 5 The gap-fill dielectric material 20 may include any dielectric material, including one of the dielectric materials described above for the first dielectric material layer 14. In one embodiment, the gap-fill dielectric material 20 is composed of a dielectric material that is compositionally the same as the dielectric material that provides the first dielectric material layer 14. In another embodiment, the gap-fill dielectric material 20 is composed of a dielectric material that is compositionally different from the dielectric material that provides the first dielectric material layer 14.

[0051] Gap-fill dielectric material 20 can be formed by depositing a dielectric material in each gap 19 and optionally atop each metal-containing wiring structure 18P. The dielectric material providing gap-fill dielectric material 20 can be deposited by CVD, PECVD, or PVD. In some embodiments, a planarization process (e.g., CMP) can be performed after the deposition of the dielectric material providing gap-fill dielectric material 20.

[0052] Gap-fill dielectric material 20 completely fills each gap 19 , and gap-fill dielectric material 20 generally has a topmost surface that is coplanar with a topmost surface of each metal-containing wiring structure 18P.

[0053] Now see Figure 7 , showing the precursor JJ material stack MS1 formed thereon Figure 6 In some embodiments, and as Figure 7As shown, a metal-containing capping layer 28 can be formed on the topmost surface of the precursor JJ material stack MS1. In this case, the precursor JJ material stack MS1 is not an active JJ structure. The precursor JJ material stack MS1 includes, from bottom to top, a first superconductor material layer 22, an amorphous silicon-manganese (aSi-Mn)-containing layer 24, and a second superconductor material layer 26. Although this specifically describes and illustrates aSi-Mn as layer 24, the present invention contemplates embodiments where layer 24 is an aX-M layer, where X is a semiconductor material such as Si, Ge, or SiGe, and M is a magnetic material such as Co, Ni, Fe, Mn, or any combination thereof.

[0054] The first superconductor material layer 22 may include one of the superconductor materials described above for the conductive plate 12. The first superconductor material layer 22 may be composed of a superconductor material that is compositionally the same as or different from the superconductor material that can be used as the conductive plate 12 and / or the metal-containing wiring structure 18P. The first superconductor material layer 22 may be formed by a deposition process including, for example, CVD, PECVD, sputtering, electroplating, or ALD. The first superconductor material layer 22 may have a thickness of from 5 nm to 50 nm, although other thicknesses of the first superconductor material layer 22 are contemplated and may be used as the first superconductor material layer 22.

[0055] The aSi-Mn layer 24 is composed of amorphous silicon into which manganese (Mn) has been introduced. The Mn content in the aSi-Mn layer 24 may be in the range of 15 atomic % to 60 atomic %. The aSi-Mn layer 24 may be formed by first depositing an amorphous silicon layer, and then Mn may be introduced into the amorphous silicon layer using techniques such as plasma doping or outward diffusion into the amorphous silicon layer. Alternatively, the aSi-Mn layer 24 may be formed using an in-situ deposition process. The aSi-Mn layer 24 is a thin layer having a thickness of 1 nm to 50 nm. This thickness allows electrons to transfer from the first and second superconductor materials. If there is sufficient Mn in the aSi-Mn layer 24 to produce a normal conductor, the thickness of the aSi-Mn layer 24 may be greater than the above range.

[0056] The second superconductor material layer 26 may include one of the superconductor materials described above for the conductive plate 12. The second superconductor material layer 26 may be composed of a superconductor material that is compositionally the same as or different from the superconductor material that may be used as the first superconductor material layer 22 and / or the conductive plate 12 and / or the metal-containing wiring structure 18P. The second superconductor material layer 26 may be formed by a deposition process including, for example, CVD, PECVD, sputtering, electroplating, or ALD. The thickness of the second superconductor material layer 26 may be 5 nm to 50 nm, although other thicknesses of the second superconductor material layer 26 are also contemplated and may be used as the second superconductor material layer 26.

[0057] A metal-containing capping layer 28 may optionally be formed on the precursor JJ material stack MS1. The metal-containing capping layer 28 may be composed of Ti, Ta, TiN, TaN, W, WN, or any other high-melting-point metal or conductive metal nitride. The metal-containing capping layer 28 may be composed of a single material, or it may be composed of a multilayer material stack. The metal-containing capping layer 28 may be formed by a deposition process including, for example, CVD, PECVD, sputtering, electroplating, or ALD. The metal-containing capping layer 28 may have a thickness of 5 nm to 50 nm, although other thicknesses of the metal-containing capping layer 28 are contemplated and may be used for the metal-containing capping layer 28.

[0058] Now see Figure 8 , showing the conversion of the precursor JJ material stack MS1 into the JJ material stack MS2 Figure 7 The JJ material stack MS2 is active after the conversion step. The conversion step converts the aSi-Mn layer 24 into a crystalline silicon layer 25 containing Mn nanoparticles (i.e., a crystalline silicon layer containing Mn nanoparticles dispersed therein; typically, the conversion step converts the aX-M material (wherein X is a semiconductor material, such as Si, Ge or SiGe, and M is a magnetic material, such as Co, Ni, Fe, Mn or any combination thereof) into a crystalline X layer containing M nanoparticles, where M and X are as defined above. This conversion does not change the first and second superconductor material layers 22, 26. The conversion includes a low oxygen content (i.e., 10E-7 to 10E-1 9). The annealing process can be performed at a temperature of 300°C to 500°C. The pressure during the annealing process can be from 2 Torr to 150 Torr. The annealing process is typically performed in hydrogen H2. In some embodiments, an inert environment such as helium (He), argon (Ar), or nitrogen (N2) can be used. In other embodiments, vacuum annealing can be used. The annealing process may include furnace annealing, laser annealing, or microwave annealing. The duration of annealing varies depending on the type of annealing process used. Typically, furnace annealing is performed for a longer duration than laser or microwave annealing.

[0059] In some embodiments, and if not previously formed, a metal-containing capping layer 28 as defined above may be formed on the JJ material stack MS2. Alternatively, the formation of the metal-containing capping layer 28 may be omitted from the process flow entirely.

[0060] Now see Figure 9 , showing that after the JJ material stack MS2 is patterned to form a plurality of JJ structures (labeled as JJ in the drawings) Figure 8In the exemplary structure of the embodiment, each of the plurality of JJ structures is located on a surface of a metal-containing wiring structure 18P (e.g., a second wiring structure) that does not directly contact the conductive plate 12. During the patterning of the JJ material stack MS2, the metal-containing capping layer 28, if present, is also patterned. Although a plurality of JJ structures are described and shown, the present invention functions when a single JJ structure is formed on a single second metal-containing wiring structure 18P.

[0061] Patterning includes photolithography and etching. Etching is typically anisotropic etching, such as RIE, ion beam etching, or plasma etching. Each JJ structure includes the remaining (i.e., unetched) portion of the first superconductor material layer 22 (hereinafter referred to as the first superconductor material portion 22P), the remaining (i.e., unetched) portion of the crystalline silicon layer 25 containing Mn nanoparticles (hereinafter referred to as the crystalline silicon portion 25P containing Mn nanoparticles), and the remaining (unetched) portion of the second superconductor material layer 26 (hereinafter referred to as the second superconductor material portion 26P). When the metal-containing capping layer 28 is present, the remaining (unetched) portion of the metal-containing capping layer 28 (hereinafter referred to as the metal-containing capping layer 28P) is present on top of each JJ structure.

[0062] Each JJ structure and, if present, the metal-containing cap 28P can be cylindrical in shape (although other shapes are possible) and have a CD that is typically, but not necessarily always, smaller than the underlying critical dimension (CD) of the surface of the metal-containing wiring structure 18P that does not directly contact the conductive plate 12. As shown, the individual elements (22P, 25P, 26P) of the JJ structure have outermost walls that are vertically aligned with each other. If present, the metal-containing cap 28P has an outermost wall that is vertically aligned with the outermost wall of the underlying JJ structure. As shown, the first wiring structure (18P / 18V) is laterally adjacent to the area containing the JJ structure.

[0063] Now see Figure 10 , showing the dielectric spacer 30 after forming each JJ structure Figure 9 The dielectric spacer 30 is composed of a dielectric material that is compositionally different from the gap-fill dielectric material 20. In some embodiments, the dielectric material providing the dielectric spacer 30 can provide passivation for the JJ structure.

[0064] In one embodiment, the dielectric spacer 30 is composed of silicon nitride. In another embodiment, the dielectric spacer 30 may be composed of a dielectric material containing silicon, carbon, and hydrogen atoms. In some embodiments, and in addition to carbon and hydrogen atoms, the dielectric material providing the dielectric spacer 30 may include atoms of at least one of nitrogen and oxygen. In other embodiments, in addition to silicon, nitrogen, carbon, and hydrogen atoms, the dielectric material providing the dielectric spacer 30 may include boron atoms. In one example, the dielectric spacer 30 may be composed of an nBLOK dielectric material containing atoms of silicon, carbon, hydrogen, nitrogen, and oxygen. In an alternative example, the dielectric spacer 30 may be composed of a SiBCN dielectric material containing atoms of silicon, boron, carbon, hydrogen, and nitrogen.

[0065] The dielectric spacer 30 can be formed by first depositing a continuous layer of dielectric material that provides the dielectric spacer 30. A spacer etch, such as RIE, follows the deposition of the dielectric material that provides the dielectric spacer 30. The dielectric spacer 30 can have a thickness from 10 nm to 200 nm. Other thicknesses are possible and can be used as the thickness of the dielectric spacer. The dielectric spacer 30 typically has a topmost surface that is coplanar with the topmost surface of the metal-containing cap 28P, or when the metal-containing cap 28P is not present, with the topmost surface of the JJ structure. Although the dielectric spacer 30 is shown as having an I-shape, the dielectric spacer 20 can be L-shaped and extend over the exposed surface of the metal-containing wiring structure 18P and / or the dielectric gap fill material 20.

[0066] Now see Figure 11 , shows that after forming the second dielectric material layer 32 Figure 10In an exemplary structure, the second dielectric material layer 32 is laterally adjacent to and above each dielectric spacer 30 that encapsulates the JJ structure. The second dielectric material layer 32 can be composed of one of the dielectric materials mentioned above for the first dielectric material layer 14; the dielectric material providing the second dielectric material layer 32 is typically different in composition from the dielectric material providing the dielectric spacers 30. The second dielectric material layer 32 can also be composed of an interlayer dielectric material, such as undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), a spin-on low-k dielectric layer, a chemical vapor deposition (CVD) low-k dielectric layer, or any combination thereof. As used herein, the term "low-k" refers to a dielectric material having a dielectric constant of less than 4.0; unless otherwise stated herein, all dielectric constants are measured under vacuum. In another embodiment, a self-planarizing material such as spin-on glass (SOG) or a spin-on low-k dielectric material can be used as the dielectric material for the second dielectric material layer 32. The second dielectric material layer 32 may be formed using a deposition process such as CVD, PECVD, or spin coating.

[0067] Now refer to Figure 12 , showing the second dielectric material layer 32 after forming a plurality of contact openings (34Z, 34Y) Figure 11 An exemplary structure. Multiple contact openings can be formed by photolithography and etching. Each contact opening 34Z physically exposes the surface of one of the metal-containing wiring structures 18P including the lower via portion 18V, while each contact opening 34Y physically exposes the topmost surface of one of the metal-containing caps 28P or the topmost surface of one of the second superconductor material portions 26P. Contact opening 34Z can be referred to as a wiring contact opening, while contact opening 34Y can be referred to as a JJ structure contact opening.

[0068] Now see Figure 13 , which shows the contact structure (36Y, 36Z) after forming a metal-containing contact structure (36Y, 36Z) in each contact opening (34Y, 34Z) Figure 12 . Each metal-containing contact structure (36Y, 36Z) can be composed of a contact metal or a contact metal alloy. Examples of contact metals include, but are not limited to, tungsten (W), aluminum (Al), or copper (Cu). An example of a contact metal alloy is a Cu-Al alloy. In some embodiments, a superconductor as described above can be used to provide each metal-containing contact structure (36Y, 36Z). Superconductors can be preferred materials for contact structures (36Y, 36Z) because they will reduce energy consumption and heating of the chip. As shown, each metal-containing contact structure (36Y, 36Z) has a topmost surface that is coplanar with the topmost surface of the second dielectric material layer 32.

[0069] Each metal-containing contact structure (36Y, 36Z) can be formed by filling a contact opening with a conductive material that provides the metal-containing contact structure (36Y, 36Z). In some embodiments, a planarization process can be performed after filling the contact opening with the conductive material that provides the metal-containing contact structure (36Y, 36Z).

[0070] In an embodiment of the present invention, each metal-containing contact structure 36Z contacts a surface of one of the metal-containing wiring structures 18P including the lower via portion 18V, and each metal-containing contact structure 36Y contacts the topmost surface of one of the metal-containing caps 28P or the topmost surface of one of the second superconductor material portions 26P. The metal-containing contact structures 36Z can be referred to as wiring contact structures, while each metal-containing contact structure 36Y can be referred to as a JJ contact structure.

[0071] Will first refer to Figures 14 to 21 , which shows a second method of the present invention, which can be used to provide a computing device that includes an on-chip magnetic control device located near a JJ structure. In this embodiment of the present invention, a conductive plate is embedded in a semiconductor substrate, and at least one JJ structure is formed on the surface of the conductive plate. A wiring structure is then formed laterally adjacent to the at least one JJ structure and contacts the surface of the semiconductor substrate. Next, a contact structure is formed. Some contact structures contact the wiring structure that directly contacts the semiconductor substrate, while other contact structures contact the JJ structure. In this embodiment, a wiring structure (rather than a conductive plate) is used as a magnetic control device located near the JJ structure. In this embodiment, the conductive sheet is a wiring structure of the JJ structure.

[0072] In this embodiment, the magnetic field is generated by the wiring structure rather than the conductive plate by passing current through it. The strength of the magnetic field can be modulated by the amount of current passing through the wiring structure. Furthermore, the magnetic field can be turned off as needed by stopping the current from flowing through the wiring structure.

[0073] First refer to Figure 14 , showing another exemplary structure that can be adopted according to an embodiment of the present invention. Figure 14 The exemplary structure of the present invention includes a conductive plate 52 embedded in a semiconductor substrate 50. The semiconductor substrate 50 and the conductive plate 52 used in this embodiment of the present invention are respectively the same as those used in the above-mentioned Figure 1 The semiconductor substrate 10 and the conductive plate 12 of the embodiment shown are the same. As described above, the conductive plate 52 of the present embodiment is not used to generate a magnetic field, but is used as a wiring structure of a JJ structure.

[0074] Now see Figure 15 , showing the JJ material stack MS2 formed on the semiconductor substrate 50 and the conductive plate 52 Figure 14The JJ material stack MS2 of this embodiment includes the first superconductor material layer 22 as defined above, the crystalline silicon layer 25 containing Mn nanoparticles as defined above, and the second superconductor material layer 26 as defined above. It should be noted that other crystalline semiconductor materials containing M nanoparticles as defined above can be used instead of the crystalline silicon containing Mn nanoparticles. The JJ material stack MS2 of this embodiment can be formed using the processing steps mentioned above in forming the JJ material stack (see, for example, the above description of the process steps for forming the JJ material stack). Figure 7-8 In some embodiments, the metal-containing capping layer 28 as defined above is present on the JJ material stack MS2. In other embodiments, the metal-containing capping layer 28 is not present on the JJ material stack MS2.

[0075] Now see Figure 16 , shows the JJ material stack MS2 after patterning to provide a JJ structure on the conductive plate 52 Figure 15 The patterning of the JJ material stack MS2 of this embodiment is the same as the patterning of the JJ material stack MS2 in the previous embodiment of the present invention (see Figure 9 and the above Figure 9 Each JJ structure includes a remaining (i.e., unetched) portion of the first superconductor material layer 22 (hereinafter referred to as the first superconductor material portion 22P), a remaining (i.e., unetched) portion of the Mn nanoparticle-containing crystalline silicon layer 25 (hereinafter referred to as the Mn nanoparticle-containing crystalline silicon portion 25P), and a remaining (unetched) portion of the second superconductor material layer 26 (hereinafter referred to as the second superconductor material portion 26P). When the metal-containing capping layer 28 is present, the remaining (unetched) portion of the metal-containing capping layer 28 (hereinafter referred to as the metal-containing capping layer 28P) exists on top of each JJ structure.

[0076] Each JJ structure and, if present, the metal-containing cap 28P can be cylindrical in shape (although other shapes are possible) and have a CD that is typically, but not necessarily always, less than the underlying CD of the surface of the conductive plate 52. As shown, the individual elements (22P, 25P, 26P) of the JJ structure have outermost walls that are vertically aligned with each other. If present, the metal-containing cap 28P has an outermost wall that is vertically aligned with the outermost wall of the underlying JJ structure.

[0077] Now see Figure 17 , showing the dielectric spacer 30 after forming the package JJ structure Figure 16 The dielectric spacer 30 of this embodiment is the same as the dielectric spacer 30 described above. Figure 10 Discussion.

[0078] Now see Figure 18 , showing the JJ structure after forming a first dielectric material layer 54 laterally adjacent to the dielectric spacer encapsulated JJ structure Figure 17 exemplary structure. The first dielectric material layer 54 of this embodiment of the present invention can be composed of one of the above-mentioned dielectric materials for the first dielectric material layer 14. Alternatively, the first dielectric material layer 54 of this embodiment can also be composed of an interlayer dielectric material, for example, undoped silicate glass (USG), fluorosilicate glass (FSG), borophosphosilicate glass (BPSG), a spin-on low-k dielectric layer, a chemical vapor deposition (CVD) low-k dielectric layer, or any combination thereof. The term "low-k" as used herein refers to a dielectric material having a dielectric constant of less than 4.0; unless otherwise stated herein, all dielectric constants are measured under vacuum). In another embodiment, a self-planarizing material such as spin-on glass (SOG) or a spin-on low-k dielectric material can be used as the dielectric material of the first dielectric material layer 54.

[0079] The first dielectric material layer 54 may be formed using a deposition process such as CVD, PECVD, or spin coating. A planarization process (e.g., CMP or an etch-back process) may be performed after the deposition of the dielectric material that provides the first dielectric material layer 54. The first dielectric material layer 54 has a topmost surface that is coplanar with the topmost surface of the first dielectric material layer 54, or in the case of the first dielectric material layer 54, with the topmost surface of the second superconductor material portion 26P.

[0080] Now refer to Figure 19 , showing the first dielectric material layer 54 after the opening 56 is formed Figure 18 , wherein each opening 56 physically exposes the surface of the semiconductor substrate 50. The openings 56 may be formed by photolithography and etching as defined above.

[0081] Now refer to Figure 20 , showing the metal-containing wiring structure 58 after forming each opening 56 Figure 19 Each metal-containing wiring structure 58 may include one of the conductive metals, conductive metal alloys, or superconductor materials mentioned above for the conductive plate 12. Each metal-containing wiring structure 58 may be composed of a material that is compositionally the same as or different from the material that provides the conductive plate 52. A pair of metal-containing wiring structures 58 is shown by way of example.

[0082] Each metal-containing wiring structure 58 can be formed by depositing one of a conductive metal, a conductive metal alloy, or a superconductor material using one of the deposition processes described above for forming the conductive plate 12. A planarization process (e.g., CMP) can be performed after the deposition of the material providing the metal-containing wiring structures 58. Each metal-containing wiring structure 58 has a topmost surface that is typically, but not necessarily always, coplanar with the topmost surface of the first dielectric material layer 54. As shown, the metal-containing wiring structure 58 is laterally adjacent to the region containing the JJ structure.

[0083] Now refer to Figure 21 , showing the second dielectric material layer 60 formed on the first dielectric material layer 54 Figure 20 1 , wherein the second dielectric material layer 60 includes a plurality of contact structures (62Y, 62Z) embedded therein.

[0084] The second dielectric material layer 60 of this embodiment of the present invention may include one of the dielectric materials mentioned above for the first dielectric material layer 54. The second dielectric material layer 60 may be composed of a dielectric material that is compositionally the same as or compositionally different from the dielectric material that provides the first dielectric material layer 54. The second dielectric material layer 60 may be formed using one of the deposition processes described above for forming the first dielectric material layer 54.

[0085] The plurality of contact structures (62Y, 62Z) embedded in the second dielectric material layer 60 can be formed by first providing contact openings in the second dielectric material layer 60, wherein some of these contact openings physically expose the metal-containing wiring structure 58 and other contact openings physically expose the topmost surface of the metal-containing cap 28P or, if no metal-containing cap 38P is present, the topmost surface of the second superconductor material portion 28P of the JJ structure. The contact openings can be formed by photolithography and etching.

[0086] Each metal-containing contact structure (62Y, 62Z) can be composed of a contact metal or a contact metal alloy. Examples of contact metals include, but are not limited to, tungsten (W), aluminum (Al), or copper (Cu). An example of a contact metal alloy is a Cu-Al alloy. In some embodiments, a superconductor as defined above can be used to provide each metal-containing contact structure. Superconductors can be preferred materials for contact structures (62Y, 62Z) because they will reduce energy consumption and heating of the chip. As shown, each metal-containing contact structure (62Y, 62Z) has a topmost surface that is coplanar with the topmost surface of the second dielectric material layer 60.

[0087] Each metal-containing contact structure (62Y, 62Z) can be formed by filling the contact openings with a conductive material that provides the metal-containing contact structures (62Y, 62Z). In some embodiments, a planarization process can be performed after filling the contact openings with the conductive material that provides the metal-containing contact structures (62Y, 62Z).

[0088] In an embodiment of the present invention, each metal-containing contact structure 62Z contacts a surface of one of the metal-containing structures 58, and each metal-containing contact structure 62Y contacts the topmost surface of one of the metal-containing caps 28P or the topmost surface of one of the second superconductor material portions 26P. The metal-containing contact structures 62Z can be referred to as wiring contact structures, while each metal-containing contact structure 62Y can be referred to as a JJ contact structure.

[0089] Although the present invention has been particularly shown and described with respect to its preferred embodiments, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made without departing from the scope of the invention. It is therefore intended that the present invention not be limited to the exact forms and details described and shown, but fall within the scope of the appended claims.

[0090] In a preferred embodiment of the present invention, a method for forming a computing device is provided, the method comprising: forming a conductive plate in a semiconductor substrate; forming at least one Josephson junction (JJ) structure on the conductive plate; forming a first dielectric material layer laterally adjacent to the at least one JJ structure, wherein the first dielectric material layer includes a wiring structure embedded therein, the wiring structure contacting the semiconductor substrate; and forming a second dielectric material layer over the first dielectric material layer and over the at least one JJ structure, wherein the second dielectric material layer includes a wiring contact structure and a JJ contact structure embedded therein, wherein the wiring contact structure contacts the wiring structure, and the JJ contact structure contacts the JJ structure. Preferably, forming the JJ structure comprises: forming a precursor JJ material stack comprising a first superconductor material layer, a manganese layer comprising amorphous silicon, and a second superconductor material layer; converting the precursor JJ material stack into a JJ material stack, wherein the converting comprises annealing, which changes the manganese layer comprising amorphous silicon into a crystalline silicon layer comprising Mn nanoparticles; and patterning the JJ material stack. The method preferably further includes: before forming the second dielectric material layer, forming a dielectric spacer, wherein the dielectric spacer encapsulates the JJ structure.

Claims

1. A computing device comprising: a conductive plate positioned in a trench formed in a semiconductor substrate, wherein at least a sidewall of the conductive plate forms an interface with laterally adjacent semiconductor material of the semiconductor substrate; at least one Josephson junction (JJ) structure located above the conductive plate; and A first wiring structure is located laterally adjacent to the at least one JJ structure, wherein one of the conductive plate or the first wiring structure is configured to induce a magnetic field into the at least one JJ structure when current is applied to the at least one JJ structure.

2. The computing device of claim 1, wherein: The first wiring structure directly contacts a surface of the conductive plate, the at least one JJ structure is spaced apart from the conductive plate, and the conductive plate induces the magnetic field to the at least one JJ structure.

3. The computing device of claim 2, wherein: The at least one JJ structure is located on a surface of a second wiring structure that is laterally spaced apart from the first wiring structure and vertically spaced apart from the conductive plate. The computing device according to claim 3 , wherein: The at least one JJ structure has a critical dimension that is smaller than a critical dimension of the second wiring structure. 5 . The computing device of claim 3 , further comprising a wiring contact structure contacting each of the first wiring structures and a JJ contact structure contacting the at least one JJ structure. The computing device according to claim 1 , wherein: The first wiring structure directly contacts a surface of the semiconductor substrate, the at least one JJ structure is located on a surface of the conductive plate, and the first wiring structure senses the magnetic field. 7 . The computing device of claim 6 , further comprising a wiring contact structure contacting each of the first wiring structures and a JJ contact structure contacting the at least one JJ structure.

8. The computing device of claim 1 , wherein: The conductive plate is made of conductive metal, conductive metal alloy or superconductor material.

9. The computing device of claim 1 , wherein: The first wiring structure is made of conductive metal, conductive metal alloy or superconductor material.

10. The computing device of claim 1, further comprising a dielectric spacer encapsulating the at least one JJ structure.

11. The computing device of claim 1 , wherein: The at least one JJ structure includes a first superconductor material portion, a crystalline silicon portion containing Mn nanoparticles, and a second superconductor material portion.

12. The computing device of claim 11, further comprising a metal-containing cap located on the second superconductor material portion of the at least one JJ structure.

13. The computing device of claim 1, wherein: The at least one JJ structure is cylindrical in shape.

14. A method of forming a computing device, the method comprising: forming a conductive plate in a semiconductor substrate; forming a first dielectric material layer on the physically exposed surface of the semiconductor substrate and the conductive plate, wherein the first dielectric material layer includes a via opening that physically exposes the surface of the conductive plate; forming a metal-containing layer in each of the via openings and on a topmost surface of the first layer of dielectric material; patterning the metal-containing layer to provide first and second metal-containing wiring structures, wherein the first metal-containing wiring structure contacts the conductive plate and the second metal-containing wiring structure is spaced apart from the conductive plate; forming a Josephson junction (JJ) structure on each second metal-containing wiring structure; as well as A second dielectric material layer is formed laterally adjacent to and above each JJ structure, wherein the second dielectric material layer includes a wiring contact structure and a JJ contact structure embedded therein, and wherein the wiring contact structure contacts the first metal-containing wiring structure, and the JJ contact structure contacts the JJ structure.

15. The method according to claim 14, wherein The forming of the JJ structure comprises: forming a precursor JJ material stack comprising a first superconductor material layer, a manganese layer containing amorphous silicon, and a second superconductor material layer; converting the precursor JJ material stack into a JJ material stack, wherein the converting includes annealing that changes the manganese layer containing amorphous silicon into a crystalline silicon layer containing Mn nanoparticles; and The JJ material stack is patterned. 16 . The method according to claim 14 , further comprising forming a dielectric spacer encapsulating the JJ structure before forming the second dielectric material layer. 17 . The method of claim 14 , further comprising forming a gap-fill dielectric material in a gap between each of the first and second wiring structures.

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