Nanosecond non-destructive readout random access memory

Abstract

An erasable magnetoresistive random access memory (MRAM) structure and method of manufacturing the same includes an MRAM cell disposed between a bit line circuit element and a word line circuit element, and a vertical cavity surface emitting laser (VCSEL) element disposed above the MRAM cell. Laser output of the VCSEL is directed toward the MRAM cell.

Description

Background Technology

[0001] This invention generally relates to nondestructive erasable magnetoresistive random access memory (MRAM). In particular, this invention relates to nanosecond nondestructive erasable MRAM structures including vertical-cavity surface-emitting laser elements.

[0002] Computing hardware and software systems are vulnerable to various external attacks. Attacks can be carried out using software or by directly targeting the system hardware. Hardware security uses physical components installed on the computer system's hardware to protect it from attacks. Hardware security can be more robust than software security and can add an additional layer of security for critical systems. Hardware security measures are often destructive in nature; attacks are prevented, but the hardware is compromised. Therefore, the system is protected, but some or all of it may become unusable.

[0003] MRAM is a type of solid-state non-volatile memory that uses tunnel magnetoresistive (TMR) to store information. MRAM consists of an array of electrically connected magnetoresistive memory elements, called a magnetic tunnel junction (MTJ). Each MTJ comprises a free layer and a fixed layer, each consisting of a layer of magnetic material separated by a non-magnetic insulating tunnel barrier. The free layer has a variable magnetization direction, while the fixed layer has a constant magnetization direction. MTJs store information by switching the magnetization state of the free layer. When the magnetization direction of the free layer is parallel to that of the fixed layer, the MTJ is in a low-resistance state. Conversely, when the magnetization direction of the free layer is antiparallel to that of the fixed layer, the MTJ is in a high-resistance state. The difference in resistance between the MTJs can be used to indicate a logic "1" or "0," thus storing one bit of information. The TMR of the MTJ determines the resistance difference between the high-resistance and low-resistance states. The relatively high difference between the high-resistance and low-resistance states facilitates read operations in the MRAM. MRAM cells can be thermally activated—raising the temperature of the cell above an activation threshold, even without an activation magnetic field, will change the state of the stored data.

[0004] A vertical-cavity surface-emitting laser (VCSEL) is a type of semiconductor laser diode that emits energy from the surface of the diode. A VCSEL consists of two opposing mirrors parallel to the wafer surface, with one or more quantum wells disposed between the mirrors. Summary of the Invention

[0005] The following overview provides a basic understanding of one or more embodiments of the invention. This overview is not intended to identify key or essential elements or to depict any scope of a particular embodiment or any scope of the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that follows. In one or more embodiments described herein, devices, systems, computer-implemented methods, apparatuses, and / or computer program products enable the streamlining of compliance reporting and remediation / override by clustering system servers according to compliance protocol deviations.

[0006] In one aspect, the present invention includes a nondestructive erasable magnetoresistive random access memory (MRAM) structure comprising an MRAM cell disposed between bit line circuit elements and word line circuit elements, and a vertical cavity surface emitting laser (VCSEL) element disposed above the MRAM cell; the laser output of the VCSEL is directed toward the MRAM cell.

[0007] In one aspect, the present invention includes a method of manufacturing a semiconductor device, comprising manufacturing a plurality of magnetoresistive random access memory (MRAM) cells electrically connected to one or more bit lines and word lines, the plurality of MRAM cells being encapsulated in a dielectric material, forming a grain filter cavity in the dielectric material, forming an oriented seed crystal in the grain filter, forming an amorphous semiconductor layer adjacent to the seed crystal, crystallizing the amorphous semiconductor layer, forming a vertical cavity surface emitting laser (VCSEL) adjacent to the semiconductor layer, removing the semiconductor layer, and forming a dielectric layer on and around the VCSEL. Attached Figure Description

[0008] The above and other objects, features and advantages of the invention will become more apparent from the more detailed description of some embodiments thereof in the accompanying drawings, wherein like reference numerals generally denote like components in the embodiments of the invention.

[0009] Figure 1 This is a cross-sectional view of a step in the fabrication of a semiconductor device according to an embodiment of the present invention, showing an array of formed MRAM cells electrically connected to bit lines and word lines and surrounded by a dielectric layer.

[0010] Figure 2 This is a cross-sectional view of the steps in the fabrication of the device, showing the deposition of an etched crystal seed cavity filled with (100) oriented Ge and a layer of amorphous Ge.

[0011] Figure 3 This is a cross-sectional view of the steps in the fabrication of the device, showing the device after amorphous Ge has been crystallized by laser annealing.

[0012] Figure 4 This is a cross-sectional view of the steps in the device fabrication process, showing the device after adding VCSEL layer stacks.

[0013] Figure 5 This is a cross-sectional view of the steps in the fabrication of the device, showing the device after patterning of the VCSEL stack, removal of crystalline Ge, and deposition of dielectric material around the VCSEL stack.

[0014] Figure 6 This is a flowchart depicting the operational steps for forming a semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0015] Some embodiments will be described in more detail with reference to the accompanying drawings, in which embodiments of the invention have been illustrated. However, the invention can be implemented in various ways and should not be construed as limited to the embodiments disclosed herein.

[0016] It should be understood that aspects of the invention will be described in accordance with the given illustrative framework; however, other frameworks, substrate materials, and process features and steps may be modified within the scope of the aspects of the invention.

[0017] It should also be understood that when a component, such as a layer, region, or substrate, is referred to as being "on" or "above" another component, it may be directly on the other component, or there may be intermediate components. Conversely, when a component is referred to as being "directly on" or "directly above" another component, there are no intermediate components. It will also be understood that when a component is referred to as being "connected" or "coupled" to another component, it may be directly connected or coupled to the other component, or there may be intermediate components. Conversely, when a component is referred to as being "directly connected" or "directly coupled" to another component, there are no intermediate components.

[0018] This embodiment may include the design of an integrated circuit chip, which may be created in a graphical computer programming language and stored in a computer storage medium (such as a disk, magnetic tape, physical hard disk drive, or virtual hard disk drive in a storage access network). If the designer does not manufacture the chip or the photomask used to manufacture the chip, the designer may transfer the obtained design directly or indirectly to such an entity by physical means (e.g., by providing a copy of the storage medium containing the design) or electronically (e.g., via the Internet). The stored design is then converted into a suitable format (e.g., GDSII) for manufacturing the photomask, which typically includes multiple copies of the chip design in question to be formed on a wafer. The photomask is used to define areas of the wafer (and / or layers on it) to be etched or otherwise processed.

[0019] The methods described herein can be used in the manufacture of integrated circuit chips. Manufacturers can distribute the resulting integrated circuit chips in the form of raw wafers (i.e., as a single wafer with multiple unpackaged chips), as bare chips, or in packages. In the latter case, the chips are mounted in a single-chip package (such as a plastic carrier with leads that are attached to a motherboard or other more advanced carrier) or a multi-chip package (such as a ceramic carrier with either surface-mount or buried interconnects, or both). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of: (a) an intermediate product (such as a motherboard) or (b) a final product. The final product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0020] It should also be understood that material compounds will be described according to the listed elements, such as SiGe. These compounds include elements in different proportions within the compound; for example, SiGe includes SixGe1-x, where x is less than or equal to 1, etc. Furthermore, other elements may be included in the compound and will still function according to this principle. Compounds with additional elements will be referred to herein as alloys.

[0021] References to "one embodiment" or "embodiment" and other variations in the specification mean that a particular feature, structure, characteristic, etc., described in connection with that embodiment is included in at least one embodiment. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing in various places throughout the specification, as well as any other variations, do not necessarily refer to the same embodiment.

[0022] It should be understood that, for example, in the cases of “A / B,” “A and / or B,” and “at least one of A and B,” the use of any of the following “ / ,” “and / or,” and “at least one of” is intended to cover the selection of only the first listed option (A), or only the selection of only the second listed option (B), or the selection of both options (A and B). As a further example, in the cases of “A, B, and / or C” and “at least one of A, B, and C,” such wording is intended to include selecting only the first listed option (A), or only the second listed option (B), or only the third listed option (C), or only the first and second listed options (A and B), or only the first and third listed options (A and C), or only the second and third listed options (B and C), or all three options (A, B, and C). This can be extended to many of the listed items, as will be apparent to those skilled in the art and related fields.

[0023] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit exemplary embodiments. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the terms “comprising,” “including,” and / or “containing” as used herein specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0024] For ease of description, this document may use spatially relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or feature and another element or feature, as shown in the figures. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation, other than those shown in the figures. For example, if the device in the figures is flipped, an element described as being “below” or “under” other elements or features would be oriented “above” other elements or features. Therefore, the term “below” can include both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other directions), and the spatially relative descriptions used herein may be interpreted accordingly. Furthermore, it should be understood that when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more intermediate layers.

[0025] It should be understood that although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the scope of this concept, the first element discussed below may be referred to as the second element.

[0026] In one embodiment, the semiconductor device includes a magnetoresistive random access memory (MRAM) array and a vertical-cavity surface-emitting laser (VCSEL) disposed above the MRAM array. In this embodiment, the device activates the VCSEL when a hardware attack is detected. In this embodiment, the hardware attack can be identified by system elements external to the MRAM device, including both hardware and software elements. In this embodiment, the device read circuitry is configured to identify the hardware attack based on user-specified criteria and initiate a non-destructive VCSEL memory erase accordingly.

[0027] Activation of the VCSEL provides localized heating of the MRAM cells, randomly altering the cell state and effectively erasing the data held in the array. No data will remain in the MRAM in the event of a vulnerability exploited for reading. The erasure is non-destructive because the functionality of the MRAM is not diminished even after the contents of the MRAM cell have been erased. After the MRAM VCSEL heating and accompanying data erasure have occurred, the system can write new data to the MRAM. In this embodiment, all MRAM cells can be heated. Changing at least half of the bits is sufficient to prevent the reconstruction of the erased data.

[0028] In one embodiment, the device includes write circuitry and uses capacitors positioned in line with the word lines and / or bit lines of the MRAM array to write "1" to all bits. In this embodiment, the system writes bits while the device is still hot, and lowers the energy barrier for writing in each MRAM cell.

[0029] In one embodiment, the device includes a destructive erasure component. In this embodiment, a large capacitor is connected to the MRAM array and configured to overcharge the magnetic tunnel junction of the MRAM cells when the VCSEL ceases operation, thereby effectively erasing the MRAM contents and destroying the device.

[0030] The following is a simplified description of the formation of an MRAM memory cell element array. Figure 1 A device 100 according to an embodiment of the present invention is shown after the fabrication of an MRAM array has been completed. Bit lines 120 are disposed on a semiconductor substrate 110. In an embodiment, bit lines 120 are formed by depositing a conductive material (not shown) on the semiconductor substrate 110. In this embodiment, the conductive material includes elemental conductors such as copper, silver, or gold. Bit lines 120 are then formed by selectively removing portions of the conductive material layer, for example, through photolithographic patterning and etching processes that remove exposed portions of the conductive material layer and form bit lines 120. This etching can be performed using timed anisotropic etching such as reactive ion etching (RIE). Etching can be performed in a single etch that removes the conductive material layer forming the bit lines 120.

[0031] After patterning and removing portions of the conductive material layer forming the bit lines 120, the gaps between the remaining bit lines 120 are filled with a dielectric material 150 (e.g., alumina, silicon oxide, or a similar dielectric material). In an embodiment, a chemical mechanical planarization process may be used to ensure that the upper surface of the dielectric material 150 and the conductive material forming the bit lines 120 are planar, in preparation for the next step in device fabrication.

[0032] A series of layers are deposited on dielectric material 150 and bit line 120 to form a magnetic tunnel junction (MTJ) stack for MRAM cells. In an embodiment, the MTJ stack includes a simplified depiction of an MTJ 130 made of a bottom contact, a free magnetic layer (a layer with switchable magnetic dipole moments), a tunnel barrier layer, and a fixed magnetic layer (a layer with fixed magnetic dipole moments). In this embodiment, the MTJ 130 includes a seed layer (not shown) on which the free layer is grown. In some embodiments, the seed layer may include, for example, tantalum (Ta) or tantalum magnesium (TaMg). The free layer may include, for example, cobalt-iron-boron (CoFeB). Next, a tunnel barrier (not shown) is formed on the free layer. The tunnel barrier may include a non-magnetic insulating material, such as magnesium oxide (MgO). After the tunnel barrier is formed, a fixed layer (not shown) is formed on top of the tunnel barrier. In various embodiments, the fixed layer may include, for example, one or more interface layers or spacers in the form of multiple layers or mixtures, and cobalt-platinum (Co|Pt) or cobalt-palladium (Co|Pd). The individual layers may be formed by radio frequency sputtering. The free layer and the fixed layer have vertical magnetic anisotropy.

[0033] In this embodiment, the final MRAM MTJ stack cell is formed using the patterning and etching processes described above. A dielectric material is deposited around the MRAM MTJ stack, and a CMP process is used to provide a flat surface for the next step, namely the formation of word lines 140. In this embodiment, word lines 140 are formed by depositing layers of conductive material, selectively etching the material, and depositing a dielectric material similar to dielectric material 150 on the etched structure.

[0034] Now for reference Figure 2A grain filter seed cavity 210 (hereinafter referred to as "seed cavity") is formed in the dielectric material 150. In an embodiment, the seed cavity 210 is formed using the patterning and etching techniques described above. In this embodiment, the seed cavity 210 has a depth of about 300 nm to about 500 nm and a width of about 100 nm to about 200 nm. In an embodiment, Ge is deposited in the seed cavity 210, and a crystalline (100) Ge seed is formed using metal-induced lateral crystallization (MILC). As shown, an amorphous Ge layer 220 has been deposited on the dielectric material 150 and the filled seed cavity 210. The amorphous Ge layer 220 can be formed on the dielectric material 150 by any suitable deposition process. For example, alternating layers can be formed by alternating deposition processes, including, for example, chemical vapor deposition (C), physical vapor deposition (PVD), atomic layer deposition (ALD), or gas cluster ion beam (GCIB) deposition. CVD is a deposition process in which the deposited material is formed by a chemical reaction between gaseous reactants at temperatures above room temperature (e.g., from about 25°C to about 900°C). The solid products of the reaction are deposited on the surface of the material to form a film, coating, or layer. Variations of CVD processes include, but are not limited to, atmospheric pressure CVD (APCVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), and metal-organic CVD (MOCVD), and combinations thereof may also be used. In alternative embodiments using PVD, the sputtering apparatus may include a DC diode system, radio frequency sputtering, magnetron sputtering, or ionized metal plasma sputtering. In alternative embodiments using ALD, chemical precursors react with the surface of the material one at a time to deposit a thin film on the surface.

[0035] Now refer to Figure 3 An amorphous Ge layer 220 was annealed using an excimer laser and a μ-Czochralski process to grow a layer of crystalline Ge from a (100)Ge seed crystal. During the annealing process, the amorphous Ge layer was excited and cooled. During this process, the amorphous Ge crystallized. The lattice of this layer grew from a (100)Ge seed crystal cavity 200. After this process, the Ge in the seed crystal cavity and the Ge of the previous amorphous Ge layer had a consistent (100) lattice.

[0036] Now refer to Figure 4A VCSEL stack 410 comprising multiple GaAs substrates is epitaxially grown on a crystalline Ge layer 220. In an embodiment, the thickness of the VCSEL stack 410 is between about 3 and about 6 micrometers (μm). In this embodiment, the length and width of the VCSEL stack 410 are such that the stack covers one or more MRAM cell structures, and one or more VCSEL stack elements cover all MRAM cell structures in the MRAM array of the device.

[0037] The terms "epitaxygian growth and / or deposition" and "epitaxically grown and / or deposited" refer to the growth of a semiconductor material on a deposition surface of a semiconductor material, wherein the grown semiconductor material has the same crystallinity as the semiconductor material on the deposition surface. In the epitaxial deposition process, the chemical reactants provided by the source gas are controlled, and the system parameters are set such that the deposited atoms reach the deposition surface of the semiconductor substrate with sufficient energy to move around on the surface and orient themselves toward the crystal arrangement of the atoms on the deposition surface. Therefore, the epitaxial semiconductor material has the same crystallinity as the deposition surface on which the epitaxial semiconductor material is formed.

[0038] In this embodiment, the VCSEL stack 410 includes a lower Bragg mirror 412 made of alternating layers of aluminum gallium arsenide (AlGaAs) and gallium arsenide (GaAs), a lower confinement layer of AlGaAs, one or more quantum well layers 414 comprising indium gallium arsenide (InGaAs) or indium arsenide (InAs), one or more quantum well barrier layers of GaAs, an upper confinement layer of AlGaAs, and an upper Bragg mirror 416 with alternating AlGaAs and GaAs layers. In this embodiment, the reflectivity of the upper Bragg mirror 416 is greater than that of the lower Bragg mirror 412, causing the output of the completed VCSEL to be guided down to the MRAM cell.

[0039] Now refer to Figure 5 In the embodiment, VCSEL stack 410 and crystalline Ge layer 220 ( Figure 4 Then, using the etching method described above, the VCSEL stack 410 is patterned and shaped, leaving the final shape on the crystalline Ge 220. Figure 4 In this embodiment, etching creates an array of VCSEL stacks 410 disposed above the MRAM cells of the device. Etching removes material between the VCSEL stacks 410 array elements, including portions of the crystalline Ge layer disposed between the VCSEL stacks 410 array elements. Stack anchors (not shown), such as lines of dielectric material, are disposed adjacent to the VCSEL stacks 410 element array. The stack anchors are positioned to contact the patterned VCSEL stacks 410 and the dielectric material 150, while simultaneously causing the VCSEL stacks 410 (… Figure 4The underlying crystalline Ge 220 is partially exposed. In an embodiment, a stack anchor is set using known mask and dielectric material deposition methods as described above. The crystalline Ge 220 is then removed and replaced. In an embodiment, the crystalline Ge 220 is etched away using H2O2 and replaced with a flowable dielectric material (FOX) or other suitable dielectric material 510.

[0040] Now for reference Figure 6 The figure provides a flowchart 600 illustrating operational steps for forming a semiconductor device according to an embodiment of the present invention. In step 610, an array of MRAM cells including appropriate bit lines and word lines is formed. The formed MRAM array is encased in a dielectric material layer.

[0041] At 620, a (100) oriented Ge seed is formed in a cavity within a dielectric layer surrounding the MRAM array. After the seed is formed, an amorphous Ge layer is deposited on the dielectric layer. At 630, the amorphous Ge is annealed, and a Ge lattice grows from the (100) Ge seed. Other orientations for the seed layer and the grown crystalline layer are also possible.

[0042] At 640, the VCSEL layer is grown on a crystalline Ge layer. This layer includes the bottom Bragg mirror, quantum well, and top Bragg mirror of the CSEL structure. Side anchors are grown adjacent to the VCSEL stack, and the crystalline Ge layer is etched away from beneath the stack. The VCSEL stack is patterned and etched to the desired size and shape. After patterning and etching, a dielectric layer is deposited beneath and around the VCSEL element.

[0043] The device is constructed using appropriate contacts of the bit lines, word lines, and VCSEL quantum well activation points. In one embodiment, capacitors are added to enable the writing of "1" or "0" values ​​to all MRAM bits after an attack and defense have occurred. In another embodiment, the capacitors are large enough to destroy the MRAM structure in the event of a VCSEL failure.

[0044] References to "an embodiment," "an embodiment," "an exemplary embodiment," etc., in this specification indicate that the described embodiment may include a particular feature, structure, or characteristic, but each embodiment may not necessarily include that particular feature, structure, or characteristic. Furthermore, these phrases do not necessarily refer to the same embodiment. Additionally, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is believed that incorporating other embodiments to affect that feature, structure, or characteristic is within the knowledge of those skilled in the art, regardless of whether it is explicitly described.

[0045] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the terms “comprising” and / or “including” as used in this specification specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0046] Various embodiments of the invention have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the invention. The terminology used herein is chosen to best explain the principles of the embodiments, their practical application, or improvements to existing technologies on the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A magnetoresistive random access memory (MRAM) structure, comprising: At least one MRAM cell is disposed between the bit line circuit element and the word line circuit element; as well as A vertical-cavity surface-emitting laser (VCSEL) element is disposed above the MRAM cell or each MRAM cell, wherein the laser output of the VCSEL is directed toward the MRAM cell or each MRAM cell. In this embodiment, at least one MRAM cell is encapsulated in a first dielectric material, the VCSEL element is encapsulated in a second dielectric material, and the second dielectric material is deposited on the first dielectric material.

2. The MRAM structure according to claim 1, comprising a plurality of MRAM cells disposed between bit line circuit elements and word line circuit elements; wherein the VCSEL element is disposed above the plurality of MRAM cells and is guided toward the plurality of MRAM cells.

3. The MRAM structure according to claim 1 or claim 2 further includes a capacitor connected to at least one word line circuit element.

4. The MRAM structure according to claim 1 or claim 2, wherein the VCSEL comprises a gallium arsenide layer.

5. The MRAM structure according to claim 1 or claim 2, wherein the MRAM cell or each MRAM cell comprises a magnetic tunnel junction.

6. The MRAM structure according to claim 1 or claim 2 further includes a capacitor, the size of which is configured to destructively erase the MRAM contents.

7. The MRAM structure according to claim 1 or claim 2, wherein at least one of the bit line circuit elements and the word line circuit elements comprises a conductive material.

8. The MRAM structure according to claim 1 or claim 2, wherein the VCSEL comprises a lower Bragg mirror, an upper Bragg mirror, and a quantum well disposed between the lower Bragg mirror and the upper Bragg mirror.

9. A method for manufacturing a semiconductor device, the method comprising: A plurality of magnetoresistive random access memory (MRAM) cells electrically connected to one or more bit lines and word lines are manufactured, the plurality of MRAM cells being encapsulated in a dielectric material; A grain filter cavity is formed in the dielectric material; Oriented seed crystals are formed in the grain filter; An amorphous semiconductor layer is formed adjacent to the seed crystal; Crystallize the amorphous semiconductor layer; A vertical cavity surface-emitting laser (VCSEL) is formed adjacent to the semiconductor layer; Remove the semiconductor layer; as well as A dielectric layer is formed on and around the VCSEL.

10. The method of claim 9, further comprising forming a capacitor electrically connected to at least one of the bit line and the word line.

11. The method of claim 9, wherein the VCSEL comprises a gallium arsenide layer.

12. The method of claim 9, wherein the MRAM cell comprises a magnetic tunnel junction.

13. The method of claim 9, wherein at least one of the bit line and the word line comprises a conductive material.

14. The method of claim 9, wherein the VCSEL comprises a lower Bragg mirror, an upper Bragg mirror, and a quantum well disposed between the lower Bragg mirror and the upper Bragg mirror.

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