Multichannel multiplexer

Abstract

A circuit (400) includes a first switching component (111) having a first input node and a first output node, and a second switching component (112) having a second input node and a second output node. The circuit further includes a third switching component (430), an operational amplifier (130), and a buffer (410). The third switching component (430) has a third input node and a third output node. The third input node is coupled to the second output node, and the third output node is coupled to the first output node. The buffer (410) has a buffer input and a buffer output. The buffer input is coupled to an input stage of the operational amplifier (130). The buffer output is coupled to the third switching component (430).

Description

BACKGROUND

[0001] Some applications include a sensor processing system and a multiplexer. One or more sensors can be coupled to the multiplexer. The sensors are coupled to the processing system through the multiplexer. The multiplexer includes a plurality of channels, each of which can be coupled to a separate sensor. The processing system processes signals from one sensor at a time. To receive and process signals from a given sensor coupled to one of the channels, a control signal to the multiplexer enables the channel corresponding to the desired sensor while disabling the remaining channels of the multiplexer. SUMMARY

[0002] In one example, a circuit includes a first switching component, a second switching component, and a third switching component, a buffer, and a bulk bias circuit. The first switching component has a first input node and a first output node. The second switching component has a second input node and a second output node. The third switching component has a third input node and a third output node. The third input node is coupled to the second output node. The third output node is coupled to the first output node. The third switching component includes a first transistor that includes a bulk. The buffer has a buffer input and a buffer output. The buffer input is coupled to the first output node, and the buffer output is coupled to the third switching component. The bulk bias circuit is coupled to the bulk of the first transistor. The bulk bias circuit is configured to bias the bulk of the first transistor at a first bias voltage in response to a voltage on the input node being above a first voltage level, and to bias the bulk of the first transistor at a second bias voltage in response to a voltage on the input node being below a second voltage level. BRIEF DESCRIPTION OF DRAWINGS

[0003] For a detailed description of various examples, reference will now be made to the accompanying drawings in which:

[0004] Figure 1 An example of a multi-channel system is illustrated.

[0005] Figure 2 An example implementation of a switch included in a multi-channel system is shown.

[0006] Figure 3 Another example of a multi-channel system is illustrated that includes a buffer for reducing leakage current through an off channel.

[0007] Figure 4 Another example of a multi-channel system is illustrated that includes a buffer for reducing leakage current through an off channel.

[0008] Figure 5 An example implementation of a buffer is shown.

[0009] Figure 6 An example of a circuit is shown that includes a portion of a multi-channel system and includes a buffer and a bulk bias circuit to reduce leakage current through an off channel. DETAILED DESCRIPTION

[0010] A multiplexer can include multiple independent channels that pass data from respective inputs to a single output, and in a sensing application, the multiplexer can pass data from a set of sensors coupled to the inputs to a processor coupled to the output. Control signals from a multiplexer controller enable one of the channels, while those corresponding to sensors not intended to be processed by the sensor processing system at a given point in time are disabled. Each channel of the multiplexer includes a solid state switch (transistor) for enabling and disabling the channel. When the transistor is "on," current can conduct through the transistor. When the transistor is "off," the primary conductive pathway (e.g., the channel in a metal oxide semiconductor field effect transistor) is off and generally does not conduct current. However, when the transistor is off, leakage current can conduct through the transistor.

[0011] In many applications, transistor leakage current is not a problem. However, in other applications, leakage current can be a problem. For example, in the application noted above, multiple sensors are coupled to a processing system through a multiplexer, and leakage current can flow through the transistor of a channel of the multiplexer even when the transistor is off for a disabled channel. If the sensor connected to the channel has a large output impedance, then even a small amount of leakage current can result in a large voltage across the sensor due to the large output impedance of the sensor. The voltage undesirably generated in the disabled channel can modify (e.g., add to) the voltage generated by the sensor enabled by the channel, thereby undesirably altering the sensor signal intended to be processed.

[0012] Examples described herein are directed to a multiplexer in which each channel of the multiplexer includes multiple metal oxide semiconductor field effect transistors (MOS transistors). One or more of the channels of the multiplexer bias a bulk of at least one of its MOS transistors to reduce leakage current that otherwise can occur from a low amplitude voltage generated by a sensor on an enabled channel. In addition, a buffer is provided, an input of the buffer coupled to an output of the multiplexer. An output of the buffer is coupled to one or more of the channels of the multiplexer. When a given channel is off, rather than grounding the internal node of the given channel, the internal node is coupled via the buffer to the output voltage level of the multiplexer. Thus, the drain to source potential difference across the MOS transistors in each "off" channel is approximately 0 V, and thus very little if any leakage current will flow between the drain and source of the transistor if any exists.

[0013] Figure 1An example of a system 100 including multiplexer ("mux") circuit 110 coupled to an operational amplifier ("op amp") 130 is shown. The multiplexer circuit 110 includes multiple channels. In this example, the multiplexer circuit 110 includes five channels shown at 101, 102, 103, 104, and 105. Each channel is coupled to a respective input, and the inputs of channels 101-105 are designated inp 1, inp 2, inp 3, inp 4, and inp 5, respectively. A device such as a sensor can be connected to each channel input. In this example, five sensors (S1, S2, S3, S4, S5) can be coupled to the operational amplifier 130 through the multiplexer circuit 110. Via control signals from a multiplexer controller 140 (in response to channel selection signals 139) to the multiplexer circuit 110, one channel at a time is enabled (turned on), while the remaining four channels are disabled (turned off). The signal from the sensor whose channel is enabled is provided through the multiplexer circuit 110 to node N1, and thus to the non-inverting (+) input of the operational amplifier 130. The output of the operational amplifier 130 is connected to its inverting (-) input, so the operational amplifier 130 is configured for unity gain. Other configurations of the operational amplifier (e.g., gain greater than 1) are also possible. The output of the operational amplifier 130 is coupled to a processing system 150 to process the output signal of the operational amplifier. The processing system 150 can include a microprocessor, a filter, or other type of processing electronics.

[0014] The multiplexer circuit 110 includes a switch assembly for each channel. Channel 101 has switch assembly 111, and channels 102-105 have switch assemblies 112-115, respectively. When switch assembly 111 is "on," input inp 1 can be coupled to node N1. Similarly, any of inputs inp 2 - inp 5 can be coupled to node N1 when their respective switch assemblies 111-115 are on. Node N1 is connected to the non-inverting input of the operational amplifier. In this example, only one of switch assemblies 111-115 is on at a time, while the remaining switch assemblies are off.

[0015] In Figure 1In the example, each switching assembly 111-115 includes three switches S1, S2, and S3. S1 and S2 are connected in series between their associated channel input and node N1. The multiplexer controller 140 generates control signals to switches S1-S3 of the switching assemblies 111-115 to turn each corresponding switch on or off. The node between S1 and S2 is designated as node N2. S3 of each switching assembly is coupled between node N2 and ground. When S3 is on, the corresponding node N2 is coupled to ground potential. To turn on a switching assembly and thus enable the channel, its switches S1 and S2 are turned on and its switch S3 is turned off. To turn off a switching assembly and thus disable the channel, its switches S1 and S2 are turned off and its switch S3 is turned on. Figure 1 As shown in the example, switches S1 and S2 of switch assembly 111 are turned on, and the corresponding switch S3 is turned off. The remaining four switch assemblies 112-115 have switches S1 and S2 turned off, while their switches S3 are turned on. Therefore, in this example, channel 101 is enabled, while channels 102-105 are turned off.

[0016] Even when the switching components of the channel are configured to be off (S1 and S2 are off, while S3 is on), leakage current can still flow through S2. Figure 1 The diagram illustrates leakage currents Ileak1, Ileak2, Ileak3, and Ileak4 to represent the leakage current through S2 of the off-state switching components 112-115. Part of the leakage current arises because the on-state channel (channel 101 in this example) supplies voltage to node N1 from its input inp1 via switching component 111, and all switching components 111-115 are coupled to node N1, as shown. Therefore, the voltage from node N1 of channel 101 is also supplied to one terminal of S2 of the four off-state switching components 112-115. Since the output impedance of the sensor connected to the channel input can be relatively high (e.g., hundreds of megohms), even a small amount of leakage current will generate a voltage across the output impedance of that channel. The voltage caused by the leakage current from the off-state channel is added to (or subtracted from, depending on the direction of the leakage current) the voltage generated by the sensor from the on-state channel, thus distorting the sensor's signal.

[0017] Figure 2 An example implementation of switch S2 for each switching assembly 111-115 is shown. The cause of leakage current can be determined by... Figure 2 The description is used to determine this. (See reference.) Figure 2S2 of each switch assembly 111-115 includes a p-type MOS (PMOS) transistor MP1 coupled to an n-type MOS (NMOS) transistor MN1. The drains of MP1 and MN1 are connected together at node N1, and the sources of MP1 and MN1 are connected together at node N2. The gates of MP1 and MN1 are driven by control signals to turn on and turn off the transistors of S2. To turn on S2, both MP1 and MN1 are turned on. To turn off S2, both MP1 and MN1 are turned off. In the example configuration shown in Figure 2 , the gate of MN1 is driven by a low (e.g., ground) control signal, and the gate of MP1 is driven by a high control signal (shown as Vdda, which is a supply voltage). With the gate of MN1 driven low and the gate of MP1 driven high, both MP1 and MN1 are turned off. Thus, Figure 2 the off state of S2 is shown.

[0018] MOS transistors have parasitic body diodes. Figure 2 The drain of MP1 to body diode D1 and body to source diode D2 are shown. As noted above, the voltage on node N1 is driven by the sensor whose switch assembly is turned on. Figure 2 S2 in represents the S2 switch of a switch assembly that is off. The voltage labeled Vin represents the voltage on node N1 from a sensor in another, turned on channel (e.g., channel 101). Figure 2 Node N2 of S2 in receives ground potential through (turned on) S3 of the respective switch assembly. The body of MP1 of S2 is biased to Vdda.

[0019] When S2 is off, S2 has multiple sources of leakage current. First, when Vin is 0V (e.g., the voltage from a sensor coupled to a turned on channel 101), D1 is reverse biased, causing current Ibl to flow through D1. Thus, the leakage current Ileak (when Vin is low, e.g., 0V) is equal to -Ibl + Idsn (Idsn is the drain current through MN1). However, Idsn can be much smaller than Ibl, so Ileak is approximately equal to -Ibl. Second, when Vin is higher (e.g., Vdda), Ileak is equal to the sum of the drain to source leakage currents of MP1 and MN1 (Idsp + Idsn). Both Idsp and Idsn are proportional to Vin (e.g., the greater Vin, the greater Idsp and Idsn). Some examples described herein reduce the leakage current Ileak through S2 of a switch assembly when the switch assembly is off by using a buffer (e.g., Figure 3 buffer 310 in Figure 4 buffer 410 in ) and body biasing circuit 610 ( Figure 6 ) in the switch assembly.

[0020] Figure 3 An example of a system 300 is shown, including multiplexer circuitry 110, operational amplifier 130, and buffer 310. For simplicity, sensors S1-S5, multiplexer controller 140, and processing system 150 are not shown. The architecture of system 300 is similar to... Figure 1 The system architecture of System 100 is largely the same, except that it includes buffer 310. Figure 1 In system 100, each switch S3 is coupled between its corresponding node N2 and ground. When S3 is in Figure 1 When the circuit is switched on, the corresponding node N2 is grounded. When node N1 has a sufficiently high voltage relative to ground, grounding node N2 will cause leakage current through transistors MP1 and MN1 in S2. Figure 3 Buffer 310 is coupled at node N3 between node N1 and switch S3 of switching assembly 112-115. Buffer 310 is configured for unity gain, and therefore the output voltage of the buffer (node ​​N3) is equal to its input voltage (node ​​N1). The voltage across N1 is approximately equal to that across its switching assembly (node ​​N1). Figure 3 In the example, the voltage generated by the sensor is turned on by the switch assembly 111). Therefore, the voltage on N3 is also equal to the voltage on N1.

[0021] exist Figure 2 In the example, when S3 is on, N2 is grounded. By grounding N2, a sufficiently large drain-to-source voltage is generated across MP1 and MN1, causing leakage currents Idsp and Idsn to flow through MP1 and MN1. Figure 3 Instead of grounding N2 in switching assemblies 112-115, N2 is coupled to N3, which has approximately the same voltage as N1. Therefore, for S2 of switching assemblies 112-115, a much lower drain-to-source voltage (approximately 0V) is generated across MP1 and MN1. Advantageously, when channel 101 is enabled and channels 102-105 are disabled, when Vin is significantly greater than 0V, the leakage current generated through MP1 and MN1 of S2 of switching assemblies 112-115 is much lower (likely due to the use of the enabled channel 101) by using buffer 310.

[0022] Because buffer 310 drives all switches S3 of switching assemblies 112, 113, 114 and 115, buffer 310 is designed to be large enough to power all four switches S3 of switching assemblies 112, 113, 114 and 115.

[0023] Figure 4An example system 400 is shown, including multiplexer circuit 402, operational amplifier 130, buffer 410, switching assembly 430, and switch S4. For simplicity, sensors S1-S5, multiplexer controller 140, and processing system 150 are not shown. Multiplexer circuit 402 has an architecture similar to multiplexer circuit 110 described above. Multiplexer circuit 402 includes switching assemblies 111-115. The nodes interconnecting all switches S2 of switching assemblies 112-115 are located at… Figure 4 The node is labeled N4. Switch assembly 430 is coupled between node N4 and the output of buffer 410. Switch assembly 430 has a similar architecture to switch assemblies 111-115. As shown, switch assembly 430 includes switches S5, S6, and S7. Switches S5 and S6 are coupled in series between nodes N1 and N4. The node between S5 and S6 is designated as the intermediate node (INT). S7 is coupled between INT and the output of buffer 410.

[0024] Buffer 410 generates an output voltage that is approximately equal to its input voltage (the voltage on node N1). Figure 4 The buffer 410 drives the switching assembly 430 instead of directly driving the switching assemblies 112-115. As a result of driving a switching assembly 430, the buffer 410 can have a lower output current requirement and is therefore smaller than... Figure 3 Buffer 310.

[0025] When the switch assembly 111 is to be turned on (e.g.) Figure 4 In the example scenario, switch components 112-115 and 430 are turned off, and switch S4 is turned on. S4 is coupled between node N4 and ground. By turning on S4, node N4 is grounded. When switch component 111 is enabled and switch components 112-115 and 430 are turned off, little or no leakage current flows through switch components 112-115 and 430. Buffer 410 provides switch component 430 with the same benefits described above regarding buffer 310 for reducing its leakage current. If any of inputs inp 2-inp 4 are to be used, the switch component for that particular input is turned on, and the remaining switch components in switch components 111-115 and S4 are turned off, while switch component 430 is turned on.

[0026] Figure 5An example implementation of a buffer 410 (or 310) coupled to the input stage 510 of operational amplifier 130 is shown. Input stage 510 includes transistors M1-M5. In this example input stage, M1, M2, and M5 are PMOS transistors, while M3 and M4 are NMOS transistors. M5 is a current source device whose gate is biased at a voltage labeled BIAS1 and generates a tail current Itail. M1 and M2 include a differential transistor pair. The sources of M1 and M2 are connected together and connected to the drain of M5. The positive (+) input of operational amplifier 130 is coupled to the gate of M1 and designated IN_P. The negative (-) input of operational amplifier 130 is coupled to the gate of M2 and designated IN_M. The gates of transistors M3 and M4 are biased at a voltage labeled BIAS2.

[0027] Buffer 410 includes transistors M6, M7, and M8. In this example, M6 and M8 are PMOS transistors, while M7 is an NMOS transistor. The gate bias of M8 is labeled as the voltage of BIAS3, and the source of M8 is connected to the power supply voltage Vdda. In one example, BIAS3 is equal to BIAS1. The drain of M8 is connected to the source of M6 and node N5. Therefore, the drain of M8 and the source of M6 are connected to the operational amplifier input stage 510 at node N5. The drains of M6 and M7 are connected together and connected to the gate of M6 at node N6. Node N6 represents the output of buffer 410, which is connected to... Figure 3 Node N3 in the buffer 410 is connected to Figure 4 Switch S3 of the switching assembly 430. The gate of M7 is biased to a voltage marked BIAS4, and the source of M7 is grounded. In one example, BIAS4 is equal to BIAS2.

[0028] The current through M8 is labeled Ii. The current Ii is a function of the size of M8 (the ratio of its channel width (W) to channel length (L)) and the gate-to-source voltage (Vgs) of M8. The source of M8 is tied to Vdda, and the gate of M8 is BIAS3. Thus, BIAS3 and the channel width-to-length ratio of M8 define the size of the current Ii. If BIAS3 is equal to BIASi, and if the W / L of M8 is one sixteenth of the W / L of M5, then Ii will be one sixteenth of Itail. In one example, BIAS3 and the channel width-to-length ratio of M8 result in Ii being one sixteenth the size of Itail, and in other examples the fraction can be different than one sixteenth. Furthermore, the channel width-to-length ratio of M6 is one eighth the size of the channel width-to-length ratio of Ml or M2 (which are themselves the same size). The sources of Ml, M2, and M6 are connected together at node N5. The current density through M6 is the same as Ml and M2. Thus, while Ii to M6 is Itail / 16, the W / L of M6 is one eighth the W / L of Ml or M2. Since the output of operational amplifier 130 is connected to its negative input (IN_M), as shown, then IN_P is substantially held equal to IN_M. Because the source voltage of M6 is equal to the source voltage of Ml and M2, and the current density is the same, the gate voltage of M6 will be equal to the gate voltage of Ml and M2, IN_P or IN_M, respectively. Thus, the output voltage of buffer 410 on node N6 will be approximately equal to IN_P. Figure 4

[0029] As described above with respect to Figure 2 When Vin is a relatively low voltage, if the bulk of the MPi transistor is biased at the supply voltage (Vdda), then the drain-to-bulk parasitic diode Dl of switch S2 of switch assembly 112-115 is reverse biased, resulting in a drain current flowing through each such switch S2.

[0030] Figure 6 The system 600 is shown, where when Vin is a low voltage, the bulk of the PMOS transistor of switch S2 is biased at a voltage lower than Vdda.

[0031] Figure 6 The example system 600 in Figure 5 ​M8 in FIG. 4. In this example, switch S6 of switch assembly 430 includes transistors M10 and M11. In addition, switch S5 includes transistors M12 and M13. Switch assembly 430 is shown in the off state, so switch S7 is on. S7 is shown in its symbolic form. In some embodiments, S7 includes a single transistor or a pair of PMOS / NMOS transistors. M10 and M12 include PMOS transistors, while M11 and M13 include NMOS transistors. The sources of M10 and M11 are connected together and to the IN_P input of operational amplifier input stage 510 (gate of Ml). The drains of M10 and M11 are connected together at node INT. S7 is shown in its closed (on) state to couple INT to the output of buffer 410 (node N6). The sources of M12 and M13 are also connected to INT. The drains of M12 and M13 are connected together at node N4, which is provided to switch assemblies 112-115, as shown in FIG. 4. Switch S4 is coupled between node N4 and ground and is closed (on) when switch assembly 430 is off. When switch assembly 430 is off, S5 and S6 are off. For S5 and S6 to be off, the gates of PMOS transistors M10 and M12 are provided with the supply voltage (Vdda), and the gates of NMOS transistors M11 and M13 are provided with ground, as shown. Figure 4

[0032] S1 includes transistors M14 and M15, and S2 includes transistors M16 and M17. In this example, M14 and M16 include PMOS transistors, while M15 and M17 include NMOS transistors. The drains of Ml5 and M16 are connected together at the input inp 1 of channel 101. The sources of M16 and M17 are connected together at node N1, to which the gate of Ml within input stage 510 of the operational amplifier is connected. Figure 6 The configuration of FIG. 4 illustrates switch assembly 111 in its on state, so the gates of PMOS transistors M14 and M16 are grounded to turn on M14 and M16, and the gates of NMOS transistors M15 and M17 receive the supply voltage Vdda to turn on M15 and M17. In addition, switch S3 Figure 4 of switch assembly 111 is off, so node N2 is not pulled to ground. S3 is not shown in FIG. 4. Figure 5

[0033] ​​The example substrate biasing circuit 610 includes transistors M18 and M19. In this implementation, M18 and M19 are PMOS transistors. The source of M18 is connected to Vdda, and the drain of M18 is connected at node N7 to the source of M19. The drain of M19 is connected to ground. The substrate of M19 is connected to the source of M19. With M19 configured as a source follower, current I2 flows in a branch from Vdda through M18 and M19 to ground. The voltage on the source of M19 is higher than the gate voltage of M19 by a threshold voltage (approximately 1 V). The signal on the gate of M19 is the voltage on node N1. When switch assembly 111 is on (S1 and S2 are on) and the voltage on inp 1 is very low, the voltage on N1 will be very low, current I2 flows through M19, causing the voltage on the source of M19 to be approximately 1 V higher than its gate voltage (Nl). Node N7 is coupled to the substrates of M1 and M2 within the operational amplifier input stage, and the substrate of M10 within switch S6, and the substrate of M16 of S2 within switch assembly 111. The respective substrates of the PMOS transistors of S2 of other switch assemblies 112-115 can also be coupled to node N7. The voltage on node N7 is used to bias the substrates of M1, M2, and M10. When input inp 1 is low enough to turn on M10, the voltage on node N7 will be pulled low to be approximately 1 V higher than the voltage on inp 1, so the substrates of M1, M2, and M10 are biased to a voltage much lower than Vdda (e.g., 1 V). With the substrate of M10 biased to a voltage much lower than Vdda, the substrate-to-source parasitic diode D3 of M10 will be biased to a voltage much closer to 0 V than if the substrate of M10 were biased to Vdda. With D3 biased to 0 V or a relatively small voltage, the leakage current through D3 will be much less than if D3 were biased to a larger voltage. By biasing the substrate of PMOS M10 within switch assembly 430 to a lower voltage when the voltage on inp 1 is low (as compared to when inp 1 has a larger voltage), the leakage current through switch assembly 430 is reduced as compared to if the substrate of M10 were biased continuously at Vdda.

[0034] The term "coupled" is used throughout the specification. This term can encompass a connection, a communication, or a signal path that causes a functional relationship between the connected components. For example, if device A generates a signal to control device B to perform an action, then in a first example, device A is coupled to device B, or in a second example, device A is coupled to device B through intervening component C, such that device B is controlled by device A via the control signal generated by device A, without substantially changing the functional relationship between device A and device B.

Claims

1. A circuit comprising: A first switching assembly having a first input node and a first output node; The second switching assembly has a second input node and a second output node; A third switching assembly has a third input node, a fourth input node, and a third output node, wherein the third input node is coupled to the second output node, and the third output node is coupled to the first output node; An operational amplifier that has an input stage; as well as A buffer having a buffer input and a buffer output, the buffer input being coupled to the input stage of the operational amplifier, and the buffer output being coupled to the third switching assembly; The third switching assembly is adapted to open or close the connection between the third input node and the third output node, and the buffer output is connected to the fourth input node to provide a voltage bias to the connection to reduce leakage current when the third switching assembly is turned off.

2. The circuit of claim 1, wherein the buffer comprises a unity-gain buffer.

3. The circuit according to claim 2, wherein the third switching component comprises: First switch; The second switch is coupled between the first switch at the intermediate node and the second output node; as well as A third switch is coupled between the intermediate node and the buffer output.

4. The circuit of claim 1, wherein the buffer comprises: A first transistor having a first gate coupled to a first bias voltage node; The second transistor has a second gate coupled to the second bias voltage node; as well as A third transistor is coupled between the first transistor and the second transistor, the third transistor having a third gate and a drain, the third gate being coupled to the drain at the output of the buffer.

5. The circuit of claim 1, wherein the third switching component includes a first transistor having a substrate, a source, and a drain, and the circuit further includes a substrate biasing circuit coupled to the substrate of the first transistor.

6. The circuit according to claim 5, wherein the first transistor is a p-type metal-oxide-semiconductor field-effect transistor.

7. The circuit of claim 5, wherein the substrate biasing circuit is configured to bias the substrate of the first transistor to a first bias voltage in response to a voltage at the third input node being higher than a first voltage level, and to bias the substrate of the first transistor to a second bias voltage in response to a voltage at the third input node being lower than a second voltage level, wherein the first voltage level is greater than the second voltage level, and wherein the second bias voltage is less than the first bias voltage.

8. The circuit of claim 5, wherein the first transistor has a first gate, the source is a first source, and the drain is a first drain, and wherein the substrate biasing circuit comprises: The second transistor includes a second gate, a second source, and a second drain; as well as The second transistor includes a third gate, a third source, and a third drain, the third source being coupled to the second drain and the substrate.

9. The circuit of claim 8, wherein the third gate is coupled to the first output node.

10. A circuit comprising: A first switching assembly having a first input node and a first output node; The second switching assembly has a second input node and a second output node; A third switching assembly having a third input node and a third output node, the third input node being coupled to the second output node and the third output node being coupled to the first output node, the third switching assembly including a first transistor having a substrate; An operational amplifier having an input stage coupled to the first output node; as well as A substrate biasing circuit coupled to the substrate of the first transistor is configured to bias the substrate of the first transistor at a first bias voltage in response to a voltage at the first input node being higher than a first voltage level, and to bias the substrate of the first transistor at a second bias voltage in response to a voltage at the first input node being lower than a second voltage level.

11. The circuit of claim 10, wherein the first voltage level is greater than the second voltage level, and wherein the second bias voltage is less than the first bias voltage.

12. The circuit of claim 10, further comprising a buffer having a buffer input and a buffer output, the buffer input being coupled to the input stage of the operational amplifier, and the buffer output being coupled to the third switching assembly.

13. The circuit of claim 12, wherein the buffer comprises a unity-gain buffer.

14. The circuit of claim 13, wherein the third switching assembly comprises: First switch; The second switch is coupled between the first switch at the intermediate node and the second output node; as well as A third switch is coupled between the intermediate node and the buffer output.

15. The circuit of claim 12, wherein the buffer comprises: The second transistor has a first gate coupled to the first bias voltage node; and A third transistor has a third gate and a drain, the third gate being coupled to the second transistor and the drain at the output of the buffer.

16. A circuit comprising: A first switching assembly having a first input node and a first output node; The second switching assembly has a second input node and a second output node; A third switching assembly has a third input node and a third output node, the third input node being coupled to a second output node, the third output node being coupled to a first output node, and the third switching assembly includes a first transistor having a substrate; A buffer having a buffer input and a buffer output, the buffer input being coupled to the first output node and the buffer output being coupled to the third switching assembly; as well as A substrate biasing circuit coupled to the substrate of the first transistor is configured to bias the substrate of the first transistor at a first bias voltage in response to a voltage at the first input node being higher than a first voltage level, and to bias the substrate of the first transistor at a second bias voltage in response to a voltage at the first input node being lower than a second voltage level.

17. The circuit of claim 16, wherein the buffer comprises a unity-gain buffer.

18. The circuit of claim 16, wherein the buffer comprises: The second transistor has a first gate coupled to the first bias voltage node; as well as A coupled third transistor having a third gate and a drain, the third gate being coupled to the second transistor and the drain at the output of the buffer.

19. The circuit of claim 16, wherein the third switching assembly comprises: A first switch, which includes the first transistor; The second switch is coupled between the first switch at the intermediate node and the second output node; as well as A third switch is coupled between the intermediate node and the buffer output.

20. The circuit of claim 16, wherein the first voltage level is greater than the second voltage level, and wherein the second bias voltage is less than the first bias voltage.

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