Enhanced FPGA SRAM array configuration method for selecting multiple addresses simultaneously

Abstract

The present invention relates to an enhanced FPGA SRAM array configuration method for simultaneously selecting multiple addresses, comprising: determining the enhanced write operation start address of the SRAM array; using the enhanced write operation to write corresponding configuration data into a first address portion; and using a normal write operation to write corresponding configuration data into a second address portion; wherein, in the SRAM array, the enhanced write operation start address and the addresses following it constitute the first address portion, and the addresses preceding the enhanced write operation start address constitute the second address portion. The enhanced FPGA SRAM array configuration method for simultaneously selecting multiple addresses of the present invention utilizes an enhanced write operation method to ensure that configuration data can be correctly written to SRAM cells that are far from the bit line driver circuit in large-scale SRAM arrays without changing existing circuitry.

Description

Technical Field

[0001] The present invention belongs to the technical field of SRAM array writing methods, and in particular relates to an enhanced FPGA SRAM array configuration method for simultaneously selecting multiple addresses. Background Art

[0002] Field-Programmable Gate Arrays (FPGAs) are configured by receiving a specific set of configuration data. Different configuration data enables the FPGA to implement different functions. Configuration data is stored in the FPGA's SRAM (Static Random-Access Memory) array. Therefore, ensuring successful writing to the SRAM array is crucial for the FPGA to implement various functions.

[0003] SRAM write operation requires opening the SRAM word line and setting the bit line to the data value to be written. Generally speaking, SRAM is composed of a two-dimensional array, including several SRAM cells. The addressing circuit selects one address at a time and writes the data at one address at the same time. Different addresses are selected in turn to write the required data into the SRAM. An SRAM array with an address length of m and a data bit width of n is shown as follows. Figure 1 As shown, during the write operation, address 0 is first selected, and the n-bit data data[n-1:0] is written to address 0. Then address 1 is selected and the new data is written to address 1 until the writing of address m-1 is completed.

[0004] In large-scale SRAM arrays, the length of the bit lines (data[j], data_n[j]) in the circuit is very long, so the parasitic resistance and parasitic capacitance are large. Figure 1 When writing to address m-1, the larger parasitic resistance results in a larger voltage drop during writes. During the manufacturing process, transistor performance may deviate from design targets, with the potential for significant deviations. This significant deviation is more pronounced in large-scale SRAM arrays. Due to these two factors, the voltage received by the SRAM cell fails to meet the requirements for correct writing, preventing the SRAM from being correctly written, ultimately impacting the FPGA's functionality. Summary of the Invention

[0005] To address the above-mentioned problems in the prior art, the present invention provides an enhanced FPGA SRAM array configuration method for simultaneously selecting multiple addresses. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0006] The present invention provides an enhanced FPGA SRAM array configuration method for simultaneously selecting multiple addresses, comprising:

[0007] Determine the enhanced write operation start address of the SRAM array;

[0008] Writing corresponding configuration data into the first address portion using an enhanced write operation;

[0009] Use a normal write operation to write corresponding configuration data into the second address portion;

[0010] Wherein, in the SRAM array, the enhanced write operation start address and the address thereafter are the first address portion, and the address before the enhanced write operation start address is the second address portion.

[0011] In one embodiment of the present invention, determining the enhanced write operation start address of the SRAM array includes:

[0012] Obtaining, through experimental testing, a starting address in the SRAM array where configuration data cannot be written;

[0013] An address before the start address is selected according to a preset length as the start address of the enhanced write operation.

[0014] In one embodiment of the present invention, the enhanced write operation is used to write corresponding configuration data into the first address portion, including:

[0015] Step 1: Select the current write address of the first address part, recorded as addr[k];

[0016] Step 2: Obtain configuration data of the current write address, and write the configuration data sequentially into a plurality of addresses adjacent to the current write address, wherein the plurality of adjacent addresses are located before the current write address;

[0017] Step 3: Open the current write address and the adjacent addresses at the same time, and write the configuration data into the current write address;

[0018] Step 4: Let k=k-1, and repeat steps 1 to 4 until the configuration data of the start address of the enhanced write operation is written and the configuration data corresponding to all addresses of the first address part are written.

[0019] In one embodiment of the present invention, when performing a write operation on the first address portion, an address farthest from the bit line driving circuit is selected as the first write address to perform the enhanced write operation to write corresponding configuration data.

[0020] In one embodiment of the present invention, step 2 includes:

[0021] Step 2.1: Obtain the configuration data of the current write address;

[0022] Step 2.2: Select address addr[kj], j≥3, open address addr[kj], and write the configuration data of the current write address into the SRAM unit of address addr[kj];

[0023] Step 2.3: Let j=j-1, and repeat steps 2.2-2.3 until the configuration data of the current write address is written into the SRAM unit at address addr[k-1].

[0024] In one embodiment of the present invention, writing corresponding configuration data into the second address portion using a normal write operation includes:

[0025] Step 1: Select the current write address of the second address part, recorded as addr[k'];

[0026] Step 2: Obtain configuration data of the current write address, and write the configuration data into the current write address;

[0027] Step 3: Let k'=k'+1, and repeat steps 1 to 3 until the configuration data of the last address of the second address part is written, and the configuration data corresponding to all addresses of the second address part are written.

[0028] Compared with the prior art, the present invention has the following beneficial effects:

[0029] The enhanced FPGA SRAM array configuration method for simultaneously selecting multiple addresses of the present invention adopts an enhanced write operation method to ensure that SRAM cells far away from the bit line driving circuit can also correctly write configuration data in a large-scale SRAM array without changing the existing circuit.

[0030] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the following preferred embodiments are specifically cited and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 This is a schematic diagram of an SRAM array structure provided by an embodiment of the present invention;

[0032] Figure 2 Schematic diagram of an enhanced FPGA SRAM array configuration method for simultaneously selecting multiple addresses provided by an embodiment of the present invention;

[0033] Figure 3 This is a schematic diagram of a multi-address SRAM configuration control flow provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0034] To further illustrate the technical means and effects employed by the present invention to achieve the intended purpose, an enhanced FPGA SRAM array configuration method for simultaneously selecting multiple addresses according to the present invention is described in detail below with reference to the accompanying drawings and specific implementations.

[0035] The aforementioned and other technical contents, features, and effects of the present invention are clearly presented in the following detailed description of the specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a deeper and more specific understanding of the technical means and effects adopted by the present invention to achieve the intended purpose can be obtained. However, the accompanying drawings are provided for reference and illustration purposes only and are not intended to limit the technical solutions of the present invention.

[0036] Example 1

[0037] See Figure 2 , Figure 2 : This is a schematic diagram of an enhanced FPGA SRAM array configuration method for simultaneously selecting multiple addresses provided by an embodiment of the present invention. As shown in the figure, the enhanced FPGA SRAM array configuration method for simultaneously selecting multiple addresses in this embodiment includes:

[0038] S1: Determine the enhanced write operation start address of the SRAM array;

[0039] Specifically, in this embodiment, a starting address in the SRAM array where configuration data cannot be written is obtained through experimental testing; then, an address before the starting address is selected as a starting address for enhanced write operation according to a preset length.

[0040] Optionally, through simulation and extensive testing, the starting address where the SRAM array is generally unable to write configuration data is obtained. Then, the address after adding an appropriate margin is designated as the starting address for enhanced write operations, and this address is recorded as addr[enhance_start]. For example, if the test shows that the starting address where the SRAM array is generally unable to write configuration data is addr

[100] , and the preset length is 20, then address addr

[80] is selected as the starting address for enhanced write operations, and this address is recorded as addr[enhance_start].

[0041] It should be noted that this part is only used as a preparation stage for testing and determining the starting address of the enhanced write operation. Once the starting address of the enhanced write operation is determined, it will no longer be performed and the write operation part will be directly carried out.

[0042] S2: Use enhanced write operation to write corresponding configuration data into the first address part;

[0043] In this embodiment, in the SRAM array, the enhanced write operation start address and the addresses following it constitute the first address portion.

[0044] It should be noted that if the SRAM cells at one or more adjacent addresses store the same data as the current write operation, when performing a write operation, the adjacent one or more addresses can be opened to use the adjacent SRAM cells to raise the bit line voltage to provide sufficient driving capability so that the SRAM cells to be written this time meet the write requirements and the write operation is successfully completed. The above operation is called an enhanced write operation.

[0045] Specifically, S2 includes:

[0046] Step 1: Select the current write address of the first address part, recorded as addr[k];

[0047] Step 2: Obtain the configuration data of the current write address, and write the configuration data into a number of addresses adjacent to the current write address in sequence, where the adjacent addresses are located before the current write address;

[0048] In this embodiment, step 2 includes:

[0049] Step 2.1: Get the configuration data of the current write address;

[0050] Step 2.2: Select address addr[kj], j ≥ 3, open address addr[kj], and write the configuration data of the current write address into the SRAM unit of address addr[kj];

[0051] Step 2.3: Let j=j-1, and repeat steps 2.2-2.3 until the configuration data of the current write address is written into the SRAM cell at address addr[k-1].

[0052] Step 3: Open the current write address and several adjacent addresses at the same time, and write the configuration data into the current write address;

[0053] In the enhanced write operation process of this embodiment, at least four addresses are selected to be opened simultaneously in order to provide sufficient driving capability. In other embodiments, more addresses may be opened simultaneously to write to more nearby addresses, but this will reduce efficiency.

[0054] Step 4: Let k=k-1, and repeat steps 1-4 until the configuration data of the start address of the enhanced write operation is written and the configuration data corresponding to all addresses in the first address part are written.

[0055] It should be noted that, when performing a write operation on the first address portion, the address farthest from the bit line driving circuit is selected as the first write address to perform an enhanced write operation to write the corresponding configuration data.

[0056] S3: Use a normal write operation to write the corresponding configuration data into the second address part;

[0057] In this embodiment, in the SRAM array, the address before the start address of the enhanced write operation is the second address part.

[0058] Specifically, S3 includes:

[0059] Step 1: Select the current write address of the second address part, recorded as addr[k'];

[0060] Step 2: Get the configuration data of the current write address and write the configuration data into the current write address;

[0061] Step 3: Let k'=k'+1, and repeat steps 1 to 3 until the configuration data of the last address in the second address section is written, and the configuration data corresponding to all addresses in the second address section are written.

[0062] Optionally, when performing a write operation on the second address part, the address closest to the bit line driving circuit is usually selected as the first write address for performing a normal write operation to write the corresponding configuration data. In other embodiments, when performing a write operation on the second address part, any address in the second address part can also be selected as the first write address for performing a normal write operation to write the corresponding configuration data. There is no limitation here.

[0063] The enhanced FPGA SRAM array configuration method for simultaneously selecting multiple addresses in this embodiment adopts an enhanced write operation method. Without changing the existing circuit, in a large-scale SRAM array, it ensures that SRAM cells far away from the bit line driver circuit can also correctly write configuration data.

[0064] Furthermore, the specific write operation steps of the enhanced FPGA SRAM array configuration method for simultaneously selecting multiple addresses in this embodiment are described in conjunction with the SRAM configuration control system.

[0065] Please refer to Figure 3 , Figure 3This is a schematic diagram of a multi-address SRAM configuration control flow provided by an embodiment of the present invention. As shown in the figure, the host computer is used to send configuration control instructions (the control instructions include selected address information and write operation requests) and configuration data (the configuration data is the data to be written into the SRAM); the configuration control module is used to receive and parse the configuration control instructions, generate word line control signals and bit line control signals, and send corresponding control signals to the word line control module and the bit line control module. The configuration control module is also used to receive configuration data; the bit line control module is used to receive the bit line control signals and the configuration data to be written, and after receiving the write operation request, controls the bit line drive circuit module to perform the write operation; the bit line drive circuit module is used to provide bit line drive capability during the write operation; the word line control module is used to receive the word line control signals and selected address information, and after receiving the write operation request, controls the word line drive circuit module to perform the write operation; the word line drive circuit module is used to provide word line drive capability during the write operation; and the SRAM array is used to store the configuration data.

[0066] by Figure 1 Taking the SRAM array with an address length of m and a data bit width of n as an example, the specific configuration method is as follows:

[0067] Preparation stage:

[0068] ① Through simulation and extensive testing, we obtain the starting address of the SRAM array that is generally inaccessible to writing. We specify the address after adding an appropriate margin as the starting address for the enhanced write operation, which is recorded as addr[enhance_start].

[0069] Enhanced write operation phase (first address write operation phase):

[0070] The address currently to be written is recorded as addr[k]:

[0071] ① Set k = m-1;

[0072] ② The host computer sends instructions to control the word line control module to select the address addr[k-3];

[0073] ③ The host computer sends instructions and configuration data that need to be written to address addr[k]. The configuration control module controls the word line control module and the bit line control module to perform a write operation, opens the address addr[k-3], and writes the received configuration data of addr[k] into the SRAM unit of addr[k-3].

[0074] ④ The host computer sends instructions to control the word line control module to select the address addr[k-2];

[0075] ⑤ According to the instructions sent by the host computer, the configuration control module controls the word line control module and the bit line control module to perform a write operation, opens the address addr[k-2], and writes the configuration data received in step ③ into the SRAM unit of addr[k-2];

[0076] ⑥The host computer sends instructions to control the word line control module to select the address addr[k-1];

[0077] ⑦ According to the instructions sent by the host computer, the configuration control module controls the word line control module and the bit line control module to perform a write operation, opens the address addr[k-1], and writes the configuration data received in step ③ into the SRAM unit at the address addr[k-1];

[0078] ⑧The host computer sends instructions to control the word line control module to select four addresses addr[k:k-3];

[0079] ⑨ According to the instructions sent by the host computer, the configuration control module controls the word line control module and the bit line control module to perform a write operation, opens the four addresses addr[k:k-3] at the same time, and writes the configuration data received in step 3 into the SRAM unit at address addr[k];

[0080] ⑩ Reset k = k-1, and repeat steps ② to ⑩ of this stage until k = enhance_start, that is, all addresses that require enhanced write operations (that is, the first address part) are written.

[0081] Normal write operation phase (second address write operation phase):

[0082] ① Set k' = 0;

[0083] ② The host computer sends instructions to control the word line control module to select the address addr[k'];

[0084] ③ The host computer sends instructions and configuration data that need to be written to addr[k']. The configuration control module controls the word line control module and the bit line control module to perform a write operation and writes the received configuration data of addr[k'] into the address addr[k'].

[0085] ④ Reset k'=k'+1 and repeat steps ② to ④ until k'=enhance_start-1, that is, all addresses requiring normal write operations (i.e., the second address portion) are written. At this point, the SRAM array is written.

[0086] It is worth noting that in other SRAM configuration control system circuit structures, the bit line driver circuit module can be located in the center of the SRAM array, driving the SRAM array upward and downward to both sides. The SRAM array is divided into upper and lower parts, and there are also areas away from the bit lines in both directions. The method of this embodiment can also be used for configuration in this architecture. Accordingly, two enhanced write operation starting addresses are determined, corresponding to two first address parts and two second address parts. Then, the enhanced write operation is used to write the corresponding configuration data in the first address part; the normal write operation is used to write the corresponding configuration data in the second address part.

[0087] The enhanced FPGA SRAM array configuration method for simultaneously selecting multiple addresses in this embodiment ensures that even SRAM cells located far from the bit line driver circuit can be correctly written to in large SRAM arrays. This provides a solution for writing to SRAM cells located far from the bit line driver circuit without changing existing circuitry. Even after modifying the circuit structure of the SRAM configuration control system, this method can serve as a backup solution for writing to SRAM cells located far from the bit line driver circuit.

[0088] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations are intended to cover non-exclusive inclusion, such that an article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the article or device comprising the element.

[0089] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. An enhanced FPGA SRAM array configuration method for simultaneously selecting multiple addresses, characterized in that: include: Determining the enhanced write operation start address of the SRAM array; comprising: obtaining a start address in the SRAM array where configuration data cannot be written through experimental testing; selecting an address before the start address according to a preset length as the enhanced write operation start address; The enhanced write operation is used to write corresponding configuration data into the first address portion; including: Step 1: Select the current write address of the first address part, recorded as addr[k]; Step 2: Obtain configuration data of the current write address, and write the configuration data sequentially into a plurality of addresses adjacent to the current write address, wherein the plurality of adjacent addresses are located before the current write address; Step 3: Open the current write address and the adjacent addresses at the same time, and write the configuration data into the current write address; Step 4: Let k = k-1, and repeat steps 1 to 4 until the configuration data of the start address of the enhanced write operation is written and the configuration data corresponding to all addresses of the first address part are written; When performing a write operation on the first address portion, selecting an address farthest from the bit line driving circuit as a first write address to perform the enhanced write operation to write corresponding configuration data; Use a normal write operation to write corresponding configuration data into the second address portion; Wherein, in the SRAM array, the enhanced write operation start address and the address thereafter are the first address portion, and the address before the enhanced write operation start address is the second address portion.

2. The enhanced FPGA SRAM array configuration method for simultaneously selecting multiple addresses according to claim 1, wherein: The step 2 includes: Step 2.1: Obtain the configuration data of the current write address; Step 2.2: Select address addr[kj], j≥3, open address addr[kj], and write the configuration data of the current write address into the SRAM unit of address addr[k-j]; Step 2.3: Let j=j-1, and repeat steps 2.2-2.3 until the configuration data of the current write address is written into the SRAM cell at address addr[k-1].

3. The enhanced FPGA SRAM array configuration method for simultaneously selecting multiple addresses according to claim 1, wherein: Use normal write operation to write corresponding configuration data in the second address part, including: Step 1: Select the current write address of the second address part, recorded as addr[k']; Step 2: Obtain configuration data of the current write address, and write the configuration data into the current write address; Step 3: Let k'=k'+1, and repeat steps 1 to 3 until the configuration data of the last address of the second address part is written, and the configuration data corresponding to all addresses of the second address part are written.

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