A data processing method, system, apparatus and medium

Abstract

The application provides a data processing method, system, device and medium, and mainly comprises the following steps: acquiring a sensor signal, sending the sensor signal to a read bit line of an SRAM array; determining that the voltage value of the read bit line is stable, and turning on a read word line of the SRAM array; acquiring a weight value of the sensor signal through the read word line, performing a multiplication operation according to the weight value, obtaining a first output voltage, and outputting the first output voltage to a shared bit line; performing binaryzation processing on the first output voltage to obtain second output data, and obtaining a convolution operation result from the second output data; the scheme can greatly reduce the hardware cost, power consumption and delay of data transmission without a series of intermediate analog-digital conversion and digital-analog conversion processing steps, can effectively improve the accuracy of the neural network algorithm, can also reduce the delay and power consumption caused by data transfer, can meet the requirements of low delay, high bandwidth and other high performance, and can be widely applied to the embedded technical field.

Description

Technical Field

[0001] This invention relates to the field of embedded systems technology, and in particular to a data processing method, system, device, and medium. Background Technology

[0002] In low-power embedded systems, the gap between complex computing needs and hardware resource availability is widening. Meanwhile, for applications such as the Internet of Things (IoT) and edge computing, there is an increasing demand for high performance and low power consumption to meet real-time requirements and ease of use.

[0003] In the traditional von Neumann computer architecture, computing units and storage units are physically separated, with data transfer between them via a data bus. The computing unit reads data from memory according to instructions and stores it back into memory after computation. This architecture has become one of the main bottlenecks restricting the performance improvement of computing systems, increasing computational latency and resulting in huge energy consumption. It is estimated that in the von Neumann computer architecture, data transfer power consumption accounts for more than 50% of the total data computation power consumption. Furthermore, the memory wall problem is even more significant. Due to the separation of computation and storage, processors and memory have evolved in their own directions and with their own philosophies. Processors pursue high frequency and high performance, while memory aims for low cost and high density, resulting in relatively slower performance development. For a long time, compared to the processor's average annual performance improvement of about 55%, memory data access latency has only decreased by a paltry 10%. At the same time, for the massive data transfer demands, the limited bandwidth of the data bus also severely restricts the performance and efficiency of system computation. Summary of the Invention

[0004] In view of this, in order to at least partially solve one of the above-mentioned technical problems, the purpose of the embodiments of the present invention is to provide a high-performance, low-power data processing method, as well as a corresponding system, device and medium capable of implementing the method.

[0005] On the one hand, the technical solution of this application provides a data processing method, including the following steps:

[0006] Acquire sensor signals and send the sensor signals to the read lines of the SRAM array; the sensor signals are voltage signals obtained by binarizing the pixels of the input feature map.

[0007] Once the voltage value of the read bit line is stable, the read word line of the SRAM array is turned on;

[0008] The weight values ​​of the sensor signals in the read character lines are obtained, and the sensor signals in the read bit lines are obtained. The weight values ​​and the sensor signals are multiplied together to obtain a first output voltage, which is then output to the shared bit line. The first output voltage is the voltage signal of a pixel in the output feature map.

[0009] The first output voltage is converted to obtain the second output data, and the second output data is used to obtain the convolution operation result.

[0010] In one feasible embodiment of the present application, the read bit line includes a first read bit line and a second read bit line. The step of obtaining the weight value of the sensor signal in the read bit line, obtaining the sensor signal in the read bit line, and performing a multiplication operation between the weight value and the sensor signal to obtain a first output voltage output to the shared bit line includes:

[0011] When the weight value is determined to be a first value, the first transistor is turned off and the second transistor is turned on, and the sensor signal in the first read bit line is sent to the shared bit line.

[0012] When the weight value is determined to be the second value, the first transistor is turned on and the second transistor is turned off, and the sensor signal in the second read bit line is sent to the shared bit line.

[0013] The weight value is determined to be a third value. The first transistor is turned off, the second transistor is turned off, and the sensor signals in the first and second read bit lines are sent to the shared bit line.

[0014] In one feasible embodiment of the present application, the step of converting the first output voltage to obtain second output data and obtaining the convolution operation result from the second output data includes:

[0015] The convolution operation result is obtained by subtracting the second output data in the first shared bit line from the second output data in the second shared bit line.

[0016] In one feasible embodiment of the present application, the data processing method further includes the following steps:

[0017] The first output voltage, which is positive and obtained through the multiplication operation, is stored in the first capacitor.

[0018] The first output voltage, which is negative and obtained through the multiplication operation, is stored in the second capacitor.

[0019] In one feasible embodiment of the present application, the convolution operation result satisfies the following formula:

[0020]

[0021] Wherein, OUT is the result of the convolution operation, and W i V represents the weight value. i Let be the voltage value of the sensor signal, and n be the number of SRAM arrays, i = 1, 2, 3, ..., N, where N is a positive integer.

[0022] On the other hand, the technical solution of this application also provides a data processing system, which includes:

[0023] A sensor storage array is used to acquire sensor signals and send the sensor signals to the read lines of an SRAM array; the sensor signals are voltage signals obtained by binarizing the pixels of the input feature map.

[0024] The readout calculation circuit is used to obtain the weight value of the sensor signal in the read word line, obtain the sensor signal in the read bit line, and perform a multiplication operation between the weight value and the sensor signal to obtain a first output voltage, which is output to the shared bit line; the first output voltage is the voltage signal of the pixel in the output feature map;

[0025] An analog-to-digital converter circuit is used to convert the first output voltage to obtain the second output data, and to obtain the convolution operation result from the second output data.

[0026] In one feasible embodiment of the present application, the sensor storage array is a ternary static random access memory; the ternary static random access memory includes a first ternary inverter and a second ternary inverter, the output of the first ternary inverter is connected to the input of the second ternary inverter; the output of the second ternary inverter is connected to the input of the first ternary inverter.

[0027] In one feasible embodiment of the present application, the first ternary inverter includes a thin-gate NMOS transistor, a thick-gate NMOS transistor, a thin-gate PMOS transistor, and a thick-gate PMOS transistor;

[0028] When the input terminal of the first ternary inverter is a high-level signal, the thick-gate NMOS transistor and the thin-gate NMOS transistor are turned on, and the output terminal of the first ternary inverter is a low-level signal.

[0029] When the input terminal of the first ternary inverter is a low-level signal, the thick-gate PMOS transistor and the thin-gate PMOS transistor are turned on, and the output terminal of the first ternary inverter is a high-level signal.

[0030] When the input signal amplitude of the first ternary inverter is half the amplitude of the high-level signal, the thin-gate NMOS transistor and the thin-gate PMOS transistor are turned on, and the output signal amplitude of the first ternary inverter is half the amplitude of the high-level signal.

[0031] The structure of the second ternary inverter is the same as that of the first ternary inverter.

[0032] On the other hand, the present application also provides a data processing apparatus, which includes:

[0033] At least one processor;

[0034] At least one memory for storing at least one program;

[0035] When the at least one program is executed by the at least one processor, the at least one processor performs a data processing method as described in any one of the first aspects.

[0036] On the other hand, the present application also provides a storage medium storing a processor-executable program, which, when executed by a processor, is used to perform a data processing method as described in any one of the first aspects.

[0037] The advantages and beneficial effects of the present invention will be set forth in part in the following description, and the rest will become apparent from the specific embodiments thereof:

[0038] This application's technical solution is based on a storage-and-computation integrated convolutional computing acceleration architecture for sensors. The solution can directly input data from the sensor without the need for a series of intermediate analog-to-digital and digital-to-analog conversion steps, greatly reducing the hardware overhead, power consumption, and latency of data transmission. It uses SRAM, which can store multiple weights, effectively improving the accuracy of neural network algorithms and reducing latency and power consumption caused by data movement. The solution meets the requirements of neural networks for reducing the cost of hardware implementation architecture, including power consumption and hardware overhead, while providing high performance such as low latency and high bandwidth. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a schematic diagram of a perceptual computing architecture commonly used in related technologies;

[0041] Figure 2 This is a schematic diagram of the in-memory computing integrated convolutional computation acceleration architecture for near-sensor applications in the technical solution of this application.

[0042] Figure 3 This is a schematic diagram of the structure of the data processing system provided by the technical solution of this application;

[0043] Figure 4 This is a schematic diagram of the structure of a ternary SRAM in the system of the embodiment of the technical solution of this application;

[0044] Figure 5 This is a schematic diagram of the ternary inverter STI in the system of the embodiment of the technical solution of this application;

[0045] Figure 6 This is a schematic diagram of the convolution calculation system in the embodiment of the technical solution of this application;

[0046] Figure 7 A flowchart illustrating the steps of a data processing method provided in this application. Detailed Implementation

[0047] The embodiments of the present invention are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. The step numbers in the following embodiments are set only for ease of explanation, and there is no limitation on the order between the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0048] In the era of intelligentization, science and technology, represented by Artificial Intelligence (AI), have greatly propelled the progress of human society. In recent years, AI technology has developed rapidly and has been widely applied in both consumer and industrial production sectors. Examples include image recognition, industrial robots, autonomous driving, metaverse, and medical image analysis. Simultaneously, with the advent of the Internet of Things (IoT) era, more and more data is flowing through the cloud, edge, and endpoints. This exponentially growing data volume places higher demands on the computing power and power consumption of existing computing architectures. Due to the existence of the memory wall and power wall, the limitations of the von Neumann computing architecture are becoming increasingly apparent. Therefore, a new computing architecture is urgently needed to meet the challenges of future application scenarios. Against this backdrop, the concept of in-memory computing has re-emerged in the vision of academia and industry.

[0049] The success of artificial neural network (ANN) algorithms and breakthroughs in powerful hardware have jointly propelled the rapid development of the artificial intelligence revolution. In recent years, ANNs have demonstrated significant advantages in many applications, including object detection, wearable devices, and natural language processing. At the software level, ANN algorithms have achieved tremendous success. To support the effective implementation of ANN models from the cloud to edge devices, researchers in academia and industry have begun designing dedicated hardware accelerators for ANNs. Currently, the mainstream platform for accelerating ANN algorithms is the Graphics Processing Unit (GPU), which offers advantages such as high computational accuracy and highly flexible programming. Training ANN algorithms is typically performed in GPU clusters, resulting in staggering energy consumption, ranging from hundreds to thousands of watts. To improve energy efficiency and make them suitable for data center environments, researchers have begun customizing dedicated integrated circuit (ASIC) architecture solutions for cloud and edge devices, such as Google's Tensor Processing Unit (TPU). However, the real problem with ANN algorithm accelerators lies in the frequent data movement between computational units and memory units—the so-called memory wall problem in the traditional von Neumann architecture. Most operations in artificial neural networks involve vector-matrix multiplication (VMM) between the input vector and the weight matrix, which is essentially performing multiply-accumulate (MAC) operations. Therefore, in-memory computation (CIM) is considered the most effective solution to break through the bottlenecks of the von Neumann architecture.

[0050] Furthermore, sensor systems are a crucial component of artificial intelligence devices. Traditional sensor systems are increasingly unsuitable for smart devices, as their energy consumption cannot support long-term continuous data acquisition tasks. In traditional technical solutions, sensor systems are physically separated from computing units due to differences in functional requirements and manufacturing technologies. Sensors primarily operate in the noisy analog domain, while computing units typically operate digitally based on traditional von Neumann computing architectures. The sensor terminal locally acquires large amounts of raw data and then transmits it to the computing unit of the local system. For example... Figure 1 As shown, in traditional intelligent systems, analog data collected by sensors is first converted into digital signals using an analog-to-digital converter (ADC), then temporarily stored in memory, and finally retrieved from memory by the processing unit for processing. Overall, the data undergoes a series of data conversions and transmissions from sensor acquisition to processing by the computing unit. Furthermore, publicly available data indicates that the ADC and data storage account for a dominant portion of the overall system's energy consumption. Therefore, this system architecture inevitably leads to significant issues with energy consumption, processing speed, and communication bandwidth.

[0051] Based on the aforementioned theoretical foundation, such as Figure 2As shown, this application proposes a memory-computing integrated convolutional computing acceleration architecture design for near-sensor applications. In the first embodiment, based on this memory-computing integrated convolutional computing acceleration architecture, an in-memory computing system is first provided. This system mainly includes a sensor storage array, a readout computing circuit, and an analog-to-digital conversion circuit.

[0052] The overall architecture of the system is as follows Figure 3 As shown, the storage array consists of SRAM. The storage array acquires sensor signals through connected sensors and sends these signals to the read bits of the SRAM array; it also stores the weights of the neural network model. The readout calculation circuit in the system determines that the voltage value of the read bits is stable, activates the read word lines of the SRAM array, and acquires the weight values ​​of the sensor signals through the read word lines. It then performs a multiplication operation based on these weight values ​​to obtain a first output voltage, which is output to the shared bit line. The analog-to-digital converter circuit in the system converts the first output voltage to obtain second output data, and subtracts the second output data to obtain the convolution operation result.

[0053] In some alternative embodiments, the sensor storage array in the system is a ternary static random access memory; the ternary static random access memory includes a first ternary inverter and a second ternary inverter, the output of the first ternary inverter is connected to the input of the second ternary inverter; the output of the second ternary inverter is connected to the input of the first ternary inverter.

[0054] Because in related technologies, the SRAM used in mainstream CIM (Computer Integrated Manufacturing) architectures can only store 2 weights W. i (1,-1), in its CIM architecture, high level V dd Represents the weight value W i 1, low level V GND The weight value W represents i The value is -1. Specifically, in the technical solution of this application, for example... Figure 3 As shown, the system in this embodiment uses a ternary SRAM, which can store three weight values ​​W. i .exist Figure 3 In the middle, point Q is a high level V. dd Represents the weight value W i The value is -1, and point Q is at a low level. GND The weight value W represents i The value is 1, and Q is 1 / 2V. dd The weight value W represents iThe value is 0. While ternary SRAM actually consumes slightly more power than a standard six-transistor SRAM, the additional weight significantly increases the accuracy of neural network models.

[0055] In some alternative embodiments, such as Figure 4 As shown, the ternary inverter (including the first ternary inverter and the second ternary inverter) in the embodiment system mainly includes a thin-gate NMOS transistor, a thick-gate NMOS transistor, a thin-gate PMOS transistor, and a thick-gate PMOS transistor.

[0056] Specifically, when the input terminal of the ternary inverter is a high-level signal, the thick-gate NMOS transistor and the thin-gate NMOS transistor are turned on, and the output terminal of the ternary inverter is a low-level signal; when the input terminal of the ternary inverter is a low-level signal, the thick-gate PMOS transistor and the thin-gate PMOS transistor are turned on, and the output terminal of the ternary inverter is a high-level signal; when the amplitude of the input signal of the ternary inverter is half the amplitude of the high-level signal, the thin-gate NMOS transistor and the thin-gate PMOS transistor are turned on, and the amplitude of the output signal of the ternary inverter is half the amplitude of the high-level signal.

[0057] Specifically, such as Figure 5 As shown, the key to the SRAM's ability to store three weights in this embodiment lies in the design of the ternary inverter (STI); in this embodiment, multi-threshold CMOS technology is used in the STI to implement ternary switching operation. The thick-gate NMOS transistor only operates when the gate voltage is V. dd Only when the gate voltage is V does it turn on. GND Only then does it conduct, while the NMOS transistor with a thinner gate conducts when the gate voltage is V. dd Or 1 / 2V dd When the PMOS transistor with a thin gate is turned on, the gate voltage is V. GND Or 1 / 2V dd On. When the input voltage In is V dd At that time, the output voltage Out is V GND When the input voltage In is V GND At that time, the output voltage Out is V GND When the input voltage In is 1 / 2V dd At that time, the output voltage Out is 1 / 2V. dd .

[0058] like Figure 6 As shown, and more specifically, when performing convolution calculations, the system provided by this application can directly input the voltage value V from the sensor. iThe data collected by the sensor does not require a series of intermediate analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) or storage. This not only saves a large amount of energy but also greatly reduces the latency of intermediate data, improving the overall system processing speed. The next step is to perform convolution calculations (multiply-accumulate MAC) within the CIM architecture.

[0059] Furthermore, based on the data processing system based on the near-sensor in-memory computing architecture proposed in the first aspect, this application also provides a data processing method. This method primarily performs multiplication and accumulation calculations on the convolutional and fully connected layers of a binary convolutional neural network (CNN). Firstly, the artificial neural network model used in this embodiment is the LeNet-5 neural network model. Binarization is then performed on the LeNet-5 neural network model to construct a binary neural network model. While full-precision floating-point CNNs can provide high recognition accuracy, the high accuracy comes at the cost of massive data computation, high power consumption, and high hardware costs. This is unacceptable for low-power, hardware-restricted embedded edge devices. From a hardware-friendly perspective, the method for binarizing CNNs is to use the sign function to determine the binarization result based on the sign of the floating-point number. Simply put, a positive number is binarized as 1, and a negative number is binarized as -1; the specific binarization formula is:

[0060]

[0061] The LeNet-5 neural network model is a CNN network model used for handwritten digit recognition. Excluding the input and output layers, the LeNet-5 neural network model has a total of 6 layers: C1 and C3 are convolutional layers, S2 and S4 are pooling layers, and F5 and F6 are fully connected layers. By binarizing the LeNet-5 neural network model, its computational cost and hardware overhead are significantly reduced. In the entire LeNet-5 neural network model, the vast majority of computation occurs in the convolutional and fully connected layers; the convolution operations in these two layers are essentially multiply-accumulate (MAC) operations. Therefore, in our implementation method, performing these two layers of computation within our proposed in-memory computing architecture (CIM) effectively reduces the overall system power consumption while accelerating the entire neural network model. Based on the aforementioned theoretical foundation, such as... Figure 7 As shown, the method in this embodiment includes steps S100-S400:

[0062] S100. Acquire sensor signal and send the sensor signal to the read bit line of SRAM array, wherein the sensor signal is the voltage signal obtained by binarizing the pixel points of the input feature map.

[0063] For example, in this embodiment, the near-sensor's in-memory computing architecture includes 64 SRAM cells per row, meaning that 64 multiplications can be performed in parallel and the results can be summed. First, the embodiment sends the voltage value Vi output by the sensor to the read lines of the SRAM array.

[0064] S200. Determine that the voltage value of the read bit line is stable, and then enable the read word line of the SRAM array.

[0065] Specifically, in this embodiment, after the voltage supplied to the read bit line stabilizes, the read word line (RWL) of the SRAM is turned on, and the weight value W pre-stored in the SRAM is read out. i .

[0066] S300. Obtain the weight value of the sensor signal in the read word line, obtain the sensor signal in the read bit line, and perform a multiplication operation between the weight value and the sensor signal to obtain a first output voltage and output it to the shared bit line; wherein, the first output voltage is the voltage signal of the pixel point in the output feature map.

[0067] In this embodiment, the read bit lines include a first read bit line and a second read bit line (RBL and RBLB). Furthermore, the step of obtaining the sensor signal weight value through the read bit lines and performing a multiplication operation based on the weight value to obtain a first output voltage output to the shared bit line may include steps S310-S330:

[0068] S310. Determine the weight value as a first value, turn off the first transistor, turn on the second transistor, and send the sensor signal in the first read bit line to the shared bit line.

[0069] like Figure 6 As shown, when the weight value W i When it is 1, that is, the voltage value of Q is V. GND Then the voltage value of QB is V. dd At this time, transistor N4 (the second transistor) is turned on, and the voltage on RBLB will be completely discharged to ground. Meanwhile, transistor N3 (the first transistor) is turned off, so the voltage on RBL remains unchanged. At this point, EN... P With the switch closed, the voltage on RBL is transferred to the V_p shared bit line. This completes the multiplication operation 1*V. i , thus obtaining the second value.

[0070] S320. Determine that the weight value is the second value, turn on the first transistor, turn off the second transistor, and send the sensor signal in the second read bit line to the shared bit line.

[0071] like Figure 6 As shown, when the weight value W iWhen it is -1, that is, the voltage value of Q is V. dd Then the voltage value of QB is V. GND At this time, transistor N3 is turned on, and the voltage across RBL will be completely discharged to ground. Meanwhile, transistor N4 is turned off, so the voltage across RBLB remains unchanged. At this point, EN... n When the switch is closed, the voltage on RBLB is transferred to the V_n shared bit line. This completes the multiplication operation -1*V. i , thus obtaining the second value.

[0072] S330. Determine the weight value as a third value, turn off the first transistor and the second transistor, and send the sensor signals in the first and second read bit lines to the shared bit line.

[0073] like Figure 6 As shown, when the weight value W i When the voltage is 0, meaning the voltage of Q is 1 / 2 Vdd, then the voltage of QB is also 1 / 2 Vdd. At this time, both transistors N3 and N4 are cut off, and the voltages on RBL and RBLB remain unchanged. At this point, EN... P EN n When the switch is closed, the voltage on RBL is transferred to the V_p shared bit line, and the voltage on RBLB is transferred to the V_n shared bit line. The multiplication operation 0*V is completed. i , thus obtaining the second value.

[0074] It should be noted that, in the embodiment, the step of binarizing the first output voltage to obtain the second output data and obtaining the convolution operation result from the second output data includes the step of subtracting the second output data in the first shared bit line from the second output data in the second shared bit line to obtain the convolution operation result.

[0075] Specifically, in this embodiment, although the voltages on the two bit lines are respectively sent to the shared bit lines V_p and V_n, the result is 0 after subtracting V_p from V_n in the next step, reaching 0*V. i The effect of multiplication.

[0076] In some feasible embodiments, after obtaining the calculation result of the multiplication operation, based on capacitive coupling and charge sharing mechanisms, for each multiplication operation, the voltage on the read bit lines (RBL, RBLB) is transferred to the shared bit lines V_p and V_n, and the voltage is accumulated and stored in capacitors Cp and Cn. A positive voltage result from the multiplication is stored on capacitor Cp on the shared bit line V_p. p The capacitor, the voltage whose multiplication result is negative, exists on the shared bit line V_n. n capacitance.

[0077] S400: Convert the first output voltage to obtain the second output data, and use the second output data to obtain the convolution operation result.

[0078] Specifically, in this embodiment, the voltage value on each shared bit line can be converted into a binary digital result by an ADC converter, and then subtracted to obtain the final result after the convolution operation.

[0079]

[0080] OUT represents the result of the convolution operation, W i V represents the weight value. i Let be the voltage value of the sensor signal, and n be the number of SRAM arrays, i = 1, 2, 3, ..., N, where N is a positive integer.

[0081] On the other hand, the technical solution of this application also provides a data processing apparatus; which includes:

[0082] At least one processor; at least one memory for storing at least one program; when the at least one program is executed by the at least one processor, the at least one processor performs a data processing method as described in the first aspect.

[0083] This invention also provides a storage medium storing a corresponding executable program, which is executed by a processor to implement a data processing method as described in the first aspect.

[0084] From the above specific implementation process, it can be concluded that the technical solution provided by the present invention has the following advantages or strengths compared with the prior art:

[0085] This application proposes a sensor-oriented in-memory computing (CIM) convolutional computation acceleration architecture. Firstly, at the input level, the data processed by the CIM architecture is directly input from the sensor, eliminating the need for intermediate analog-to-digital (A / D) and digital-to-analog (D / A) conversion steps, significantly reducing data transmission hardware overhead, power consumption, and latency. Secondly, this application utilizes SRAM capable of storing three weights, effectively improving the accuracy of neural network algorithms. Furthermore, the CIM architecture overcomes the bottlenecks of traditional von Neumann architectures, directly performing multiply-accumulate (MAC) operations in SRAM memory, reducing latency and power consumption caused by data movement. The sensor-oriented in-memory computing (CIM) convolutional computation acceleration architecture designed in this patent is suitable as a hardware implementation architecture for convolutional operations in neural network algorithms, meeting the requirements of neural networks for reduced hardware implementation costs, including power consumption and hardware overhead, while providing high performance such as low latency and high bandwidth.

[0086] In some alternative embodiments, the functions / operations mentioned in the block diagrams may not occur in the order shown in the operation diagrams. For example, depending on the functions / operations involved, two consecutively shown blocks may actually be executed substantially simultaneously, or the blocks may sometimes be executed in reverse order. Furthermore, the embodiments presented and described in the flowcharts of this invention are provided by way of example to provide a more comprehensive understanding of the technology. The disclosed methods are not limited to the operations and logic flows presented herein. Alternative embodiments are contemplated in which the order of various operations is altered and sub-operations described as part of a larger operation are executed independently.

[0087] Furthermore, although the invention has been described in the context of functional modules, it should be understood that, unless otherwise stated, one or more of the functions and / or features may be integrated into a single physical device and / or software module, or one or more functions and / or features may be implemented in a separate physical device or software module. It is also understood that a detailed discussion of the actual implementation of each module is unnecessary for understanding the invention. Rather, given the properties, functions, and internal relationships of the various functional modules in the apparatus disclosed herein, the actual implementation of the module will be understood within the scope of conventional skill of an engineer. Therefore, those skilled in the art can implement the invention as set forth in the claims using ordinary techniques without excessive experimentation. It is also understood that the specific concepts disclosed are merely illustrative and not intended to limit the scope of the invention, which is determined by the full scope of the appended claims and their equivalents.

[0088] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus or device (such as a computer-based system, a processor-included system or other system that can fetch and execute instructions from, an instruction execution system, apparatus or device).

[0089] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0090] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

[0091] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A data processing method, characterized in that, Includes the following steps: Acquire sensor signals and send the sensor signals to the read lines of the SRAM array. The sensor signals are the voltage signals obtained by binarizing the pixels of the input feature map. Once the voltage value of the read bit line is stable, the read word line of the SRAM array is turned on; The weight values ​​of the sensor signals in the read character lines are obtained, and the sensor signals in the read bit lines are obtained. The weight values ​​and the sensor signals are multiplied together to obtain a first output voltage, which is then output to the shared bit line. The first output voltage is the voltage signal of a pixel in the output feature map. The first output voltage is converted to obtain the second output data, and the second output data is used to obtain the convolution operation result; The step of converting the first output voltage to obtain the second output data, and then obtaining the convolution operation result from the second output data, includes: The convolution operation result is obtained by subtracting the second output data in the first shared bit line from the second output data in the second shared bit line. The data processing method further includes the following steps: The first output voltage, which is positive and obtained through the multiplication operation, is stored in the first capacitor. The first output voltage, which is negative and obtained through the multiplication operation, is stored in the second capacitor.

2. The data processing method according to claim 1, characterized in that, The read bit line includes a first read bit line and a second read bit line. The step of obtaining the weight value of the sensor signal in the read bit line, obtaining the sensor signal in the read bit line, and performing a multiplication operation between the weight value and the sensor signal to obtain a first output voltage output to the shared bit line includes: When the weight value is determined to be a first value, the first transistor is turned off and the second transistor is turned on, and the sensor signal in the first read bit line is sent to the shared bit line. When the weight value is determined to be the second value, the first transistor is turned on and the second transistor is turned off, and the sensor signal in the second read bit line is sent to the shared bit line. The weight value is determined to be a third value. The first transistor is turned off, the second transistor is turned off, and the sensor signals in the first and second read bit lines are sent to the shared bit line.

3. The data processing method according to claim 1, characterized in that, The result of the convolution operation satisfies the following formula: Among them, the The result of the convolution operation. For weight values, The voltage value of the sensor signal. The number of SRAM arrays, , It is a positive integer.

4. A data processing system, characterized in that, The system includes: A sensor storage array is used to acquire sensor signals and send the sensor signals to the read lines of an SRAM array; the sensor signals are voltage signals obtained by binarizing the pixels of the input feature map. The readout calculation circuit is used to determine that the voltage value of the read bit line is stable, enable the read word line of the SRAM array, and obtain the weight value of the sensor signal in the read word line. The weight value and the sensor signal in the read bit line are multiplied to obtain a first output voltage, which is output to the shared bit line. The first output voltage is the voltage signal of the pixel in the output feature map. An analog-to-digital converter circuit is used to convert the first output voltage to obtain the second output data, and to subtract the second output data to obtain the convolution operation result; The step of converting the first output voltage to obtain the second output data, and then obtaining the convolution operation result from the second output data, includes: The convolution operation result is obtained by subtracting the second output data in the first shared bit line from the second output data in the second shared bit line. The data processing method further includes the following steps: The first output voltage, which is positive and obtained through the multiplication operation, is stored in the first capacitor. The first output voltage, which is negative and obtained through the multiplication operation, is stored in the second capacitor.

5. A data processing system according to claim 4, characterized in that, The sensor storage array is a ternary static random access memory; the ternary static random access memory includes a first ternary inverter and a second ternary inverter, the output of the first ternary inverter is connected to the input of the second ternary inverter; the output of the second ternary inverter is connected to the input of the first ternary inverter.

6. A data processing system according to claim 5, characterized in that, The first ternary inverter includes a thin-gate NMOS transistor, a thick-gate NMOS transistor, a thin-gate PMOS transistor, and a thick-gate PMOS transistor; When the input terminal of the first ternary inverter is a high-level signal, the thick-gate NMOS transistor and the thin-gate NMOS transistor are turned on, and the output terminal of the first ternary inverter is a low-level signal. When the input terminal of the first ternary inverter is a low-level signal, the thick-gate PMOS transistor and the thin-gate PMOS transistor are turned on, and the output terminal of the first ternary inverter is a high-level signal. When the input signal amplitude of the first ternary inverter is half the amplitude of the high-level signal, the thin-gate NMOS transistor and the thin-gate PMOS transistor are turned on, and the output signal amplitude of the first ternary inverter is half the amplitude of the high-level signal. The structure of the second ternary inverter is the same as that of the first ternary inverter.

7. A data processing apparatus, characterized in that, include: At least one processor; At least one memory for storing at least one program; When the at least one program is executed by the at least one processor, the at least one processor performs a data processing method as described in any one of claims 1-3.

8. A storage medium storing a processor-executable program, characterized in that, The processor-executable program, when executed by the processor, is used to run a data processing method as described in any one of claims 1-3.

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