A 12T TFET SRAM cell circuit with read-write separation

Abstract

The present invention discloses a read-write separated 12T TFET SRAM unit circuit, comprising eight NTFET transistors and four PTFET transistors, wherein PTFET transistor P3 and NTFET transistor N3 form an inverter, and PTFET transistor P4 and NTFET transistor N4 form another inverter; and PTFET transistors P1 and P2 are used as a pull-up circuit structure during write operation; NTFET transistors N1, N2, N5, and N6 constitute a write circuit part, which can eliminate the forward bias leakage current problem caused by the forward bias voltage when TFET is used as an SRAM transmission tube; NTFET transistors N7 and N8 constitute a read circuit part. The above circuit not only improves the write capability of the SRAM unit, but also eliminates the forward bias leakage current leakage problem when TFET is used as a transmission transistor of the SRAM unit.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a read-write separated 12T TFET (12-tube tunneling field effect transistor) SRAM unit circuit. Background Art

[0002] With the advent of the fourth industrial revolution, people's demand for low power consumption of integrated circuits has become increasingly strong. MOSFET devices constitute an important part of digital integrated circuit design and analog integrated circuit design. However, with the development of integrated circuit process nodes, some shortcomings of MOSFET in ultra-low power circuits make it difficult to obtain satisfactory results. Because the characteristic size of MOSFET continues to decrease with the proportional reduction rule, its subthreshold swing, current switching ratio and other performance deteriorate, and the static power consumption of the static random-access memory (SRAM) composed of it is high, which hinders its application in low-power devices. In addition, the subthreshold swing of MOSFET at room temperature is theoretically difficult to be less than 60mv / decade. In microprocessors, static random access memory (SRAM) occupies more than 50% of the chip area and consumes most of the static power consumption of the processor. Although many methods for reducing the static power consumption of SRAM at subthreshold voltages have been widely proposed, due to the above-mentioned shortcomings of MOSFET, further reducing static power consumption at subthreshold operating voltages is still very limited.

[0003] Compared with MOSFET, tunneling field effect transistor TFET has a lower subthreshold swing and a higher switching ratio, making TFET a promising alternative to MOSFET. However, in the existing technical solutions, due to the unidirectional conduction characteristics of TFET devices, when used as a transfer transistor of SRAM, as the operating voltage increases, the forward bias leakage current of TFET may cause the static power consumption of SRAM to increase by an order of magnitude. Summary of the invention

[0004] The object of the present invention is to provide a read-write separated 12T TFET SRAM cell circuit, which not only improves the write capability of the SRAM cell, but also eliminates the problem of forward bias leakage current leakage when the TFET is used as a transfer transistor of the SRAM cell, effectively reduces the static power consumption of the SRAM cell, and improves the retention noise margin and write capability of the SRAM.

[0005] The objective of the present invention is achieved through the following technical solutions:

[0006] A read-write separated 12T TFET SRAM unit circuit, the circuit comprises eight NTFET transistors and four PTFET transistors, the eight NTFET transistors are sequentially recorded as N1 to N8, and the four PTFET transistors are sequentially recorded as P1 to P4, wherein:

[0007] A power source VDD is electrically connected to the sources of the PTFET transistors P1 and P2;

[0008] The drain of the PTFET transistor P1 is electrically connected to the source of the PTFET transistor P3;

[0009] The drain of the PTFET transistor P2 is electrically connected to the source of the PTFET transistor P4;

[0010] The gate of the PTFET transistor P1 is electrically connected to the gate of the NTFET transistor N2;

[0011] The gate of the PTFET transistor P2 is electrically connected to the gate of the NTFET transistor N6;

[0012] The drain of the PTFET transistor P3 is electrically connected to the drain of the NTFET transistor N1, the drain of the NTFET transistor N3, the gate of the PTFET transistor P4, and the gate of the NTFET transistor N4;

[0013] The drain of PTFET transistor P4 is electrically connected to the drain of NTFET transistor N5, the drain of NTFET transistor N4, the gate of PTFET transistor P3, the gate of NTFET transistor N3, and the gate of NTFET transistor N8;

[0014] The source of NTFET transistor N1 is electrically connected to the drain of NTFET transistor N2;

[0015] The source of NTFET transistor N5 is electrically connected to the drain of NTFET transistor N6;

[0016] The source of NTFET transistor N7 is electrically connected to the drain of NTFET transistor N8;

[0017] The sources of the NTFET transistors N2, N3, N4, N6 and N8 are electrically connected to the ground line GND;

[0018] In addition, a write word line WL is electrically connected to the gates of the NTFET transistors N1 and N5 and the gate of the PTFET transistor P4;

[0019] The read word line RWL is electrically connected to the gate of the NTFET transistor N7;

[0020] The bit line BL is electrically connected to the gates of the PTFET transistor P1 and the NTFET transistor N2;

[0021] The bit line BLB is electrically connected to the gates of the PTFET transistor P2 and the NTFET transistor N6;

[0022] The read bit line RBL is electrically connected to the drain of the NTFET transistor N7;

[0023] Among them, the PTFET transistor P3 and the NTFET transistor N3 form an inverter, the PTFET transistor P4 and the NTFET transistor N4 form another inverter, and the two inverters form a latch circuit; and the PTFET transistors P1 and P2 serve as a pull-up circuit structure during a write operation;

[0024] NTFET transistors N1, N2, N5, and N6 form the write circuit part, which can eliminate the forward bias leakage current problem caused by the forward bias voltage when TFET is used as an SRAM transmission tube;

[0025] NTFET transistors N7 and N8 form part of the read circuit, which can improve the read capability and speed of the SRAM cell.

[0026] It can be seen from the technical solution provided by the present invention that the above circuit not only improves the write capability of the SRAM cell, but also eliminates the problem of forward bias leakage current leakage when the TFET is used as the transfer transistor of the SRAM cell, effectively reduces the static power consumption of the SRAM cell, and improves the retention noise margin and write capability of the SRAM. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0028] Figure 1 A schematic diagram of the overall structure of a 12T TFET SRAM unit circuit with read-write separation provided by an embodiment of the present invention;

[0029] Figure 2 is a working timing diagram of the circuit described in the embodiment of the present invention;

[0030] Figure 3 A data diagram comparing the holding margin of the circuit provided by the embodiment of the present invention with the holding margin of other units;

[0031] Figure 4 A data diagram comparing the write margin of the circuit provided by the embodiment of the present invention with the write margin of other units;

[0032] Figure 5 The storage data of the circuit provided by the embodiment of the present invention are static power consumption comparison data diagrams when Q=0 and Q=1 respectively. DETAILED DESCRIPTION

[0033] The following is a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments, which does not constitute a limitation of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0034] like Figure 1 The figure shows the overall structure of the read-write separation 12T TFET SRAM unit circuit provided by an embodiment of the present invention. The circuit includes eight NTFET transistors and four PTFET transistors. The eight NTFET transistors are sequentially denoted as N1 to N8, and the four PTFET transistors are sequentially denoted as P1 to P4, wherein:

[0035] A power source VDD is electrically connected to the sources of the PTFET transistors P1 and P2;

[0036] The drain of the PTFET transistor P1 is electrically connected to the source of the PTFET transistor P3;

[0037] The drain of the PTFET transistor P2 is electrically connected to the source of the PTFET transistor P4;

[0038] The gate of the PTFET transistor P1 is electrically connected to the gate of the NTFET transistor N2;

[0039] The gate of the PTFET transistor P2 is electrically connected to the gate of the NTFET transistor N6;

[0040] The drain of the PTFET transistor P3 is electrically connected to the drain of the NTFET transistor N1, the drain of the NTFET transistor N3, the gate of the PTFET transistor P4, and the gate of the NTFET transistor N4;

[0041] The drain of PTFET transistor P4 is electrically connected to the drain of NTFET transistor N5, the drain of NTFET transistor N4, the gate of PTFET transistor P3, the gate of NTFET transistor N3, and the gate of NTFET transistor N8;

[0042] The source of NTFET transistor N1 is electrically connected to the drain of NTFET transistor N2;

[0043] The source of NTFET transistor N5 is electrically connected to the drain of NTFET transistor N6;

[0044] The source of NTFET transistor N7 is electrically connected to the drain of NTFET transistor N8;

[0045] The sources of the NTFET transistors N2, N3, N4, N6 and N8 are electrically connected to the ground line GND;

[0046] In addition, a write word line WL is electrically connected to the gates of the NTFET transistors N1 and N5 and the gate of the PTFET transistor P4;

[0047] The read word line RWL is electrically connected to the gate of the NTFET transistor N7;

[0048] The bit line BL is electrically connected to the gates of the PTFET transistor P1 and the NTFET transistor N2;

[0049] The bit line BLB is electrically connected to the gates of the PTFET transistor P2 and the NTFET transistor N6;

[0050] The read bit line RBL is electrically connected to the drain of the NTFET transistor N7;

[0051] Based on the connection relationship of the above devices, PTFET transistor P3 and NTFET transistor N3 form an inverter, PTFET transistor P4 and NTFET transistor N4 form another inverter, and the two inverters form a latch circuit; and PTFET transistors P1 and P2 serve as a pull-up circuit structure during write operation;

[0052] NTFET transistors N1, N2, N5, and N6 constitute a write circuit part, which can eliminate the forward bias leakage current problem caused by the forward bias voltage when TFET is used as an SRAM transmission tube; in a specific implementation, NTFET transistors N2 and N6 are used to form a discharge path during a write operation, so as to achieve the purpose of improving the unit write capability when the SRAM unit is performing a write operation;

[0053] NTFET transistors N7 and N8 form part of the read circuit, which can improve the read capability and speed of the SRAM cell.

[0054] like Figure 2 The figure shows a working timing diagram of the circuit according to an embodiment of the present invention. In a specific implementation, based on the circuit:

[0055] In the hold state, the write word line WL and the read word line RWL are at a low level, the bit line BL and the bit line BLB are at a low level, the NTFET transistors N1, N2, N5, N6 and N7 are in a closed state, and the PTFET transistors P1 and P2 are turned on, so that the latch circuit composed of P3, P4, N3, and N4 is in a latched state, ensuring the stability of the SRAM cell in the hold state;

[0056] Since there will be no forward bias voltage in the transmission tube NTFET transistors N1, N2, N5, and N6 in the write circuit part, and there will be no forward bias voltage in the transmission tube NTFET transistors N7 and N8 in the read circuit part, the forward bias leakage current problem caused by TFET as the SRAM unit transmission tube can be effectively eliminated.

[0057] like Figure 2 As shown, based on the circuit:

[0058] In the write operation phase, it is assumed that the SRAM cell will perform a write 0 operation. At this time, the write word line WL is set to a high level, while the read word line RWL maintains the original state, that is, a low level, the bit line BL is set to a high level, and the bit line BLB maintains the original state, that is, a low level; at this time, the NTFET transistors N1 and N2 are turned on, the PTFET transistor P2 is turned on, the NTFET transistor N6 is turned off, and the PTFET transistor P1 is turned off. The power supply VDD charges the storage node QB through the PTFET transistors P2 and P4, so that the voltage of the storage node QB rises rapidly to a high level; the storage node Q is discharged to the ground through the NTFET transistors N1 and N2, causing the inverter composed of the PTFET transistor P3 and the NTFET transistor N3 to flip to 0. After the storage node Q is flipped, it will be fed back to another inverter composed of the PTFET transistor P4 and the NTFET transistor N4, so that the storage node QB is stabilized at a high level. When the storage node Q is pulled low and the storage node QB is pulled high, the write 0 operation is completed;

[0059] Assume that the SRAM cell will perform a write 1 operation, at this time, the write word line WL is set to a high level, while the read word line RWL remains in its original state, that is, a low level, the bit line BLB is set to a high level, and the bit line BL remains in its original state, that is, a low level; at this time, the NTFET transistors N5 and N6 are turned on, the PTFET transistor P1 is turned on, the NTFET transistor N2 is turned off, and the PTFET transistor P2 is turned off. The power supply VDD charges the storage node Q through the PTFET transistors P1 and P3, so that the voltage of the storage node Q rises rapidly to a high level; the storage node QB is discharged to the ground through the NTFET transistors N5 and N6, causing the inverter composed of the PTFET transistor P4 and the NTFET transistor N4 to flip to 0. After the storage node QB flips, it will be fed back to another inverter composed of the PTFET transistor P3 and the NTFET transistor N3, so that the storage node Q is stabilized at a high level; when the storage node Q is pulled high and the storage node QB is pulled low, the write 1 operation is completed.

[0060] By setting the above-mentioned writing operation charging and discharging path, the writing capability and writing margin of the SRAM unit are greatly improved; when the writing operation is completed, the writing word line WL is set to a low level, the storage nodes Q and QB store opposite values, and the two inverters restore the latched state to ensure the stability of the SRAM unit.

[0061] In addition, if Figure 2 As shown, based on the circuit:

[0062] In the read operation phase, when the SRAM cell performs a read operation, the read bit line RBL is first precharged to a high level, the write word line WL remains in its original state, the bit lines BL and BLB remain in their original states, and the read word line RWL where the cell to be read is located is set to a high level;

[0063] Assume that the data stored in the storage node Q of the SRAM cell is "0". Since the voltage of the storage node Q is "0" and the voltage of the storage node QB is "1", the NTFET transistor N8 is turned on. At the same time, since the read word line RWL is at a high level, the NTFET transistor N7 is also in an on state, and the read bit line RBL is discharged to a low level through the NTFET transistors N7 and N8. The sensitive amplifier SA in the SRAM cell array detects the change in the level of the read bit line RBL. When the voltage of the read bit line RBL is lower than the reference voltage value, the data "0" stored in the SRAM cell is read.

[0064] Assume that the data stored in the storage node Q of the SRAM cell is "1". Since the voltage of the storage node Q is "1" and the voltage of the storage node QB is "0", the NTFET transistor N8 is turned off. Since the read word line RWL is at a high level, the NTFET transistor N7 is in an on state. Since the NTFET transistor N8 is in an off state, the read bit line RBL cannot be discharged to a low level through the NTFET transistors N7 and N8. The sensitive amplifier SA in the SRAM cell array detects that the level of the read bit line RBL has not changed to be lower than the reference voltage value, thereby realizing the reading of the data "1" stored in the SRAM cell.

[0065] In order to more clearly demonstrate the scheme of the circuit described in the embodiment of the present invention and the technical effect produced, the performance of the 12T TFET SRAM cell provided by the embodiment of the present invention is compared with other TFET SRAM cells in conjunction with the accompanying drawings, as follows:

[0066] (1) Figure 3The figure shows a data diagram comparing the retention margin of the circuit provided by the embodiment of the present invention with the retention margin of other units, and the figure shows the retention static noise margin (HSNM) of four TFET SRAM units. According to the experimental simulation results, the structure of the unit circuit proposed by the embodiment of the present invention has a strong retention stability. When the driving voltage is greater than 0.6V, the retention static noise margin of the 6T O-AT unit will gradually decrease. This is because the forward bias leakage current of its two transmission transistors is very large, which seriously affects the stability of the 6T O-AT structure. The 8T DP structure has the same problem as the 6T O-AT, that is, the forward bias leakage current of its transmission transistor is very large under high operating voltage, which seriously affects the stability of the storage unit in the retention state. Because the access transistor of the 12TTFET SRAM unit circuit proposed by the present invention will not have a forward bias leakage current problem in the retention state, it will not cause voltage fluctuations at the storage points Q and QB, so even under high voltage working conditions, it still has a larger retention noise margin than other units.

[0067] (2) Figure 4 The figure shows the comparison data of the write margin of the circuit provided by the embodiment of the present invention and the write margin of other cells. The figure shows the comparison of the write noise tolerance of four TFET SRAM cells. The write noise tolerance is obtained from the VTC curve. According to the experimental simulation results, Figure 4 It can be seen that the SRAM cell proposed in the embodiment of the present invention has a larger write margin than other cell structures. This is because the structure proposed in the present invention adopts a parallel operation of opening the charging and discharging paths of the pull-up tubes during the write operation, which improves the write capability and does not affect the retention state of other cells. Since the write coupling part of the 6T O-AT structure and the 8T DP structure is the same, they have the same write margin.

[0068] (3) Figure 5 The figure shows a static power consumption comparison data diagram of the circuit provided by the embodiment of the present invention when the storage data are Q=0 and Q=1 respectively. Figure 5 The static power consumption of the 12T TFET SRAM cell in the hold state is shown. According to the experimental simulation results, as the operating voltage increases, the forward bias voltage of the access transistor gradually increases in the hold state. The static power consumption of the SRAM cell increases by an order of magnitude without eliminating the forward bias voltage. However, the 12T TFET SRAM cell proposed by the present invention eliminates the TFET forward bias phenomenon, and there is no positive leakage current in the transmission tube transistor in the hold state. Therefore, as the driving voltage increases, even at 0.8V, the static power consumption of the storage cell will not increase too much.

[0069] It is worth noting that the contents not described in detail in the embodiments of the present invention belong to the prior art known to professional and technical personnel in the field.

[0070] In summary, the read-write separation 12T TFET SRAM unit circuit provided by the embodiment of the present invention solves the problem of increased static power consumption caused by forward bias leakage current when TFET is used as an SRAM transmission tube, and at the same time improves the write margin of the SRAM unit and maintains the static noise margin. For example, when the operating voltage is 0.4V-0.8V, its static power consumption is only 122pw-442pw, and the write margin and stability of the TFET SRAM unit are improved.

[0071] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with the technical field within the technical scope disclosed in the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims. The information disclosed in the background technology section of this article is only intended to deepen the understanding of the overall background technology of the present invention, and should not be regarded as an admission or in any form that the information constitutes prior art known to those skilled in the art.

Claims

1. A read-write separated 12T TFET SRAM cell circuit, characterized in that: The circuit includes eight NTFET transistors and four PTFET transistors, the eight NTFET transistors are sequentially denoted as N1 to N8, and the four PTFET transistors are sequentially denoted as P1 to P4, wherein: A power source VDD is electrically connected to the sources of the PTFET transistors P1 and P2; The drain of the PTFET transistor P1 is electrically connected to the source of the PTFET transistor P3; The drain of the PTFET transistor P2 is electrically connected to the source of the PTFET transistor P4; The gate of the PTFET transistor P1 is electrically connected to the gate of the NTFET transistor N2; The gate of the PTFET transistor P2 is electrically connected to the gate of the NTFET transistor N6; The drain of the PTFET transistor P3 is electrically connected to the drain of the NTFET transistor N1, the drain of the NTFET transistor N3, the gate of the PTFET transistor P4, and the gate of the NTFET transistor N4; The drain of PTFET transistor P4 is electrically connected to the drain of NTFET transistor N5, the drain of NTFET transistor N4, the gate of PTFET transistor P3, the gate of NTFET transistor N3, and the gate of NTFET transistor N8; The source of NTFET transistor N1 is electrically connected to the drain of NTFET transistor N2; The source of NTFET transistor N5 is electrically connected to the drain of NTFET transistor N6; The source of NTFET transistor N7 is electrically connected to the drain of NTFET transistor N8; The sources of the NTFET transistors N2, N3, N4, N6 and N8 are electrically connected to the ground line GND; In addition, a write word line WL is electrically connected to the gates of the NTFET transistors N1 and N5 and the gate of the PTFET transistor P4; The read word line RWL is electrically connected to the gate of the NTFET transistor N7; The bit line BL is electrically connected to the gates of the PTFET transistor P1 and the NTFET transistor N2; The bit line BLB is electrically connected to the gates of the PTFET transistor P2 and the NTFET transistor N6; The read bit line RBL is electrically connected to the drain of the NTFET transistor N7; Among them, the PTFET transistor P3 and the NTFET transistor N3 form an inverter, the PTFET transistor P4 and the NTFET transistor N4 form another inverter, and the two inverters form a latch circuit; and the PTFET transistors P1 and P2 serve as a pull-up circuit structure during a write operation; NTFET transistors N1, N2, N5, and N6 constitute the write circuit part, which can eliminate the forward bias leakage current problem caused by the forward bias voltage when TFET is used as an SRAM transmission tube; NTFET transistors N7 and N8 form part of the read circuit, which can improve the read capability and speed of the SRAM cell.

2. The read-write separated 12T TFET SRAM unit circuit according to claim 1, characterized in that: Based on the circuit: In the hold state, the write word line WL and the read word line RWL are at a low level, the bit line BL and the bit line BLB are at a low level, the NTFET transistors N1, N2, N5, N6 and N7 are in a closed state, and the PTFET transistors P1 and P2 are turned on, so that the latch circuit composed of P3, P4, N3, and N4 is in a latched state, ensuring the stability of the SRAM cell in the hold state; Since there will be no forward bias voltage in the transmission tube NTFET transistors N1, N2, N5, and N6 in the write circuit part, and there will be no forward bias voltage in the transmission tube NTFET transistors N7 and N8 in the read circuit part, the forward bias leakage current problem caused by TFET as the SRAM unit transmission tube can be effectively eliminated.

3. The read-write separated 12T TFET SRAM unit circuit according to claim 1, characterized in that: Based on the circuit: In the write operation phase, it is assumed that the SRAM cell will perform a write 0 operation. At this time, the write word line WL is set to a high level, while the read word line RWL maintains the original state, that is, a low level, the bit line BL is set to a high level, and the bit line BLB maintains the original state, that is, a low level; at this time, the NTFET transistors N1 and N2 are turned on, the PTFET transistor P2 is turned on, the NTFET transistor N6 is turned off, and the PTFET transistor P1 is turned off. The power supply VDD charges the storage node QB through the PTFET transistors P2 and P4, so that the voltage of the storage node QB rises rapidly to a high level; the storage node Q is discharged to the ground through the NTFET transistors N1 and N2, causing the inverter composed of the PTFET transistor P3 and the NTFET transistor N3 to flip to 0. After the storage node Q is flipped, it will be fed back to another inverter composed of the PTFET transistor P4 and the NTFET transistor N4, so that the storage node QB is stabilized at a high level. When the storage node Q is pulled low and the storage node QB is pulled high, the write 0 operation is completed; Assume that the SRAM cell will perform a write 1 operation, at this time, the write word line WL is set to a high level, while the read word line RWL remains in its original state, that is, a low level, the bit line BLB is set to a high level, and the bit line BL remains in its original state, that is, a low level; at this time, the NTFET transistors N5 and N6 are turned on, the PTFET transistor P1 is turned on, the NTFET transistor N2 is turned off, and the PTFET transistor P2 is turned off. The power supply VDD charges the storage node Q through the PTFET transistors P1 and P3, so that the voltage of the storage node Q rises rapidly to a high level; the storage node QB is discharged to the ground through the NTFET transistors N5 and N6, causing the inverter composed of the PTFET transistor P4 and the NTFET transistor N4 to flip to 0, and after the storage node QB flips, it will be fed back to another inverter composed of the PTFET transistor P3 and the NTFET transistor N3, so that the storage node Q is stabilized at a high level; When the storage node Q is pulled high and the storage node QB is pulled low, the write 1 operation is completed; When the write operation is completed, the write word line WL is set to a low level, the PTFET transistors P3 and P4 are turned on, and the two inverters resume the latched state to ensure the stability of the SRAM unit.

4. The read-write separated 12T TFET SRAM unit circuit according to claim 1, characterized in that: Based on the circuit: In the read operation phase, when the SRAM cell performs a read operation, the read bit line RBL is first precharged to a high level, the write word line WL remains in its original state, the bit lines BL and BLB remain in their original states, and the read word line RWL where the cell to be read is located is set to a high level; Assuming that the data stored in the storage node Q of the SRAM cell is "0", since the voltage of the storage node Q is "0" and the voltage of the storage node QB is "1", the NTFET transistor N8 is turned on, and since the read word line RWL is at a high level, the NTFET transistor N7 is also in an on state, and the read bit line RBL is discharged to a low level through the NTFET transistors N7 and N8; the sensitive amplifier SA in the SRAM cell array detects the change in the level of the read bit line RBL, and when the voltage of the read bit line RBL is lower than the reference voltage value, the data "0" stored in the SRAM cell is read; Assume that the data stored in the storage node Q of the SRAM cell is "1". Since the voltage of the storage node Q is "1" and the voltage of the storage node QB is "0", the NTFET transistor N8 is turned off. Since the read word line RWL is at a high level, the NTFET transistor N7 is turned on. Since the NTFET transistor N8 is turned off, the read bit line RBL cannot be discharged to a low level through the NTFET transistors N7 and N8. The sense amplifier SA in the SRAM cell array detects that the level of the read bit line RBL has not changed to be lower than the reference voltage value, thereby realizing the reading of the data "1" stored in the SRAM cell.

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