Three-dimensional ferroelectric memory with igzo channel and method of fabrication

Abstract

This application relates to the field of in-memory computing memory technology, and more particularly to a three-dimensional ferroelectric memory with an IGZO channel and its fabrication method. The three-dimensional ferroelectric memory with an IGZO channel includes: a bottom global gate line; a center select gate extending vertically relative to the bottom global gate line; a semiconductor stack structure including a gate metal layer, a ferroelectric layer, a gate oxide layer, and an IGZO channel sequentially surrounding the center select gate; a drain and a source extending horizontally relative to the center select gate into the semiconductor stack structure and contacting the ferroelectric layer; and multiple pairs of drains and sources spaced apart along the extension direction of the center select gate to form multiple ferroelectric memory transistor cells. The three-dimensional ferroelectric memory with an IGZO channel of this application improves the durability and reliability of non-volatile memory devices.

Description

Technical Field

[0001] This application relates to the field of in-memory computing memory technology, and in particular to a three-dimensional ferroelectric memory with an IGZO channel and its fabrication method. Background Technology

[0002] In the fields of artificial intelligence (AI) and high-performance computing, the access speed and durability of memory directly affect the overall computing efficiency of the system. High-bandwidth flash memory (HBF), as an emerging non-volatile memory architecture, aims to provide high-speed read and write capabilities close to dynamic random access memory (DRAM) while maintaining the non-volatility and high-density advantages of flash memory.

[0003] However, the inherent operating mechanism of current mainstream non-volatile memory, especially 3D NAND flash memory, severely hinders its application in high-bandwidth flash memory. 3D NAND uses block erase as the basic operation unit, meaning that when erasing any memory cell, the entire physical block containing that cell must be erased at once, making it impossible to achieve independent bit-level or page-level erasure.

[0004] This mechanism leads to two interconnected technical drawbacks: First, before each erase operation, the valid data within the block needs to be migrated to other locations, resulting in a significant write amplification effect, which greatly extends the average access time, usually far exceeding the 50 nanosecond level required by high-speed applications; Second, frequent block erase operations accelerate the aging of the storage medium, which limits the durability cycle count of 3D NAND to several thousand to tens of thousands of cycles, making it difficult to meet the application scenarios in AI accelerators and edge computing devices that require continuous high-speed data updates. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the purpose of this application is to provide a three-dimensional ferroelectric memory with IGZO channels and its fabrication method, thereby improving the durability and reliability of non-volatile memory devices.

[0006] To achieve the above objectives, this application provides a three-dimensional ferroelectric memory with an IGZO channel, comprising: Bottom global grid; A center selection gate is provided, extending in a direction perpendicular to the bottom global gate line; A semiconductor stacked structure, the semiconductor stacked structure comprising a gate metal layer, a ferroelectric layer, a gate oxide layer and an IGZO channel sequentially surrounding the central selected gate; The drain and source electrodes extend in the semiconductor stacked structure and contact the ferroelectric layer in a horizontal direction relative to the center selection gate. Multiple pairs of drain and source electrodes are arranged at intervals along the extension direction of the center selection gate, thereby forming multiple ferroelectric memory transistor cells.

[0007] Furthermore, the ferroelectric layer is composed of doped... The ferroelectric material is formed by selecting one or more of Si, Zr, Al, La, Y, Sr, Gd, Nb, Ni, and Ta as the dopant.

[0008] Furthermore, the ferroelectric layer is The x ranges from 0.02 to 0.05, the y ranges from 1.8 to 2.2, and the thickness ranges from 5 nm to 15 nm.

[0009] Furthermore, the ferroelectric layer is The range of x is 0.4 to 0.6, the range of y is 1.8 to 2.2, and the thickness is 5 nm to 15 nm.

[0010] Furthermore, the gate oxide layer is or The thickness is less than 20nm.

[0011] Furthermore, the thickness of the IGZO channel is 5 nm to 20 nm.

[0012] Furthermore, the drain and source electrodes each comprise N+IGZO; one end of the N+IGZO extends into the semiconductor stacked structure and contacts the ferroelectric layer, while the other end is filled with a contact metal and tungsten.

[0013] Furthermore, the gate metal layer comprises any one of molybdenum, aluminum, or copper.

[0014] Furthermore, the three-dimensional ferroelectric memory is one of a plurality of three-dimensional ferroelectric memories in a memory array, wherein the memory array is in a stepped configuration, the stepped configuration providing electrical contact with each of the source or drain.

[0015] To achieve the above objectives, this application also provides a method for fabricating a three-dimensional ferroelectric memory with an IGZO channel, comprising the following steps: A bottom global gate line is formed, and a bottom stop layer is etched and patterned above the bottom global gate line; A predetermined number of alternating layers of intermediate insulating material and first dielectric material are formed; Etching downwards from the top to the bottom stop layer forms multiple memory channels; An IGZO channel, a gate oxide layer, a ferroelectric layer, a gate metal layer, and a center select gate are sequentially formed in the memory channel. Form a top isolation layer; An isolation groove is formed, wherein the isolation grooves are spaced apart from adjacent memory channels; A trench is formed by removing the first dielectric material and the IGZO channel, gate oxide layer and part of the ferroelectric layer between the first dielectric material and the gate metal layer through an isolation trench. N+IGZO is deposited and annealed in the trench, and then contact metal and tungsten are deposited sequentially to form the source or drain. The isolation tank is filled with oxide.

[0016] Furthermore, the specific steps of sequentially forming an IGZO channel, a gate oxide layer, a ferroelectric layer, a gate metal layer, and a center selection gate in the memory channel include: In the memory channel, IGZO channel, gate oxide layer and protective layer are sequentially deposited and etched to form the memory channel; Remove the protective layer, deposit a ferroelectric layer in the memory channel, and etch it through the bottom stop layer; Etch memory channels down to the bottom global gate line, deposit gate metal to form a gate metal layer, and then perform bottom etching; A central selection gate is formed by deposition in the memory channel.

[0017] Furthermore, both the IGZO channel and the N+IGZO are formed using atomic layer deposition (ALD) at a deposition temperature of 150°C to 300°C.

[0018] Furthermore, the indium precursor used in the ALD process is InCp or Gallium precursor is The zinc precursor is diethylzinc (DEZn), and the oxidant is... .

[0019] Furthermore, the ferroelectric layer is formed using an atomic layer deposition (ALD) process, wherein or The deposition was achieved through alternating lamination layers at temperatures ranging from 150°C to 400°C.

[0020] To achieve the above objectives, this application also provides a memory array comprising a plurality of three-dimensional ferroelectric memories with IGZO channels arranged in an array as described above.

[0021] The three-dimensional ferroelectric memory with an IGZO channel provided in this application uses IGZO as the channel material, and its off-state leakage current... Compared to traditional polysilicon (Poly-Si) channels This represents a reduction of approximately three orders of magnitude. The extremely low leakage current significantly reduces static power consumption and bit line leakage in the memory array, facilitating high-density integration and low-power operation.

[0022] The 3D ferroelectric memory with IGZO channel provided in this application benefits from the high electron mobility of the IGZO channel and its excellent interface characteristics with ferroelectric materials. The power consumption of the ferroelectric memory transistor cell in this application during programming operations is only 40% to 60% of that of the traditional polysilicon channel solution, meaning that programming power consumption is reduced by more than 40%. This advantage makes the 3D ferroelectric memory of this application particularly suitable for AI edge computing and mobile terminal devices with stringent energy efficiency requirements.

[0023] The 3D ferroelectric memory with IGZO channel provided in this application is fabricated using atomic layer deposition (ALD) at a low temperature of 250°C to 400°C, while traditional polysilicon channels require high-temperature annealing at 900°C to 1000°C. High-temperature processes significantly reduce the ferroelectric layer (e.g., ... The remanent polarization intensity ( This leads to a reduction in the memory window; the low-temperature process of this application can keep the residual polarization of the ferroelectric layer essentially unchanged, thereby avoiding the depolarization effect of ferroelectric materials and ensuring the long-term reliability and data retention capability of the memory device.

[0024] The IGZO channel three-dimensional ferroelectric memory provided in this application adopts a three-dimensional vertical structure, which breaks through the integration limit of planar structure and enables the design of high-density, large-capacity ferroelectric memory.

[0025] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing this application. Attached Figure Description

[0026] The accompanying drawings are provided to further illustrate the present application and form part of the specification. Together with the embodiments of the present application, they serve to explain the present application but do not constitute a limitation thereof. In the drawings: Figure 1 This is a schematic diagram of the structure of a three-dimensional vertical ferroelectric memory with IGZO channels according to Embodiment 1 of this application; Figure 2 for Figure 1 A schematic diagram of the structure of a China Railway Electric Power memory transistor unit; Figure 3 A schematic diagram of the polarization voltage waveform for a three-dimensional ferroelectric memory with an IGZO channel; Figure 4 This is a programming diagram of the ferroelectric memory transistor cell of this application; Figure 5This is a schematic diagram of erasing the ferroelectric storage transistor cell of this application; Figure 6 This is a schematic diagram of the reading of the ferroelectric memory transistor cell of this application; Figure 7 This is a transfer characteristic curve of the ferroelectric memory transistor cell in this application; Figure 8 This is a schematic flowchart of the fabrication method of the IGZO channel three-dimensional ferroelectric memory in Embodiment 2 of this application; Figures 9-22 This is a schematic diagram of the structure of the three-dimensional ferroelectric memory with IGZO channel during the manufacturing process of Embodiment 2 of this application; Figure 23 This is a schematic diagram of the memory array structure of Embodiment 3 of this application; Figure 24 This is a voltage diagram of an unselected row cell in the memory array during the programming process. Figure 25 This is a schematic diagram showing the voltage of unselected column cells in the memory array during the programming process. Figure 26 This is a schematic diagram of the voltage of unselected row and column cells in the memory array during the programming process; Figure 27 This is a schematic diagram showing the voltage of unselected row cells in the memory array during the erasure process; Figure 28 This is a schematic diagram showing the voltage of unselected column cells in the memory array during the erase process. Figure 29 This is a schematic diagram showing the voltage of unselected row and column cells in the memory array during the erasure process; Figure label: 100-Bottom global gate line, 101-Bottom oxide layer, 102-Bottom stop layer, 103-Intermediate oxide layer, 104-Source line, 105-Drain line, 106-Top isolation layer, 200-Ferroelectric memory transistor cell, 201-IGZO channel, 202-Gate oxide layer, 203-Ferroelectric layer, 204-Gate metal layer, 205-Center select gate, 206-N+IGZO, 207-Contact metal, 208-W layer, 301-Oxide layer, 302-SiN layer, 400-Memory channel, 500-Protective layer, 600-Isolation trench, 700-Isolation oxide layer. Detailed Implementation

[0027] The preferred embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit this application.

[0028] Embodiments of this application will now be described in more detail with reference to the accompanying drawings. While some embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this application. It should be understood that the drawings and embodiments of this application are for illustrative purposes only and are not intended to limit the scope of protection of this application.

[0029] The term "comprising" and its variations as used herein are open-ended inclusions, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below.

[0030] It should be noted that the terms "first" and "second" may be used in this application only to distinguish different devices, components or parts, and are not used to define the order of functions performed by these devices, components or parts or their interdependence.

[0031] It should be noted that the terms "one" and "more" used in this application are illustrative rather than restrictive, and those skilled in the art should understand that, unless explicitly stated otherwise in the context, they should be understood as "one or more". "More" should be understood as two or more.

[0032] Example 1 In Embodiment 1 of this application, a three-dimensional ferroelectric memory with an IGZO channel is provided. Figure 1 This is a schematic diagram of the structure of the IGZO channel three-dimensional ferroelectric memory of Embodiment 1 of this application, as shown below. Figure 1 As shown, the IGZO channel three-dimensional ferroelectric memory of this application includes: A bottom global gate line 100 is formed, a bottom oxide layer 101 is formed on the bottom global gate line 100, an intermediate oxide layer 103 is formed on the bottom oxide layer 101, and a bottom stop layer 102 is patterned on the intermediate oxide layer 103. The center selection gate 205 extends in a vertical direction relative to the bottom global gate line 100, passes through the bottom stop layer 102 and the bottom oxide layer 101, and is connected to the bottom global gate line 100. A semiconductor stacked structure is provided, wherein the semiconductor stacked structure is arranged around the central selection gate 205 to form a plurality of ferroelectric memory transistor units 200.

[0033] Figure 2 for Figure 1 A schematic diagram of the structure of the CRRC Electric memory transistor unit is shown below. Figure 1 and Figure 2 As shown, the semiconductor stacked structure includes: a gate metal layer 204, a ferroelectric layer 203, a gate oxide layer 202, and an IGZO channel 201 that sequentially surround the center selected gate 205; Drain 105 and source 104 extend in a horizontal direction relative to the center select gate 205 into the semiconductor stack structure and contact the ferroelectric layer 203. The drain and source are arranged in pairs at intervals along the extension direction of the center select gate 205 to form a plurality of ferroelectric memory transistor cells 200. The bottom global gate line 220 is connected to the center select gate 210 via gate contact 219.

[0034] like Figure 1 and Figure 2 As shown, a three-dimensional ferroelectric memory with an IGZO channel includes multiple ring drains and multiple ring sources surrounding a central select gate 205. A pair of adjacent ring sources and the ring sources together with the central select gate and the semiconductor stack-up structure constitute a ferroelectric memory transistor cell 200. The top of the IGZO channel three-dimensional ferroelectric memory is also provided with a top isolation layer 106 to achieve electrical isolation.

[0035] In the embodiments of this application, the drain and source electrodes each comprise N+IGZO206; one end of the N+IGZO206 extends into the semiconductor stacked structure and contacts the ferroelectric layer 203, and the other end is filled with contact metal 207 and tungsten, the contact metal comprising ITO / Mo / Ti.

[0036] In embodiments of this application, the ferroelectric layer 203 is composed of doped... The ferroelectric material is formed by selecting one or more of Si, Zr, Al, La, Y, Sr, Gd, Nb, Ni, and Ta as the dopant.

[0037] In the embodiments of this application, the ferroelectric layer 203 is The x ranges from 0.02 to 0.05, the y ranges from 1.8 to 2.2, and the thickness ranges from 5 nm to 15 nm.

[0038] In other embodiments, the ferroelectric layer 203 is The range of x is 0.4 to 0.6, the range of y is 1.8 to 2.2, and the thickness is 5 nm to 15 nm.

[0039] In embodiments of this application, the gate metal layer 204 comprises any one of molybdenum, aluminum, or copper.

[0040] In the embodiments of this application, the thickness of the IGZO channel 201 is 5 nm to 20 nm.

[0041] like Figure 1 As shown, Figure 1 A three-dimensional ferroelectric memory with three IGZO channels is shown. Multiple ferroelectric storage transistor cells 200 are formed on each of the three three-dimensional ferroelectric memories. The three three-dimensional ferroelectric memories share the same bottom global gate line 100.

[0042] Figure 3 This is a schematic diagram of the polarization voltage waveform of a three-dimensional ferroelectric memory with an IGZO channel, as shown below. Figure 3 As shown, the positive switching polarization voltage of the three-dimensional ferroelectric memory is +1.5V, and the negative switching polarization voltage is -1.5V.

[0043] like Figure 4 As shown in the embodiments of this application, when it is desired to program the selected ferroelectric memory transistor cell, the source voltage and drain voltage of the selected ferroelectric memory transistor cell are configured to be 0V by the source line corresponding to the source 104 and the drain line corresponding to the source 105, and the gate-source voltage is configured to be a programming voltage of 6~7V by the bottom global gate line.

[0044] like Figure 5 As shown in the embodiments of this application, when it is desired to erase a selected ferroelectric storage transistor cell, the source voltage and drain voltage of the selected ferroelectric storage transistor cell are configured to be 6~7V through the source line and drain line, and the gate-source voltage is configured to be 0V through the bottom global gate line for erasure.

[0045] like Figure 6 As shown in the embodiments of this application, when it is desired to read the selected ferroelectric memory transistor cell, the drain voltage of the selected ferroelectric memory transistor cell is configured to be 0.05-0.2VDD voltage through the source line 104 and the drain line 105, the source voltage is configured to be 0V, and the gate-source voltage is configured to be 0-0.5V read voltage through the bottom global gate line.

[0046] In embodiments of this application, a stepped configuration used in 3D NAND non-volatile memory arrays is also used to connect the drain or source electrodes. The stepped structure provides electrical contact or connection to the drain or source electrodes, and global gate lines are used to provide contact or connection to the center select gate. The stepped configuration and associated manufacturing methods are known to those skilled in the art.

[0047] like Figure 7 As shown, Figure 7 This is a transfer characteristic curve of the ferroelectric memory transistor cell of this application. The horizontal axis in the figure represents the gate voltage. (Unit: V), vertical axis represents drain current. (Unit: A, logarithmic coordinates), test condition is drain-source voltage The red curve represents the read result after the ferroelectric layer undergoes a +3V polarization operation. At this point, the residual polarization of the ferroelectric layer makes the channel more conductive, shifting the threshold voltage to the left. The green curve represents the read result after the ferroelectric layer undergoes a -3V polarization operation. At this point, the residual polarization direction is reversed, shifting the threshold voltage to the right. The horizontal distance between the two curves is the memory window of the ferroelectric memory, reflecting the ability of the residual polarization of the ferroelectric layer to regulate the threshold voltage. This is a core feature of ferroelectric memory transistors in achieving non-volatile data storage.

[0048] Example 2 Example 2 of the application also provides a method for fabricating a three-dimensional ferroelectric memory with an IGZO channel. Figure 8 This is a schematic flowchart illustrating the fabrication method of the IGZO channel three-dimensional ferroelectric memory according to Embodiment 2 of this application. The following will refer to... Figure 8 The fabrication method of the IGZO channel three-dimensional ferroelectric memory of Embodiment 2 of this application is described in detail below: Step 101: Form the bottom global gate line, and form and pattern the bottom stop layer above the bottom global gate line; In this embodiment, based on the desired location and number of three-dimensional ferroelectric memories, a bottom global gate line 100 is formed, and a patterned bottom stop layer 21 is formed at the corresponding position on the bottom oxide layer 101 on the bottom global gate line 100, such as... Figure 9 and Figure 10 As shown.

[0049] Step 102: Form a predetermined number of alternating layers of intermediate insulating material and first dielectric material; In this embodiment, the number of alternating oxide layers 301 and SiN layers 302 corresponds to the number of ferroelectric memory transistor cells to be fabricated. The oxide layer 301 serves as an isolation layer, and the SiN layer 302 serves as the first dielectric material. Figure 11 As shown.

[0050] In step 103, the bottom stop layer is etched downwards from the top to form a plurality of memory channels; In this embodiment, a memory channel 400 is formed by etching to the bottom stop layer using a high aspect ratio, such as... Figure 12 As shown, Figure 12 The right image is Figure 12 The left image shows the horizontal structure diagram.

[0051] Step 104: In the memory channel 400, an IGZO channel, a gate oxide layer, a ferroelectric layer, a gate metal layer and a center selection gate are formed sequentially. First, an IGZO channel 201, a gate oxide layer 202, and a protective layer 500 are conformally deposited and etched on the surface, such as... Figure 13 As shown; The material of the protective layer 500 is selected from silicon nitride (SiN) and silicon dioxide (SiN). ), aluminum oxide ( The material can be either titanium oxide (TiN) or titanium nitride (TiN). The main purpose of the deposited protective layer 500 includes protecting the underlying gate oxide layer 202 and device structure during subsequent etching and patterning processes, serving as an etch stop layer, a moisture barrier, a mechanical protection layer, and providing isolation protection during spacer formation. Then, a spacer etch process is performed to remove the bottom film to form the gate sidewall spacer and remove excess protective layer material located on the top horizontal surface, the bottom of the trench, and the source / drain regions. After this etching process, only the sidewall spacer material on both sides of the gate remains, thereby exposing the source / drain regions for subsequent processes such as ferroelectric layer deposition.

[0052] Then, the protective layer 500 is removed, a ferroelectric layer 203 is deposited in the memory channel 400, and etched through to the bottom stop layer 102, as shown. Figure 14 As shown; Next, the memory channel 400 is etched down to the bottom global gate line 100, gate metal is deposited to form the gate metal layer 204, and bottom etching is performed, such as... Figure 15 and Figure 16 As shown.

[0053] Finally, a centrally selected gate 205 is deposited in the memory channel 400, such as... Figure 17 As shown.

[0054] Ferroelectric layer 203 can be formed by doping The ferroelectric material is formed by selecting one or more of Si, Zr, Al, La, Y, Sr, Gd, Nb, Ni, and Ta as the dopant.

[0055] In this embodiment, the ferroelectric layer 203 is formed using an atomic layer deposition (ALD) process, wherein and The deposition was achieved through alternating lamination layers at temperatures ranging from 150°C to 400°C.

[0056] In the embodiments of this application, the ferroelectric layer 203 is Where x ranges from 0.02 to 0.05, y ranges from 1.8 to 2.2, and the thickness ranges from 5 nm to 15 nm. The precursor can be tetra(ethylmethylamino)hafnium (TEMAH), tetra(dimethylamino)hafnium (TDMAH), or hafnium tetrachloride (TDMAH). ), The precursor can be tetra(dimethylamino)silane (4DMAS), tri(dimethylamino)silane (3DMAS), tetra(ethylmethylamino)silane (TEMA-Si), or silicon tetrachloride ( ).

[0057] In other embodiments, the ferroelectric layer 203 is Where x ranges from 0.4 to 0.6, y ranges from 1.8 to 2.2, and the thickness ranges from 5 nm to 15 nm. The precursor can be TEMAH, TDMAH or . The precursor can be tetra(ethylmethylamino)zirconium (TEMAZ), tetra(dimethylamino)zirconium (TDMAZ), or zirconium tetrachloride (Zr). ).

[0058] In embodiments of this application, the gate metal layer 204 comprises any one of molybdenum, aluminum, or copper.

[0059] In the embodiments of this application, the thickness of the IGZO channel 201 is 5 nm to 20 nm, and the growth rate is about 0.1–1 Å / cycle.

[0060] Step S105: Form a top isolation layer and etch an isolation trench extending to the bottom substrate, the isolation trench being spaced apart from adjacent memory channels.

[0061] A top isolation layer 106 is formed using silicon nitride on top, such as Figure 18 As shown; Then, patterned etching is used to form isolation trenches 600 extending to the bottom substrate, such as... Figure 19 As shown, Figure 19 The left image is Figure 19 The right figure shows the horizontal structure diagram.

[0062] Step 106: Remove the first dielectric material and the IGZO channel, gate oxide layer and part of the ferroelectric layer between the first dielectric material and the gate metal layer through an isolation trench to form a trench; In this embodiment, the SiN layer in the alternating layers is removed by wet etching through the isolation trench 213. The IGZO channel 201 between the SiN layer and the gate metal layer 204, the gate oxide layer 202, and 1 / 3 to 1 / 2 of the ferroelectric layer 203 form a trench, as shown below. Figure 20 As shown.

[0063] Understandably, a protective coating is used during layer-by-layer etching to protect the material being etched.

[0064] Step 107: N+IGZO is deposited and annealed in the trench, and then contact metal and tungsten are deposited sequentially to form the source or drain. In this embodiment, a layer of N+IGZO2O6 is then deposited and annealed in the trench, followed by the sequential deposition of contact metal 207 and tungsten 205. Excess N+IGZO2O6, contact metal 207, and tungsten 208 are removed from the isolation trench. Figure 21 and Figure 2 As shown, the inner side of N+IGZO206 extends to contact the ferroelectric layer 203, and the outer side of N+IGZO206 is lined with contact metal 207 and the gaps are filled with tungsten 208. N+IGZO 206 becomes the drain and source regions of the ferroelectric memory transistor cell, and the contact metal 207 and tungsten 208 become the source electrode or drain electrode.

[0065] In the embodiments of this application, the annealing temperature of N+IGZO is 200-400 degrees Celsius.

[0066] In other embodiments, both the IGZO channel 201 and the N+IGZO 206 are formed using atomic layer deposition (ALD) at temperatures ranging from 150°C to 300°C, and the indium precursor used is InCp or Gallium precursor is The zinc precursor is diethylzinc (DEZn), and the oxidant is... .

[0067] Step 108: Fill the isolation trench with oxide; In this embodiment, the isolation trench is first filled with oxide and CMP is performed to form an isolation oxide layer 700, followed by annealing at 500°C to 600°C for approximately 60 seconds. Figure 22 As shown.

[0068] In this application embodiment, a ladder configuration used in 3D NAND non-volatile memory arrays is also used to connect the drain electrode or the source electrode. The ladder configuration and associated manufacturing method are known to those skilled in the art and will not be described in detail here.

[0069] Example 3 In embodiments of this application, a memory array is also provided. Figure 23 This is a schematic diagram of the memory array structure, such as... Figure 23As shown, it includes: a plurality of three-dimensional ferroelectric memories with IGZO channels arranged in an array as described above. Each three-dimensional ferroelectric memory includes a plurality of ferroelectric storage transistor cells. Ferroelectric storage transistor cells with a common bottom global gate line are located in the same column and the same row of ferroelectric storage transistor cells share the same source line and drain line.

[0070] In the embodiments of this application, when programming the selected ferroelectric memory transistor cell, the source and drain lines of the ferroelectric memory transistor cell are configured to be 0V, and a programming voltage of 6~7V is configured through the bottom global gate line; like Figure 24 As shown, for unselected row cells in the same row, their source and drain lines are configured to 0V, and the bottom global gate line is configured to 1 / 3 of the programming voltage. like Figure 25 As shown, for unselected column cells in the same column, configure their source and drain lines to 2 / 3 of the programming voltage (programming voltage is 6~7V). like Figure 26 As shown, for unselected row and column cells in different rows and columns, their source and drain lines are configured to 2 / 3 of the programming voltage (programming voltage is 6~7V), and the bottom global gate line is configured to 1 / 3 of the programming voltage; thus, no interference is caused to other ferroelectric memory transistor cells during programming.

[0071] When erasing the selected ferroelectric memory transistor cell, the source and drain lines of the ferroelectric memory transistor cell are configured with an erase voltage of 6~7V, and the bottom global gate line is erased with 0V. like Figure 27 As shown, for unselected row cells in the same row, the bottom global gate line is erased at 2 / 3 of the erase voltage; like Figure 28 As shown, for unselected column cells in the same column, their source and drain lines are configured to have a 1 / 3 erase voltage. like Figure 29 As shown, for unselected row and column cells in different rows and columns, their global gate line is configured to 2 / 3 erase voltage, and their source line and drain line are configured to 1 / 3 erase voltage.

[0072] When reading a selected ferroelectric memory transistor cell, the drain line of the selected ferroelectric memory transistor cell is configured with a VDD voltage of 0.05-0.2V, the source line with 0V, and the bottom global gate line with a read voltage of 0-0.5V, and the read is performed by configuring the source line and drain line. For unselected row cells in the same column, configure the bottom global gate voltage to 0 volts; For unselected column cells in the same row, configure the source and drain voltages to 0 volts; For row and column cells in different rows and columns, configure the global gate voltage to 0 volts, and configure the source and drain voltages to 0 volts to avoid any potential interference.

[0073] It will be understood by those skilled in the art that the above descriptions are merely preferred embodiments of this application and are not intended to limit this application. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A three-dimensional ferroelectric memory with an IGZO channel, characterized in that, include: Bottom global grid; A center selection gate is provided, extending in a direction perpendicular to the bottom global gate line; A semiconductor stacked structure, the semiconductor stacked structure comprising a gate metal layer, a ferroelectric layer, a gate oxide layer and an IGZO channel sequentially surrounding the central selected gate; The drain and source electrodes extend in the semiconductor stacked structure and contact the ferroelectric layer in a horizontal direction relative to the center selection gate. Multiple pairs of drain and source electrodes are arranged at intervals along the extension direction of the center selection gate, thereby forming multiple ferroelectric memory transistor cells.

2. The three-dimensional ferroelectric memory with IGZO channels according to claim 1, characterized in that, The ferroelectric layer is formed of a doped HfO2-based ferroelectric material, wherein the dopant is selected from one or more of Si, Zr, Al, La, Y, Sr, Gd, Nb, Ni, and Ta.

3. The three-dimensional ferroelectric memory with IGZO channels according to claim 2, characterized in that, The ferroelectric layer is Hf( 1-x) Si (x) O y The x ranges from 0.02 to 0.05, the y ranges from 1.8 to 2.2, and the thickness ranges from 5 nm to 15 nm.

4. The three-dimensional ferroelectric memory with IGZO channels according to claim 2, characterized in that, The ferroelectric layer is Hf x Zr (1-x) O y The range of x is 0.4 to 0.6, the range of y is 1.8 to 2.2, and the thickness is 5 nm to 15 nm.

5. The three-dimensional ferroelectric memory with IGZO channels according to claim 1, characterized in that, The gate oxide layer is Al2O3 or HfO2, with a thickness of less than 20 nm.

6. The three-dimensional ferroelectric memory with IGZO channels according to claim 1, characterized in that, The thickness of the IGZO channel is 5 nm to 20 nm.

7. The three-dimensional ferroelectric memory with IGZO channels according to claim 1, characterized in that, The drain and source electrodes each comprise N+IGZO; one end of the N+IGZO extends into the semiconductor stacked structure and contacts the ferroelectric layer, while the other end is filled with a contact metal and tungsten.

8. The three-dimensional ferroelectric memory with IGZO channels according to claim 1, characterized in that, The gate metal layer includes any one of molybdenum, aluminum, or copper.

9. The three-dimensional ferroelectric memory with IGZO channels according to claim 1, characterized in that, The three-dimensional ferroelectric memory is one of a plurality of three-dimensional ferroelectric memories in a memory array, wherein the memory array is configured in a stepped manner, the stepped configuration providing electrical contact with each of the source or drain.

10. A method for fabricating a three-dimensional ferroelectric memory with an IGZO channel, characterized in that, Includes the following steps: A bottom global gate line is formed, and a bottom stop layer is etched and patterned above the bottom global gate line; A predetermined number of alternating layers of intermediate insulating material and first dielectric material are formed; Etching downwards from the top to the bottom stop layer forms multiple memory channels; An IGZO channel, a gate oxide layer, a ferroelectric layer, a gate metal layer, and a center select gate are sequentially formed in the memory channel. A top isolation layer is formed, and isolation grooves are formed, the isolation grooves being spaced apart from adjacent memory channels; A trench is formed by removing the first dielectric material and the IGZO channel, gate oxide layer and part of the ferroelectric layer between the first dielectric material and the gate metal layer through an isolation trench. N+IGZO is deposited and annealed in the trench, and then contact metal and tungsten are deposited sequentially to form the source or drain. The isolation tank is filled with oxide.

11. The method for fabricating a three-dimensional ferroelectric memory with an IGZO channel according to claim 10, characterized in that, The specific steps for sequentially forming an IGZO channel, a gate oxide layer, a ferroelectric layer, a gate metal layer, and a center-select gate in the memory channel include: In the memory channel, IGZO channel, gate oxide layer and protective layer are sequentially deposited and etched to form the memory channel; Remove the protective layer, deposit a ferroelectric layer in the memory channel, and etch it through the bottom stop layer; Etch memory channels down to the bottom global gate line, deposit gate metal to form a gate metal layer, and then perform bottom etching; A central selection gate is formed by deposition in the memory channel.

12. The method for fabricating a three-dimensional ferroelectric memory with an IGZO channel according to claim 10, characterized in that, Both the IGZO channel and the N+IGZO are formed using atomic layer deposition (ALD) at temperatures ranging from 150°C to 300°C.

13. The method for fabricating a three-dimensional ferroelectric memory with an IGZO channel according to claim 12, characterized in that, The indium precursor used in the ALD process is InCp or In(acac)3, the gallium precursor is Ga(CH3)3 (TMGa), the zinc precursor is diethylzinc (DEZn), and the oxidant is H2O or O3.

14. The method for fabricating a three-dimensional ferroelectric memory with an IGZO channel according to claim 10, characterized in that, The ferroelectric layer is formed using atomic layer deposition (ALD) technology, wherein HfO2 and SiO2 or HfO2 and ZrO2 are deposited alternately through lamination layers at a deposition temperature of 150°C to 400°C.

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