Pixel signal reading circuit and method, image sensor and electronic equipment

Abstract

The invention relates to the technical field of image processing, and discloses a pixel signal reading circuit and method, an image sensor and electronic equipment, and the circuit comprises a pixel signal reading module, a switched capacitor amplifier, an analog-to-digital converter and a control module. A first signal node and a second signal node of the pixel signal reading module respectively store a pixel reset level and an illumination level; the switched capacitor amplifier adopts a single operational amplifier structure, and realizes self-return-to-zero sampling through a first feedback switch and a second feedback switch; the control module conducts the feedback switch in a sampling stage to capture operational amplifier imbalance, disconnects the feedback switch in an amplification stage and conducts the first signal node and the second signal node to enable the potentials to be equal, and differential signal amplification and column fixed mode noise compensation are achieved; the analog-to-digital converter quantizes the amplified signal. The functions of signal amplification, level shift and noise elimination are integrated through a single operational amplifier framework, and the circuit area and power consumption are remarkably reduced.

Description

Technical Field

[0001] This application relates to the field of image processing technology, and in particular to a pixel signal reading circuit, method, image sensor and electronic device. Background Technology

[0002] With the widespread application of Complementary Metal-Oxide-Semiconductor (CMOS) image sensors in consumer electronics, medical imaging, and industrial inspection, the design of their analog front-end circuits has become one of the key factors affecting sensor performance. In existing technologies, the analog front-end circuits of CMOS image sensors typically employ a multi-stage operational amplifier structure to achieve high-gain and low-noise signal amplification, while simultaneously using a pipelined analog-to-digital converter to complete high-speed, high-precision analog-to-digital signal conversion. This architecture, through multi-stage amplification and successive quantization, can effectively improve the dynamic range and signal-to-noise ratio of signal processing.

[0003] However, the cascaded design of multi-stage operational amplifiers requires a significant chip area to achieve gain distribution and noise optimization at each stage, while the complex structure of pipelined analog-to-digital converters further increases the layout area. Furthermore, the accumulated bias current of the multi-stage amplifiers and the quiescent operating current of each stage in the pipelined analog-to-digital converter significantly increase the overall static power consumption of the analog front-end circuit. Therefore, the large chip area and high static power consumption of existing CMOS image sensor analog front-end circuits due to the use of multi-stage operational amplifiers and pipelined analog-to-digital converters limit their adoption in low-power, miniaturized applications. Summary of the Invention

[0004] In view of this, the embodiments of this application provide a pixel signal reading circuit, method, image sensor and electronic device, which can effectively solve the problem that the analog front-end circuit of the CMOS image sensor in the prior art has a large chip area and high static power consumption due to the use of multi-stage operational amplifiers and pipelined analog-to-digital converters, which limits its promotion in low-power and miniaturized application scenarios.

[0005] In a first aspect, the present invention provides a pixel signal readout circuit, comprising: The pixel signal readout module includes a first signal node and a second signal node. The first signal node is used to store the pixel reset level, and the second signal node is used to store the illumination level. The input terminal of the pixel signal readout module is used to input the pixel signal. A switched-capacitor amplifier includes an operational amplifier, a first feedback switch, and a second feedback switch. The non-inverting input of the operational amplifier is electrically connected to the first output node of the pixel signal readout module, and the inverting input of the operational amplifier is electrically connected to the second output node of the pixel signal readout module. The first feedback switch is connected between the inverting input of the operational amplifier and the output of the operational amplifier, and the second feedback switch is connected between the non-inverting input of the operational amplifier and the output of the operational amplifier. An analog-to-digital converter, with its input terminal connected to the output terminal of the switched-capacitor amplifier, is used to receive and quantize the amplified analog signal from the switched-capacitor amplifier. The control module is electrically connected to the pixel signal readout module and the switched capacitor amplifier, respectively. The control module is configured to control the pixel signal readout module to generate a differential voltage signal and control the first feedback switch and the second feedback switch to be turned on during the sampling phase. The control module is also configured to, during the amplification phase following the sampling phase, disconnect the first feedback switch and the second feedback switch, and control the first signal node and the second signal node to be connected, so that the potentials of the first signal node and the second signal node are equal.

[0006] In some embodiments, the pixel signal readout module further includes: The pixel sensing unit includes a load element for providing bias current, a first switch for sampling the pixel reset level, and a second switch for sampling the illumination level. The control terminals of the first switch and the second switch are electrically connected to the control module. The input terminals of the first switch and the second switch and the load element are used to input the pixel signal. The output terminal of the first switch is connected to the first signal node, and the output terminal of the second switch is connected to the second signal node. The storage unit includes a first storage capacitor and a second storage capacitor connected in series, wherein one end of the first storage capacitor is connected to the output terminal of the first switch and forms the first signal node, and one end of the second storage capacitor is connected to the output terminal of the second switch and forms the second signal node. A balance switch, the two ends of which are respectively connected to the first signal node and the second signal node, and the control terminal of the balance switch is connected to the control module; The readout source follower includes a first source follower transistor and a second source follower transistor. The gate of the first source follower transistor is connected to the first signal node, and the gate of the second source follower transistor is connected to the second signal node. The drains of the first source follower transistor and the second source follower transistor serve as the first output node and the second output node, respectively, for outputting the differential voltage signal.

[0007] In some embodiments, the switched-capacitor amplifier further includes: The first input capacitor is connected between the first output node and the non-inverting input terminal of the operational amplifier; The second input capacitor is connected between the second output node and the inverting input terminal of the operational amplifier; The first feedback capacitor is connected between the inverting input terminal and the output terminal of the operational amplifier; The second feedback capacitor is connected between the non-inverting input and the output of the operational amplifier.

[0008] In some embodiments, the first feedback switch and the second feedback switch are self-zeroing switches.

[0009] In some embodiments, the first input capacitor and / or the second input capacitor are programmable capacitors.

[0010] In some embodiments, the switched-capacitor amplifier further includes: A first bias capacitor, one end of which is used to input a second power supply signal, and the other end of which is connected to the non-inverting input terminal of the operational amplifier. The second bias capacitor has one end used to input the second power supply signal, and the other end connected to the inverting input terminal of the operational amplifier. The first bias capacitor and the second bias capacitor are configured to couple the second power supply signal to the corresponding input terminal during the amplification stage, so as to set the DC operating point of the operational amplifier.

[0011] In some embodiments, the analog-to-digital converter includes a digital-to-analog converter, a comparator, and a successive approximation logic unit connected in series. The input terminal of the digital-to-analog converter is connected to the output terminal of the switched-capacitor amplifier. The successive approximation logic unit is configured to drive the digital-to-analog converter to perform a successive approximation quantization process. The control module is also used to enter the conversion stage after the amplification stage, start the sampling and quantization operation of the analog-to-digital converter, quantize the amplified signal, and output a digital result.

[0012] Secondly, embodiments of this application provide a pixel signal reading method, wherein the pixel signal reading method is applied to at least one pixel signal reading circuit described in the first aspect above, comprising: Sampling stage: The pixel signal readout module is controlled to store the pixel reset level and illumination level of the pixel signal, and output the corresponding differential voltage signal to the switched capacitor amplifier, while simultaneously turning on the first feedback switch and the second feedback switch in the switched capacitor amplifier; Amplification stage: Disconnect the first feedback switch and the second feedback switch, and connect the first signal node and the second signal node to make the potentials of the first signal node and the second signal node equal; Conversion stage: The analog-to-digital converter initiates sampling and quantization operations, outputting the corresponding digital image data.

[0013] Thirdly, embodiments of this application provide an image sensor, which includes at least one pixel signal readout circuit as described in the first aspect above.

[0014] Fourthly, embodiments of this application provide an electronic device, which includes the image sensor described in the first aspect above.

[0015] The embodiments of this application have the following beneficial effects: The pixel signal readout circuit of this application includes: a pixel signal readout module, a switched-capacitor amplifier, a successive approximation analog-to-digital converter, and a control module. The pixel signal readout module includes a first signal node and a second signal node. The first signal node is used to store the pixel reset level, and the second signal node is used to store the illumination level. The input terminal of the pixel signal readout module is used to input the pixel signal. The switched-capacitor amplifier includes an operational amplifier, a first feedback switch, and a second feedback switch. The non-inverting input terminal of the operational amplifier is electrically connected to the first output node of the pixel signal readout module, and the inverting input terminal of the operational amplifier is electrically connected to the second output node of the pixel signal readout module. The first feedback switch is connected to the control module. A second feedback switch is connected between the inverting input terminal and the output terminal of the operational amplifier, and between the non-inverting input terminal and the output terminal of the operational amplifier. The input terminal of the successive approximation analog-to-digital converter is connected to the output terminal of the switched-capacitor amplifier to receive and quantize the amplified analog signal from the switched-capacitor amplifier. The control module is configured to control the pixel signal readout module to generate a differential voltage signal and control the first and second feedback switches to be turned on during the sampling phase. During the amplification phase after the sampling phase, the first and second feedback switches are turned off, and the first and second signal nodes are turned on to make the potentials of the first and second signal nodes equal.

[0016] This solution employs an architecture combining a switched-capacitor amplifier with a single operational amplifier and a successive approximation analog-to-digital converter. The control module activates a feedback switch during the sampling phase to achieve self-zeroing correction of the operational amplifier offset voltage. During the amplification phase, the feedback switch is deactivated, and the first and second signal nodes are activated to complete charge balance and differential signal amplification. This effectively achieves differential processing of pixel reset level and illumination level, as well as suppression of column fixed-mode noise. This structure integrates signal amplification, DC level adjustment, and noise cancellation, significantly reducing the circuit complexity, chip area, and static power consumption of the analog front-end, thereby improving the system's energy efficiency ratio. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A schematic diagram of the pixel signal readout circuit according to an embodiment of this application is shown; Figure 2 A circuit diagram of the pixel signal reading circuit according to an embodiment of this application is shown; Figure 3 This diagram illustrates the first timing control schematic of the pixel signal readout circuit according to an embodiment of this application. Figure 4 This illustrates a second timing control schematic diagram of the pixel signal readout circuit according to an embodiment of this application; Figure 5 A third timing control schematic diagram of the pixel signal readout circuit according to an embodiment of this application is shown; Figure 6 The diagram shown is a flowchart of a pixel signal reading method according to an embodiment of this application.

[0019] Explanation of key component symbols: 10: Pixel signal readout module; 20: Switched capacitor amplifier; 30: Analog-to-digital converter; 40: Control module. Detailed Implementation

[0020] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0021] The components of the embodiments of this application described and illustrated in the accompanying drawings can be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of this application provided in the drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0022] In the following text, the terms "comprising," "having," and their cognates, which may be used in various embodiments of this application, are intended only to indicate a particular feature, number, step, operation, element, component, or combination thereof, and should not be construed as primarily excluding the presence of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, or adding the possibility of one or more combinations thereof. Furthermore, the terms "first," "second," "third," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance.

[0023] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of this application pertain. Terms (such as those defined in commonly used dictionaries) shall be interpreted as having the same meaning as in their contextual meaning in the relevant technical field and shall not be construed as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of this application.

[0024] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0025] In existing image sensor designs, common solutions typically employ a combination of pixel units, switched-capacitor amplifier circuits, and pipelined analog-to-digital converters, supporting differential sampling to eliminate fixed-mode noise in the column direction. Specifically, the column readout section of the image sensor reduces common-mode interference by outputting a pair of differential signals; the analog front-end circuit corrects fixed-mode image noise in the column and performs signal gain adjustment and DC-DC level shifting. Because the operating characteristics of the switched-capacitor amplifier circuit are well-matched with the pipelined analog-to-digital converter structure, this combination is widely used in conventional imaging systems.

[0026] However, even with optimization techniques such as shared operational amplifiers, a pipelined analog-to-digital converter still requires at least five operational amplifiers to complete the multi-stage sampling, step-by-step amplification, and digitization process when an overall accuracy of eight bits is required. This design leads to a significant increase in the size of the analog circuitry, occupying a larger chip area and resulting in higher static power consumption, making it difficult to meet the needs of low-power imaging applications with strict cost and energy consumption control requirements.

[0027] This application provides a pixel signal readout circuit, method, image sensor, and electronic device. This solution employs an architecture combining a switched-capacitor amplifier 20 (composed of a single operational amplifier) ​​with a successive approximation analog-to-digital converter 30. In conjunction with a control module 40, the feedback switch is turned on during the sampling phase to achieve self-zero correction of the operational amplifier offset voltage. During the amplification phase, the feedback switch is turned off and the first and second signal nodes are turned on to complete charge balance and differential signal amplification. This effectively achieves differential processing of pixel reset level and illumination level, as well as suppression of column fixed-mode noise. This structure integrates signal amplification, DC level adjustment, and noise cancellation, significantly reducing the circuit complexity, chip area, and static power consumption of the analog front-end, and improving the system's energy efficiency ratio.

[0028] The pixel signal reading circuit will be described below with reference to some specific embodiments.

[0029] Figure 1 A schematic diagram of a pixel signal readout circuit according to an embodiment of this application is shown. The circuit includes a pixel signal readout module 10, a switched-capacitor amplifier 20, an analog-to-digital converter 30, and a control module 40. These modules are connected sequentially to form a complete column-level signal processing path. This circuit can be installed inside an image sensor and is particularly suitable for cost- and power-sensitive applications, such as CMOS image sensor chips in low-power imaging systems like mouse photoelectric sensor modules and gesture recognition modules.

[0030] Figure 2 A circuit diagram of a pixel signal readout circuit according to an embodiment of this application is shown, illustrating the complete analog front-end architecture from pixel unit to digital output. This circuit, centered on a single operational amplifier, combines differential sampling technology with a successive approximation analog-to-digital converter structure to achieve high-efficiency column signal readout. The entire readout process is coordinated and timed by the control module 40 to ensure accurate execution of each stage of the operation.

[0031] The pixel signal readout module 10 is used to collect and temporarily store the reset level and illumination level output by the pixel unit, including a first signal node N1 and a second signal node N2. The first signal node N1 is used to store the reset level of the pixel in the unexposed state, and the second signal node N2 is used to store the illumination level of the pixel after exposure. The pixel signal readout module 10 further includes a pixel sensing unit, a storage unit, a balance switch, and a column readout source follower.

[0032] The pixel sensing unit includes NM1 and NM2, which serve as active loads in the 3-transistor active pixel structure. Their gates receive a constant bias signal to maintain the stability of the pixel diode's operating point. The pixel sensing unit also includes a first switch NM3 for sampling the pixel reset level and a second switch NM4 for sampling the illumination level. The control terminal of the first switch NM3 receives a control signal NG3 from the control module 40, its input is connected to the pixel signal input line, and its output is connected to the first signal node N1. Similarly, the control terminal of the second switch NM4 receives a control signal NG4 from the control module 40 and is turned on at different times to write the illumination signal into the second signal node N2. The control module 40 stores the pixel reset level and illumination level by time-division controlling the on / off states of the first switch NM3 and the second switch NM4.

[0033] The storage unit includes a first storage capacitor C1 and a second storage capacitor C2 connected in series. One end of the first storage capacitor C1 is connected to the output of the first switch NM3, forming a first signal node N1. One end of the second storage capacitor C2 is connected to the output of the second switch NM4, forming a second signal node N2, thus forming an independent charge storage path. The first storage capacitor C1 and the second storage capacitor C2 are used to maintain the sampled pixel reset level and illumination level until they are used in subsequent processing stages.

[0034] The balance switch is NM5. The two ends of the balance switch NM5 are connected to the first signal node N1 and the second signal node N2 respectively. The control terminal of the balance switch NM5 is connected to the control module 40. The control module 40 outputs the control signal NG5 to control the balance switch NM5. During the amplification stage, the control module 40 turns on the balance switch NM5, forcing the potentials of the two signal nodes to be consistent, realizing charge neutralization and common mode establishment, and creating conditions for single-ended amplification of differential signals.

[0035] The column readout source follower includes a first source follower transistor PM1 and a second source follower transistor PM2. The gate of the first source follower transistor PM1 is connected to a first signal node N1, and the gate of the second source follower transistor PM2 is connected to a second signal node N2. The drains of the first source follower transistor PM1 and the second source follower transistor PM2 serve as the first and second output nodes, respectively, for outputting a differential voltage signal based on the difference between reset and illumination levels to the switched-capacitor amplifier 20. Due to manufacturing process mismatches, there may be a threshold voltage or transconductance deviation between the first source follower transistor PM1 and the second source follower transistor PM2. This deviation will manifest as fixed-pattern noise in the column direction in the image, and therefore needs to be eliminated in subsequent stages.

[0036] The switched-capacitor amplifier 20 is the core analog circuit module in this embodiment that realizes signal gain adjustment and fixed-mode noise cancellation. It is built around a single-stage operational amplifier U1, and through precise timing control, it achieves a high degree of integration of multiple functions such as self-zero correction, differential signal amplification, and DC level shifting. This circuit directly receives the differential voltage signals output from the first and second output nodes of the pixel signal readout module 10, and performs high-precision analog processing internally, providing a stable and low-noise input signal for subsequent analog-to-digital conversion.

[0037] Operational amplifier U1 has three key nodes: a non-inverting input, an inverting input, and an output. Its gain characteristics and bandwidth performance can meet the dynamic range and response speed requirements of an 8-bit precision image sensor. In terms of circuit connection, the non-inverting input of operational amplifier U1 is connected to the first output node of pixel signal readout module 10 through the first input capacitor C3, and the inverting input is connected to the second output node through the second input capacitor C4, forming a capacitively coupled differential input structure. This structure effectively isolates the DC offset voltage in the preceding circuit, preventing it from accumulating in the signal chain, while completely preserving the effective differential information between the reset level and the illumination level.

[0038] The switched-capacitor amplifier 20 also includes a first feedback switch NM6 and a second feedback switch NM7. The first feedback switch NM6 is connected between the inverting input terminal and the output terminal of the operational amplifier U1, and the second feedback switch NM7 is connected between the non-inverting input terminal and the output terminal of the operational amplifier U1, forming part of the closed-loop feedback path. The control module 40 controls the first feedback switch NM6 and the second feedback switch NM7 through output control signals NG6 and NG7, respectively. Specifically, during the sampling phase, the control module 40 drives the first feedback switch NM6 and the second feedback switch NM7 to conduct synchronously, causing the operational amplifier U1 to enter a unity-gain buffer state, i.e., a self-reset zero operating mode. At this time, the output terminal is locked at the intermediate level, while the offset voltage present in the input stage is sampled and stored in the internal parasitic capacitance or compensation node, realizing pre-compensation for the non-ideal characteristics of the operational amplifier itself.

[0039] The first feedback switch NM6 and the second feedback switch NM7 are used as self-resetting switches, and their gates receive the sampling clock signal from the control module 40, turning on synchronously during the sampling phase. Due to transistor threshold voltage mismatch and carrier mobility fluctuations in the CMOS process, static offset is inevitably introduced into the operational amplifier input stage. This self-resetting mechanism, by capturing and memorizing the offset in real time, lays the foundation for error cancellation in subsequent amplification stages, significantly improving system linearity and consistency, and effectively suppressing column stripe noise, especially in multi-column parallel readout.

[0040] The switched-capacitor amplifier 20 also includes a first feedback capacitor C7 and a second feedback capacitor C8. The first feedback capacitor C7 is connected between the inverting input and output of the operational amplifier U1; the second feedback capacitor C8 is connected between the non-inverting input and output of the operational amplifier U1. During the amplification phase, the first feedback switch NM6 and the second feedback switch NM7, along with the first feedback capacitor C7 and the second feedback capacitor C8, form a stable closed-loop gain path. The system voltage gain is determined by the ratio of the input capacitor to the feedback capacitor, ensuring the predictability and controllability of the amplification factor.

[0041] To further optimize the operation of the operational amplifier, the switched-capacitor amplifier 20 is also equipped with a first bias capacitor C6 and a second bias capacitor C5. One end of the first bias capacitor C6 is connected to the non-inverting input of the operational amplifier U1, and the other end is used to input the second power supply signal; one end of the second bias capacitor C5 is connected to the inverting input of the operational amplifier U1, and the other end is also used to input the second power supply signal. At the beginning of the amplification stage, the second power supply signal undergoes a jump, injecting a predetermined voltage pulse into the two inputs of the operational amplifier U1 through capacitive coupling, dynamically raising or lowering its common-mode level, thereby setting a suitable DC operating point. This mechanism helps to expand the swing range of the output signal, improve the dynamic utilization of the analog link, and avoid signal clipping caused by level mismatch.

[0042] The entire operation of the switched-capacitor amplifier 20 is divided into two main stages. In the sampling stage, the feedback switch is on, the bias capacitor has not yet played its role, the input signal is isolated, and the operational amplifier U1 performs a self-zeroing operation, completing the sampling and storage of its own offset. In the subsequent amplification stage, the feedback switch is off, and the balance switch NM5 is simultaneously turned on, shorting the first signal node N1 and the second signal node N2 of the preceding stage. Charge is redistributed, and the potentials of the two nodes are leveled. At this time, the effective information of the differential signal excites the operational amplifier U1 to generate an output response through the first input capacitor C3 and the second input capacitor C4. The final output voltage is the original differential signal minus the initial offset by a preset multiple, achieving integrated processing of gain adjustment, noise suppression, and level shifting.

[0043] The first input capacitor C3 and the second input capacitor C4 not only perform the function of coupling and transmitting AC signals, but also participate in closed-loop calculations as gain setting elements. The first input capacitor C3 is designed as a programmable capacitor, allowing different numbers of sub-capacitors to be connected via a switch array to adjust its equivalent capacitance. When operating in a low-light environment, the control module 40 can configure the first input capacitor C3 to a larger capacitance value to improve system gain, enhance the response capability of weak light signals, and improve the signal-to-noise ratio. Under strong light conditions, it switches to a smaller capacitance value to avoid amplifier output saturation and ensure signal linearity and quantization accuracy.

[0044] If the input signal of operational amplifier U1 is The second power signal is Then the output voltage of operational amplifier U1 Satisfy expression ,in This is the ratio of the first input capacitor C3 to the first feedback capacitor C7. This is the ratio of the first bias capacitor C6 to the first feedback capacitor C7. It features additive amplification, supports multiple signal inputs and flexible level adjustment, and is suitable for applications requiring signal synthesis and offset correction.

[0045] The analog-to-digital converter 30 is a key functional module in this embodiment that performs analog-to-digital conversion. Its input is directly connected to the output of the switched-capacitor amplifier 20 to receive the amplified analog voltage signal and perform high-precision quantization processing on it. This conversion process is completed under the timing coordination of the control module 40 to ensure that it starts after the signal has stabilized, thereby guaranteeing the accuracy and consistency of the conversion result.

[0046] The analog-to-digital converter 30 in this application adopts a successive approximation structure, which has the advantages of low circuit complexity, low power consumption, and area saving, making it particularly suitable for eight-bit precision image sensor applications. This structure comprises three core components: a digital-to-analog converter U2, a comparator U3, and a successive approximation logic unit U4. These three components work together to form a complete closed-loop feedback quantization system. The entire conversion process gradually approximates the true value of the input signal within one or more clock cycles.

[0047] The digital-to-analog converter (DAC) U2, as the core component of the feedback network, is driven by the successive approximation logic unit U4. The input of DAC U2 is connected to the output of the switched-capacitor amplifier 20. The successive approximation logic unit U4 is configured to drive DAC U2 to perform the successive approximation quantization process. Specifically, the output of DAC U2 is connected to the reference input of comparator U3. After the conversion begins, the successive approximation logic unit U4 generates a set of digital codewords based on the current estimate and converts them into the corresponding analog voltage through DAC U2. This voltage will serve as the judgment benchmark for subsequent comparisons. In the initial stage, the process starts with the most significant bit and proceeds sequentially downwards, achieving bit-by-bit judgment.

[0048] Comparator U3 performs voltage comparison operations in the analog domain. The positive input of comparator U3 is connected to the analog signal to be tested output from switched-capacitor amplifier 20, and the negative input is connected to the reference voltage generated by digital-to-analog converter U2. Comparator U3 continuously compares the magnitudes of the two signals and outputs the comparison result to successive approximation logic unit U4. If the signal to be tested is higher than the reference voltage, the current bit is kept at one; otherwise, it is set to zero, and the test proceeds to the next bit.

[0049] The successive approximation logic unit U4 is the control center of the entire analog-to-digital converter 30. It is responsible for managing the quantization timing, generating trial codewords, and updating the results based on the comparator feedback. After the amplification stage, the control module 40 issues a start command, and the successive approximation logic unit U4 begins operation. It completes the determination of the most significant bit within the first sampling clock cycle, and then performs a step-by-step search for the least significant bit until all bits are determined. Finally, it outputs complete digital image data.

[0050] Since the switched-capacitor amplifier 20 has already completed signal amplification, offset correction, and level shifting in the pre-stage, the signal input to the analog-to-digital converter 30 has good signal-to-noise ratio and stability, which is beneficial for improving comparison accuracy and convergence speed. Meanwhile, the successive approximation structure itself has good process adaptability; even with a decrease in device gain under advanced processes, it can still maintain reliable conversion performance, making it suitable for low-cost imaging chip designs under deep submicron CMOS processes. The analog-to-digital converter 30 has a compact operating timing and short inter-stage delay; only one phase cycle elapses between the preparation of the output signal from the switched-capacitor amplifier 20 and the start of conversion, effectively improving frame rate processing capabilities. For example, in optical mouse sensors, it can support fast response requirements of thousands of frames per second, and in gesture recognition modules, it can also meet the latency requirements of real-time interaction.

[0051] The control module 40 is the core control unit for timing coordination and function scheduling in this embodiment. It is electrically connected to the pixel signal readout module 10, the switched capacitor amplifier 20, and the analog-to-digital converter 30, respectively. It is used to precisely control the on and off states of each switching element according to a preset timing sequence, ensuring that the entire signal reading process is executed in an orderly manner in stages. The control module 40 outputs multiple clock drive signals, which are applied to the sampling switch, feedback switch, and balancing switch, respectively, forming a strict time-division multiplexing operation sequence to ensure the accuracy and stability of signal processing.

[0052] like Figure 3 As shown, at time T1, the control module 40 first triggers the first sampling switch NM3 to turn on, causing the reset level of the pixel unit to be written into the first signal node N1 and stored in the first storage capacitor C1, completing the acquisition of the pixel's unexposed state voltage. Subsequently, at time T2, the control module 40 turns off the first sampling switch NM3 and turns on the second sampling switch NM4, writing the signal level of the same pixel after illumination into the second signal node N2, which is held by the second storage capacitor C2. The voltage difference between these two nodes reflects the actual light sensitivity of the pixel, and by time T3, the initial signal basis has been formed.

[0053] like Figure 4 As shown, after time T4, the sampling phase begins. Control module 40 synchronously drives the first source follower transistor PM1 and the second source follower transistor PM2 of the column readout source follower to operate, causing the first output node and the second output node to output a pair of differential voltage signals. Simultaneously, control module 40 turns on the first feedback switch NM6 and the second feedback switch NM7, causing operational amplifier U1 to enter self-reset mode. During this period, the output of the operational amplifier is locked to its DC operating point, while the offset voltage present in the input stage is sampled through the feedback path and stored in internal nodes or parasitic capacitances, achieving pre-compensation for the non-ideal characteristics of the operational amplifier itself.

[0054] Meanwhile, the first input capacitor C3 and the second input capacitor C4 prepare for coupling the differential signal from the preceding stage. However, due to the closed feedback switch, the input signal has not yet entered the amplification path. This stage mainly accomplishes two key tasks: first, eliminating the input offset error of the operational amplifier; and second, establishing initial conditions for the accurate transmission of the subsequent differential signal. This self-zeroing mechanism effectively suppresses fixed-mode noise caused by transistor mismatch, and can significantly reduce inter-column deviation, especially in multi-column parallel readout.

[0055] Upon entering the amplification phase at time T5, the control module 40 immediately disconnects the first feedback switch NM6 and the second feedback switch NM7, cutting off the feedback loop. Simultaneously, it triggers the balance switch NM5 to conduct, forcing the first signal node N1 and the second signal node N2 to short-circuit, causing their potentials to converge. At this time, the charge between the two storage capacitors is redistributed, the common-mode voltage is flattened, and the difference information originally existing between the two storage capacitors is converted into a single-ended excitation signal through the input capacitor, driving the operational amplifier U1 to begin the amplification process.

[0056] In this stage, operational amplifier U1, with its open-loop gain and main feedback capacitor, forms a closed-loop amplification structure, generating a voltage at its output that is proportional to the original differential signal, expressed as: This process not only effectively amplifies the signal but also cancels out pixel-level fixed-pattern noise. At the same time, with the help of the level shifting effect of the bias capacitor, the output signal falls within the optimal input range of the analog-to-digital converter 30.

[0057] like Figure 5 As shown, at the end of stage T5, the output signal of the switched-capacitor amplifier 20 has been fully established and tends to stabilize. The control module 40 then starts the conversion stage, sending a start command to the successive approximation logic unit to initiate the analog-to-digital conversion process. Comparator U3 successively compares the amplified analog signal with the reference voltage generated by the digital-to-analog converter U2. The successive approximation logic unit U4 iteratively adjusts the digital codeword according to the comparison results, gradually approximating the true value from the most significant bit to the least significant bit.

[0058] The entire quantization process is completed within one or more clock cycles, ultimately outputting the corresponding digital image data at time T7. Since the sampling operation begins after T5 and before the next sampling clock T6, the front-end operational amplifier U1 must have sufficient bandwidth to ensure the signal is fully established before T6, meeting the sampling accuracy requirements. The entire analog-to-digital conversion process can begin after T5 and completes the conversion in just one sampling cycle, with extremely short inter-stage delays, amounting to only one clock cycle.

[0059] Compared to traditional pipelined analog-to-digital converter designs, this solution integrates multiple functions such as signal amplification, offset correction, level shifting, and noise suppression using only a single operational amplifier through timing-coordinated control. This significantly reduces analog circuit area and static power consumption, while also lowering chip manufacturing costs. It is particularly suitable for low-cost imaging systems with high power consumption and integration requirements, such as optical mouse sensors and gesture recognition modules.

[0060] This application also provides a pixel signal reading method. Figure 6 The diagram shown is a schematic flowchart of a pixel signal reading method according to an embodiment of this application. This pixel signal reading method is applied to the pixel signal reading circuit mentioned in the above embodiment and includes: Step S101: Sampling stage: The control pixel signal readout module 10 stores the pixel reset level and illumination level of the pixel signal, and outputs the corresponding differential voltage signal to the switched capacitor amplifier 20, while simultaneously turning on the first feedback switch and the second feedback switch in the switched capacitor amplifier 20. Step S102: Amplification stage: Disconnect the first feedback switch and the second feedback switch, and make the first signal node N1 and the second signal node N2 conduct, so that the potentials of the first signal node N1 and the second signal node N2 are equal; Step S103: Conversion stage: Start the sampling and quantization operation of analog-to-digital converter 30 and output the corresponding digital image data.

[0061] The pixel signal reading method provided in this application embodiment can realize the function of the corresponding pixel signal reading circuit described above and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0062] This application also provides an image sensor, exemplary of which the image sensor includes the pixel signal readout circuit described above.

[0063] This application also provides an electronic device, exemplary of which includes the image sensor described above. Exemplarily, the electronic device may be an optical mouse sensor or a gesture recognition module.

[0064] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that, in alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0065] In addition, the functional modules or units in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0066] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a smartphone, personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application.

[0067] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A pixel signal reading circuit, characterized in that, include: The pixel signal readout module includes a first signal node and a second signal node. The first signal node is used to store the pixel reset level, and the second signal node is used to store the illumination level. The input terminal of the pixel signal readout module is used to input pixel signals. A switched-capacitor amplifier includes an operational amplifier, a first feedback switch, and a second feedback switch. The non-inverting input of the operational amplifier is electrically connected to the first output node of the pixel signal readout module, and the inverting input of the operational amplifier is electrically connected to the second output node of the pixel signal readout module. The first feedback switch is connected between the inverting input of the operational amplifier and the output of the operational amplifier, and the second feedback switch is connected between the non-inverting input of the operational amplifier and the output of the operational amplifier. An analog-to-digital converter, with its input terminal connected to the output terminal of the switched-capacitor amplifier, is used to receive and quantize the amplified analog signal from the switched-capacitor amplifier. The control module is electrically connected to the pixel signal readout module and the switched capacitor amplifier, respectively. The control module is configured to control the pixel signal readout module to generate a differential voltage signal and control the first feedback switch and the second feedback switch to be turned on during the sampling phase. The control module is also configured to, during the amplification phase following the sampling phase, disconnect the first feedback switch and the second feedback switch, and control the first signal node and the second signal node to be connected, so that the potentials of the first signal node and the second signal node are equal.

2. The pixel signal reading circuit according to claim 1, characterized in that, The pixel signal readout module further includes: The pixel sensing unit includes a load element for providing bias current, a first switch for sampling the pixel reset level, and a second switch for sampling the illumination level. The control terminals of the first switch and the second switch are electrically connected to the control module. The input terminals of the first switch and the second switch and the load element are used to input the pixel signal. The output terminal of the first switch is connected to the first signal node, and the output terminal of the second switch is connected to the second signal node. The storage unit includes a first storage capacitor and a second storage capacitor connected in series, wherein one end of the first storage capacitor is connected to the output terminal of the first switch and forms the first signal node, and one end of the second storage capacitor is connected to the output terminal of the second switch and forms the second signal node. A balance switch, the two ends of which are respectively connected to the first signal node and the second signal node, and the control terminal of the balance switch is connected to the control module; The readout source follower includes a first source follower transistor and a second source follower transistor. The gate of the first source follower transistor is connected to the first signal node, and the gate of the second source follower transistor is connected to the second signal node. The drains of the first source follower transistor and the second source follower transistor serve as the first output node and the second output node, respectively, for outputting the differential voltage signal.

3. The pixel signal reading circuit according to claim 1, characterized in that, The switched capacitor amplifier also includes: The first input capacitor is connected between the first output node and the non-inverting input terminal of the operational amplifier; The second input capacitor is connected between the second output node and the inverting input terminal of the operational amplifier; The first feedback capacitor is connected between the inverting input terminal and the output terminal of the operational amplifier; The second feedback capacitor is connected between the non-inverting input and the output of the operational amplifier.

4. The pixel signal reading circuit according to claim 1, characterized in that, The first feedback switch and the second feedback switch are self-zeroing switches.

5. The pixel signal reading circuit according to claim 3, characterized in that, The first input capacitor and / or the second input capacitor are programmable capacitors.

6. The pixel signal reading circuit according to claim 1, characterized in that, The switched capacitor amplifier also includes: A first bias capacitor is used as the input for the second power supply signal, and the other end of the first bias capacitor is connected to the non-inverting input of the operational amplifier. A second bias capacitor is used as the input for the second power supply signal, and the other end of the second bias capacitor is connected to the inverting input of the operational amplifier. The first bias capacitor and the second bias capacitor are configured to couple the second power supply signal to the corresponding input terminal during the amplification stage, so as to set the DC operating point of the operational amplifier.

7. The pixel signal reading circuit according to claim 1, characterized in that, The analog-to-digital converter includes a digital-to-analog converter, a comparator, and a successive approximation logic unit connected in series. The input terminal of the digital-to-analog converter is connected to the output terminal of the switched-capacitor amplifier. The successive approximation logic unit is configured to drive the digital-to-analog converter to perform a successive approximation quantization process. The control module is also used to enter the conversion stage after the amplification stage, start the sampling and quantization operation of the analog-to-digital converter, quantize the amplified signal, and output a digital result.

8. A method for reading pixel signals, characterized in that, The pixel signal reading method is applied to the pixel signal reading circuit according to any one of claims 1-7, comprising: Sampling stage: The pixel signal readout module is controlled to store the pixel reset level and illumination level of the pixel signal, and output the corresponding differential voltage signal to the switched capacitor amplifier, while simultaneously turning on the first feedback switch and the second feedback switch in the switched capacitor amplifier; Amplification stage: Disconnect the first feedback switch and the second feedback switch, and connect the first signal node and the second signal node to make the potentials of the first signal node and the second signal node equal; Conversion stage: The analog-to-digital converter initiates sampling and quantization operations, outputting the corresponding digital image data.

9. An image sensor, characterized in that, The image sensor includes: a pixel signal readout circuit as described in any one of claims 1-7.

10. An electronic device, characterized in that, The electronic device includes the image sensor as described in claim 9.

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