A method for reading data and CPLD / FPGA

Abstract

This specification provides a data reading method and CPLD / FPGA. The method includes: upon detecting that the CS and OE terminals on the CPU side are at a low voltage, constructing a read request signal with an N-cycle pulse width and sending it to a second CPLD / FPGA; receiving a response signal with an N-cycle pulse width from the second CPLD / FPGA; sampling a data read value with the N-cycle pulse width sent by the second CPLD / FPGA based on the response signal; and sending the N-cycle pulse width data read value to the CPU, causing the CPU to execute the data read. This method effectively reduces the number of wiring between CPLDs / FPGAs and conserves CPLD / FPGA pin resources.

Description

Technical Field

[0001] The present disclosure relates to the field of communication technology, and in particular to a data reading method and a CPLD / FPGA. Background Art

[0002] With the development of digital circuits, chips are becoming more and more powerful and integrated. A circuit board usually contains several functional chips, and the chips communicate with each other through various buses (such as the local bus LocalBus).

[0003] The LocalBus parallel bus is a common proprietary method for CPU subsystems to access registers of external devices, such as CPLDs / FPGAs (Complex Programmable Logic Devices) and / or FPGAs (Field-Programmable Gate Arrays). This access method consists of chip select, address latch, read, write, and AD address data multiplexing signals, which are directly output from the CPU chip pins. While faster than serial access, the number of traces is large, typically 36, increasing PCB routing complexity and occupying pin resources of external devices (such as CPLDs / FPGAs). Summary of the Invention

[0004] The present disclosure provides a data reading method and a CPLD / FPGA, by which the number of wirings between CPLDs / FPGAs and CPLD / FPGAs can be effectively reduced, thereby saving CPLD / FPGA pin resources.

[0005] An embodiment of the present disclosure provides a method for reading data, which is applied to a first CPLD / FPGA, where one end of the first CPLD / FPGA is connected to a second CPLD / FPGA. The method includes:

[0006] When it is known that the CS terminal and the OE terminal on the CPU side are at a low potential, a read request signal with a pulse width of N cycles is constructed and sent to the second CPLD / FPGA;

[0007] Receiving a response signal of N cycle pulse widths sent by the second CPLD / FPGA, and sampling a data reading value of the N cycle pulse widths sent by the second CPLD / FPGA according to the response signal of the N cycle pulse widths;

[0008] Send the data reading value of N cycle pulse width to the CPU so that the CPU can execute the data reading;

[0009] Wherein, N is greater than or equal to 2, and the read request signal of each cycle pulse width corresponds to a partial read address.

[0010] In another example, constructing a read request signal having a pulse width of N cycles and sending it to a second CPLD / FPGA includes:

[0011] Get the address bits of the second CPLD / FPGA;

[0012] The address bits are divided, and a read request signal with a pulse width of N cycles is constructed according to the division result.

[0013] The step of dividing the address bits and constructing a read request signal with N cycle pulse widths according to the division result includes:

[0014] The address bits are divided into equal parts, and a read request signal with a pulse width of N cycles is constructed according to the division result.

[0015] In another example, constructing a read request signal with a pulse width of N cycles and sending it to a second CPLD / FPGA includes:

[0016] Obtain a periodic pulse clock signal, and send read request signals with periodic pulse widths to the second CPLD / FPGA one by one according to the edges of the periodic pulse clock signal.

[0017] In another example, sampling the data reading value of the N cycle pulse widths sent by the second CPLD / FPGA according to the response signal of the N cycle pulse widths includes:

[0018] Obtain a periodic pulse clock signal, and sample the data reading value of N periodic pulse widths sent by the second CPLD / FPGA according to the edge of the periodic pulse clock signal.

[0019] The above method demonstrates that multiple-cycle pulse width signals are constructed to transmit read request signals, write request information, and data read and write data between the first CPLD / FPGA and the second CPLD / FPGA, thereby enabling pin multiplexing. Compared to a 36-bit parallel LOCALBUS, this frees up a significant amount of pin resources and reduces PCB routing pressure. Furthermore, the CPU reads and writes data to the second CPLD / FPGA at the same rate, allowing data reads and writes to be completed within the original frame length without adding any additional timing overhead.

[0020] The present disclosure also provides a method for reading data, which is applied to a second CPLD / FPGA, where one end of the second CPLD / FPGA is connected to a second CPLD / FPGA. The method includes:

[0021] Receive a read request signal with N cycle pulse widths sent by the first CPLD / FPGA, wherein each cycle pulse width of the read request signal corresponds to a portion of the read address;

[0022] Send a response signal of N cycle pulse widths and a data reading value of the N cycle pulse widths to the first CPLD / FPGA, so that the first CPLD / FPGA samples the data reading value of the N cycle pulse widths according to the response signal of the N cycle pulse widths.

[0023] The present disclosure also provides a method for writing data, which is applied to a first CPLD / FPGA, where one end of the first CPLD / FPGA is connected to a second CPLD / FPGA. The method includes:

[0024] When it is known that the CS and WE terminals on the CPU side are at a low potential, a write request signal with an N-cycle pulse width and write data with an N-cycle pulse width are constructed and sent to the second CPLD / FPGA.

[0025] So that the second CPLD / FPGA executes writing data according to the write request information signal of N cycle pulse width and the write data of N cycle pulse width;

[0026] The write request information number of each cycle pulse width carries part of the write address.

[0027] The step of constructing a write request signal with N cycle pulse widths and write data with N cycle pulse widths and sending them to a second CPLD / FPGA includes:

[0028] Obtain a periodic pulse clock signal, and send write request signals of each periodic pulse width and write data of each periodic pulse width to the second CPLD / FPGA in sequence according to the edge of the periodic pulse clock signal.

[0029] The present disclosure also provides a CPLD / FPGA, wherein the CPLD / FPGA includes:

[0030] A construction module is used to construct a read request signal with a pulse width of N cycles and send it to the next-level CPLD / FPGA when it is informed that the CS and OE terminals on the CPU side are at a low potential;

[0031] A receiving module is used to receive a response signal of N cycle pulse widths sent by the next-level CPLD / FPGA, and sample a data reading value of the N cycle pulse widths sent by the next-level CPLD / FPGA according to the response signal of the N cycle pulse widths;

[0032] The sending module is used to send the data reading value of N cycle pulse widths to the CPU so that the CPU can execute the data reading;

[0033] Wherein, N is greater than or equal to 2, and the read request signal of each cycle pulse width corresponds to a partial read address.

[0034] The present disclosure also provides a CPLD / FPGA, wherein the CPLD / FPGA includes:

[0035] A receiving module is used to receive a read request signal of N cycle pulse widths sent by the previous-level CPLD / FPGA, wherein each cycle pulse width of the read request signal corresponds to a portion of the read address;

[0036] The sending module is used to send a response signal of N cycle pulse widths and a data reading value of N cycle pulse widths to the upper-level CPLD / FPGA, so that the upper-level CPLD / FPGA samples the data reading value of N cycle pulse widths according to the response signal of N cycle pulse widths.

[0037] The present disclosure also provides a CPLD / FPGA, wherein the CPLD / FPGA includes:

[0038] The construction module is used to construct a write request information number with an N-cycle pulse width and write data with an N-cycle pulse width and send them to the next-level CPLD / FPGA when it is known that the CS terminal and WE terminal on the CPU side are at a low potential.

[0039] So that the next level CPLD / FPGA executes writing data according to the write request information signal of N cycle pulse width and the write data of N cycle pulse width;

[0040] The write request information number of each cycle pulse width carries part of the write address. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the specification and, together with the description, serve to explain the principles of the specification.

[0042] Figure 1 A flowchart of a MIPS series CPU read timing provided by an embodiment of the present disclosure.

[0043] Figure 2 A flowchart of a MIPS series CPU write sequence is provided in an embodiment of the present disclosure.

[0044] Figure 3 A schematic diagram of the logic of pins between various devices provided in an embodiment of the present disclosure.

[0045] Figure 4 A flowchart of a method for reading data provided by an embodiment of the present disclosure is provided.

[0046] Figure 5 A logical diagram of a MIPS series CPU read timing provided by an embodiment of the present disclosure.

[0047] Figure 6A flowchart of a method for writing data provided by an embodiment of the present disclosure.

[0048] Figure 7 A schematic diagram of the logic of pins between various devices provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0049] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with this specification. Rather, they are merely examples of apparatus and methods consistent with certain aspects of this specification, as detailed in the appended claims.

[0050] The terms used in this specification are for the purpose of describing specific embodiments only and are not intended to limit this specification. As used in this specification and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0051] It should be understood that although the terms first, second, third, etc. may be used in this specification to describe various information, such information should not be limited to these terms. These terms are merely used to distinguish information of the same type from one another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information without departing from the scope of this specification. Depending on the context, the term "if" as used herein may be interpreted as "when," "when," or "in response to determining."

[0052] like Figure 1As shown, a MIPS series CPU read timing is shown, which consists of a chip select signal IO_CS[7:0]_L (using one bit CS as the chip select signal), a read signal IO_OE_L, an address latch bit IO_ALE, and a 32-bit address data multiplexing line IO_AD[31:0]. A read operation proceeds as follows: after IO_CS is pulled low and a certain time interval (ALE_TO_CS-1) elapses, the address latch bit IO_ALE becomes low and becomes effective. During the effective period (ALE_WIDTH), the read address (Read Address) is sent to the external device (such as CPLD / FPGA) via IO_AD[31:0]. The external device (such as CPLD / FPGA) receives the IO_CS, IO_ALE, and IO_OE_L signals from the CPU and reconstructs the read timing. Based on the address obtained from IO_AD[31:0], it returns the corresponding value to the CPU. The CPU samples / reads the data (Read Data, the reading time is the Data sample point) returned by the external device (such as CPLD / FPGA) at a fixed time (WAIT_TO_DATA-2 seconds after IO_OE_L goes low), completing a read operation.

[0053] like Figure 2 As shown, a MIPS series CPU write timing is also shown. During the period when the address latch bit IO_ALE becomes low and effective (ALE_WIDTH), the write address (Write Address) is issued, and then during the period when the write operation bit IO_WE_L becomes low and effective, the write data (Write Data) is sent to the external device (such as CPLD / FPGA) to complete a write operation.

[0054] The logic diagram related to the above example is as follows Figure 3 As shown, the wiring within the dotted box 3 between CPU1 and CPLD / FPGA2 (corresponding to the first CPLD / FPGA in this embodiment), and the wiring within the dotted box 5 between CPLD / FPGA2 and CPLD / FPGA4 (corresponding to the second CPLD / FPGA in this embodiment) are the existing 36-bit parallel LOCALBUS, including a 32-bit address data multiplexing line AD[31:0], a chip select signal CS, an address latch ALE, a write signal WE, and a read signal OE.

[0055] The parallel LOCALBUS of the subsequent CPLD / FPGA4 is transparently transmitted from the previous CPLD / FPGA2, which directly increases the resource usage of the pins of the previous CPLD / FPGA2.

[0056] As can be seen from the above two examples, when PCB layout space is limited, a parallel LOCALBUS consisting of 36-bit signals not only increases the number of PCB traces and increases wiring difficulty, but also occupies pin resources of external devices (such as CPLD and FPGA).

[0057] To solve the above technical problems, the present disclosure provides a method for reading data. Figure 4 As shown, the method is applied to a first CPLD / FPGA, one end of the first CPLD / FPGA is connected to a second CPLD / FPGA, and the method includes:

[0058] S401: When it is known that the CS terminal and the OE terminal on the CPU side are at a low potential, a read request signal with a pulse width of N cycles is constructed and sent to the second CPLD / FPGA;

[0059] S402 receives a response signal of N cycle pulse widths sent by the second CPLD / FPGA, and samples a data reading value of the N cycle pulse widths sent by the second CPLD / FPGA according to the response signal of the N cycle pulse widths;

[0060] S403 sends the data reading value of N cycle pulse width to the CPU, so that the CPU executes data reading;

[0061] Wherein, N is greater than or equal to 2, and the read request signal of each cycle pulse width corresponds to a partial read address.

[0062] In this embodiment, the parallel LOCALBUS lines between CPLD / FPGA and CPLD / FPGA are mainly simplified to solve the wiring difficulty caused by the increase in the number of PCB traces and the large amount of pin resources occupied by external devices (such as CPLD, FPGA).

[0063] In this embodiment, one end of the first CPLD / FPGA may be connected to the CPU, and the other end may be connected to the second CPLD / FPGA. The first CPLD / FPGA monitors the potential of each pin connected to the CPU.

[0064] Generally, when the first CPLD / FPGA monitors that the CS terminal of the CPU is at the ground potential, it indicates that the CPU has enabled the first CPLD / FPGA.

[0065] At the same time, the CPU can determine whether it wants to read or write data by comparing the potentials of the OE and WE terminals of the first CPLD / FPGA. Generally, when the OE terminal is at a low potential, it indicates that the CPU wants to read data, and when the WE terminal is at a low potential, it indicates that the CPU wants to write data.

[0066] In step S401, when the first CPLD / FPGA learns that the CS and OE terminals on the CPU side are at a low potential, it indicates that the CPU wants to execute a data read. At this time, the CPU will send the address information of the CPLD / FPGA to be read to the first CPLD / FPGA. For example, if the CPU needs to read the second CPLD / FPGA, the first CPLD / FPGA will construct a read request signal with a pulse width of N cycles based on the CS and OE terminals being at a low potential and send it to the second CPLD / FPGA.

[0067] In this embodiment, N is greater than or equal to 2, and the cycle pulse width can be determined based on the cycle pulse width of the network. For example, the cycle pulse width can be 50 MHz (in other embodiments, the cycle pulse width can also be 40 MHz, 60 MHz, 100 MHz, etc., and different cycle pulse widths do not affect the implementation of this solution).

[0068] In this embodiment, the read request signal with a pulse width of N cycles may carry a portion of the read address, or the read address may be sent according to the read request signal with a pulse width of N cycles.

[0069] In one embodiment, if Figure 5 As shown, the read address is sent according to the read request signal of N cycle pulse widths, wherein the address bit number of the read request signal corresponding to each cycle pulse width is 8 bits (saving 24 bits of resources compared to the existing 32 bits). Since the address of the second CPLD / FPGA is 16 bits, in this embodiment, the number of N is 2, and the read address is sent using two LB_DATA[7:0] corresponding to the read request signal of each cycle pulse width. Specifically, Addr[15:8] is used to carry the high 8-bit information, and Addr[7:0] carries the low 8-bit information, that is, part of the read address is sent corresponding to the read request information of each cycle pulse width.

[0070] It should be noted that in this embodiment, two 8-bit bits are used to transmit the 16-bit read address (i.e., the 16-bit read address is divided into two 8-bit bits). In other embodiments, other bit numbers can also be used to transmit the read address, for example, three 7-bit bits are used to transmit the 16-bit read address, and there is no limitation here.

[0071] In this embodiment, when the first CPLD / FPGA sends a read address to the second CPLD / FPGA, the read address (read request signal with periodic pulse width) may be sent to the second CPLD / FPGA one by one according to the edge of the periodic pulse clock signal.

[0072] In step S402, the first CPLD / FPGA receives N (2 in this embodiment) periodic pulse width response signals (LB_BACK response signals) sent by the second CPLD / FPGA, and samples 16-bit data twice (for example, divided into high 8-bit data Data[15:8] and low 8-bit data Data[7:0]) according to the edge of the periodic pulse clock signal (preferably using falling edge sampling to ensure that the sampling time point is in the middle of the data and that the sampling establishment and holding margin is sufficient). After the first CPLD / FPGA completes the 16-bit data sampling, it transmits it to CPU1 through the parallel LOCALBUS3. CPU1 performs data sampling 13 after the T_DELAY2 delay interval of the LB_BACK10 response signal (the purpose of the delay is to ensure that the 16-bit data is reliably transmitted to the CPU1 port) to complete the read operation.

[0073] As can be seen from the above embodiments, the address information and data information between the first CPLD / FPGA and the second CPLD / FPGA no longer occupy 32-bit line resources. Instead, the line resources are divided into N blocks, each containing a small amount of line resources. This achieves line (pin) multiplexing, and thus frees up a large number of pin resources compared to a 36-bit parallel LOCALBUS, reducing PCB routing pressure. At the same time, the CPU reads and writes the second CPLD / FPGA at the same rate, and can complete a data read and write within the original frame length without adding additional timing overhead.

[0074] The present disclosure also provides a method for reading data, which is applied to a second CPLD / FPGA, where one end of the second CPLD / FPGA is connected to a second CPLD / FPGA. The method includes:

[0075] Receive a read request signal with N cycle pulse widths sent by the first CPLD / FPGA, wherein each cycle pulse width of the read request signal corresponds to a portion of the read address;

[0076] Send a response signal of N cycle pulse widths and a data reading value of the N cycle pulse widths to the first CPLD / FPGA, so that the first CPLD / FPGA samples the data reading value of the N cycle pulse widths according to the response signal of the N cycle pulse widths.

[0077] This embodiment corresponds to the above embodiment, where the second CPLD / FPGA is a lower-level device of the first CPLD / FPGA.

[0078] When the second CPLD / FPGA receives the read request signal with N cycle pulse width sent by the first CPLD / FPGA, it can complete the processing within T_DELAY1 time according to the clock signal with cycle pulse width, the read request signal with N cycle pulse width (LB_REQ read request signal 7) and the 16-bit read address 8, and return the LB_BACK response signal 10 and the 16-bit data read value 11, so that the first CPLD / FPGA can sample the data read value 11.

[0079] The present disclosure also provides a method for writing data. Figure 6 As shown, the method is applied to a first CPLD / FPGA, one end of the first CPLD / FPGA is connected to a second CPLD / FPGA, and the method includes:

[0080] S601: When it is learned that the CS terminal and the WE terminal on the CPU side are at a low potential, a write request signal with an N-cycle pulse width and write data with an N-cycle pulse width are constructed and sent to the second CPLD / FPGA;

[0081] S602: enabling the second CPLD / FPGA to write data according to the write request information signal of N cycle pulse width and the write data of N cycle pulse width;

[0082] The write request information number of each cycle pulse width carries part of the write address.

[0083] In step S601, when the first CPLD / FPGA learns that the CS and WE terminals on the CPU side are at a low potential, it knows that the CPU is going to write data. The first CPLD / FPGA learns the write address of the CPU, and constructs a write request information number with an N-cycle pulse width and write data with an N-cycle pulse width and sends them to the second CPLD / FPGA.

[0084] For the sake of explanation, reference Figure 5 To illustrate, the timing of CPU1's write operation on the CPLD / FPGA4 (second CPLD / FPGA) register is as follows; after the CS and WE signals are pulled low to take effect, CPLD / FPGA2 (first CPLD / FPGA) constructs an LB_REQ write request signal (i.e., a write request information number with a pulse width of N cycles) 14 with a pulse width of 4 clock cycles (clock frequency 50MHz) based on the CS and WE signals.

[0085] Within the 4 clock cycles of the LB_REQ write request signal 14, the 16-bit write address 16 (divided into the upper 8-bit write address Addr[15:8] and the lower 8-bit write address Addr[7:0]) and the 16-bit write data 17 (divided into the upper 8-bit write data Data[15:8] and the lower 8-bit write data Data[7:0]) are respectively issued on the 4 consecutive rising edges of the 50MHz clock, and the write operation is completed.

[0086] like Figure 7 As shown, for ease of distinction, the original 36-bit line is used between CPLD / FPGA2 (the first CPLD / FPGA) and CPU1, and the 11-bit line is used between CPLD / FPGA4 (the second CPLD / FPGA) and CPLD / FPGA2 after applying this solution.

[0087] It can be seen that after adopting this solution, both read requests and write requests can be represented by LB_REQ. At the same time, the read address, write address, read data and write data (LB_DATA) all use 8 bits. When the read / write address and read / write data exceed 8 bits, the 8 bits can be reused again in the next cycle pulse width, thus saving 24 bits compared to the original 32 bits of AD[31:0], thereby saving CPLD / FPGA pins and simplifying wiring.

[0088] Based on the above method embodiments, the present disclosure further provides a CPLD / FPGA, wherein the CPLD / FPGA includes:

[0089] A construction module is used to construct a read request signal with a pulse width of N cycles and send it to the next-level CPLD / FPGA when it is informed that the CS and OE terminals on the CPU side are at a low potential;

[0090] A receiving module is used to receive a response signal of N cycle pulse widths sent by the next-level CPLD / FPGA, and sample a data reading value of the N cycle pulse widths sent by the next-level CPLD / FPGA according to the response signal of the N cycle pulse widths;

[0091] The sending module is used to send the data reading value of N cycle pulse widths to the CPU so that the CPU can execute the data reading;

[0092] Wherein, N is greater than or equal to 2, and the read request signal of each cycle pulse width corresponds to a partial read address.

[0093] Based on the above method embodiments, the present disclosure further provides a CPLD / FPGA, wherein the CPLD / FPGA includes:

[0094] A receiving module is used to receive a read request signal of N cycle pulse widths sent by the previous-level CPLD / FPGA, wherein each cycle pulse width of the read request signal carries a corresponding read address;

[0095] The sending module is used to send a response signal of N cycle pulse widths and a data reading value of N cycle pulse widths to the upper-level CPLD / FPGA, so that the upper-level CPLD / FPGA samples the data reading value of N cycle pulse widths according to the response signal of N cycle pulse widths.

[0096] Based on the above method embodiments, the present disclosure further provides a CPLD / FPGA, wherein the CPLD / FPGA includes:

[0097] The construction module is used to construct a write request information number with an N-cycle pulse width and write data with an N-cycle pulse width and send them to the next-level CPLD / FPGA when it is known that the CS terminal and WE terminal on the CPU side are at a low potential.

[0098] So that the second CPLD / FPGA executes writing data according to the write request information signal of N cycle pulse width and the write data of N cycle pulse width;

[0099] The write request information number of each cycle pulse width carries part of the write address.

[0100] The foregoing description of this specification describes specific embodiments. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in an order different from that described in the embodiments and still achieve the desired results. Furthermore, the processes depicted in the accompanying drawings do not necessarily require the specific order shown or the sequential order to achieve the desired results. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0101] Other embodiments of the present invention will readily occur to those skilled in the art upon consideration of the present invention and practice of the invention claimed herein. This specification is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of this specification and include common knowledge or customary techniques in the art not claimed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present invention being indicated by the following claims.

[0102] It should be understood that the present description is not limited to the exact structure that has been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present description is limited only by the appended claims.

[0103] The above description is only a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this specification should be included in the scope of protection of this specification.

Claims

1. A method for reading data, characterized in that: The method is applied to a first CPLD / FPGA, one end of which is connected to a second CPLD / FPGA, and the method includes: When it is known that the CS terminal and the OE terminal on the CPU side are at a low potential, a read request signal with a pulse width of N cycles is constructed and sent to the second CPLD / FPGA; Receiving a response signal of N cycle pulse widths sent by the second CPLD / FPGA, and sampling a data reading value of the N cycle pulse widths sent by the second CPLD / FPGA according to the response signal of the N cycle pulse widths; Send the data reading value of N cycle pulse width to the CPU so that the CPU can execute the data reading; Wherein, N is greater than or equal to 2, and the read request signal of each cycle pulse width corresponds to a partial read address.

2. The method according to claim 1, characterized in that The step of constructing a read request signal having N cycle pulse widths and sending it to a second CPLD / FPGA includes: Get the address bits of the second CPLD / FPGA; The address bits are divided, and a read request signal with a pulse width of N cycles is constructed according to the division result.

3. The method according to claim 2, characterized in that The step of dividing the address bits and constructing a read request signal with N cycle pulse widths according to the division result includes: The address bits are divided into equal parts, and a read request signal with a pulse width of N cycles is constructed according to the division result.

4. The method according to claim 1, wherein Constructing a read request signal with a pulse width of N cycles and sending it to the second CPLD / FPGA includes: Obtain a periodic pulse clock signal, and send read request signals with periodic pulse widths to the second CPLD / FPGA one by one according to the edges of the periodic pulse clock signal.

5. The method according to claim 1, characterized in that The method of sampling the data reading value of the N cycle pulse widths sent by the second CPLD / FPGA according to the response signal of the N cycle pulse widths includes: Obtain a periodic pulse clock signal, and sample the data reading value of N periodic pulse widths sent by the second CPLD / FPGA according to the edge of the periodic pulse clock signal.

6. The method according to claim 1, characterized in that The method is applied to a second CPLD / FPGA, one end of the second CPLD / FPGA is connected to a second CPLD / FPGA, and the method includes: Receive a read request signal with N cycle pulse widths sent by the first CPLD / FPGA, wherein each cycle pulse width of the read request signal corresponds to a portion of the read address; Send a response signal of N cycle pulse widths and a data reading value of the N cycle pulse widths to the first CPLD / FPGA, so that the first CPLD / FPGA samples the data reading value of the N cycle pulse widths according to the response signal of the N cycle pulse widths.

7. A method for writing data, characterized in that: The method is applied to a first CPLD / FPGA, one end of which is connected to a second CPLD / FPGA, and the method includes: When it is known that the CS and WE terminals on the CPU side are at a low potential, a write request signal with an N-cycle pulse width and write data with an N-cycle pulse width are constructed and sent to the second CPLD / FPGA. So that the second CPLD / FPGA executes writing data according to the write request information signal of N cycle pulse width and the write data of N cycle pulse width; The write request information number of each cycle pulse width carries part of the write address.

8. The method according to claim 7, characterized in that The step of constructing a write request signal with N cycle pulse widths and write data with N cycle pulse widths and sending them to a second CPLD / FPGA includes: Obtain a periodic pulse clock signal, and send write request signals of each periodic pulse width and write data of each periodic pulse width to the second CPLD / FPGA in sequence according to the edge of the periodic pulse clock signal.

9. A CPLD / FPGA, characterized in that: The CPLD / FPGA includes: A construction module is used to construct a read request signal with a pulse width of N cycles and send it to the next-level CPLD / FPGA when it is informed that the CS and OE terminals on the CPU side are at a low potential; A receiving module is used to receive a response signal of N cycle pulse widths sent by the next-level CPLD / FPGA, and sample a data reading value of the N cycle pulse widths sent by the next-level CPLD / FPGA according to the response signal of the N cycle pulse widths; The sending module is used to send the data reading value of N cycle pulse widths to the CPU so that the CPU can execute the data reading; Wherein, N is greater than or equal to 2, and the read request signal of each cycle pulse width corresponds to a partial read address.

10. The CPLD / FPGA according to claim 9, wherein: The CPLD / FPGA includes: A receiving module is used to receive a read request signal of N cycle pulse widths sent by the previous-level CPLD / FPGA, wherein each cycle pulse width of the read request signal carries a corresponding read address; The sending module is used to send a response signal of N cycle pulse widths and a data reading value of N cycle pulse widths to the upper-level CPLD / FPGA, so that the upper-level CPLD / FPGA samples the data reading value of N cycle pulse widths according to the response signal of N cycle pulse widths.

11. A CPLD / FPGA, characterized in that: The CPLD / FPGA includes: The construction module is used to construct a write request information number with an N-cycle pulse width and write data with an N-cycle pulse width and send them to the next-level CPLD / FPGA when it is known that the CS terminal and WE terminal on the CPU side are at a low potential. So that the next level CPLD / FPGA executes the write data according to the write request information number of N cycle pulse width and the write data of N cycle pulse width; The write request information number of each cycle pulse width carries part of the write address.

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