Method for manufacturing trench gate field effect transistor

Abstract

The application provides a trench gate field effect transistor manufacturing method. By etching the top corner of the gate trench to form a gentle transition section, the etching rate at the top corner of the trench in the etching process is reduced, so that the oxide layer on the top corner of the trench is not quickly consumed and can be reserved, effectively avoiding the problem of ion diffusion between the gate electrode and the well region.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for fabricating a trench gate field-effect transistor. Background Technology

[0002] In trench gate field-effect transistors (FETs), the gate structure is disposed within a gate trench in the substrate, and a well region and a source region are formed in the substrate on the side of the gate trench. Currently, the fabrication method for trench gate FETs generally involves first forming a gate electrode within the gate trench in the substrate, and then forming a well region in the substrate on the side of the gate trench. However, trench gate FETs fabricated using current processes are prone to ion interdiffusion between the gate electrode and the well region, leading to a drift in the device's electrical performance. Summary of the Invention

[0003] The purpose of this invention is to provide a method for fabricating a trench gate field-effect transistor to solve the problem of ion interdiffusion between the gate electrode and the well region in existing trench gate field-effect transistors.

[0004] To address the aforementioned technical problems, the present invention provides a method for fabricating a trench gate field-effect transistor, comprising: forming a gate trench in a substrate, and forming a gate oxide layer and a gate electrode, wherein the gate oxide layer covers the inner wall of the gate trench and the top surface of the substrate, and the gate electrode fills the gate trench; etching back the gate oxide layer on the top surface of the substrate until the apex of the gate trench is exposed, and etching the apex of the gate trench to form a transition segment; forming an oxide layer at least on the transition segment; and performing an ion implantation process to form a well region in the substrate on the side of the gate trench.

[0005] Optionally, during the etching process of the gate oxide layer on the top surface of the substrate, the etching rate at the apex of the gate trench is higher than the etching rate on the top surface of the substrate, so that when the apex of the gate trench is exposed, a portion of the gate oxide layer is still retained on the top surface of the substrate.

[0006] Optionally, the apex corners of the exposed gate trench are isotropically etched to form the transition segment.

[0007] Optionally, after forming the transition section, the process further includes: performing a first thermal annealing process, and oxidizing the transition section during the thermal annealing process to form the oxide layer.

[0008] Optionally, the first thermal annealing process includes performing thermal annealing treatment in an oxygen atmosphere.

[0009] Optionally, in the first thermal annealing process, the top surface of the substrate is further oxidized to form an oxide layer; and, before performing the ion implantation process, a back etching process is performed to reduce the thickness of the oxide layer on the top surface of the substrate.

[0010] Optionally, the thickness of the oxide layer on the top surface of the substrate can be reduced to less than 300 angstroms.

[0011] Optionally, after performing the ion implantation process, a second thermal annealing process may also be performed.

[0012] Optionally, the inclination angle of the sidewalls of the gate trench relative to the height direction is less than or equal to 5°.

[0013] Optionally, the trench gate field-effect transistor is a shielded gate field-effect transistor. Furthermore, before forming the gate electrode, the method further includes forming a shielding electrode within the gate trench.

[0014] In the trench gate field-effect transistor fabrication method provided by the present invention, by etching the apex of the gate trench, the apex position of the gate trench is changed from a convex sharp corner structure to a more gentle transition section (e.g., an arc-shaped structure), which reduces the etching rate at the apex position of the trench during the etching process. This ensures that the oxide layer on the apex of the trench is not consumed quickly but can be retained, effectively avoiding the problem of ion diffusion between the gate electrode and the well region.

[0015] Furthermore, the oxide layer at the apex of the gate trench (i.e., the oxide layer formed on the transition section) can be formed simultaneously with the thermal annealing of the gate electrode, which helps to reduce the number of preparation steps and simplify the process. Attached Figure Description

[0016] Figure 1 This is a schematic flowchart of a method for fabricating a trench gate field-effect transistor according to an embodiment of the present invention.

[0017] Figures 2-9 This is a schematic diagram of the trench gate field-effect transistor in one embodiment of the present invention during its fabrication process.

[0018] The reference numerals in the attached figures are as follows:

[0019] 100-substrate;

[0020] 110 - Gate trench;

[0021] 210 - Insulating dielectric layer;

[0022] 220 - Gate oxide layer;

[0023] 310 - Shielding electrode;

[0024] 320 - Gate electrode;

[0025] 400-Oxide layer;

[0026] 500-well region. Detailed Implementation

[0027] As described in the background section, existing trench gate field-effect transistors often experience a shift in electrical performance due to ion diffusion between the gate electrode and the well region. In response, the inventors of this invention, through research, discovered that a primary diffusion channel for ion diffusion between the gate electrode within the gate trench and the well region on the side of the gate trench is located at the apex of the gate trench.

[0028] Specifically, before performing ion implantation to form the well region, it is typically necessary to thin the film layer on the top surface of the substrate to facilitate ion implantation. However, during the etching process to thin the film layer on the top surface of the substrate, the etching rate at the apex of the gate trench is relatively high, causing the film layer at the trench apex to be completely consumed, exposing the apex of the gate trench. As a result, when a high-temperature thermal annealing process is subsequently performed to activate the doped ions in the well region, ions in the gate electrode and ions in the well region will diffuse into each other through the apex of the trench.

[0029] In view of this, the present invention provides a method for fabricating a trench gate field-effect transistor, the details of which can be found in [reference needed]. Figure 1 As shown, the preparation method includes the following steps.

[0030] In step S100, a gate trench is formed in a substrate, and a gate oxide layer and a gate electrode are formed. The gate oxide layer covers the inner wall of the gate trench and the top surface of the substrate, and the gate electrode fills the gate trench.

[0031] In step S200, the gate oxide layer on the top surface of the substrate is etched back until the apex of the gate trench is exposed, and the apex of the gate trench is etched to form a transition segment.

[0032] Step S300: An oxide layer is formed at least on the transition section.

[0033] Step S400: Perform an ion implantation process to form a well region in the substrate on the side of the gate trench.

[0034] In other words, the trench gate field-effect transistor fabrication method provided by this invention reduces the etching rate at the apex of the gate trench by transforming the apex into a gentle transition section. This allows the oxide layer at the apex of the trench to be well preserved, avoiding ion diffusion between the gate electrode and the well region. In particular, the oxide layer at the apex of the gate trench can be formed simultaneously with the thermal annealing of the gate electrode, which helps reduce fabrication steps and simplify the process.

[0035] The following is in conjunction with the appendix Figures 2-9 The method for fabricating the trench gate field-effect transistor proposed in this invention will be further described in detail with specific embodiments, wherein... Figures 2-9 This is a schematic diagram of the trench gate field-effect transistor in the fabrication process according to an embodiment of the present invention. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise scales, used only to facilitate and clarify the illustration of the embodiments of the present invention. It should be understood that relative terms such as "above," "below," "top," "bottom," and "over" shown in the drawings can be used to describe the relationships between various elements. These relative terms are intended to cover different orientations of elements other than those depicted in the drawings. For example, if the device is inverted relative to the view in the drawings, an element described, for example, as being "above" another element would now be below that element.

[0036] In step S100, please refer to the following for details. Figures 2-4 As shown, a gate trench 110 is formed in a substrate 100 (e.g., a silicon substrate), and a gate oxide layer 220 and a gate electrode 320 are formed. The gate oxide layer 220 covers the inner wall of the gate trench 110 and the top surface of the substrate 100, and the gate electrode 320 fills the gate trench 110.

[0037] Specifically, the method for forming the gate trench 110 includes, for example, forming a mask layer on the top surface of the substrate 100 to define the pattern of the gate trench; then, etching the substrate 100 using the mask layer as a mask to form the gate trench 110. In this embodiment, the sidewalls of the gate trench 110 can be vertical sidewalls or near-vertical sidewalls. That is, the tilt angle of the sidewalls of the gate trench 110 relative to the height direction is small, for example, the tilt angle is less than or equal to 5°, and even further less than or equal to 1°. It should be noted that the "tilt angle of the sidewalls of the gate trench 110 relative to the height direction" mentioned here refers to the angle between the sidewalls of the gate trench 110 and the height direction.

[0038] After the gate trench 110 is formed, a gate structure can be formed within the gate trench 110. In this embodiment, the trench gate field-effect transistor is specifically a shielded gate field-effect transistor (SGT). Based on this, before forming the gate electrode 320, a shielding electrode 310 is also formed within the gate trench 110, and the gate electrode 320 is isolated and disposed above the shielding electrode 310.

[0039] Key reference Figure 3 As shown, after forming the gate trench 110 and before forming the shielding electrode 310, the method further includes forming an insulating dielectric layer 210 in the gate trench 110, the insulating dielectric layer 210 covering the sidewalls and bottom wall of the gate trench 110. The insulating dielectric layer 210 may be formed, for example, using a thermal oxidation process, and the material of the insulating dielectric layer 210 may include, for example, silicon oxide (SiO). After forming the insulating dielectric layer 210, the shielding electrode 310 is filled into the gate trench 110, and the shielding electrode 310 is correspondingly formed on the insulating dielectric layer 210. In this embodiment, after forming the shielding electrode 310, an isolation layer is also formed on the shielding electrode 310 to isolate the shielding electrode 310 from the subsequently formed gate electrode 320.

[0040] Furthermore, a gate oxide layer 220 is formed, which covers the sidewalls of the gate trench and also covers the top surface of the substrate 100. The gate oxide layer 220 has a thickness greater than 500 angstroms, for example, 500-800 angstroms; and the material of the gate oxide layer 220 includes silicon oxide.

[0041] Next, refer to Figure 4 As shown, a gate electrode 320 is formed. In one example, the method for forming the gate electrode 320 includes, for example, depositing an electrode material layer that fills the gate trench 110 and covers the top surface of the substrate 100, wherein the electrode material layer may be made of polysilicon; then, performing an etch-back process to remove the electrode material on the top surface of the substrate, such that the remaining electrode material remains within the gate trench 110 to form the gate electrode 320. Specifically, the gate electrode 320 may be an N-doped gate electrode or a P-doped gate electrode. Alternatively, the doped gate electrode 320 may be formed by in-situ doping; or, an ion implantation process may be performed after the formation of the gate electrode to form the doped gate electrode 320.

[0042] In step S200, please refer to the following for details. Figures 5-6As shown, the gate oxide layer 220 on the top surface of the substrate is etched back to expose the apex of the gate trench 110, and the apex of the gate trench is etched to form a transition segment.

[0043] Specifically, the apex of the gate trench 110 has a sharp angle structure. Therefore, during the etching process of the gate oxide layer 220 on the top surface of the substrate, the etching rate for the apex of the gate trench 110 will be higher than the etching rate for the gate oxide layer on the top surface of the substrate. As a result, when the apex of the gate trench 110 is exposed, a portion of the gate oxide layer 220 is still retained on the top surface of the substrate.

[0044] Continue to refer to Figure 6 As shown, the apex of the exposed gate trench 110 is etched to form a smooth transition section, thereby alleviating the sharp corner structure at the apex of the gate trench. Specifically, an isotropic etching process can be performed on the apex of the exposed gate trench 110 to remove the sharp corner, and further, the apex of the gate trench 110 can be made into a concave structure. That is, after etching the apex of the gate trench 110, the surface at the etched apex position becomes a concave arc surface, forming a smooth transition section.

[0045] It should be noted that when etching the apex of the gate trench 110, since a portion of the gate oxide layer 220 is still covered on the top surface of the substrate, the top surface of the substrate 100 will not be completely consumed when etching the apex of the gate trench 110, and the protruding sharp corner of the trench can be precisely removed.

[0046] In step S300, please refer to the following for details. Figure 7 As shown, an oxide layer is formed at least on the transition section. In this embodiment, the oxide layer 400 can be formed in a first thermal annealing process, which can be used to repair crystal damage within the gate electrode 320 and activate doped ions within the gate electrode 320. That is, during the execution of the first thermal annealing process, the transition section at the apex of the gate trench 110 can be oxidized simultaneously to form an oxide layer.

[0047] In a specific embodiment, the first thermal annealing process can be performed in an oxygen atmosphere, thereby simultaneously oxidizing the apex of the gate trench 110. For example, oxygen can be introduced into an annealing furnace to perform the thermal annealing process. Furthermore, the first thermal annealing process also oxidizes the top surface of the substrate to form an oxide layer, such as... Figure 7 As shown, an oxide layer 400 can be formed on the top surface of the substrate and the apex corner of the trench through a first thermal annealing process.

[0048] In this embodiment, the first thermal annealing process increases the thickness of the oxide layer 400 on the top surface of the substrate to at least 800 angstroms, for example, the thickness of the oxide layer 400 is 800-1200 angstroms.

[0049] It should be noted that in this embodiment, the first thermal annealing process simultaneously forms oxide layers 400 on both the top surface of the substrate and the apex corners of the trenches, resulting in a relatively large thickness of the oxide layer 400 on the top surface of the substrate. Therefore, before performing the ion implantation process, the process further includes thinning the thickness of the oxide layer 400 to facilitate the subsequent ion implantation process. See details... Figure 8 As shown, in this embodiment, the thickness of the oxide layer 400 can be reduced to less than 400 angstroms through a back etching process, for example, the thickness of the oxide layer 400 can be reduced to 300-200 angstroms.

[0050] It should be noted that during the etching of the oxide layer 400 to reduce its thickness, since the apex of the gate trench 110 is a gentle transition section without sharp corners, the etching rate at the apex of the trench can be reduced, so that the oxide layer on the top surface of the substrate and the apex of the trench can be consumed evenly, avoiding the complete removal and exposure of the oxide layer at the apex of the trench.

[0051] In step S400, please refer to the following for details. Figure 9 As shown, an ion implantation process is performed to form a well region 500 in the substrate on the side of the gate trench. The ion doping type of the well region 500 is opposite to that of the gate electrode 320; for example, if the gate electrode 320 is N-doped, then the well region 500 is P-doped.

[0052] Furthermore, after performing the ion implantation process, a second thermal annealing process is used to repair crystal damage within the ion-doped region and activate the doped ions. It should be noted that during the second thermal annealing process, the gate electrode 320 and the well region 500 are isolated by an oxide layer, and the apex of the gate trench 110 is still covered by the oxide layer 400, effectively preventing ion interdiffusion between the gate electrode 320 and the well region 500 during the second thermal annealing process.

[0053] In summary, in the trench gate field-effect transistor fabrication method provided in this embodiment, the gate oxide layer on the top surface of the substrate is etched to expose the apex of the gate trench, and the apex of the gate trench is further etched to form a smooth transition section. For example, the apex of the gate trench can be changed from a convex sharp corner structure to a concave arc-shaped structure. Furthermore, while performing crystal repair and ion activation on the gate electrode using the first thermal annealing process, the apex of the gate trench can also be oxidized to form an oxide layer. Because the apex of the gate trench is more rounded, the oxide layer at the apex of the trench is less likely to be rapidly consumed and can be retained. Thus, the problem of ion diffusion between the gate electrode and the well region through the trench apex can be avoided.

[0054] Furthermore, during the process of etching the gate oxide layer on the top surface of the substrate to expose the apex of the gate trench, the etching process can be used to target the etching rate difference between the top surface of the substrate and the apex of the trench. This allows a portion of the gate oxide layer to remain on the top surface of the substrate even when the apex of the gate trench is exposed, thus enabling better rounding of the apex of the gate trench under the coverage of the gate oxide layer.

[0055] It should be noted that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the scope of protection of the present invention.

[0056] It should also be understood that, unless otherwise specified or indicated, the terms "first," "second," "third," etc., used in the specification are merely for distinguishing individual components, elements, steps, etc., and are not for indicating logical or sequential relationships between them. Furthermore, it should be recognized that the terms described herein are used only to describe specific embodiments and are not intended to limit the scope of the invention. It must be noted that the singular forms "a" and "an" used herein and in the appended claims include a plural basis unless the context clearly indicates the opposite. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps and secondary devices. All conjunctions used should be understood in the broadest sense. And the word "or" should be understood to have the definition of logical "or," not logical "exclusive or," unless the context clearly indicates the opposite.

Claims

1. A method for fabricating a trench gate field-effect transistor, characterized in that, include: A gate trench is formed in a substrate, and a gate oxide layer and a gate electrode are formed therein. The gate oxide layer covers the inner wall of the gate trench and the top surface of the substrate, and the gate electrode fills the gate trench. The gate oxide layer on the top surface of the substrate is etched back until the apex of the gate trench is exposed; and when the apex of the gate trench is exposed, a portion of the gate oxide layer is still retained on the top surface of the substrate. Using the portion of the gate oxide layer retained on the top surface of the substrate as a barrier, the apex corner of the gate trench is etched to form a gentle transition section; An oxide layer is formed at least on the transition section; as well as, An ion implantation process is performed to form a well region in the substrate on the side of the gate trench.

2. The method for fabricating a trench gate field-effect transistor as described in claim 1, characterized in that, During the etching process of the gate oxide layer on the top surface of the substrate, the etching rate at the apex of the gate trench is higher than the etching rate on the top surface of the substrate, so that when the apex of the gate trench is exposed, a portion of the gate oxide layer is still retained on the top surface of the substrate.

3. The method for fabricating a trench gate field-effect transistor as described in claim 1, characterized in that, The exposed gate trench is isotropically etched at its apex to form the transition section.

4. The method for fabricating a trench gate field-effect transistor as described in claim 1, characterized in that, After the transition section is formed, the process further includes: performing a first thermal annealing process, and oxidizing the transition section during the thermal annealing process to form the oxide layer.

5. The method for fabricating a trench gate field-effect transistor as described in claim 4, characterized in that, The first thermal annealing process includes performing thermal annealing treatment in an oxygen atmosphere.

6. The method for fabricating a trench gate field-effect transistor as described in claim 4, characterized in that, In the first thermal annealing process, the top surface of the substrate is also oxidized to form an oxide layer; In addition, prior to performing the ion implantation process, a back etching process is performed to reduce the thickness of the oxide layer on the top surface of the substrate.

7. The method for fabricating a trench gate field-effect transistor as described in claim 6, characterized in that, The thickness of the oxide layer on the top surface of the substrate is reduced to less than 300 angstroms.

8. The method for fabricating a trench gate field-effect transistor as described in claim 1, characterized in that, Following the ion implantation process, a second thermal annealing process is also performed.

9. The method for fabricating a trench gate field-effect transistor as described in claim 1, characterized in that, The sidewalls of the gate trench have an inclination angle of less than or equal to 5° relative to the height direction.

10. The method for fabricating a trench gate field-effect transistor according to any one of claims 1-9, characterized in that, The trench gate field-effect transistor is a shielded gate field-effect transistor.

11. The method for fabricating a trench gate field-effect transistor as described in claim 10, characterized in that, Before forming the gate electrode, the method further includes forming a shielding electrode within the gate trench.

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