Method of manufacturing a semiconductor structure, semiconductor structure and memory

Abstract

The application provides a semiconductor structure preparation method, a semiconductor structure and a memory. The semiconductor structure preparation method comprises the following steps: providing a substrate, wherein the substrate comprises an array region, a core region and a boundary region located between the array region and the core region; forming a first isolation layer, wherein the first isolation layer is located in the array region and a second part of the boundary region adjacent to the array region; and forming a first conductive layer, wherein the first conductive layer is located in the core region and a first part of the boundary region adjacent to the core region. The first conductive layer is subjected to a planarization treatment to obtain a flat top surface. Therefore, the semiconductor structure preparation method, the semiconductor structure and the memory provided by the application can improve the flatness of the surface of the first conductive layer, thereby avoiding or reducing the influence on the structure and performance of the semiconductor structure and the memory.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor structure, a semiconductor structure, and a memory. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory that allows for high-speed, random writing and reading of data and is widely used in data storage devices.

[0003] In related technologies, DRAM includes a substrate, which includes an array region and a peripheral region disposed outside the array region. During DRAM fabrication, an isolation layer is typically formed on the substrate, extending from the array region to the peripheral region, and a conductive layer is formed on the isolation layer.

[0004] However, in the aforementioned DRAM manufacturing process, the surface flatness of the conductive layer is poor, which affects the structure and performance of the DRAM. Summary of the Invention

[0005] This application provides a method for fabricating a semiconductor structure, a semiconductor structure, and a memory, which can improve the surface flatness of the conductive layer, thereby avoiding affecting the structure and performance of the semiconductor structure and the memory.

[0006] The embodiments of this application provide the following technical solutions:

[0007] A first aspect of this application provides a method for fabricating a semiconductor structure, comprising: providing a substrate, the substrate including an array region, a core region, and a boundary region located between the array region and the core region; forming a first initial isolation layer, the first initial isolation layer being located in the array region, the boundary region, and the core region, and the first initial isolation layer covering the substrate; removing the first initial isolation layer located in the core region and a first portion of the boundary region adjacent to the core region to obtain a first isolation layer; forming a first initial conductive layer, the first initial conductive layer being located in the array region, the boundary region, and the core region, and the first initial conductive layer covering the substrate and the first isolation layer; planarizing the first initial conductive layer to obtain a first intermediate conductive layer; and removing the first intermediate conductive layer located in the array region and a second portion of the boundary region adjacent to the array region to obtain a first conductive layer; wherein the orthographic projection of the first conductive layer on the substrate partially overlaps with the orthographic projection of the first isolation layer on the substrate, and the overlapping portion of the orthographic projection of the first conductive layer on the substrate and the orthographic projection of the first isolation layer on the substrate is located within the boundary region.

[0008] The second aspect of this application provides a semiconductor structure, which is prepared by the semiconductor structure preparation method described in the first aspect above.

[0009] A third aspect of this application provides a memory, including a semiconductor structure prepared by the semiconductor structure preparation method described in the first aspect above.

[0010] The semiconductor structure fabrication method, semiconductor structure, and memory provided in this application embodiment include: providing a substrate, the substrate including an array region, a core region, and a boundary region located between the array region and the core region; forming a first initial isolation layer, the first initial isolation layer being located in the array region, the boundary region, and the core region, and the first initial isolation layer covering the substrate; removing the first initial isolation layer located in the core region and a first portion of the boundary region adjacent to the core region to obtain a first isolation layer; forming a first initial conductive layer, the first initial conductive layer being located in the array region, the boundary region, and the core region, and the first initial conductive layer covering the substrate and the first isolation layer; planarizing the first initial conductive layer to obtain a first intermediate conductive layer; and removing the first intermediate conductive layer located in the array region and a second portion of the boundary region adjacent to the array region to obtain a first conductive layer; wherein the orthographic projection of the first conductive layer on the substrate partially overlaps with the orthographic projection of the first isolation layer on the substrate, and the overlapping portion of the orthographic projection of the first conductive layer on the substrate and the orthographic projection of the first isolation layer on the substrate is located within the boundary region. Because the first initial conductive layer is planarized, the surface of the first conductive layer is relatively flat, which in turn makes the other functional layers prepared above the first conductive layer relatively flat and the thickness of the functional layer above the first conductive layer more uniform. This avoids or reduces the occurrence of functional layer residues during the etching process, thereby avoiding or reducing the impact on the structure and performance of the semiconductor structure and memory.

[0011] The structure of this application, as well as its other inventive objectives and beneficial effects, will become more apparent from the description of the preferred embodiments taken in conjunction with the accompanying drawings. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic diagram of a semiconductor structure;

[0014] Figure 2 A schematic flowchart illustrating the method for fabricating a semiconductor structure provided in this application embodiment;

[0015] Figure 3 A schematic diagram of the structure providing the substrate is provided for an embodiment of this application;

[0016] Figure 4 This is a schematic diagram of the structure forming the first initial isolation layer provided in an embodiment of this application;

[0017] Figure 5 This is a schematic diagram of the structure forming the first isolation layer provided in an embodiment of this application;

[0018] Figure 6 This is a schematic diagram of the structure for forming the first initial conductive layer provided in an embodiment of this application;

[0019] Figure 7 This is a schematic diagram of a structure for planarizing the first initial conductive layer, provided in an embodiment of this application.

[0020] Figure 8 This is a schematic diagram of the structure for forming the second initial mask layer provided in an embodiment of this application;

[0021] Figure 9 This is a schematic diagram of the structure for forming the second mask layer provided in an embodiment of this application;

[0022] Figure 10 This is a schematic diagram of the ion implantation structure provided in an embodiment of this application;

[0023] Figure 11 This is a schematic diagram of the structure for removing the second mask layer provided in an embodiment of this application;

[0024] Figure 12 This is a schematic diagram of the structure of the first initial conductive layer after thermal annealing, provided in an embodiment of this application.

[0025] Figure 13 This is a schematic diagram of the structure for forming the first conductive layer provided in an embodiment of this application;

[0026] Figure 14 This is a schematic diagram of the structure for forming the second conductive layer provided in an embodiment of this application;

[0027] Figure 15 This is a schematic diagram of the structure for forming the third conductive layer provided in an embodiment of this application;

[0028] Figure 16 This is a schematic diagram of the structure forming the second isolation layer provided in an embodiment of this application;

[0029] Figure 17 A schematic diagram of the structure of the second conductive layer, the third conductive layer, and the second isolation layer with the boundary region removed, provided in an embodiment of this application;

[0030] Figure 18 This is a schematic diagram of the structure of the first conductive layer with the boundary region removed, provided in an embodiment of this application.

[0031] Explanation of reference numerals in the attached figures:

[0032] 100 - Semiconductor structure; 110 - Substrate;

[0033] 110a - Array area; 110b - Core area;

[0034] 110c - Boundary area; 110d - First part of the boundary area;

[0035] 110e - Second boundary zone; 110f - Third boundary zone;

[0036] 111 - Active region; 112 - Isolation structure;

[0037] 121 - First initial isolation layer; 122 - First isolation layer;

[0038] 131 - First initial conductive layer; 132 - First intermediate conductive layer;

[0039] 133 - First conductive layer; 134 - Step portion;

[0040] 135 - Doped material; 141 - Second initial mask layer;

[0041] 142 - Second mask layer; 151 - Second conductive layer;

[0042] 152 - Third conductive layer; 153 - Second isolation layer. Detailed Implementation

[0043] In related technologies, DRAM comprises multiple repeating memory cells. Each memory cell includes a capacitor and a transistor. The gate of the transistor is connected to a word line (WL), one of its drain and source is connected to a bit line, and the other of its source is connected to a capacitor. Voltage signals on the word line control the transistor to turn on or off, thereby reading data stored in the capacitor via the bit line, or writing data into the capacitor via the bit line for storage. The word line is connected to the word line driver via a contact structure (LICON) located around the memory cell, facilitating the input of voltage signals by the word line driver to the word line. Figure 1As shown, the DRAM may include a substrate 110, which includes an array region 110a, a boundary region 110c, and a core region 110b, with the boundary region 110c located between the array region 110a and the core region 110b. During DRAM fabrication, a first isolation layer 122 is first formed on the substrate. The first isolation layer 122 is located in a portion of the array region 110a and the boundary region 110c near the array region 110a, exposing the remaining areas of the substrate 110. Then, a first conductive layer 133 is formed on the first isolation layer 122 in the portion of the boundary region 110c and on the exposed substrate 110.

[0044] However, in the aforementioned DRAM manufacturing process, because the first isolation layer 122 covers a portion of the array region 110a and the boundary region 110c near the array region 110a, while the portion of the boundary region 110c near the core region 110b and the core region 110b are not covered by the first isolation layer 122, a step exists between the area covered by the first isolation layer 122 and the area not covered by the first isolation layer 122. This results in steps forming on the first conductive layer 133 of the boundary region 110c and other functional layers covering the first conductive layer 133, leading to poor surface flatness of the first conductive layer 133 and the functional layers located on it. Specifically, with... Figure 1 Taking the functional layer containing part A as an example, in the actual process, this functional layer located at the step (i.e. Figure 1 The thickness of the functional layer in part A is greater than that of the rest of the functional layer. The functional layer in part A is not easy to etch cleanly compared to the functional layer in other areas, and residues are more likely to appear, which will affect the structure and performance of the DRAM.

[0045] While over-etching can be used to remove the remaining functional layer, this may damage other structural layers in the remaining areas where the functional layer is not present, thus affecting the structure and performance of the DRAM.

[0046] This application provides a method for fabricating a semiconductor structure, a semiconductor structure, and a memory. The method for fabricating the semiconductor structure may include providing a substrate, the substrate including an array region, a core region, and a boundary region located between the array region and the core region; forming a first initial isolation layer, the first initial isolation layer being located in the array region, the boundary region, and the core region, and the first initial isolation layer covering the substrate; removing the first initial isolation layer located in the core region and a first portion of the boundary region adjacent to the core region to obtain a first isolation layer; forming a first initial conductive layer, the first initial conductive layer being located in the array region, the boundary region, and the core region, and the first initial conductive layer covering the substrate and the first isolation layer; planarizing the first initial conductive layer to obtain a first intermediate conductive layer; and removing the first intermediate conductive layer located in the array region and a second portion of the boundary region adjacent to the array region to obtain a first conductive layer; wherein the orthographic projection of the first conductive layer on the substrate partially overlaps with the orthographic projection of the first isolation layer on the substrate, and the overlapping portion of the orthographic projection of the first conductive layer on the substrate and the orthographic projection of the first isolation layer on the substrate is located within the boundary region. Because the first initial conductive layer is planarized, the surface of the first conductive layer is relatively smooth, which in turn makes the other functional layers prepared above the first conductive layer relatively smooth and the thickness of the functional layer above the first conductive layer more uniform. This avoids or reduces the occurrence of functional layer residues during the etching process, thereby avoiding or reducing the impact on the structure and performance of the semiconductor structure and memory.

[0047] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0048] The following will combine Figures 1-18 The method for preparing the semiconductor structure 100 provided in the embodiments of this application will be described.

[0049] like Figure 2 As shown, the method for fabricating the semiconductor structure 100 may include the following steps:

[0050] S100: Provides a substrate, which includes an array region, a core region, and a boundary region located between the array region and the core region.

[0051] like Figure 3As shown, a substrate 110 is first provided. The substrate 110 may include an array region 110a, a boundary region 110c, and a core region 110b arranged sequentially and adjacently, with the boundary region 110c located between the array region 110a and the core region 110b. For example, the boundary region 110c and the core region 110b may be located on at least one side of the array region 110a. Exemplarily, the boundary region 110c may be located on the outer periphery of the array region 110a, that is, the boundary region 110c may surround the array region 110a. In addition, the core region 110b may be located on the outer periphery of the boundary region 110c, that is, the core region 110b may surround the boundary region 110c.

[0052] A capacitor may subsequently be formed above the array region 110a of the substrate 110; a peripheral circuit may subsequently be formed above the core region 110b of the substrate 110, for example, the peripheral circuit may include transistors, etc. The boundary region 110c is a transition region located between the array region 110a and the core region 110b.

[0053] For example, such as Figure 3 As shown, boundary region 110c includes a first boundary region 110d, a second boundary region 110e, and a third boundary region 110f located between the first boundary region 110d and the second boundary region 110e. The first boundary region 110d is a portion of boundary region 110c that is close to the core region 110b, and the first boundary region 110d is adjacent to the core region 110b; the second boundary region 110e is a portion of boundary region 110c that is close to the array region 110a, and the second boundary region 110e is adjacent to the array region 110a; the third boundary region 110f is the region of boundary region 110c located between the first boundary region 110d and the second boundary region 110e.

[0054] Continue to refer to Figure 3 Active regions 111 can be disposed within the substrate 110. A portion of the active regions 111 can be located in the array region 110a and used to form transistors. The active regions 111 located in the array region 110a can be arranged in an array. A portion of the active regions 111 can be located in the core region 110b and used to form transistors. For example, the spacing between the active regions 111 located in the array region 110a is smaller, while the spacing between the active regions 111 located in the core region 110b is larger. An isolation structure 112 is disposed between the active regions 111 to separate them. For example, the isolation structure 112 can include an oxide, such as silicon oxide.

[0055] For example, substrate 110 may include a substrate and an oxide layer on the substrate, with both active region 111 and isolation structure 112 located within the substrate. The oxide layer on the substrate can prevent active region 111 from being exposed. The thickness of the oxide layer located in array region 110a may be greater than the thickness of the oxide layer located in core region 110b. A thick oxide layer may be formed on the substrate first, then the thick oxide layer in core region 110b may be removed, while the thick oxide layer in array region 110a may be retained. Alternatively, part or all of the thick oxide layer in boundary region 110c may be removed, or the thick oxide layer in boundary region 110c may be retained. Then, a thin oxide layer is formed on the substrate in core region 110b. This thin oxide layer can be a high-quality oxide layer to improve the performance of devices (e.g., transistors) with thin oxide layers.

[0056] For example, the thin oxide layer can have a high dielectric constant to improve its insulation properties and increase the breakdown voltage of the transistor containing the thin oxide layer. The material with the high dielectric constant can include any one or more of tantalum oxide (Ta₂O₅), aluminum oxide (Al₂O₃), hafnium oxide (HfO), silicon titanium oxide (SiTiO₃), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), and zirconium silicon oxynitride (ZrSiON).

[0057] For example, the substrate material can be monocrystalline silicon, polycrystalline silicon, amorphous silicon, germanium silicide, silicon carbide, gallium nitride, etc. The substrate can be a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. The substrate provides a supporting foundation for other structural layers on top of it.

[0058] S200: Form a first initial isolation layer, which is located in the array region, the boundary region and the core region, and covers the substrate.

[0059] like Figure 4 As shown, a first initial isolation layer 121 is formed on the substrate 110, and the first initial isolation layer 121 covers the array region 110a, the boundary region 110c, and the core region 110b of the substrate 110. For example, the material of the first initial isolation layer 121 can be silicon nitride, which has a good isolation effect.

[0060] The first initial isolation layer 121 can be formed on the substrate 110 by a deposition process. For example, the first initial isolation layer 121 can be formed on the substrate 110 by processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0061] S300: Remove the first initial isolation layer located in the core area and the first part of the boundary area adjacent to the core area to obtain the first isolation layer.

[0062] like Figure 5 As shown, a portion of the first initial isolation layer 121 is removed to form a first isolation layer 122. The first isolation layer 122 is used to isolate the substrate 110 located below the first isolation layer 122 from other structural layers located above the first isolation layer 122.

[0063] For example, the first initial isolation layer 121 in the core region 110b and the boundary region 110c can be removed, while the first initial isolation layer 121 in the array region 110a is retained, and the first isolation layer 122 is formed on the substrate 110 of the array region 110a.

[0064] For example, such as Figure 5 As shown, the first initial isolation layer 121 in the core region 110b and the first partial boundary region 110d can be removed, while the first initial isolation layer 121 in the array region 110a, the second partial boundary region 110e, and the third partial boundary region 110f is retained, so that a first isolation layer 122 is formed on the substrate 110 of the array region 110a, the second partial boundary region 110e, and the third partial boundary region 110f. For example, the orthographic projection of the array region 110a on the substrate 110 lies within the orthographic projection of the first isolation layer 122 on the substrate 110, thereby ensuring that the first isolation layer 122 completely covers the array region 110a, resulting in a better isolation effect on the substrate 110 of the array region 110a.

[0065] For example, S300 may include:

[0066] An initial mask layer is formed on the first initial isolation layer 121. This initial mask layer can be a first initial mask layer, which covers the array region 110a, the boundary region 110c, and the core region 110b of the substrate 110. The first initial mask layer can be a photoresist.

[0067] The first initial mask layer in the core region 110b and the first partial boundary region 110d is removed to form a first mask layer. The first mask layer covers the first initial isolation layer 121 in the array region 110a, the second partial boundary region 110e, and the third partial boundary region 110f, exposing the first initial isolation layer 121 in the core region 110b and the first partial boundary region 110d.

[0068] Using the first mask layer as a mask, the first initial isolation layer 121 in the areas not covered by the first mask layer, namely the core region 110b and the first partial boundary region 110d, is removed to form the first isolation layer 122. The first isolation layer 122 is located on the substrate 110 of the array region 110a, the second partial boundary region 110e, and the third partial boundary region 110f.

[0069] Remove the first mask layer to expose the first isolation layer 122.

[0070] It should be noted that in some examples, before forming the first initial isolation layer 121, a thick oxide layer located in the array region 110a and a thin oxide layer located in the core region 110b can be formed respectively, with the first initial isolation layer 121 covering the thick oxide layer and the thin oxide layer. In other examples, before forming the first initial isolation layer 121, a thick oxide layer can be formed first, covering the substrate of the array region 110a, the boundary region 110c, and the core region 110b, with the first initial isolation layer 121 covering the thick oxide layer; then, while removing the first initial isolation layer 121 in the core region 110b and the first partial boundary region 110d, the thick oxide layer in the core region 110b and the first partial boundary region 110d is also removed, thus eliminating the need to remove the thick oxide layer and the first initial isolation layer 121 in stages, which simplifies the fabrication process. Then a thin oxide layer is formed on the substrate in the core region 110b and the first partial boundary region 110d. Part of the thin oxide layer can cover the edge of the first isolation layer 122, thereby avoiding exposure of the substrate and protecting the substrate.

[0071] S400: Forming a first initial conductive layer, the first initial conductive layer is located in the array region, the boundary region and the core region, and the first initial conductive layer covers the substrate and the first isolation layer.

[0072] like Figure 6As shown, a first initial conductive layer 131 is formed on the first isolation layer 122 and the exposed substrate 110. The first initial conductive layer 131 is located in the array region 110a, the boundary region 110c, and the core region 110b. Because there is a step between the substrate 110 covered by the first isolation layer 122 and the substrate 110 not covered by the first isolation layer 122, a step is formed in the first initial conductive layer 131, resulting in a step portion 134 on the upper part of the first initial conductive layer 131. The step portion 134 causes other functional layers subsequently formed on the first initial conductive layer 131 to also have steps, affecting the flatness of other functional layers, thereby affecting the structure and performance of the semiconductor structure 100.

[0073] For example, the material of the first initial conductive layer 131 may be polycrystalline silicon.

[0074] For example, the thickness d of the first initial conductive layer 131 Figure 6 The thickness d of the first initial conductive layer 131 can be 40nm-120nm. For example, the thickness d of the first initial conductive layer 131 can be 40nm, 60nm, 80nm, 100nm, 120nm, or any thickness between 40nm and 120nm. This avoids the first initial conductive layer 131 being too thin, thus preventing the retained thickness of the first initial conductive layer 131 from being too low after subsequent planarization processing; it also avoids the first initial conductive layer 131 being too thick, thus preventing the subsequent planarization process from taking too long.

[0075] S500: The first initial conductive layer is planarized to obtain the first intermediate conductive layer.

[0076] like Figure 7 As shown, the first initial conductive layer 131 is planarized, a portion of the thickness of the first initial conductive layer 131 is removed, and a portion of the thickness of the first initial conductive layer 131 is retained, thereby obtaining the first intermediate conductive layer 132.

[0077] For example, S500 may include:

[0078] The doping process is applied to the first initial conductive layer 131 located in the array region 110a and the boundary region 110c.

[0079] The step portion 134 is doped to change the properties of the doped first initial conductive layer 131, making the doped first initial conductive layer 131 easier to remove. The removal speed of the doped first initial conductive layer 131 is faster than that of the undoped first initial conductive layer 131. Thus, the step portion 134 can be removed while removing a portion of the first initial conductive layer 131, so that the top surface of the retained first initial conductive layer 131 forms a relatively flat surface.

[0080] For example, the thickness of the first initial conductive layer 131 after doping can range from 5 nm to 10 nm. That is, the doping thickness of the step portion 134 can range from 5 nm to 10 nm. For instance, the thickness of the doped step portion 134 can be any thickness between 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, or 5 nm and 10 nm. This avoids the situation where the thickness of the doped step portion 134 is too low, making it difficult to remove the step portion 134 effectively; and it also avoids the situation where the thickness of the doped step portion 134 is too high, reducing the doping precision.

[0081] For example, the doped material 135 may include any one or more of group V elements such as arsenic atoms and phosphorus atoms, and group IV elements such as carbon atoms.

[0082] The first initial conductive layer 131 is etched or chemically mechanically polished to obtain the first intermediate conductive layer 132. The planarization process can include dry etching, wet etching, or chemically mechanical polishing. The planarization process removes a portion of the thickness of the first initial conductive layer 131, and the remaining first initial conductive layer 131 forms the first intermediate conductive layer 132. The top surface of the first intermediate conductive layer 132 can be a plane with good flatness, avoiding or reducing the impact on the flatness of other functional layers subsequently formed on the first intermediate conductive layer 132, thereby avoiding or reducing the impact on the structure and performance of the semiconductor structure 100.

[0083] For example, such as Figures 8-12 As shown, the step of doping the first initial conductive layer 131 located in the array region 110a and the boundary region 110c may include:

[0084] like Figure 8 As shown, an initial mask layer is formed, located in array region 110a, boundary region 110c, and core region 110b, covering a first initial conductive layer 131. An additional initial mask layer is formed on the first initial conductive layer 131. This initial mask layer can be a second initial mask layer 141, located in array region 110a, boundary region 110c, and core region 110b. For example, the second initial mask layer 141 can be photoresist.

[0085] like Figure 9 As shown, the second initial mask layer 141 located in the array region 110a and the boundary region 110c is removed to obtain a mask layer, which can be a second mask layer 142. That is, the second initial mask layer 141 above the step portion 134 can be removed to expose the step portion 134 so as to facilitate the doping process of the step portion 134.

[0086] It should be noted that, as Figure 9 As shown, the sidewall of the stepped portion 134 near the core region 110b can be an arc surface, meaning the height of the sidewall of the stepped portion 134 gradually increases, and the sidewall is inclined. In this case, the second mask layer 142 can cover part of the sidewall of the stepped portion 134 near the core region 110b, thereby avoiding doping treatment on this part of the sidewall of the stepped portion 134 near the core region 110b. This would result in a large thickness of the doped material 135 distributed along the sidewall, making it impossible to accurately control the thickness of the doping treatment, and even causing the doped material 135 to enter below the stepped portion 134 through the sidewall with a smaller height, thus affecting the uniformity of the doping treatment and the accuracy of thickness control.

[0087] like Figure 10 As shown, ion implantation is performed on the first initial conductive layer 131 in the array region 110a and the boundary region 110c. The doping process may include ion implantation.

[0088] For example, the dose range of ion implantation is 10. 13 Number of atoms per square centimeter - 10 15 Atoms per square centimeter. For example, the dose range for ion implantation is 10. 13 Number of atoms per square centimeter, 10 14 Number of atoms per square centimeter, 10 15 Number of atoms per square centimeter or 10 13 Number of atoms per square centimeter - 10 15 Any dose between the number of atoms per square centimeter. This avoids the ion implantation dose being too small, thus avoiding the dopant material 135 content being too low in the first initial conductive layer 131, resulting in a better improvement effect on the properties of the first initial conductive layer 131; it also avoids the ion implantation dose being too large, which is beneficial for controlling the dopant material 135 content in the first initial conductive layer 131.

[0089] For example, the ion implantation energy range can be 30keV-100keV. Specifically, the ion implantation energy can be 30keV, 50keV, 70keV, 90keV, 100keV, or any energy between 30keV and 100keV. This avoids ion implantation energy that is too low, preventing the dopant material 135 implanted into the first initial conductive layer 131 from being too low in content or too shallow in depth, thus achieving a better improvement in the properties of the first initial conductive layer 131. Conversely, it avoids ion implantation energy that is too high, preventing the dopant material 135 from being implanted too deeply, allowing for better control of the doping thickness (i.e., depth).

[0090] like Figure 11 As shown, the second mask layer 142 is removed. After the doping process, the second mask layer 142 can be removed to expose the first initial conductive layer 131 located in the core region 110b.

[0091] After doping the first initial conductive layer 131 located in the array region 110a and the boundary region 110c, and before the step of etching or chemical mechanical polishing the first initial conductive layer 131 to obtain the first intermediate conductive layer 132, the process may further include: thermal annealing the first initial conductive layer 131. For example... Figure 12 As shown, after removing the second mask layer 142, the first initial conductive layer 131 that has undergone doping can be thermally annealed. Thermal annealing can repair surface crystal damage to the first initial conductive layer 131 caused by ion implantation, activate the ion-implanted dopant material 135, and simultaneously ensure that the dopant material 135 is uniformly distributed in the first initial conductive layer 131 of the required thickness.

[0092] S600: Remove the first intermediate conductive layer located in the array region and the second boundary region adjacent to the array region to obtain the first conductive layer.

[0093] like Figure 13 As shown, the first intermediate conductive layer 132 located in array region 110a and the second partial boundary region 110e is removed, while the first intermediate conductive layer 132 located in the first partial boundary region 110d, the third partial boundary region 110f, and the core region 110b is retained to form a first conductive layer 133. The first conductive layer 133 covers the first partial boundary region 110d, the third partial boundary region 110f, and the core region 110b.

[0094] like Figure 13As shown, the orthographic projection of the first conductive layer 133 on the substrate 110 partially overlaps with the orthographic projection of the first insulating layer 122 on the substrate 110, and the overlapping portion of the orthographic projections of the first conductive layer 133 and the first insulating layer 122 on the substrate 110 is located in the third boundary region 110f. The overlapping portion of the first conductive layer 133 and the first insulating layer 122 can prevent the substrate 110 from being exposed, thus protecting the substrate 110.

[0095] After obtaining the first conductive layer 133, the process may further include:

[0096] like Figure 14 As shown, a second conductive layer 151 is formed, which is located in the array region 110a, the boundary region 110c, and the core region 110b. The second conductive layer 151 covers the first isolation layer 122 and the first conductive layer 133. That is, the second conductive layer 151 is formed on the first conductive layer 133 and the first isolation layer 122, and the second conductive layer 151 covers the array region 110a, the boundary region 110c, and the core region 110b.

[0097] After the step of forming the second conductive layer 151, the method may further include:

[0098] like Figure 15 As shown, a third conductive layer 152 is formed, which is located in the array region 110a, the boundary region 110c, and the core region 110b, and covers the second conductive layer 151. That is, the third conductive layer 152 is formed on the second conductive layer 151, and the third conductive layer 152 covers the array region 110a, the boundary region 110c, and the core region 110b.

[0099] For example, the second conductive layer 151 can be made of titanium nitride, and the third conductive layer 152 can be made of tungsten. Titanium nitride can prevent tungsten from diffusing and reacting with silicon to form a low-resistance ohmic contact, which is beneficial to improving the adhesion of tungsten. In addition, tungsten has good step coverage.

[0100] After the step of forming the third conductive layer 152, the method may further include:

[0101] like Figure 16 As shown, a second isolation layer 153 is formed, which is located in the array region 110a, the boundary region 110c, and the core region 110b. The second isolation layer 153 covers the third conductive layer 152. That is, the second isolation layer 153 is formed on the third conductive layer 152, and the second isolation layer 153 covers the array region 110a, the boundary region 110c, and the core region 110b.

[0102] For example, the material of the second isolation layer 153 may be silicon nitride.

[0103] It should be noted that any one or more of the second conductive layer 151, the third conductive layer 152, and the second isolation layer 153 can form the functional layer in the above embodiments.

[0104] The second conductive layer 151 and the third conductive layer 152 located in the array region 110a can subsequently form bit lines.

[0105] The thin oxide layer, the first conductive layer 133, the second conductive layer 151, the third conductive layer 152, and the active region 111 in the substrate 110 located in the core region 110b can subsequently form a device, such as a transistor.

[0106] After the step of forming the second isolation layer 153, it may further include:

[0107] like Figure 17 As shown, the second isolation layer 153, the third conductive layer 152 and the second conductive layer 151 located in the boundary region 110c are removed in sequence. The second conductive layer 151 located in the core region 110b is electrically isolated from the second conductive layer 151 located in the array region 110a. The third conductive layer 152 located in the core region 110b is electrically isolated from the third conductive layer 152 located in the array region 110a.

[0108] When removing the second isolation layer 153, the third conductive layer 152, and the second conductive layer 151 in the boundary region 110c, the thickness of the second isolation layer 153, the third conductive layer 152, and the second conductive layer 151 located above the first conductive layer 133 is relatively uniform due to the good flatness of the top surface of the first conductive layer 133. This can avoid or reduce the residue of the second conductive layer 151, thereby avoiding or reducing the impact of the residual second conductive layer 151 on the structure and performance of the semiconductor structure 100.

[0109] After removing the second conductive layer 151 of the boundary region 110c, part or all of the first conductive layer 133 of the boundary region 110c can also be removed. Figure 18 Alternatively, the first conductive layer 133 of the boundary region 110c can be retained. Figure 17 ).

[0110] For example, insulating material can be filled in the boundary region 110c to ensure the necessary electrical isolation between the array region 110a and the core region 110b.

[0111] This application also provides a semiconductor structure 100, which can be prepared by the preparation method of the semiconductor structure 100 in the above embodiments.

[0112] like Figure 13As shown, the semiconductor structure 100 may include a substrate 110, which includes an array region 110a, a core region 110b, and a boundary region 110c located between the array region 110a and the core region 110b. A first isolation layer 122 and a first conductive layer 133 are sequentially stacked on the substrate 110. The first isolation layer 122 covers the array region 110a, the second partial boundary region 110e, and the third partial boundary region 110f on the substrate 110, and the first conductive layer 133 covers the first isolation layer 122 and the substrate 110 in the core region 110b, the first partial boundary region 110d, and the third partial boundary region 110f. The top surface of the first conductive layer 133 can be planar, thereby ensuring good flatness of the top surface of the first conductive layer 133. For example, the first conductive layer 133 can be planarized to form a flat surface on its top surface, so as to avoid affecting the flatness of other functional layers (e.g., the second conductive layer 151, the third conductive layer 152, and the second isolation layer 153) subsequently formed on the first conductive layer 133, and to avoid or reduce the functional layers remaining in the boundary region 110c in subsequent etching processes, thereby avoiding or reducing the impact on the structure and performance of the semiconductor structure 100.

[0113] Wherein, the orthographic projection of the first conductive layer 133 on the substrate 110 and the orthographic projection of the first insulating layer 122 on the substrate 110 partially overlap, and the overlapping portion of the orthographic projection of the first conductive layer 133 on the substrate 110 and the orthographic projection of the first insulating layer 122 on the substrate 110 is located within the third boundary region 110f, thereby preventing the substrate 110 from being exposed and thus protecting the substrate 110.

[0114] It should be noted that in some examples, the first conductive layer 133 in the boundary region 110c can be retained in subsequent processes. Figure 17 Alternatively, part or all of the first conductive layer 133 in the boundary region 110c can be removed. Figure 18 The semiconductor structure 100 may be a semiconductor structure 100 formed by retaining at least a portion of the first conductive layer 133 in the boundary region 110c, or it may be a semiconductor structure 100 formed by removing the first conductive layer 133 in the boundary region 110c.

[0115] This application embodiment also provides a memory, which may include a semiconductor structure 100 prepared by the preparation method of the semiconductor structure 100 in the above embodiment.

[0116] For example, the memory may include, for instance, dynamic random access memory, static random access memory (SRAM), flash memory, electrically erasable programmable read-only memory (EEPROM), phase change random access memory (PRAM), or magnetoresistive random access memory (MRAM).

[0117] For example, the semiconductor structure 100 in the above embodiments can be applied to non-memory devices. Non-memory devices can be logic devices (e.g., microprocessors, digital signal processors, or microcontrollers) or similar devices.

[0118] This application uses a DRAM memory as an example for illustration.

[0119] The semiconductor structure 100 described in the above embodiments can be applied to a memory, which includes the semiconductor structure 100. The semiconductor structure 100 may include a substrate 110, which includes an array region 110a, a core region 110b, and a boundary region 110c located between the array region 110a and the core region 110b. A first isolation layer 122 and a first conductive layer 133 are sequentially stacked on the substrate 110. The first isolation layer 122 covers the array region 110a, the second partial boundary region 110e, and the third partial boundary region 110f on the substrate 110. The first conductive layer 133 covers the first isolation layer 122 and the substrate 110 in the core region 110b, the first partial boundary region 110d, and the third partial boundary region 110f. The top surface of the first conductive layer 133 can be planar, thereby ensuring good flatness of the top surface of the first conductive layer 133. For example, the first conductive layer 133 can be planarized to form a flat surface on its top surface, so as to avoid affecting the flatness of other functional layers (e.g., the second conductive layer 151, the third conductive layer 152, and the second isolation layer 153) subsequently formed on the first conductive layer 133, and to avoid or reduce the functional layers remaining in the boundary region 110c in subsequent etching processes, thereby avoiding or reducing the impact on the structure and performance of the memory.

[0120] Wherein, the orthographic projection of the first conductive layer 133 on the substrate 110 and the orthographic projection of the first insulating layer 122 on the substrate 110 partially overlap, and the overlapping portion of the orthographic projection of the first conductive layer 133 on the substrate 110 and the orthographic projection of the first insulating layer 122 on the substrate 110 is located within the third boundary region 110f, thereby preventing the substrate 110 from being exposed and thus protecting the substrate 110.

[0121] It should be noted that in some examples, the first conductive layer 133 in the boundary region 110c can be removed in subsequent processes to achieve electrical isolation between the first conductive layer 133 located in the core region 110b and the first conductive layer 133 located in the array region 110a. In other examples, some or all of the first conductive layer 133 in the boundary region 110c can be retained.

[0122] It should be noted that the numerical values ​​and ranges involved in the embodiments of this application are approximate values. Due to the influence of the manufacturing process, there may be a certain range of errors, which can be considered negligible by those skilled in the art.

[0123] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including an array region, a core region, and a boundary region located between the array region and the core region; A first initial isolation layer is formed, the first initial isolation layer is located in the array region, the boundary region and the core region, and the first initial isolation layer covers the substrate; Remove the first initial isolation layer located in the core region and the first portion of the boundary region adjacent to the core region to obtain the first isolation layer; A first initial conductive layer is formed, the first initial conductive layer is located in the array region, the boundary region and the core region, and the first initial conductive layer covers the substrate and the first isolation layer; The first initial conductive layer is planarized to obtain the first intermediate conductive layer; as well as Remove the first intermediate conductive layer located in the array region and the second boundary region adjacent to the array region to obtain the first conductive layer; The first conductive layer is in contact with both the substrate and the first isolation layer. The orthographic projection of the first conductive layer on the substrate overlaps with the orthographic projection of the first isolation layer on the substrate, and the overlapping portion of the orthographic projection of the first conductive layer on the substrate and the orthographic projection of the first isolation layer on the substrate is located within the boundary region.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The planarization process is performed on the first initial conductive layer to obtain the first intermediate conductive layer, comprising: The doping process is applied to the first initial conductive layer located in the array region and the boundary region; and The first initial conductive layer is etched or chemically mechanically polished to obtain the first intermediate conductive layer.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, The doping process for the first initial conductive layer located in the array region and the boundary region includes: An initial mask layer is formed, the initial mask layer being located in the array region, the boundary region, and the core region, and the initial mask layer covering the first initial conductive layer; Remove the initial mask layer located in the array region and the boundary region to obtain a mask layer; Ion implantation is performed on the first initial conductive layer in the array region and the boundary region; and Remove the mask layer.

4. The method for preparing a semiconductor structure according to claim 2 or 3, characterized in that, After doping the first initial conductive layer located in the array region and the boundary region, and before etching or chemically mechanically polishing the first initial conductive layer to obtain the first intermediate conductive layer, the method further includes: thermally annealing the first initial conductive layer.

5. The method for preparing a semiconductor structure according to any one of claims 1-3, characterized in that, The thickness of the first initial conductive layer ranges from 40 nm to 120 nm.

6. The method for preparing a semiconductor structure according to any one of claims 1-3, characterized in that, The material of the first initial conductive layer is polycrystalline silicon.

7. The method for preparing a semiconductor structure according to claim 2 or 3, characterized in that, The thickness of the first initial conductive layer after doping is greater than 5 nm but less than 10 nm.

8. The method for preparing a semiconductor structure according to claim 3, characterized in that, The dose range for ion implantation is 10. 13 Number of atoms per square centimeter - 10 15 Atoms per square centimeter, ion implantation energy range of 30keV-100keV.

9. The method for preparing a semiconductor structure according to any one of claims 2 or 3, characterized in that, The doping material for the doping treatment includes arsenic, phosphorus, or carbon atoms.

10. The method for preparing a semiconductor structure according to any one of claims 1-3, characterized in that, The boundary region includes a first partial boundary region, a second partial boundary region, and a third partial boundary region located between the first partial boundary region and the second partial boundary region, wherein the overlapping portion of the orthographic projection of the first conductive layer on the substrate and the orthographic projection of the first insulating layer on the substrate is located within the third partial boundary region.

11. The method for preparing a semiconductor structure according to any one of claims 1-3, characterized in that, After obtaining the first conductive layer, the method further includes: A second conductive layer is formed, which is located in the array region, the boundary region and the core region, and covers the first isolation layer and the first conductive layer.

12. The method for preparing a semiconductor structure according to claim 11, characterized in that, The material of the second conductive layer is titanium nitride.

13. The method for preparing a semiconductor structure according to claim 11, characterized in that, After forming the second conductive layer, the method further includes: A third conductive layer is formed, which is located in the array region, the boundary region and the core region, and covers the second conductive layer.

14. The method for preparing a semiconductor structure according to claim 13, characterized in that, The material of the third conductive layer is tungsten.

15. The method for preparing a semiconductor structure according to claim 13, characterized in that, After forming the third conductive layer, the method further includes: A second isolation layer is formed, which is located in the array region, the boundary region and the core region, and covers the third conductive layer.

16. The method for preparing a semiconductor structure according to claim 15, characterized in that, The material of the first isolation layer and / or the second isolation layer is silicon nitride.

17. The method for preparing a semiconductor structure according to claim 15, characterized in that, After the second isolation layer is formed, it also includes: The second isolation layer, the third conductive layer, and the second conductive layer located in the boundary region are removed sequentially. The second conductive layer located in the core region is electrically isolated from the second conductive layer located in the array region, and the third conductive layer located in the core region is electrically isolated from the third conductive layer located in the array region.

18. A semiconductor structure, characterized in that, It is prepared by the semiconductor structure preparation method according to any one of claims 1-17.

19. A memory, characterized in that, The semiconductor structure prepared by the method of semiconductor structure preparation according to claim 17 includes semiconductor structures.

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