A high voltage field effect transistor and a method for manufacturing the same

Abstract

The present application discloses a high voltage field effect transistor (HFET) and a method for manufacturing the same, the high voltage field effect transistor comprising a first semiconductor material, a second semiconductor material and a heterojunction. The heterojunction is arranged between the first semiconductor material and the second semiconductor material. The HFET also includes a plurality of composite passivation layers, wherein the first composite passivation layer comprises a first insulating layer and a first passivation layer, and the second composite passivation layer comprises a second insulating layer and a second passivation layer, and the third composite passivation layer comprises a third insulating layer and a third passivation layer, wherein the insulating layer in the plurality of composite passivation layers is made of a dielectric suitable for forming a gate insulator. The gate dielectric is arranged between the first passivation layer and the second semiconductor material. The gate electrode is arranged between the gate dielectric and the first passivation layer. The first gate field plate is arranged between the first passivation layer and the second passivation layer, wherein the first gate field plate is coupled to the gate electrode.

Description

[0001] This application is a divisional application of Chinese invention patent application No. 2017102324102, filed on April 11, 2017, with the invention name “Protective Insulator for HFET Devices”. Technical Field

[0002] The present disclosure relates generally to high voltage field effect transistors (HFETs), and particularly, but not exclusively, to protective insulators in HFET devices. Background Art

[0003] High breakdown voltage and high electron mobility have made GaN an ideal choice for high power transistor applications. In addition, GaN's large bandgap means that GaN transistors can maintain their performance at much higher temperatures than other traditional semiconductor options. Applications include, but are not limited to, microwave RF amplifiers, high voltage switching devices, and power supplies. One mass market application is the microwave source in microwave ovens (replacing magnetrons).

[0004] Despite their potential for ubiquitous use in consumer electronics, GaN-based devices are subject to several limitations due to the high-voltage environments in which they are used. The device layers in GaN transistors can accumulate charge during use, causing device performance variations due to electric field redistribution and thermal stress. In the worst case, HFET devices can fail catastrophically due to dielectric breakdown or cracking of the device layers. Summary of the invention

[0005] In one aspect, the present invention provides a high-voltage field effect transistor, the high-voltage field effect transistor comprising: a first semiconductor material, a second semiconductor material and a heterojunction, wherein the heterojunction is arranged between the first semiconductor material and the second semiconductor material; a plurality of composite passivation layers, the plurality of composite passivation layers comprising: a first composite passivation layer, the first composite passivation layer having a first insulating layer and a first passivation layer, wherein the first passivation layer is arranged between the second semiconductor material and the first insulating layer; a second composite passivation layer, the second composite passivation layer having a second insulating layer and a second passivation layer, wherein the second passivation layer is arranged between the first insulating layer and the second insulating layer; and a third composite passivation layer, the third composite passivation layer having a third insulating layer. A composite passivation layer and a third passivation layer, wherein the third passivation layer is arranged between the second insulating layer and the third insulating layer, wherein the insulating layer in the plurality of composite passivation layers is made of a dielectric suitable for forming a gate insulator; a first gate field plate, the first gate field plate is arranged between the first passivation layer and the second passivation layer, wherein the first gate field plate is coupled to the gate electrode; a second gate field plate, the second gate field plate is coupled to the first gate field plate, wherein the second gate field plate extends from the second passivation layer and passes through the second insulating layer; and a gate dielectric, the gate dielectric is arranged between the first passivation layer and the second semiconductor material; wherein the gate electrode is arranged between the gate dielectric and the first passivation layer.

[0006] According to some embodiments, the high voltage field effect transistor further includes a fourth passivation layer, wherein the third insulating layer is arranged between the fourth passivation layer and the third passivation layer, and wherein the second gate field plate extends from the second passivation layer, through the second insulating layer, through the third passivation layer, and into the fourth passivation layer.

[0007] According to some embodiments, the second gate field plate comprises metal and is continuous.

[0008] According to some embodiments, the high voltage field effect transistor further includes a source field plate coupled to the source electrode, and wherein the third passivation layer is disposed between the source field plate and the second insulating layer.

[0009] According to some embodiments, the first insulating layer and the second insulating layer have a wider band gap than the first passivation layer and the second passivation layer.

[0010] According to some embodiments, the first insulating layer and the second insulating layer are longer than the source field plate but do not occupy the entire corresponding composite passivation layer.

[0011] According to some embodiments, the high voltage field effect transistor further includes a third gate field plate coupled to the second gate field plate and disposed between the third passivation layer and the fourth passivation layer.

[0012] According to some embodiments, a lateral boundary of the first insulating layer is substantially coextensive with a lateral boundary of the first gate field plate, a lateral boundary of the second insulating layer is substantially coextensive with a lateral boundary of the second gate field plate, and a lateral boundary of the third insulating layer is substantially coextensive with a lateral boundary of the source field plate.

[0013] According to some embodiments, the gate dielectric and the first insulating layer in the plurality of composite passivation layers are made of the same material composition.

[0014] According to some embodiments, the first passivation layer and the second passivation layer in the plurality of composite passivation layers include SiN, and the gate dielectric and the first insulating layer include metal oxide.

[0015] In another aspect, the present invention provides a method comprising manufacturing the above-mentioned high voltage field effect transistor.

[0016] According to some embodiments, the first insulating layer in the method has a larger band gap than the first passivation layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

[0018] Figure 1 is a cross-sectional view of an exemplary HFET device having a composite passivation layer according to the teachings of the present disclosure.

[0019] Figure 2 is a cross-sectional view of an exemplary HFET device having a composite passivation layer according to the teachings of the present disclosure.

[0020] Figure 3 is a cross-sectional view of an exemplary HFET device having a composite passivation layer according to the teachings of the present disclosure.

[0021] Figure 4 is a cross-sectional view of an exemplary HFET device having a composite passivation layer according to the teachings of the present disclosure.

[0022] Figure 5 is a flow chart illustrating a method of fabricating a HFET according to the teachings of the present disclosure.

[0023] Figure 6 is a flow chart illustrating a method of fabricating a HFET according to the teachings of the present disclosure.

[0024] Figure 7 is a cross-sectional view of an exemplary HFET device having a composite passivation layer according to the teachings of the present disclosure.

[0025] Figure 8 is a cross-sectional view of an exemplary HFET device having a composite passivation layer according to the teachings of the present disclosure.

[0026] Fig. 9 is a cross-sectional view of an exemplary HFET device having a composite passivation layer according to the teachings of the present disclosure.

[0027] Throughout the several views in the accompanying drawings, corresponding reference numerals represent corresponding parts. The skilled person will recognize that the elements in the figures are illustrated for simplicity and clarity, and that these elements are not necessarily drawn to scale. For example, the size of some elements in the figures may be enlarged relative to other elements to help improve the understanding of the various embodiments of the present invention. In addition, common but well-known elements that are useful or necessary in commercially feasible embodiments are generally not depicted to make the observation of these various embodiments of the present invention less obstructed. DETAILED DESCRIPTION

[0028] Embodiments of apparatus and methods for protecting insulators for high voltage field effect transistors (HFETs) are described herein. In the following description, many specific details are set forth to provide a thorough understanding of the embodiments. However, those skilled in the relevant art will appreciate that the techniques described herein may be practiced without one or more of these specific details, or by other methods, components, materials, etc. In other cases, known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

[0029] References throughout the specification to "one embodiment" or "an implementation" mean that the specific features, structures, or characteristics described in conjunction with the embodiment are included in at least one embodiment of the present invention. Therefore, the phrases "in one embodiment" or "in one implementation" appearing in various places throughout the specification do not necessarily refer to the same embodiment. In addition, the specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0030] Throughout the specification, many technical terms are used. These terms should be understood according to their ordinary meaning in the technical field to which they belong, unless explicitly defined herein or the context in which they are used clearly indicates another meaning. It should be noted that component names and symbols can be used interchangeably throughout the document (e.g., Si and silicon); however, the two have the same meaning.

[0031] Figure 1 1 is a cross-sectional view of an exemplary HFET 100 having a composite passivation layer 199. The HFET 100 includes a first semiconductor material 105, a second semiconductor material 110, and a heterojunction 115. A gate dielectric 155 is disposed on the second semiconductor material 110. The heterojunction 115 is disposed between the first semiconductor material 105 and the second semiconductor material 110. When the device is turned on, a two-dimensional electron gas 120 appears at the heterojunction 115 due to the material properties of the semiconductor materials 105, 110.

[0032] A plurality of composite passivation layers 199 are disposed over the second semiconductor material 110. A first composite passivation layer is disposed in the plurality of composite passivation layers 199, and the first composite passivation layer includes a first insulating layer 170 and a first passivation layer 165. The plurality of composite passivation layers 199 also includes a second composite passivation layer having a second insulating layer 192 and a second passivation layer 175, wherein the second passivation layer 175 is disposed between the first insulating layer 170 and the second insulating layer 192. In one embodiment, the gate dielectric 155 and the first insulating layer 170 include the same material composition. In another or the same embodiment, the first passivation layer 165 and the second passivation layer 175 include SiN, and the gate dielectric 155 and the first insulating layer 170 include a metal oxide. In the depicted embodiment, the gate dielectric 155 is disposed between the first passivation layer 165 and the second semiconductor material 110, and the gate electrode 135 is disposed between the gate dielectric 155 and the first passivation layer 165. Selective biasing of the gate electrode 135 adjusts conductivity between the source electrode 125 and the drain electrode 130. The first gate field plate 140 is disposed between the first passivation layer 165 and the second passivation layer 175. In one embodiment, the first gate field plate 140 is coupled to the gate electrode 135. Both the source electrode 125 and the drain electrode 130 are coupled to the second semiconductor material 110, and the source field plate 145 is coupled to the source electrode 125. In one embodiment, the drain electrode 130 extends from the second semiconductor material 110 through at least one of the plurality of composite passivation layers 199.

[0033] In the illustrated embodiment, the gate electrode 135, the first gate field plate 140, and the source field plate 145 have a generally rectangular cross-section. The gate electrode 135 includes a first edge 150. The first edge 150 is arranged at a lateral distance d0 from the source electrode 125 and a vertical distance d5 above the second semiconductor material 110. The first edge 150 is vertically spaced apart from the second semiconductor material 110 by the gate dielectric 155 and the first passivation layer 165.

[0034] In one embodiment, the HFET includes a third passivation layer 195. The second insulating layer 192 is disposed between the second passivation layer 175 and the third passivation layer 195. In another embodiment or the same embodiment, the source field plate 145 can be disposed between the second insulating layer 192 and the third passivation layer 195. In addition, the first gate field plate 140 can be disposed between the first insulating layer 170 and the second passivation layer 175.

[0035] The first gate field plate 140 includes a second edge 160. The second edge 160 is arranged to be spaced apart by a lateral distance d0+d1 towards the drain electrode 130 and a vertical distance d5+d6 above the second semiconductor material 110. The second edge 160 is vertically spaced apart from the second semiconductor material 110 by the gate dielectric 155, the first passivation layer 165, and the first insulating layer 170. The source field plate 145 includes a third edge 174. The third edge 174 is arranged to be spaced apart by a lateral distance d0+d1+d3 from a side of the source electrode 125 facing the drain electrode 130 and a vertical distance d5+d6+d7 above the second semiconductor material 110. The third edge 174 is vertically spaced apart from the second semiconductor material 110 by the gate dielectric 155, the first passivation layer 165, the first insulating layer 170, the second passivation layer 175, and the second insulating layer 192. It should be noted that under certain bias conditions, the electric field between each of the gate electrode 135 , the first gate field plate 140 , the source field plate 145 , and the heterojunction 115 is highest at their respective edges 150 , 160 , 174 .

[0036] The gate electrode 135 can be electrically connected to the first gate field plate 140 in a variety of ways. In the illustrated embodiment, the connection between the gate electrode 135 and the first gate field plate 140 is outside the cross-sectional view. However, the gate electrode 135 and the first gate field plate 140 can be formed by an integral member having a generally L-shaped cross-section.

[0037] The source electrode 125 can be electrically connected to the source field plate 145 in a variety of ways. In the illustrated embodiment, the source electrode 125 is electrically connected to the source field plate 145 through a source via member 180. In other embodiments, the source electrode 125 can be electrically connected to the source field plate 145 outside the illustrated cross section.

[0038] In the depicted embodiment, the drain electrode 130 is electrically connected to a pair of drain via members 185, 190. The drain via members 185, 190 extend through the second passivation layer 175 to the same vertical level as the source field plate 145, thus serving as an extension of the drain electrode 130. Being located at the same vertical level as the source field plate 145, the via member 190 is the closest extension of the drain electrode 130 to the source field plate 145. One side of the source field plate 145 including the third edge 174 is arranged to be away from the drain via member 190 at the same vertical level by a lateral distance d4. In some embodiments, the lateral distance d4 is no greater than the distance required to maintain the lateral dielectric breakdown voltage of a particular device. In the illustrated embodiment, the source field plate 145 and the drain via member 190 are covered by the third passivation layer 195.

[0039] In the illustrated embodiment, both the source electrode 125 and the drain electrode 130 are disposed directly on the upper surface of the second semiconductor material 110 to achieve electrical contact with the second semiconductor material 110. However, in some embodiments, the source electrode 125 and / or the drain electrode 130 penetrate into the second semiconductor material 110. In some embodiments, the penetration is deep enough so that the source electrode 125 and / or the drain electrode 130 contacts or even passes through the heterojunction 115. In another or the same embodiment, one or more interstitial glue metals or other conductive materials are disposed between the source electrode 125 and / or the drain electrode 130 and one or both of the semiconductor materials 105, 110.

[0040] In the depicted embodiment, the gate electrode 135 is electrically insulated from the second semiconductor material 110 by a single electrically insulating layer (gate dielectric 155) having a uniform thickness d5. However, in other non-depicted embodiments, multiple layers may be used to insulate the gate electrode 135 from the second semiconductor material 110. In another embodiment, a single layer or multiple layers having non-uniform thicknesses may be used to insulate the gate electrode 135 from the second semiconductor material 110.

[0041] It is noteworthy that the various features of the lateral channel HFET 100 can be implemented by a variety of different materials. For example, the first semiconductor material 105 can include GaN, InN, AlN, AlGaN, InGaN, AlInGaN. In some embodiments, the first semiconductor material 105 can also include a compound semiconductor containing arsenic, such as, for example, GaAs, InAs, AlAs, InGaAs, AlGaAs, InAlGaAs. The second semiconductor material 110 can be, for example, AlGaN, GaN, InN, AlN, InGaN, AlInGaN. The second semiconductor material 110 can also include a compound semiconductor containing arsenic, such as one or more of GaAs, InAs, AlAs, InGaAs, AlGaAs, InAlGaAs. The composition of the first and second semiconductor materials 105, 110 - which can also be referred to as "active layers" - is designed so that a two-dimensional electron gas 120 is formed at the heterojunction 115. For example, the composition of the first and second semiconductor materials 105, 110 can be designed so that 10 11 to 10 14 cm -2 The carrier surface density (more specifically, 5x10 12 to 5x10 13 cm -2 or 8x10 12 to 1.2x10 13 cm -2 The first semiconductor material 105 and 110 may be formed on a substrate. In one embodiment, the substrate may include gallium nitride, gallium arsenide, silicon carbide, sapphire, silicon, etc. The first semiconductor material 105 may be directly in contact with such a substrate, or one or more intermediate layers may be present.

[0042] The source electrode 125, the drain electrode 130, and the gate electrode 135 may be made of various electrical conductors, including, for example, metals such as Al, Ni, Ti, TiW, TiN, TiAu, TiAlMoAu, TiAlNiAu, TiAlPtAu, etc. The insulating layers 170, 192, and the gate dielectric 155 may be made of various dielectrics suitable for forming a gate insulator, such as aluminum oxide (Al2O3), zirconium dioxide (ZrO2), aluminum nitride (AlN), hafnium oxide (HfO2), silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum silicon nitride (AlSiN), or other suitable gate dielectric materials.

[0043] The passivation layers 165 , 175 , 195 may be made of various dielectrics including silicon nitride, silicon oxide, silicon oxynitride, etc. The composite passivation layer may weaken or prevent surface charge states in the underlying second semiconductor material 110 or layer 155 , 165 , 175 .

[0044] In some embodiments, the passivation layer 165, 175, 195 has a composition such that after an extended period of operation at steady-state operating parameters, the number of charge defects per unit area in the passivation layer 165, 175, 195 is less than the surface density of carriers at the heterojunction. In other words, the sum of the products of each three-dimensional defect density in the passivation layer 165, 175, 195 and the corresponding thickness of the layer is less than the (two-dimensional) surface density of carriers at the heterojunction 115. For example, the number of charge defects per unit area in the passivation layer 165, 175, 195 may be less than 20% of the surface density of carriers at the heterojunction 115, or less than 10% thereof.

[0045] The source electrode 125 is arranged to be a lateral distance d2 from the drain electrode 130. In some embodiments, the lateral distance d2 is between 5 microns and 50 microns (more specifically between 9 microns and 30 microns). In some embodiments, the lateral distance d1 is between 1 micron and 5 microns (more specifically between 1.5 microns and 3.5 microns). In some embodiments, the thickness of the second passivation material 175 is between 0.2 microns and 1 micron (more specifically between 0.35 microns and 0.75 microns). In some embodiments, the lateral distance d4 is between 1 micron and 8 microns (more specifically between 2 microns and 6 microns). In some embodiments, the thickness of the third passivation layer 195 is between 0.4 microns and 3 microns (more specifically between 0.5 microns and 2 microns). In some embodiments, the lateral distance d3 is between 1 micron and 10 microns (more specifically between 2.5 microns and 7.5 microns).

[0046] In operation, the insulating layers (e.g., the first insulating layer 170 and the second insulating layer 192) and the gate dielectric 155 are arranged to prevent the passivation layers (e.g., passivation layers 165, 175, and 195) in the plurality of composite passivation layers 199 from charging. Field distribution and charge shielding metallization can be used in GaN-based electronic devices (such as high voltage and / or high frequency transistors and diodes) to obtain high performance metrics. A promising passivation material for GaN electronic devices is silicon nitride (SiN). Therefore, the above-mentioned metallization is usually formed on top of the SiN passivation layer. However, among dielectrics, SiN has a relatively narrow band gap, which may result in charge injection from adjacent materials into silicon nitride under electric field stress. As a result of charging, both the material properties of the passivation material (SiN) and the metallization pattern may change over time. This may cause performance fluctuations and, in some cases, irreversible failure of the device. Therefore, by including a gate dielectric (e.g., gate dielectric 155) and an insulating layer (e.g., insulating layers 170 and 192) within the passivation layer of a GaN-based device, charging in the passivation layer can be reduced because, in some embodiments, the insulating layer has a wider bandgap than the passivation layer. The reduction in charging in the passivation layer can result in a lower likelihood of device failure / performance fluctuations. Additionally, since the insulating layer can be made of the same material as the gate dielectric, additional process steps / materials can be avoided.

[0047] Figure 2 is a cross-sectional view of an exemplary HFET 200 having a composite passivation layer 299. The HFET 200 is similar in many respects to Figure 1 240 . However, one significant difference is that in HFET 200, the area of ​​insulating layers 270, 292 does not occupy the entire composite passivation layer. In other words, the lateral boundaries of the first insulating layer 270 are substantially coextensive with the lateral boundaries of the source field plate 245, and the lateral boundaries of the second insulating layer 292 are also substantially coextensive with the lateral boundaries of the source field plate 245. In one embodiment, the lateral boundaries of the first insulating layer 270 can extend past the first gate field plate 240 and end before the via member 285. In another or the same embodiment, the length of the second insulating layer 292 can extend past the source field plate 274 and end before the via member 290.

[0048] Figure 3 is a cross-sectional view of an exemplary HFET 300 having a composite passivation layer 399. The HFET 300 is similar in many respects to Figure 1 to Figure 2394. The HFET 300 is similar to the HFET 100 and 200 of FIG. 300. However, the HFET 300 includes a third composite passivation layer including a third passivation layer 387 and a third insulating layer 394. The HFET 300 also includes a fourth passivation layer 396. The third insulating layer 394 is disposed between the third passivation layer 387 and the fourth passivation layer 396. The second gate field plate 342 is disposed between the second insulating layer 392 and the third passivation layer 387 and is coupled to the first gate field plate 340. As illustrated, the source field plate 345 is disposed between the third insulating layer 394 and the fourth passivation layer 396.

[0049] The HFET 300 also includes a first gate field plate 340, a source field plate 345, and a second gate field plate 342. The second gate field plate 342 is electrically connected to the gate electrode 335. In some embodiments, the source field plate 345 serves as a so-called "shieldwrap". As discussed above, some GaN devices are affected by parasitic DC to RF dispersion that is believed to occur (at least in part) due to the exchange of surface charge with the environment during high-voltage operation. In particular, the surface states are charged and discharged with relatively slow response times. Subsequently, the performance of the GaN device under high-frequency operation is affected. The metal shield can weaken or eliminate these effects by improving shielding and preventing the movement of surface charge. In some embodiments, the source field plate 345 can reduce the peak value of the electric field in the HFET 300 (e.g., the electric field between the heterojunction 315 and the third edge 344 of the second gate field plate 342). In some embodiments, the source field plate 345 is also used to deplete carriers of the heterojunction 315, as further discussed below. In some embodiments, source field plate 345 plays multiple roles, namely as a shield, a field plate, and / or for depleting heterojunction 315. The specific use of source field plate 345 in a device will depend on any of a number of different geometric parameters, material parameters, and operating parameters. Because of the possibility of source field plate 345 performing one or more roles, it is simply referred to herein as a "source field plate."

[0050] In the illustrated embodiment, the source field plate 345 has a substantially rectangular cross-section. The source field plate 345 includes a fourth edge 374. The fourth edge 374 is arranged to be spaced apart from the side of the source electrode 325 facing the drain electrode 330 by a lateral distance d0+d1+d3+d11 and a vertical distance d5+d6+d7+d8 above the second semiconductor material 110. In some embodiments, the lateral distance d0+d1+d3+d11 is greater than or equal to twice the vertical distance d5+d6+d7+d8. For example, the lateral distance d0+d1+d3+d11 can be greater than or equal to three times d5+d6+d7+d8. The fourth edge 374 is vertically spaced apart from the second semiconductor material 110 by the gate dielectric 355, the first passivation layer 365, the first insulating layer 370, the second passivation layer 375, the second insulating layer 392, the third passivation layer 387, and the third insulating layer 394. As discussed further below, under certain bias conditions, the electric field between the source field plate 345 and the heterojunction 315 is highest at the fourth edge 374.

[0051] The source field plate 345 can be electrically connected to the source electrode 325 in a variety of ways. In the illustrated embodiment, the source electrode 325 is electrically connected to the source field plate 345 through a source via member 380. In other embodiments, the source electrode 325 can be electrically connected to the source field plate 345 outside the illustrated cross section.

[0052] As shown, the drain electrode 330 is electrically connected to another drain via via members 385, 390. The drain via member 388 extends through the third passivation layer 387 to the same vertical level as the second gate field plate 342, thus serving as an extension of the drain electrode 330. Being located at the same vertical level as the source field plate 345, the via member 388 is the closest extension of the drain electrode 330 to the source field plate 345. The fourth composite passivation material has a thickness d10.

[0053] In some embodiments, d1+d3+d4 is between 5 microns and 35 microns (more specifically, between 8 microns and 26 microns). In some embodiments, the lateral distance d9 is between 1 micron and 10 microns (more specifically, between 2 microns and 6 microns). In some embodiments, the layers 365, 375, 387, 396 have a composition and quality such that after an extended period of operation at steady-state operating parameters, the number of charge defects per unit area in the layers 365, 375, 387, 396 is less than the surface density of carriers at the heterojunction. In other words, the sum of the products of each three-dimensional defect density in the passivation layers 365, 375, 387, 396 and the corresponding thickness of the layer is less than the (two-dimensional) surface density of carriers at the heterojunction 115. For example, the number of charge defects per unit area in the insulating material layers 365, 375, 387, 396 is less than 20% (more specifically, less than 10%) of the surface density of carriers at the heterojunction 315.

[0054] Figure 4 499. HFET 400 is similar to HFET 300; however, the lateral boundaries of the first insulating layer 470 are substantially coextensive with the lateral boundaries of the first gate field plate 440, the lateral boundaries of the second insulating layer 492 are substantially coextensive with the lateral boundaries of the second gate field plate 442, and the lateral boundaries of the third insulating layer 494 are substantially coextensive with the lateral boundaries of the source field plate 445. In other words, HFET 400 is similar to HFET 300, except that the regions of the insulating layers 470, 492, 494 in HFET 400 do not occupy the entire passivation layer. In one embodiment, the length of the first insulating layer 470 can extend past the first gate field plate 440 and end before the via member 485. In one embodiment, the length of the second insulating layer 492 can extend past the second gate field plate 442 and end before the via member 490. In one embodiment, the length of the third insulating layer 494 can extend past the source field plate 445 and end before the drain 488.

[0055] Figure 5 is a flow chart illustrating an exemplary method 500 of HFET fabrication. The order of process blocks 502 to 510 in method 500 should not be considered limiting. As one skilled in the relevant art will recognize, process blocks 502 to 510 can occur in any order, and even in parallel. Additionally, process blocks may be added to / removed from method 500, as process blocks 502 to 510 depict a highly simplified form of method 500 to avoid obscuring certain aspects of the present disclosure.

[0056] Process block 502 depicts depositing a semiconductor layer (eg, first semiconductor material 105 and second semiconductor material 110) on a substrate. In one embodiment, the semiconductor layer and substrate may be formed by Figures 1 to 4 In one embodiment, a heterojunction can be formed between a first semiconductor material and a second semiconductor material (e.g., first semiconductor material 105 and second semiconductor material 110). In another embodiment or the same embodiment, both the source electrode and the drain electrode are coupled to the second semiconductor material. In addition, a gate dielectric can be deposited proximate to the second semiconductor material such that the second semiconductor material is disposed between the gate dielectric and the first semiconductor material.

[0057] Process block 504 illustrates depositing one or more composite passivation layers on the semiconductor layer. In one embodiment, this may include depositing a plurality of composite passivation layers, wherein a first composite passivation layer of the plurality of composite passivation layers includes a first insulating layer and a first passivation layer. In the foregoing embodiment, the first passivation layer is disposed between the gate dielectric and the first insulating layer, and the gate may be formed between the gate dielectric and the plurality of composite passivation layers. In another embodiment or the same embodiment, a second composite passivation layer of the plurality of composite passivation layers may be deposited. The second composite passivation layer may include a second insulating layer and a second passivation layer, wherein the first insulating layer is disposed between the first passivation layer and the second passivation layer. In one embodiment, the first insulating layer has a larger band gap than the first passivation layer. In another embodiment or the same embodiment, the first passivation layer includes SiN, and the gate dielectric and the first insulating layer include a metal oxide.

[0058] In one embodiment, depositing a plurality of composite passivation layers includes depositing a first insulating layer and a second insulating layer, so that a lateral boundary between the first insulating layer and the second insulating layer is less than a lateral distance between the source electrode and the drain electrode. In another embodiment or the same embodiment, a third composite passivation layer is deposited, and the third composite passivation layer includes a third insulating layer and a third passivation layer. In this embodiment, the second insulating layer is arranged between the second passivation layer and the third passivation layer.

[0059] Process block 506 shows the formation of an ohmic contact by recess etching, metal deposition, metal patterning, and rapid thermal annealing. The ohmic contact is connected to a substrate such as Figures 1 to 4 The top surface of the semiconductor layer is contacted.

[0060] Process block 508 depicts patterning one or more field plates on one or more composite passivation layers. In one embodiment, a first gate field plate is formed between the first passivation layer and the second passivation layer. In another embodiment or the same embodiment, the first gate field plate is coupled to the gate electrode. In addition, the source field plate can be deposited on the second insulating layer. In one embodiment, the first gate field plate is arranged between the first insulating layer and the second passivation layer. In another embodiment, a second gate field plate (coupled to the first gate field plate) is formed and arranged between the second insulating layer and the third passivation layer. The source field plate can be coupled to the source electrode and formed on the third insulating layer.

[0061] Process block 510 shows depositing an encapsulation layer on the topmost composite passivation layer. In one embodiment, depositing the encapsulation layer includes a fourth passivation layer, wherein the fourth passivation layer is disposed on the source field plate and the third insulating layer.

[0062] Figure 6 6 is a flow chart illustrating an exemplary method 600 of HFET fabrication. The order of process blocks 602 to 622 in method 600 should not be considered limiting. As one skilled in the relevant art will recognize, process blocks 602 to 622 can occur in any order, and even in parallel. Additionally, process blocks may be added to / removed from method 600, as process blocks 602 to 622 depict a highly simplified form of method 600 to avoid obscuring certain aspects of the present disclosure.

[0063] In block 602, a semiconductor layer is deposited on a substrate. In one embodiment, the semiconductor layer and the substrate may be formed by Figures 1 to 4 Any of the materials listed in the discussion.

[0064] Process block 604 depicts depositing one or more composite passivation layers on the semiconductor layer. It should be appreciated that the insulating material and the passivation material in the composite passivation layer may include the same or different material compositions.

[0065] Block 606 shows the occupied area of ​​the ohmic contact formed via plasma etching. The occupied area can be formed by using a composite passivation layer as an etch stop. As mentioned before, the composite passivation layer includes a gate dielectric layer and a passivation layer. In one embodiment, the gate dielectric layer can be made of aluminum oxide, and the passivation layer can be made of silicon nitride (SiN). The plasma etching rate of the passivation material is greater than the etching rate of the gate dielectric material. In one embodiment, the plasma etching rate of the passivation material is much greater than the etching rate of the gate dielectric. In one embodiment, the etching rate of the passivation layer can be up to 100 times greater than the etching rate of the gate dielectric and the isolation layer. This allows the thickness of the device layer under each field plate (i.e., gate field plate, source field plate, drain field plate) to be precisely controlled. In one embodiment, the gate dielectric and the insulating layer can be used as an etching stop layer.

[0066] In process block 608, ohmic contacts are formed by recess etching, metal deposition, metal patterning, and high temperature annealing.

[0067] Optional process block 610 shows depositing an additional composite passivation layer.

[0068] In block 614, a gate contact is formed by metal deposition and metal patterning. An optional field plate may also be formed in this step.

[0069] In the exemplary method 600, process blocks 616 to 620 are optional. Block 616 depicts depositing an additional composite passivation layer. In block 618, an additional footprint for a field plate may be formed via plasma etching with an etch stop. Block 620 shows depositing and patterning an additional metal field plate.

[0070] In block 622 , an encapsulation layer is deposited over the topmost composite passivation layer.

[0071] Figure 7 is a cross-sectional view of an exemplary HFET 700 having a composite passivation layer 799. HFET 700 is similar in many respects to Figure 1100. However, one significant difference is that in HFET 700, a second gate field plate 742 is included that is coupled to the first gate field plate 740 and disposed between the second insulating layer 792 and the third passivation layer 795. It is recognized that in another embodiment of HFET 700, the region of insulating layers 770 and 792 does not occupy the entire composite passivation layer. In this embodiment, the lateral boundaries of the first insulating layer 770 can be substantially coextensive with the lateral boundaries of the first gate field plate 740, and the lateral boundaries of the second insulating layer 792 can be substantially coextensive with the second gate field plate 742. In other words, the insulating layers 770 and 792 do not extend as long as the entire distance between the source electrode 725 and the drain electrode 730.

[0072] Figure 8 899. HFET 800 is similar in many respects to the HFETs shown in the previous figures. However, HFET 800 includes a third composite passivation layer including a third passivation layer 887 and a third insulating layer 894. HFET 800 also includes a fourth passivation layer 896. The third insulating layer 394 is disposed between the third passivation layer 887 and the fourth passivation layer 896. The second gate field plate 842 is disposed between the second passivation layer 875 and the third passivation layer 887 and is coupled to the first gate field plate 840. As illustrated, the third gate field plate 846 is disposed between the third insulating layer 894 and the fourth passivation layer 896. The third gate field plate 846 is coupled to the second gate field plate 842. It is recognized that in another embodiment of HFET 800, the area of ​​the insulating layers 870, 892, and 894 does not occupy the entire composite passivation layer 899. In this embodiment, lateral boundaries of the third insulating layer 894 are substantially coextensive with the third gate field plate 846. In other words, the insulating layers 870, 892, and 894 do not extend the entire distance between the source electrode 825 and the drain electrode 830.

[0073] Fig. 9 is a cross-sectional view of an exemplary HFET 900 having a composite passivation layer 999. HFET 900 is similar in many respects to Figures 1 to 4 , Figure 7 and Figure 8900. However, HFET 900 includes another embodiment of a field plate 942 for a second gate connection. The second gate field plate 942 is coupled to the first gate field plate 940. It should be appreciated that in another embodiment of HFET 900, the region of insulating layers 970, 992, 994 does not occupy the entire composite passivation layer. In other words, as in other HFET embodiments, insulating layers 970, 992, 994 do not extend as long as the entire distance between source electrode 825 and drain electrode 830.

[0074] The HFET 900 includes a first semiconductor material 905, a second semiconductor material 910, and a heterojunction 915 (arranged therebetween). The HFET 900 also has a plurality of composite passivation layers. The first composite passivation layer includes a first insulating layer 970 and a first passivation layer 965, and the first passivation layer 965 is arranged between the second semiconductor material 910 and the first insulating layer 970. The second composite passivation layer includes a second insulating layer 992 and a second passivation layer 975, and the second passivation layer 975 is arranged between the first insulating layer 970 and the second insulating layer 992. The third composite passivation layer includes a third insulating layer 994 and a third passivation layer 987. The third passivation layer 987 is arranged between the second insulating layer 992 and the third insulating layer 994. In the depicted embodiment, the first gate field plate 940 is arranged between the first passivation layer 965 and the second passivation layer 975. In addition, the gate dielectric 955 is arranged between the first passivation layer 965 and the second semiconductor material 910. The gate electrode 935 is disposed between the gate dielectric 955 and the first passivation layer 965. The HFET 900 may include a fourth passivation layer 996, and a third insulating layer 994 is disposed between the fourth passivation layer 996 and the third passivation layer 987.

[0075] In one embodiment, the second gate field plate 942 extends from the second passivation layer 975, through the second insulating layer 992, through the third passivation layer 987, and into the fourth passivation layer 996. Notably, in the depicted embodiment, the second gate field plate 942 has a large continuous bulk metal feature disposed in the third passivation layer 987. In one embodiment, the lateral dimension of the bulk feature of the second gate field plate 942 occupies less than 50% of the distance between the source electrode 925 and the drain electrode 930 in the third passivation layer 987. In another embodiment, the lateral dimension of the bulk feature of the second gate field plate 942 occupies less than 33% of the distance between the source electrode 925 and the drain electrode 930 in the third passivation layer 987. In the illustrated embodiment, the second gate field plate 942 has a larger lateral cross-sectional diameter than the first gate field plate 940, and the second gate field plate 942 is disposed above the first gate field plate 940. As depicted, the second gate field plate 942 has a feature disposed between the third passivation layer 987 and the fourth passivation layer 996. In the depicted embodiment, the feature is segmented; however, in other embodiments, the feature may be continuous. It should be noted that the second gate field plate 942 may take the form of Figures 1 to 4 , Figure 7 and Figure 8 Any of the shapes of the first gate field plate, the second gate field plate, and / or the third gate field plate in any of the embodiments depicted in . These shapes can be achieved by manufacturing a single continuous gate field plate (e.g., the second gate field plate 942) rather than by dividing the gate field plate manufacturing process into multiple steps for forming separate gate field plates.

[0076] In one embodiment, the HFET 900 may be fabricated by the following method. It should be noted that these steps may be completed in any order, and even in parallel. In addition, as will be appreciated by those skilled in the relevant art, the following method may omit steps, or alternatively, may include unnecessary steps.

[0077] A first semiconductor material and a second semiconductor material are provided. A heterojunction is arranged between the first semiconductor material and the second semiconductor material. In one embodiment, the first and / or second semiconductor material may include GaN.

[0078] The source electrode and the drain electrode are formed on the second semiconductor material. In one embodiment, the source electrode and the drain electrode may extend into the second semiconductor material and may even contact the first semiconductor material.

[0079] The gate dielectric is formed on the second semiconductor material. In one embodiment, the gate dielectric comprises AlO x , HfO xOr other suitable dielectric materials (high dielectric constant or other forms).

[0080] A gate electrode is formed proximate to a surface of the second semiconductor material, and a gate dielectric is disposed between the gate electrode and the second semiconductor material.

[0081] A plurality of composite passivation layers are deposited adjacent to the gate dielectric, and the gate dielectric is disposed between the plurality of composite passivation layers and the second semiconductor material. In one embodiment, a first composite passivation layer in the plurality of composite passivation layers comprises a first passivation layer and a first insulating layer. The first passivation layer is disposed between the gate dielectric and the first insulating layer. In another or the same embodiment, a second composite passivation layer in the plurality of composite passivation layers comprises a second passivation layer and a second insulating layer. The second passivation layer is disposed between the first insulating layer and the second insulating layer.

[0082] The patterned trenches are then etched into the multiple composite passivation layers to form one or more gate field plates. The geometry of these patterned trenches can be controlled by depositing and decomposing a photoresist (positive or negative) on the appropriate layers of the device architecture. The trench geometry can match the shape of the field plate to be formed (for details on the trench geometry, see above in conjunction with Figures 1 to 4 as well as Figures 7 to 9 Description of the first, second and third gate field plates discussed). In one embodiment, etching of the first composite passivation layer may occur before forming the second composite passivation layer. However, in another embodiment, multiple composite passivation layers may be formed and then all of the composite passivation layers may be etched together. The etching may include wet etching and / or dry etching. It should be noted that the passivation layer may include SiN and may be etched up to 100 times faster than the insulating layer, depending on the etchant used and the process employed. Therefore, the insulating layer and / or the gate dielectric may be used as an etch stop layer to precisely control the geometry of the gate field plate.

[0083] The etched pattern / hole can then be backfilled with metal or other conductive material to form a gate field plate (such as Figures 1 to 4 as well as Figures 7 to 9 The field plates may be deposited in one or more steps, and their geometry may include a continuous layer or multiple independent structures. Fig. 9 In the embodiment depicted in , the bulk of the second gate field plate 942 can be formed in one metal deposition step by depositing metal in trenches etched into the third passivation layer 987. Thereafter, the portion of the second gate field plate 942 disposed on the third passivation layer 987 can be patterned and deposited.

[0084] It should be noted that after the gate field plate has been formed, excess metal / deposition flux can be removed by chemical mechanical polishing, etc. Additional isolation and / or passivation layers can be deposited after the various field plate architectures are formed. In addition, the above-described processes can be used to fabricate any of the geometries depicted in the figures and described in the specification.

[0085] The above description of the illustrated embodiments of the present invention (including what is described in the Abstract) is not exhaustive or intended to limit the invention to the exact form disclosed. Although specific embodiments of the present invention are described herein for illustrative purposes, as will be appreciated by those skilled in the relevant art, many modifications are possible within the scope of the present invention.

[0086] These modifications can be made to the invention in light of the above detailed description. The terms used in the appended claims should not be construed to limit the invention to the specific embodiments disclosed in the specification. Instead, the scope of the invention will be determined entirely by the appended claims, which will be interpreted in accordance with established principles of claim interpretation.

[0087] The technical solution disclosed in this application can also be configured as follows:

[0088] Item 1. A high voltage field effect transistor (HFET), comprising:

[0089] a first semiconductor material, a second semiconductor material, and a heterojunction, wherein the heterojunction is disposed between the first semiconductor material and the second semiconductor material;

[0090] a plurality of composite passivation layers, wherein a first composite passivation layer of the plurality of composite passivation layers comprises a first insulating layer and a first passivation layer, wherein a second composite passivation layer of the plurality of composite passivation layers comprises a second insulating layer and a second passivation layer, and wherein the second passivation layer is arranged between the first insulating layer and the second insulating layer;

[0091] a gate dielectric disposed between the first passivation layer and the second semiconductor material;

[0092] a gate electrode disposed between the gate dielectric and the first passivation layer;

[0093] a first gate field plate disposed between the first passivation layer and the second passivation layer;

[0094] a source electrode and a drain electrode, wherein the source electrode and the drain electrode are coupled to the second semiconductor material; and

[0095] A source field plate is coupled to the source electrode.

[0096] Item 2. The HFET of item 1, wherein the first gate field plate is coupled to the gate electrode.

[0097] Item 3. The HFET of Item 1, further comprising a third passivation layer, wherein the second insulating layer is disposed between the second passivation layer and the third passivation layer.

[0098] Item 4. The HFET of Item 3, further comprising a second gate field plate disposed between the second insulating layer and the third passivation layer.

[0099] Item 5. The HFET of Item 3, wherein the source field plate is disposed between the second passivation layer and the third passivation layer, and wherein the first gate field plate is disposed between the first insulating layer and the second passivation layer.

[0100] Item 6. The HFET of Item 5, wherein a lateral boundary of the first insulating layer is substantially coextensive with a lateral boundary of the source field plate, and wherein a lateral boundary of the second insulating layer is substantially coextensive with a lateral boundary of the source field plate.

[0101] Item 7. The HFET of item 3, further comprising:

[0102] a third composite passivation layer, the third composite passivation layer comprising the third passivation layer and a third insulating layer;

[0103] a fourth passivation layer, wherein the third insulating layer is disposed between the third passivation layer and the fourth passivation layer; and

[0104] A second gate field plate is coupled to the first gate field plate, wherein the second gate field plate is disposed between the second passivation layer and the third passivation layer, and wherein the source field plate is disposed between the third passivation layer and the fourth passivation layer.

[0105] Item 8. The HFET of Item 7, further comprising a third gate field plate coupled to the second gate field plate and disposed between the third passivation layer and the fourth passivation layer.

[0106] Item 9. An HFET according to Item 7, wherein a lateral boundary of the first insulating layer is substantially coextensive with a lateral boundary of the first gate field plate, wherein a lateral boundary of the second insulating layer is substantially coextensive with a lateral boundary of the second gate field plate, and wherein a lateral boundary of the third insulating layer is substantially coextensive with a lateral boundary of the source field plate.

[0107] Item 10. The HFET of Item 1, wherein the gate dielectric and the first insulating layer of the plurality of composite passivation layers comprise the same material composition.

[0108] Item 11. The HFET of item 1, wherein the first passivation layer and the second passivation layer of the plurality of composite passivation layers comprise SiN, and wherein the gate dielectric and the first insulating layer comprise a metal oxide.

[0109] Item 12. The HFET of Item 1, wherein the insulating layer in the plurality of said composite passivation layers is arranged to prevent charging of the passivation layer in the plurality of said composite passivation layers.

[0110] Item 13. The HFET of Item 1, wherein the drain electrode extends from the second semiconductor material through at least one of the plurality of composite passivation layers.

[0111] Item 14. A high voltage field effect transistor (HFET), comprising:

[0112] a first semiconductor material, a second semiconductor material, and a heterojunction, wherein the heterojunction is disposed between the first semiconductor material and the second semiconductor material;

[0113] Multiple composite passivation layers, including:

[0114] a first composite passivation layer, the first composite passivation layer comprising a first insulating layer and a first passivation layer, wherein the first passivation layer is arranged between the second semiconductor material and the first insulating layer;

[0115] a second composite passivation layer, the second composite passivation layer having a second insulating layer and a second passivation layer, wherein the second passivation layer is arranged between the first insulating layer and the second insulating layer; and

[0116] a third composite passivation layer, the third composite passivation layer comprising a third insulating layer and a third passivation layer, wherein the third passivation layer is arranged between the second insulating layer and the third insulating layer;

[0117] a first gate field plate disposed between the first passivation layer and the second passivation layer; and

[0118] A second gate field plate is coupled to the first gate field plate, wherein the second gate field plate extends from the second passivation layer and passes through the third insulating layer.

[0119] Item 15. The HFET of Item 14, further comprising:

[0120] a gate dielectric disposed between the first passivation layer and the second semiconductor material; and

[0121] A gate electrode is disposed between the gate dielectric and the first passivation layer.

[0122] Item 16. The HFET of Item 14, further comprising a fourth passivation layer, wherein the third insulating layer is disposed between the fourth passivation layer and the third passivation layer, and wherein the second gate field plate extends from the second passivation layer, through the second insulating layer, through the third passivation layer, and into the fourth passivation layer.

[0123] Item 17. The HFET of Item 14, wherein the second gate field plate comprises metal and is continuous.

[0124] Item 18. The HFET of Item 14, further comprising a source field plate coupled to the source electrode, and wherein the third passivation layer is disposed between the source field plate and the second insulating layer.

[0125] Item 19. A method of manufacturing a high voltage field effect transistor (HFET), comprising:

[0126] forming a heterojunction between the first semiconductor material and the second semiconductor material;

[0127] forming a source electrode and a drain electrode, wherein the source electrode and the drain electrode are both coupled to the second semiconductor material;

[0128] depositing a gate dielectric, wherein the second semiconductor material is disposed between the gate dielectric and the first semiconductor material;

[0129] Depositing a plurality of composite passivation layers, wherein a first composite passivation layer of the plurality of composite passivation layers comprises a first insulating layer and a first passivation layer, and wherein the first passivation layer is disposed between the gate dielectric and the first insulating layer;

[0130] forming a gate electrode between the gate dielectric and the plurality of composite passivation layers;

[0131] Depositing a second composite passivation layer among the plurality of composite passivation layers, the second composite passivation layer comprising a second insulating layer and a second passivation layer, wherein the second passivation layer is arranged between the first insulating layer and the second insulating layer; and

[0132] A first gate field plate is formed between the first passivation layer and the second passivation layer.

[0133] Item 20. The method of Item 19, wherein the first insulating layer has a larger band gap than the first passivation layer.

[0134] Item 21. The method of Item 19, wherein the first gate field plate is coupled to the gate electrode.

[0135] Item 22. The method of Item 19, further comprising forming a source field plate on the second insulating layer.

[0136] Item 23. The method of Item 19, further comprising forming a second gate field plate coupled to the first gate field plate, wherein the second gate field plate is disposed on the second insulating layer.

[0137] Item 24. A method according to Item 19, wherein depositing the plurality of composite passivation layers includes depositing the first insulating layer and the second insulating layer so that a lateral boundary between the first insulating layer and the second insulating layer is shorter than a lateral distance between the source electrode and the drain electrode.

[0138] Item 25. The method according to Item 19, further comprising:

[0139] Depositing a third composite passivation layer, the third composite passivation layer comprising a third insulating layer and a third passivation layer, wherein the third passivation layer is arranged between the second insulating layer and the third insulating layer;

[0140] forming a second gate field plate coupled to the first gate field plate, wherein the second gate field plate is disposed between the second passivation layer and the third passivation layer; and

[0141] A source field plate is formed, wherein the third passivation layer is disposed between the source field plate and the second insulating layer.

[0142] Item 26. The method of Item 25, further comprising forming a third gate field plate coupled to the second gate field plate and disposed on the third insulating layer.

[0143] Item 27. The method of Item 25, further comprising depositing a fourth passivation layer, wherein the fourth passivation layer is disposed on the source field plate and the third insulating layer.

[0144] Item 28. The method of Item 20, wherein the first gate field plate is disposed between the first insulating layer and the second passivation layer.

[0145] Item 29. The method of Item 20, wherein the first passivation layer comprises SiN, and the gate dielectric and the first insulating layer comprise a metal oxide.

Claims

1. A high voltage field effect transistor, comprising: a first semiconductor material, a second semiconductor material, and a heterojunction, wherein the heterojunction is disposed between the first semiconductor material and the second semiconductor material; Multiple composite passivation layers, including: a first composite passivation layer, the first composite passivation layer having a first insulating layer and a first passivation layer, wherein the first passivation layer is arranged between the second semiconductor material and the first insulating layer, and the first insulating layer is made of a dielectric suitable for forming a gate insulator; a second composite passivation layer, the second composite passivation layer having a second insulating layer and a second passivation layer, wherein the second passivation layer is arranged between the first insulating layer and the second insulating layer, and the second insulating layer is made of a dielectric suitable for forming a gate insulator; and a third composite passivation layer, the third composite passivation layer comprising a third insulating layer and a third passivation layer, wherein the third passivation layer is arranged between the second insulating layer and the third insulating layer; a fourth passivation layer, wherein the third insulating layer is arranged between the fourth passivation layer and the third passivation layer, a first gate field plate, the first gate field plate being arranged between the first passivation layer and the second passivation layer, wherein the first gate field plate is coupled to the gate electrode; a second gate field plate coupled to the first gate field plate, wherein the second gate field plate extends from the second passivation layer, through the second insulating layer, through the third passivation layer, and into the fourth passivation layer; and a gate dielectric disposed between the first passivation layer and the second semiconductor material; Wherein, the gate electrode is arranged between the gate dielectric and the first passivation layer.

2. The high voltage field effect transistor according to claim 1, wherein: the second gate field plate having a large continuous bulk metal feature disposed in the third passivation layer, the second gate field plate has a larger lateral cross-section than the first gate field plate, and The second gate field plate is arranged above the first gate field plate, and The second gate field plate has a feature disposed between the third passivation layer and the fourth passivation layer. 3 . The high voltage field effect transistor of claim 1 , wherein the second gate field plate comprises metal and is continuous. 4 . The high voltage field effect transistor of claim 1 , further comprising a source field plate coupled to the source electrode, and wherein the third passivation layer is disposed between the source field plate and the second insulating layer.

5. The high voltage field effect transistor according to claim 1, wherein: The first insulating layer has a wider band gap than the first passivation layer, and the second insulating layer has a wider band gap than the second passivation layer. 6 . The high voltage field effect transistor of claim 4 , wherein the first insulating layer and the second insulating layer are longer than the source field plate but do not occupy the entire corresponding composite passivation layer. 7 . The high voltage field effect transistor of claim 1 , further comprising a third gate field plate coupled to the second gate field plate and disposed between the third passivation layer and a fourth passivation layer.

8. The high-voltage field effect transistor of claim 4 , wherein a lateral boundary of the first insulating layer is substantially coextensive with a lateral boundary of the first gate field plate, wherein a lateral boundary of the second insulating layer is substantially coextensive with a lateral boundary of the second gate field plate, and wherein a lateral boundary of the third insulating layer is substantially coextensive with a lateral boundary of the source field plate. 9 . The high voltage field effect transistor of claim 1 , wherein the gate dielectric and the first insulating layer in the plurality of composite passivation layers are made of the same material composition. 10 . The high voltage field effect transistor of claim 1 , wherein the first passivation layer and the second passivation layer of the plurality of composite passivation layers comprise SiN, and wherein the gate dielectric and the first insulating layer comprise metal oxide.

11. A method comprising manufacturing a high voltage field effect transistor according to any one of claims 1 to 10. 12 . The method of claim 11 , wherein the first insulating layer has a larger band gap than the first passivation layer.

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