Flat panel detector, driving method, driving device and flat panel detection device

Abstract

The present invention discloses a flat panel detector, a driving method, a driving device and a flat panel detection device. By providing a compensation structure of a semiconductor material, the compensation structure can form a Schottky contact with the gate of the detection transistor, thereby forming a Schottky diode form. In this way, the adverse effects of the coupling capacitances Cgs and Cgd on the imaging detection voltage can be reduced, thereby improving the uniformity of the imaging detection voltage and the gray level uniformity of the formed detection image.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and particularly to a flat panel detector, a driving method, a driving device, and a flat panel detection device. Background Art

[0002] X-ray radiography utilizes the properties of short wavelength and easy penetration of X-rays, as well as the characteristics that different tissues absorb X-rays differently, and forms an image by detecting the intensity of X-rays passing through an object. As the core component of an X-ray imaging system, a flat panel detector (FPD) is responsible for converting X-rays into electrical signals and recording the image, which can be displayed in real time through a display or stored for subsequent reading. Generally speaking, an FPD includes a scintillator, an image sensor, a control module, a signal processing module, and a communication module. The scintillator absorbs X-rays and converts them into visible light; the image sensor is composed of a pixel array formed by photodiodes and thin film transistor (TFT) switches. Under the drive of a control circuit, the visible light generated by the scintillator is converted into an electrical signal; the signal processing module amplifies the electrical signal, converts it into a digital signal through an analog-to-digital converter, and then forms an image through compensation processing. Summary of the Invention

[0003] Embodiments of the present invention provide a flat panel detector, a driving method, a driving device, and a flat panel detection device to improve imaging uniformity.

[0004] A flat panel detector provided by an embodiment of the present invention includes: a substrate; and a plurality of detection units located on the substrate; each of the detection units includes a photodiode and a detection transistor.

[0005] The flat panel detector further includes: a compensating semiconductor material layer; the compensating semiconductor material layer includes a plurality of compensating structures arranged at intervals; wherein, one compensating structure is correspondingly arranged for one detection transistor, and the compensating structure is located between the gate and the gate insulating layer of the corresponding detection transistor.

[0006] In some examples, the orthographic projection of the compensating structure on the substrate at least covers the orthographic projection on the substrate of the surface of the gate of the corresponding detection transistor facing the active layer.

[0007] In some examples, the material of the gate includes metal; the material of the compensating semiconductor material layer includes: a doped P-type semiconductor material.

[0008] In some examples, the work function of the compensating semiconductor material layer is greater than the work function of the gate.

[0009] In some examples, the gate includes a plurality of gate film layers;

[0010] The work function of the compensating semiconductor material layer is greater than the work function of the nearest gate film layer in the gate.

[0011] A driving method for a flat panel detector provided by an embodiment of the present invention includes: an imaging detection stage; wherein, the imaging detection stage includes: N consecutive row acquisition stages; wherein, N is the total number of rows of detection units in the flat panel detector;

[0012] In the nth row acquisition stage, control the detection transistors in each of the detection units to be turned off, and obtain the imaging noise voltage corresponding to the photodiode in each of the detection units in the nth row; wherein, 1 ≤ n ≤ N, and n is an integer;

[0013] Control the detection transistors in each of the detection units in the nth row to be turned on, and obtain the imaging detection voltage corresponding to the photodiode in each of the detection units in the nth row;

[0014] According to the imaging noise voltage and the imaging detection voltage corresponding to the photodiodes in each of the detection units in the nth row, determine the imaging effective voltage corresponding to the photodiodes in each of the detection units in the nth row.

[0015] In some examples, before the imaging detection stage, it further includes:

[0016] In the current reset stage, simultaneously control the detection transistors in each of the detection units to be turned on to reset the photodiodes in each of the detection units.

[0017] In some examples, after simultaneously controlling the detection transistors in each of the detection units to be turned on to reset the photodiodes in each of the detection units, the current reset stage further includes:

[0018] Control the detection transistors in at least one row of the detection units to be turned on, and obtain the detection control voltage corresponding to the photodiode electrically connected to the turned-on detection transistor;

[0019] Determine whether at least one of the obtained detection control voltages meets a voltage threshold;

[0020] If so, enter the imaging detection stage;

[0021] If not, enter the next reset stage.

[0022] In some examples, the duration of maintaining one detection transistor being turned on in the reset stage is the same as the duration of maintaining one detection transistor being turned on in the imaging detection stage.

[0023] A driving device for a flat panel detector provided by an embodiment of the present invention includes: a driving circuit;

[0024] The driving circuit is configured to execute the above driving method.

[0025] A flat panel detection device provided by an embodiment of the present invention includes the above flat panel detector and / or the above driving device of the flat panel detector.

[0026] The beneficial effects of the present invention are as follows:

[0027] The flat panel detector, driving method, driving device, and flat panel detection device provided by the embodiments of the present invention can form a Schottky contact between the compensation structure and the gate of the detection transistor by setting the compensation structure of the semiconductor material, thereby forming a Schottky diode form. In this way, the adverse effects of the coupling capacitances Cgs and Cgd on the imaging detection voltage can be reduced, thereby improving the uniformity of the imaging detection voltage and the gray level uniformity of the formed detection image. Description of the Drawings

[0028] Figure 1 It is a schematic structural diagram of the flat panel detector in the embodiment of the present invention;

[0029] Figure 2 It is some partial cross-sectional structural diagrams of the flat panel detector in the embodiment of the present invention;

[0030] Figure 3 It is a schematic structural diagram of the detection transistor in the embodiment of the present invention;

[0031] Figure 4 It is some other partial cross-sectional structural diagrams of the flat panel detector in the embodiment of the present invention;

[0032] Figure 5 It is some other partial cross-sectional structural diagrams of the flat panel detector in the embodiment of the present invention;

[0033] Figure 6 It is some other partial cross-sectional structural diagrams of the flat panel detector in the embodiment of the present invention;

[0034] Figure 7 It is a flowchart of the driving method of the flat panel detector in the embodiment of the present invention;

[0035] Figure 8 It is some signal timing diagrams in the embodiment of the present invention;

[0036] Figure 9 It is some other signal timing diagrams in the embodiment of the present invention. Detailed Embodiments

[0037] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are some but not all of the embodiments of the present invention. And, without conflict, the embodiments in the present invention and the features in the embodiments may be combined with each other. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention.

[0038] Unless otherwise defined, the technical terms or scientific terms used in the present invention shall have the ordinary meanings as understood by those of ordinary skill in the art to which the present invention pertains. The "first", "second" and similar terms used in the present invention do not denote any order, quantity or importance, but are only used to distinguish different components. The terms such as "comprising" or "including" mean that the elements or items appearing before this term cover the elements or items listed after this term and their equivalents, without excluding other elements or items. The terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0039] It should be noted that the sizes and shapes of the various figures in the drawings do not reflect the actual scale, and the purpose is only to schematically illustrate the content of the present invention. And, the same or similar reference numerals represent the same or similar elements or elements having the same or similar functions throughout.

[0040] The embodiments of the present invention provide a flat panel detector, as Figure 1 shown, which may include: a substrate 100, a plurality of detection units 110, a plurality of scan lines GA and a plurality of detection lines SL located on the substrate 100; wherein, the detection units 110 can define the area where they are located through the plurality of scan lines GA and the plurality of detection lines SL. Exemplarily, the plurality of detection units 110 are arranged in an array on the substrate 100. In this way, the detection units 110 can be periodically arranged in the row direction and the column direction. And, these scan lines GA extend in the row direction and are arranged in the column direction. These data lines can extend in the column direction and are arranged in the row direction. Also, one row of detection units 110 corresponds to one scan line GA, and one column of detection units 110 corresponds to one detection line SL.

[0041] In specific implementation, in the embodiments of the present invention, as Figure 1As shown, each detection unit 110 may include a photodiode L and a detection transistor M1. Among them, the gate M1-G of the detection transistor M1 is electrically connected to the corresponding scan line GA, the second pole of the detection transistor M1 is electrically connected to the negative electrode of the corresponding photodiode L, and the first pole of the detection transistor M1 is electrically connected to the corresponding detection line SL.

[0042] Furthermore, the flat panel detector may further include a bias voltage signal line BL, and the positive electrode of the photodiode L is electrically connected to the bias voltage signal line BL. In this way, a bias voltage can be input to the photodiode L through the bias voltage signal line BL. When the photodiode L receives an optical signal, an electrical signal can be generated through the photoelectric conversion effect. This electrical signal can be transmitted to the detection transistor M1, so that when the detection transistor M1 is turned on, it can be transmitted to the detection line SL through the detection transistor M1. Exemplarily, the detection transistor M1 may be, for example, a PIN-type photodiode L.

[0043] In specific implementation, in the embodiments of the present invention, as Figure 2 shown, the detection transistor M1 may include a gate M1-G located on the substrate 100, a gate insulating layer 210 located on the side of the gate M1-G away from the substrate 100, an active layer M1-A located on the side of the gate insulating layer 210 away from the substrate 100, and a source-drain layer located on the side of the active layer M1-A away from the substrate 100. Among them, the source-drain layer includes the second pole M1-2 and the first pole M1-1 of the detection transistor M1.

[0044] In specific implementation, in the embodiments of the present invention, as Figure 2 shown, the photodiode L may include a negative electrode, a photoelectric conversion layer, and a positive electrode stacked on the substrate 100. For example, the photoelectric conversion layer can be patterned so that an independent photoelectric conversion layer is provided in one detection unit 110. And the negative electrode is also patterned so that an independent negative electrode is provided in one detection unit 110. And the positive electrode can cover the substrate 100 in a whole-layer manner.

[0045] In specific implementation, in the embodiments of the present invention, as Figure 2 shown, a planarization layer 230 is provided between the layer where the detection transistor M1 is located and the layer where the photodiode L is located. Exemplarily, the layer where the photodiode L is located is on the side of the planarization layer 230 away from the substrate 100. And the second pole of the detection transistor M1 is electrically connected to the negative electrode of the photodiode L through a via hole penetrating the planarization layer 230.

[0046] In specific implementation, in the embodiments of the present invention, as Figure 2As shown, the flat panel detector further includes: a photoelectric insulating layer located on the side of the photodiode L away from the substrate 100, a bias voltage signal line BL located on the side of the photoelectric insulating layer away from the substrate 100, an adhesive layer located on the side of the bias voltage signal line BL away from the substrate 100, and a protective cover plate GB located on the side of the adhesive layer away from the substrate 100.

[0047] During imaging detection, generally, first control the detection transistors M1 in each detection unit 110 to be all cut off, and obtain the imaging noise voltage V corresponding to the photodiode L in each detection unit 110 cds1 . Then, control the detection transistors M1 in the detection unit 110 to be turned on row by row, and obtain the imaging detection voltage V corresponding to the photodiode L in each detection unit 110 cds2 . Then, for each photodiode L, subtract the imaging noise voltage V corresponding to the photodiode L cds1 and the imaging detection voltage V cds2 , that is, V cds2 - V cds1 , so as to form a detection image through the voltage of V cds2 - V cds1 .

[0048] However, since there is a coupling capacitance C between the gate M1-G and the first pole M1-1 of the detection transistor M1 gs , and there is a coupling capacitance C between the gate M1-G and the second pole M1-2 gd , the coupling capacitance of the detection transistor M1 when conducting and when cut off is different. Specifically: when the detection transistor M1 is conducting, the coupling capacitance between its gate M1-G and the first pole M1-1 is C gs-on , and the coupling capacitance C between its gate M1-G and the second pole M1-2 gd-on .

[0049] And, as shown in Figure 3

[0050] when the detection transistor M1 is cut off, the coupling capacitance between its gate M1-G and the first pole M1-1 is C gs-off , and the coupling capacitance C between its gate M1-G and the second pole M1-2 gd-off .

[0051] And,

[0052] where ε0 represents the permittivity of vacuum, ε rrepresents the relative dielectric constant, L represents the distance in the F2 direction between the orthographic projection of the first pole M1-1 of the detection transistor M1 on the substrate 100 and the orthographic projection of the second pole M1-2 on the substrate 100, W represents the width in the F1 direction of the orthographic projection of the first pole M1-1 (or the second pole M1-2) of the detection transistor M1 that overlaps with the gate M1-G on the substrate 100, and Wef represents the width in the F1 direction between the orthographic projection of the first pole M1-1 (or the second pole M1-2) of the detection transistor M1 on the substrate 100 and the orthographic projection of the gate M1-G on the substrate 100. ΔL represents the width in the F2 direction between the orthographic projection of the first pole M1-1 (or the second pole M1-2) of the detection transistor M1 that overlaps with the gate M1-G on the substrate 100 and the orthographic projection of the gate M1-G on the substrate 100, t ox represents the thickness of the insulating layer between the gate M1-G and the active layer M1-A of the detection transistor M1 located in the overlapping region, t si represents the thickness of the active layer M1-A of the detection transistor M1. It should be noted that the widths W of the orthographic projections of the first pole M1-1 and the second pole M1-2 of the detection transistor M1 that overlap with the gate M1-G along the F1 direction on the substrate 100 are equal. Also, the widths ΔL in the F2 direction between the orthographic projections of the first pole M1-1 and the second pole M1-2 of the detection transistor M1 that overlap with the gate M1-G and the orthographic projection of the gate M1-G on the substrate 100 are equal. The widths Wef in the F1 direction between the orthographic projections of the first pole M1-1 and the second pole M1-2 of the detection transistor M1 on the substrate 100 and the orthographic projection of the gate M1-G on the substrate 100 are equal.

[0053] From the above formula, it can be seen that C gs-on and C gd-on are significantly greater than C gs-off and C gd-off . And, V cds2 = V cds1 + VL + ΔV o - ΔV o ’. Wherein, VL represents the voltage after the light incident on the photodiode L is photoelectrically converted. ΔV o represents the change amount of V cds2 when the detection transistor M1 changes from conducting to cutoff, and ΔV o ’ represents the change amount of V cds2 when the detection transistor M1 changes from cutoff to conducting. And, C F represents the sum of the capacitance of the detection transistor M1 and the capacitance of the photodiode L, ΔV gRepresents the difference between the voltage on the gate M1-G of the detection transistor M1 when it is turned off and the voltage on the gate M1-G of the detection transistor M1 when it is turned on. It should be noted that the capacitance of the detection transistor M1 can be, for example, the coupling capacitance existing in the detection transistor M1. The capacitance of the photodiode L can be, for example, the capacitance formed between the positive and negative electrodes of the photodiode L. Since the capacitance of the detection transistor M1 is smaller than the capacitance of the photodiode L, in practical applications, C F can also be considered as the capacitance of the photodiode L.

[0054] Then, V cds2 -V cds1 = VL + ΔV o -ΔV o ’. Therefore, V cds2 -V cds1 In addition to the voltage VL for forming the detection image, it also includes the voltage ΔV caused by the coupling capacitance o -ΔV o ’. Therefore, by eliminating the influence of the coupling capacitance, V cds2 -V cds1 can be the effective voltage after the photodiode L undergoes photoelectric conversion. Thus, the uniformity of the formed detection image can be improved.

[0055] In view of this, in the flat panel detector provided by the embodiment of the present invention, as Figure 4 shown, it can also include: a compensating semiconductor material layer; wherein, the compensating semiconductor material layer is located between the gate M1-G of the detection transistor M1 and the gate insulating layer 210. Exemplarily, the compensating semiconductor material layer can include a plurality of compensating structures 310 arranged at intervals; wherein, one compensating structure 310 is correspondingly arranged for one detection transistor M1, and the compensating structure 310 is located between the gate M1-G of the corresponding detection transistor M1 and the gate insulating layer 210. By providing the compensating structure 310 of the semiconductor material, the compensating structure 310 can form a Schottky contact with the gate M1-G of the detection transistor M1, thereby forming a Schottky diode form. In this way, the adverse effects of the coupling capacitances C gs and C gd on the imaging detection voltage can be reduced, thereby improving the uniformity of the imaging detection voltage and the gray level uniformity of the formed detection image.

[0056] In specific implementation, in the embodiment of the present invention, as Figure 4As shown, the positive projection of the compensation structure 310 on the substrate 100 at least covers the positive projection on the substrate 100 of the surface of the gate M1-G of the corresponding detection transistor M1 facing the active layer M1-A. Exemplarily, the positive projection of the compensation structure 310 on the substrate 100 can overlap with the positive projection on the substrate 100 of the surface of the gate M1-G of the corresponding detection transistor M1 facing the active layer M1-A. Alternatively, a spacing can be provided between the positive projection of the compensation structure 310 on the substrate 100 and the positive projection on the substrate 100 of the surface of the gate M1-G of the corresponding detection transistor M1 facing the active layer M1-A, so that the compensation structure 310 surrounds the upper gate M1-G.

[0057] In specific implementation, in the embodiments of the present invention, the material of the gate M1-G can include metals, such as Al, Mo, Cu, etc. Exemplarily, as Figure 4 shown, the gate M1-G can be a single-layer structure, such as a gate M1-G formed only of Al or Mo.

[0058] Alternatively, exemplarily, the gate M1-G can also be a stacked structure. As Figure 5 shown, the gate M1-G includes multiple gate M1-G film layers. Among them, the materials of different gate M1-G film layers can be different. For example, the gate M1-G includes two gate M1-G film layers. The material of the gate M1-G film layer directly in contact with the compensation structure 310 can be Mo, and the material of the gate M1-G film layer far from the compensation structure 310 can be Al. Alternatively, the materials of some gate M1-G film layers can be different, and the materials of some gate M1-G film layers can be the same, which is not limited herein.

[0059] In specific implementation, in the embodiments of the present invention, the material of the compensation semiconductor material layer can include: doped P-type semiconductor material. For example, the material of the compensation semiconductor material layer can include: P-type a-si after ion doping.

[0060] In specific implementation, in the embodiments of the present invention, in order to form a good Schottky contact between the compensation structure 310 and the gate M1-G, the work function of the compensation semiconductor material layer can be made greater than the work function of the gate M1-G. Further, the work function of the compensation semiconductor material layer is greater than the work function of the gate M1-G film layer closest to the gate M1-G. For example, when the material of the compensation semiconductor material layer includes P-type a-si after ion doping and the material of the gate M1-G film layer directly in contact with the compensation structure 310 is Mo, the work function of Mo can be made less than the work function of doped P-type a-si. In practical applications, the work function of Mo is approximately 4.2 - 4.4 eV. For P-type a-si, as the doping concentration increases, its work function also increases. When the doping concentration reaches 10 14cm -3 When it is 14 cm -3 ), that is, a good Schottky contact can be formed between the gate M1-G and the compensation structure 310. Of course, in practical applications, it can be designed and determined according to the actual application requirements, which is not limited here.

[0061] Since V cds2 -V cds1 =VL + ΔV o -ΔV o ’. In order to eliminate the influence of the coupling capacitance, ΔV o -ΔV o ’ can be made equal to 0, that is then C gd-off = 2C gd-on . In specific implementation, in the embodiment of the present invention, the thickness h o of the compensation structure 310 can satisfy the following formula: This can make C gd-off = 2C gd-on , thereby eliminating the influence of the coupling capacitance and improving the gray-scale uniformity of the detected image.

[0062] In order to improve the characteristics of the detection transistor M1, in specific implementation, in the embodiment of the present invention, as Figure 6 shown, the flat panel detector may further include: a contact semiconductor material layer. Among them, the contact semiconductor material layer is located between the active layer M1-A and the source-drain layer. Exemplarily, the contact semiconductor material layer may include a plurality of first contact structures 321 and a plurality of second contact structures 322 arranged at intervals. One first pole of a detection transistor M1 corresponds to one first contact structure 321, one second pole of a detection transistor M1 corresponds to one second contact structure 322, and the positive projection of the first pole of the detection transistor M1 on the substrate 100 covers the positive projection of the corresponding first contact structure 321 on the substrate 100, and the first pole of the detection transistor M1 is in contact with the active layer M1-A through the corresponding first contact structure 321. And, the positive projection of the second pole of the detection transistor M1 on the substrate 100 covers the positive projection of the corresponding second contact structure 322 on the substrate 100, and the second pole of the detection transistor M1 is in contact with the active layer M1-A through the corresponding second contact structure 322.

[0063] In specific implementation, in the embodiment of the present invention, the material of the contact semiconductor material layer may include an N-type semiconductor material layer. For example, the material of the contact semiconductor material layer may be N-type a-Si.

[0064] An embodiment of the present invention also provides a driving method for a flat panel detector. The driving method may include: an imaging detection stage. Exemplarily, the driving method may operate based on the flat panel detector having the above structure.

[0065] In specific implementation, in the embodiment of the present invention, the imaging detection stage may include: N consecutive row acquisition stages; where N is the total number of rows of detection units in the flat panel detector. That is to say, one row of detection units corresponds to one row acquisition stage. For example, the nth row of detection units may correspond to the nth row acquisition stage; where 1 ≤ n ≤ N and n is an integer.

[0066] As Figure 7 shown, for the driving method provided by the embodiment of the present invention, in the nth row acquisition stage, the following steps may be included:

[0067] S10. Control the detection transistors in each detection unit to be all cut off, and obtain the imaging noise voltage corresponding to the photodiodes in each detection unit of the nth row.

[0068] Exemplarily, a gate cut-off signal is loaded on each scan line to make each detection transistor cut off. Through each detection line, the imaging noise voltage V corresponding to the photodiodes in each detection unit of the nth row is obtained. cds1 .

[0069] S20. Control the detection transistors in each detection unit of the nth row to be turned on, and obtain the imaging detection voltage corresponding to the photodiodes in each detection unit of the nth row.

[0070] Exemplarily, only control the detection transistors in each detection unit of the nth row to be turned on, and control the detection transistors in each detection unit of the remaining rows to be cut off, so as to obtain the imaging detection voltage V corresponding to the photodiodes in each detection unit of the nth row through each detection line. cds2 .

[0071] S30. Determine the imaging effective voltage corresponding to each photodiode in the nth row according to the imaging noise voltage and the imaging detection voltage corresponding to each photodiode in the nth row.

[0072] Exemplarily, determine the difference between the imaging detection voltage V cds2 and the imaging noise voltage V cds1 , and take this difference as the imaging effective voltage: V cds2 - V cds1 = VL, so as to form a detection image through the imaging effective voltage V cds2 - V cds1 after the end of the Nth row acquisition stage in this imaging detection stage. Since V cds2 - Vcds1 It is not affected by the coupling capacitance, so the grayscale uniformity of the formed detection image can be improved.

[0073] In a specific implementation, before the imaging detection stage, it may also include: a self-clearing stage for self-clearing the charge of the photodiode L in the detection unit. In the self-clearing stage, the detection transistor M1 in the detection unit 110 is controlled to be turned on row by row to release the charge of the photodiode L in the detection unit 110.

[0074] Combination Figure 8 As shown, ga-n represents the signal loaded on the gate M1-G of the detection transistor M1 in the detection unit 110 of the nth row. In the self-clearing stage T00-1, the detection transistor M1 in the detection unit 110 can be controlled to be turned on row by row to release the charge of the photodiode L in the detection unit 110. In the self-clearing stage T00-2, when scanning to the nth row, if an exposure request signal is detected, the self-clearing will be stopped immediately and the exposure will start immediately, that is, the exposure will start from the n+1th row to the Nth row. This will cause a large difference between the grayscale displayed from the 1st row to the nth row and the grayscale displayed from the n+1th row to the Nth row, resulting in a problem of split screen detection image.

[0075] In view of this, in a specific implementation, in an embodiment of the present invention, before the imaging detection stage, it may further include: at least one reset stage; wherein, in the current reset stage, the detection transistors M1 in each detection unit 110 are simultaneously controlled to be turned on, so as to reset the photodiodes L in each detection unit 110. In this way, by simultaneously controlling the detection transistors M1 in each detection unit 110 to be turned on, it is not necessary to scan each row of detection units 110 line by line, so that when exposure is detected, the imaging detection stage can be directly entered after the photodiodes L in all detection units 110 are discharged, thereby solving the problem of detecting image split screen.

[0076] In a specific implementation, in an embodiment of the present invention, after simultaneously controlling the detection transistors M1 in each detection unit 110 to be turned on to reset the photodiodes L in each detection unit 110, the current reset phase may further include:

[0077] Controlling the detection transistors M1 in at least one row of detection units 110 to be turned on, and obtaining a detection control voltage corresponding to the photodiode L electrically connected to the turned-on detection transistors M1;

[0078] Determining whether at least one of the acquired detection control voltages meets a voltage threshold;

[0079] If yes, then the imaging detection phase is entered;

[0080] If not, enter the next reset phase.

[0081] Exemplarily, after discharging all the photodiodes L each time, the detection control voltage in the detection units 110 of at least one row can be detected to determine whether exposure is received according to the detection control voltage, so that when exposure is received, the imaging detection phase can be directly entered. When exposure is not received, the imaging detection phase is not entered and the reset phase is repeated again.

[0082] Exemplarily, the detection transistor M1 in one row of the detection units 110 can be controlled to conduct, and the detection control voltage corresponding to the photodiode L electrically connected to the conducting detection transistor M1 can be obtained. Alternatively, the detection transistors M1 in two or more rows of the detection units 110 can also be controlled to conduct, and the detection control voltage corresponding to the photodiode L electrically connected to the conducting detection transistors M1 can be obtained.

[0083] In order to enable rapid switching between consecutive reset phases, in a specific implementation, in the embodiments of the present invention, the maintaining duration for controlling one detection transistor M1 to conduct in the reset phase can be the same as the maintaining duration for controlling one detection transistor M1 to conduct in the imaging detection phase.

[0084] The driving method provided by the present invention will be described in detail below with reference to specific embodiments. It should be noted that this embodiment is for better explaining the present invention, but does not limit the present invention.

[0085] Combined with Figure 9 As shown, ga-n represents the signal loaded on the gate M1-G of the detection transistor M1 in the nth row of the detection units 110.

[0086] In the reset phase T01-1, the detection transistors M1 in each of the detection units 110 are simultaneously controlled to conduct to reset the photodiodes L in each of the detection units 110. Specifically, a gate M1-G opening signal (such as a high-level signal) is first loaded on the scan line GA electrically connected to each row of the detection transistors M1, and the detection transistors M1 in each of the detection units 110 can be simultaneously controlled to conduct, so that the negative electrode of the photodiode L is conducted to the detection line SL, thereby enabling the charge in the photodiode L to be released through the detection line SL.

[0087] Turn on the detection transistor M1 in one row of the detection units 110, and obtain the detection control voltage corresponding to the photodiode L electrically connected to the turned-on detection transistor M1. Specifically, a gate M1-G turn-on signal can be loaded onto the scan line GA electrically connected to the detection transistor M1 in the second row of detection units 110, and a gate M1-G cut-off signal (low-level signal) can be loaded onto the scan lines GA electrically connected to the detection transistors M1 in the remaining detection units 110, so that only the detection transistor M1 in the second row can be turned on, and the detection transistors M1 in the remaining rows are turned off. Thus, the detection control voltages corresponding to the respective photodiodes L in the second row can be obtained through the detection line SL.

[0088] Determine whether at least one of the obtained detection control voltages meets the voltage threshold; among them, it can be determined whether one obtained detection control voltage meets the voltage threshold, or it can also be determined whether multiple obtained detection control voltages meet the voltage threshold, or it can also be determined whether all the obtained detection control voltages meet the voltage threshold.

[0089] Taking the case where the obtained detection control voltage does not meet the voltage threshold as an example, enter the next reset stage T01-2.

[0090] In the reset stage T01-2, simultaneously turn on the detection transistors M1 in each detection unit 110 to reset the photodiodes L in each detection unit 110. Specifically, first, a gate M1-G turn-on signal (such as a high-level signal) is loaded onto the scan line GA electrically connected to each row of detection transistors M1, so that the detection transistors M1 in each detection unit 110 can be turned on simultaneously, and the negative electrode of the photodiode L can be electrically connected to the detection line SL, so that the charge in the photodiode L can be released through the detection line SL.

[0091] Turn on the detection transistor M1 in one row of the detection units 110, and obtain the detection control voltage corresponding to the photodiode L electrically connected to the turned-on detection transistor M1. Specifically, a gate M1-G turn-on signal can be loaded onto the scan line GA electrically connected to the detection transistor M1 in the second row of detection units 110, and a gate M1-G cut-off signal (low-level signal) can be loaded onto the scan lines GA electrically connected to the detection transistors M1 in the remaining detection units 110, so that only the detection transistor M1 in the second row can be turned on, and the detection transistors M1 in the remaining rows are turned off. Thus, the detection control voltages corresponding to the respective photodiodes L in the second row can be obtained through the detection line SL.

[0092] Determine whether at least one of the acquired detection control voltages meets the voltage threshold; among them, it is possible to determine whether one acquired detection control voltage meets the voltage threshold, or it is also possible to determine whether multiple acquired detection control voltages meet the voltage threshold, or it is also possible to determine whether all the acquired detection control voltages meet the voltage threshold.

[0093] Taking the acquired detection control voltage meeting the voltage threshold as an example, enter the imaging detection stage T11.

[0094] In the imaging detection stage T11, in the first row acquisition stage T111, a gate M1-G cut-off signal is loaded onto the scan line GA electrically connected to each row of detection transistors M1 to control all the detection transistors M1 in each detection unit 110 to be cut off, and the imaging noise voltage V corresponding to the photodiode L in each detection unit 110 of the first row is obtained. cds1-1 。

[0095] A gate M1-G turn-on signal is loaded onto the scan line GA electrically connected to the detection transistors M1 of the first row, and a gate M1-G cut-off signal is loaded onto the scan lines GA electrically connected to the detection transistors M1 of the remaining rows, controlling the detection transistors M1 in each detection unit 110 of the first row to turn on, and controlling all the detection transistors M1 in each detection unit 110 of the remaining rows to be cut off, so as to obtain, through each detection line SL, the imaging detection voltage V corresponding to the photodiode L in each detection unit 110 of the first row. cds2-1 。

[0096] Determine the imaging effective voltage corresponding to the photodiode L in each detection unit 110 of the first row: V cds2-1 -V cds1-1 。

[0097] In the second row acquisition stage T112, a gate M1-G cut-off signal is loaded onto the scan line GA electrically connected to each row of detection transistors M1 to control all the detection transistors M1 in each detection unit 110 to be cut off, and the imaging noise voltage V corresponding to the photodiode L in each detection unit 110 of the second row is obtained. cds1-2 。

[0098] A gate M1-G turn-on signal is loaded onto the scan line GA electrically connected to the detection transistors M1 of the second row, and a gate M1-G cut-off signal is loaded onto the scan lines GA electrically connected to the detection transistors M1 of the remaining rows, controlling the detection transistors M1 in each detection unit 110 of the second row to turn on, and controlling all the detection transistors M1 in each detection unit 110 of the remaining rows to be cut off, so as to obtain, through each detection line SL, the imaging detection voltage V corresponding to the photodiode L in each detection unit 110 of the second row. cds2-2 。

[0099] Determine the imaging effective voltage corresponding to the photodiode L in each detection unit 110 of the second row: V cds2-2 -V cds1-2 。

[0100] In the third row acquisition stage T113, a gate M1-G cut-off signal is loaded onto the scan line GA electrically connected to each row detection transistor M1 to control all the detection transistors M1 in each detection unit 110 to be cut off, and the imaging noise voltage V corresponding to the photodiode L in each detection unit 110 of the third row is obtained cds1-3 。

[0101] A gate M1-G turn-on signal is loaded onto the scan line GA electrically connected to the third row detection transistor M1, and a gate M1-G cut-off signal is loaded onto the scan lines GA electrically connected to the detection transistors M1 of the remaining rows, controlling the detection transistors M1 in each detection unit 110 of the third row to be turned on and controlling all the detection transistors M1 in each detection unit 110 of the remaining rows to be cut off, so as to obtain the imaging detection voltage V corresponding to the photodiode L in each detection unit 110 of the third row through each detection line SL cds2-3 。

[0102] Determine the imaging effective voltage corresponding to the photodiode L in each detection unit 110 of the third row: V cds2-3 -V cds1-3 。

[0103] The working processes of the fourth row acquisition stage to the Nth row acquisition stage are carried out in the same way by analogy, which will not be elaborated here

[0104] The embodiment of the present invention also provides a driving device for a flat panel detector, and the driving device may include: a driving circuit; wherein, the driving circuit is configured to execute the above driving method

[0105] Exemplarily, the driving circuit may be a driving IC (Integrated Circuit).

[0106] It should be noted that the driving principle and specific implementation manner of this driving circuit are the same as those of the embodiment of the above driving method. Therefore, the working process of this driving circuit can be implemented with reference to the specific implementation manner of the driving method in the above embodiment, which will not be elaborated here

[0107] The embodiment of the present invention also provides a flat panel detection device, including the above flat panel detector provided by the embodiment of the present invention and / or the driving device of the flat panel detector. The principle of solving problems of this flat panel detection device is similar to that of the foregoing display panel. Therefore, the implementation of this flat panel detection device can be referred to the implementation of the foregoing display panel, and the repeated parts will not be elaborated here

[0108] In specific implementation, in the embodiments of the present invention, other essential components of the flat panel detection device are those that should be understood by those of ordinary skill in the art and will not be elaborated herein, nor should they be considered as a limitation to the present invention.

[0109] Obviously, those skilled in the art can make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these modifications and variations.

Claims

1. A flat panel detector, comprising: A substrate, and a plurality of detection units located on the substrate; Each of the detection units includes a photodiode and a detection transistor; characterized in that, The flat panel detector further includes: a compensating semiconductor material layer; the compensating semiconductor material layer includes a plurality of compensating structures arranged at intervals; wherein, one compensating structure is correspondingly arranged for one detection transistor, and the compensating structure is located between the gate and the gate insulating layer of the corresponding detection transistor, and the compensating structure forms a Schottky contact with the gate of the detection transistor to reduce the influence of the coupling capacitance between the gate of the detection transistor and the first pole and the second pole of the detection transistor on the imaging detection voltage.

2. The flat panel detector according to claim 1, characterized in that, The orthographic projection of the compensating structure on the substrate covers at least the orthographic projection on the substrate of the surface of the gate of the corresponding detection transistor facing the active layer.

3. The flat panel detector according to claim 1, characterized in that, The material of the gate includes metal; the material of the compensating semiconductor material layer includes: a doped P-type semiconductor material.

4. The flat panel detector according to claim 3, characterized in that, The work function of the compensating semiconductor material layer is greater than the work function of the gate.

5. The flat panel detector according to claim 4, characterized in that The gate includes a plurality of gate film layers; The work function of the compensating semiconductor material layer is greater than the work function of the nearest gate film layer in the gate.

6. A driving method for a flat panel detector according to any one of claims 1-5, characterized in that, Including: An imaging detection stage; wherein, the imaging detection stage includes: N consecutive row acquisition stages; wherein, N is the total number of rows of detection units in the flat panel detector; In the nth row acquisition stage, control the detection transistors in each of the detection units to be turned off, and obtain the imaging noise voltage corresponding to the photodiode in each of the detection units in the nth row; wherein, 1 ≤ n ≤ N, and n is an integer; Control the detection transistors in each of the detection units in the nth row to be turned on, and obtain the imaging detection voltage corresponding to the photodiode in each of the detection units in the nth row; According to the imaging noise voltage and the imaging detection voltage corresponding to the photodiodes in the nth row, determine the imaging effective voltage corresponding to the photodiodes in the nth row.

7. The driving method of the flat panel detector according to claim 6, wherein Before the imaging detection stage, it further includes: In the current reset stage, simultaneously control the detection transistors in each of the detection units to be turned on to reset the photodiodes in each of the detection units.

8. The driving method of the flat panel detector according to claim 7, wherein, After simultaneously controlling the detection transistors in each of the detection units to be turned on to reset the photodiodes in each of the detection units, the current reset stage further includes: Control the detection transistors in at least one row of the detection units to be turned on, and obtain the detection control voltage corresponding to the photodiode electrically connected to the turned-on detection transistor; Judge whether at least one of the obtained detection control voltages meets the voltage threshold; If so, enter the imaging detection stage; If not, enter the next reset stage.

9. The driving method of the flat panel detector according to claim 7 or 8, characterized in that, The maintaining duration of controlling one detection transistor to be turned on in the reset stage is the same as the maintaining duration of controlling one detection transistor to be turned on in the imaging detection stage.

10. A driving device for a flat panel detector, characterized in that, Including: A driving circuit; The driving circuit is configured to execute the driving method according to any one of claims 6-9.

11. A flat panel detection device, characterized in that, Comprising the flat panel detector according to any one of claims 1-5, and / or the driving device of the flat panel detector according to claim 10.

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