Enhance systems and methods for MMU TLBs used to translate virtual addresses to physical addresses.

Abstract

Process-specific memory translation lookaside buffers (TLBs) (mTLBs) for enhancing a memory management unit (MMU) TLB for translating virtual addresses (VAs) to physical addresses (PAs) in a processor-based system are disclosed. In the disclosed examples, a per-process specific on-chip TLB is supported in system memory such that a cached page table entry for one process does not displace a cached page table entry for another process. When a process is scheduled to execute in a central processing unit (CPU), the stored on-chip TLB address for the process can be used by a page table walker circuit in the CPU MMU to access the specific on-chip TLB for performing the process for performing a VA to PA translation when a TLB miss occurs in the MMU TLB. If the on-chip TLB experiences a TLB miss, the page table walker circuit can walk the page tables in the MMU.

Description

Technical Field

[0001] The technology disclosed herein relates to processor-based systems employing a central processing unit (CPU) (also referred to as a “processor”), and more specifically to a memory management unit (MMU) in a processor that includes a translation back buffer (TLB) and page tables accessed to provide translation of virtual addresses (VA) to physical addresses (PA). Background Technology

[0002] A microprocessor, also known as a "processor," performs computational tasks for a wide variety of applications. A traditional microprocessor includes one or more Central Processing Units (CPUs), also called processor cores. Processors are implemented in processor-based systems that include a memory system accessed to retrieve computer instructions executed by the processor to perform tasks. The memory system is also accessed to retrieve data used to execute the computer instructions. The results of the executed computer instructions can be stored as data in the memory system. The memory system includes main memory or system memory, which is located on-chip or off-chip with the processor and is configured to retrieve and store data associated with physical memory addresses, also known as physical addresses (PAs) provided by the processor. The memory system may also include a cache memory system, which includes one or more levels of cache memory (which is faster than system memory) and is configured to store data for a subset of the PAs that are accessed more frequently by the processor to improve memory access performance.

[0003] An operating system executing processes on a processor can be configured to use virtual memory as a virtual memory system. In a virtual memory system, each process is given the impression that there are more memory addresses available for retrieving and storing data than the physical address space (PA) in the memory system. For example, for a given process, each CPU in the processor might have a larger virtual address space (VA) that must be mapped into the memory system, ranging from a smaller PA space of 0x00000000 to 0x00FFFFFF and a larger VA space of 0x00000000 to 0x7FFFFFFF. When a process requests access to data in memory, it provides a memory address that is a virtual address (VA) based on the larger PA space. The VA must be mapped into the actual PA in the memory system where the data is stored or retrieved. In this respect, each CPU in the processor can contain a memory management unit (MMU), which is used to translate VAs to PAs. Most processor architectures support tables in memory called “page tables” used to map VAs to PAs. A page table is a data structure where each memory page contains a page table entry (PTE) to map the VA to the PA. Most page tables have multiple levels, depending on the base page size, the number of page table entries at each level, and the number of bits in the supported VA space.Figure 1 An example of a multi-level page table 100 is illustrated, comprising three (3) levels of hierarchical page tables 102(2)-102(0) configured to be accessed to transform VA 104 into PA. The hierarchical page tables 102(2)-102(0) are organized to provide a base page size of 4 kilobytes (KB), with 512 PTEs per page table level (i.e., addressable with 9 bits), supporting a 39-bit VA space. The top-level (second-level) page table 102(2) is located in the second level and is indexed by a second-level index in bits 38-30 of VA 104. Page table entries (entries 0-511) of the second-level page table 102(2) point to one of “X” first-level page tables 102(1)(0)-102(1)(X), which are then indexed by a first-level index in bits 29-21. Page table entries in the first hierarchical page table 102(1) point to one of the "Y" hierarchical page tables 102(0)(0)-102(0)(Y), which are then indexed by the level 0 index in bits 20-12 of VA104. In this example, page table entries accessed across hierarchical page tables 102(2)-102(0) in page table 100 identify the PA of a 4KB page in physical memory. In this example, the offset bit of the PA in VA 104 is the offset in VA 104 in bits 11-0.

[0004] MMUs typically provide a hardware page table traverser architecture to translate VAs to PAs. For a given VA, the page table traverser traverses the page table from top to bottom, level by level, until it finds a leaf PTE containing the PA for that VA. Page table traversal involves memory references at each page table level, which can be very time-consuming. To address this inefficiency of page table traversal, MMUs typically include a cache memory called a Translation Lookaside Buffer (TLB) to cache the latest VA-to-PA translations. In response to a memory address request that requires a VA-to-PA translation, the MMU first accesses the TLB based on the VA of the memory access request. If the VA-to-PA translation is not found in the TLB, a TLB miss occurs, and the MMU traverses the page table until it finds the VA-to-PA translation, then loads it into the TLB for future access. If the VA-to-PA translation is found in the TLB, this is a TLB hit, and a page table traversal is avoided. Therefore, the TLB hit rate is a critical part of the memory access performance of the memory system in a processor-based system.

[0005] When performing workloads on the CPU, multiple processes and the operating system kernel compete for entries in the TLB within the MMU. The MMU can use the Least Recently Used (LRU) algorithm to evict older entries from the TLB, as new entries are inserted into the TLB as a result of TLB misses and page table traversals. As workload pressure on memory increases, the TLB may begin to thrash, meaning that TLB misses and the resulting evictions and insertions occur frequently, degrading performance. At the MMU hardware level, there are two approaches to address this issue. One solution is to increase the size of the TLB to make TLB misses less frequent. The second solution is to provide a cache of intermediate page table pointers within the MMU. In this scenario, when a TLB miss occurs, the page table traverser searches for a matching intermediate page table in this cache of intermediate page table pointers. When a cache hit occurs, the page table traverser starts traversing from the matching intermediate page table instead of from the top-level page table, reducing the page table traversal time. However, each of these solutions increases the cost and complexity of the MMU hardware. Furthermore, these solutions may ultimately only delay the final TLB thrashing. This problem is further exacerbated in virtual environments. When guest virtual machines run on a host computer, the guest virtual machine has its own page table for translating guest VAs to guest PAs. The host computer also has its own page table for translating guest PAs to host PAs. Since memory can only be accessed by the CPU using the host PA, each guest PA must be translated by the CPU to its host PA. When the page table traverser traverses the guest page table, it needs to translate the guest PA to the host PA at each level of the guest page table in order to access the guest intermediate page table at that level. For guests running on nested hypervisors, the translation overhead can be even greater. Summary of the Invention

[0006] The aspects disclosed herein include, in processor-based systems, a process-specific translation lookahead buffer (mTLB) in memory used to enhance the Memory Management Unit (MMU) TLB for translating virtual addresses (VA) to physical addresses (PA). A processor-based system includes a processor having one or more central processing units (CPUs), each CPU configured to execute computer software instructions for a process. The processor-based system also includes a memory system comprising main physical memory addressable via PA. The processor is a virtual memory system that employs virtual addressing to make the available memory space greater than the amount of physical memory space in the main system memory of the processor-based system. In some examples, a shared or dedicated MMU is provided for each CPU for VA translation to PA. The MMU is associated with a system-in-memory TLB (“MMU TLB”) and page tables (which are memory circuits). System memory is memory addressable entirely by the PA space of the processor-based system. The MMU TLB is a cache memory associated with the MMU and is configured as a page table entry in the cache page table to avoid the need for a full traversal of the page table when the MMU TLB contains page table entries for VA to PA translations.

[0007] In the exemplary aspects disclosed herein, to enhance the MMU TLB to reduce the need to traverse page tables or perform full page table traversals to translate VA to PA, processor-based systems also support in-memory TLBs allocated in system memory. In this regard, in response to an MMU TLB miss for a VA-to-PA translation, the in-memory TLB is accessed to determine whether the page table entry for the VA-to-PA translation is contained in the in-memory TLB. If the page table entry for the VA-to-PA translation is contained in the in-memory TLB, the page table entry in the in-memory TLB is used to perform the VA-to-PA translation. In this way, additional page table entries for the VA-to-PA translation can be cached without expanding the size of the MMU TLB. The size of the in-memory TLB can be adjusted to provide a higher hit rate if desired. If the page table entry for the VA-to-PA translation is not contained in the in-memory TLB, the MMU traverses its page tables to perform the VA-to-PA translation.

[0008] In the examples disclosed herein, a dedicated in-memory TLB is supported in system memory for each process in the processor and is not shared across processes; therefore, a cache page table entry for one process does not supersede a cache page table entry for another process. In this regard, each CPU in the processor supports storing a pointer address to the in-memory TLB in system memory, allowing the MMU in the CPU to access the dedicated in-memory TLB corresponding to a specific process. In the examples disclosed herein, the dedicated in-memory TLB can also be supported for use by the operating system kernel and / or hypervisor that oversees the virtualization of guest processes executing on the host CPU. When a process is scheduled to execute in the CPU, the in-memory TLB address stored for that process can be loaded into the in-memory TLB register in the CPU. This allows the MMU's page table traverser circuitry to access the dedicated in-memory TLB for use by the executing process performing a VA to PA translation in the event of a TLB miss by the MMU. If an in-memory TLB miss occurs, the MMU's page table traverser circuitry can traverse the page table. Supporting a dedicated in-memory TLB for each process also allows different-sized in-memory TLBs to be allocated to different processes, if desired, for example, based on their memory access patterns and the number of process threads sharing the in-memory TLB. In another example, the in-memory TLB in system memory is directly memory-mapped to memory addresses, which can also simplify cache page table entry replacement strategies.

[0009] In other examples, the in-memory TLB can be configured to cache page table entries at different levels in the page table into the MMU TLB. In another example, the in-memory TLB can be configured to cache only certain levels of hierarchical page tables in the page table into the MMU TLB. For example, the in-memory TLB associated with a given MMU can be configured to cache page table entries from page tables at higher levels than those cached in the MMU TLB to improve performance. Therefore, if a TLB hit occurs on any cached non-leaf page table entry in the MMU TLB, the page table traverser circuitry will only need to traverse the lower-level page table to convert the VA to PA. If a TLB miss occurs in the MMU TLB, the page table traverser circuitry can query the in-memory TLB for the matching page table entry to convert the VA to PA.

[0010] In this regard, in one exemplary aspect, a memory management system in a CPU of a processor-based system is provided. The memory management system includes: page tables in the system memory of the processor-based system, the page tables including at least one hierarchical page table, each page table including multiple page table entries, each page table entry being addressable via a VA and configured to store a PA associated with the VA; an MMU TLB including multiple MMU TLB entries, each MMU TLB entry being configured to store cached page table entries in the page table; an in-memory TLB in the system memory, the in-memory TLB including multiple in-memory TLB entries, each in-memory TLB entry being configured to store cached page table entries in the page table; page table traversal circuitry configured to access multiple page table entries in at least one hierarchical page table in the page table based on the VA; and MMU circuitry. The MMU circuitry is configured to: receive a memory access request including a VA based on computer software instructions executed for a process in the CPU, and determine whether an MMU TLB entry in the MMU TLB contains a page table entry including a PA corresponding to the VA. In response to determining that the MMU TLB does not contain an MMU TLB entry containing a page table entry directly corresponding to the VA, the MMU circuitry is further configured to: determine whether the VA stored in the in-memory TLB entry corresponding to the VA in the in-memory TLB of a process allocated to the system memory of a processor-based system matches the VA of the memory access request, and in response to determining that the VA stored in the in-memory TLB entry matches the VA of the memory access request, convert the VA to a PA based on the page table entry accessed in the in-memory TLB entry corresponding to the VA.

[0011] In another exemplary aspect, a method is provided for translating a VA to a PA in a CPU of a processor-based system. The method includes: receiving a memory access request including a VA based on computer software instructions executed for a process in the CPU; and determining whether an MMU Translation Backing Buffer (TLB) entry in an MMU TLB comprising a plurality of MMU TLB entries contains a page table entry including a PA corresponding to the VA, each of the plurality of MMU TLB entries being configured to store a cached page table entry in a page table. The page table entry is included in a page table comprising at least one hierarchical page table, each hierarchical page table comprising a plurality of page table entries, each page table entry being addressable by the VA and configured to store the PA associated with the VA. In response to determining that the MMU TLB does not contain an MMU TLB entry containing a page table entry corresponding to the VA, the method further includes: determining whether the VA stored in an in-memory TLB entry corresponding to the VA in an in-memory TLB of the system memory of a process allocated in the system memory of the processor-based system matches the VA of the memory access request. In response to determining that a VA stored in an in-memory TLB entry matches a VA of a memory access request, the method further includes converting the VA to a PA based on the page table entry accessed in the in-memory TLB entry corresponding to the VA.

[0012] In another exemplary aspect, a processor-based system is provided. The processor-based system includes system memory and a processor, the processor including one or more CPUs, each CPU configured to execute computer instructions and one or more processes in an operating system software program. Each of the one or more CPUs includes a memory management system comprising: a page table in the system memory, the page table including a plurality of hierarchical page tables, each hierarchical page table including a plurality of page table entries, each page table entry being addressable via a VA and configured to store a PA associated with the VA; an MMU TLB including a plurality of MMU TLB entries, each MMU TLB entry being configured to store cached page table entries in the page table; an in-memory TLB in the system memory, the in-memory TLB including a plurality of in-memory TLB entries, each in-memory TLB entry being configured to store cached page table entries in the page table; page table traverser circuitry configured to access page table entries in at least one hierarchical page table in the page table based on the VA; and MMU circuitry. The MMU circuitry is configured to: receive a memory access request including a VA based on computer software instructions executed on one or more processes of one or more CPUs, and determine whether an MMUTLB entry in the MMU TLB contains a page table entry containing a PA corresponding to the VA. In response to determining that the MMU TLB does not contain an MMU TLB entry containing a page table entry corresponding to the VA, the MMU circuitry is further configured to: determine whether the VA stored in the in-memory TLB entry corresponding to the VA allocated to the process in system memory of the processor-based system matches the VA of the memory access request. In response to determining that the VA stored in the in-memory TLB entry matches the VA of the memory access request, the MMU circuitry is further configured to: convert the VA to a PA based on the fact that the accessed page table entry in the in-memory TLB entry corresponds to the VA.

[0013] After reading the following detailed description of preferred embodiments in conjunction with the accompanying drawings, those skilled in the art will understand the scope of this disclosure and implement its additional aspects. Attached Figure Description

[0014] The accompanying drawings, which are incorporated in and form part of this specification, illustrate several aspects of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0015] Figure 1 This is an example of a multi-level page table included in the processor's memory management unit (MMU) for translating virtual addresses (VA) into physical addresses (PA) in memory;

[0016] Figure 2This is a schematic diagram of an exemplary processor-based system, which includes a processor having multiple central processing units (CPUs), each CPU being configured to process instructions fetched from memory, including instructions for fetching data from memory and storing data into memory.

[0017] Figure 3 This is a schematic diagram of an exemplary memory management system, which includes at least one MMU provided in the CPU and system memory including an MMU translation back buffer (TLB) for translating VA to PA and page tables, wherein the memory management system is also configured to include a process-specific in-memory TLB in the system memory, which is configured to store cached page table entries in the page tables for translating VA to PA in the event of an MMU TLB miss.

[0018] Figure 4A The illustration shows an exemplary bit format of an exemplary VA, which can be... Figure 2 The CPU in the processor is used to address the memory system;

[0019] Figure 4B The diagram shows that it can be used Figure 3 The example page table provided in the MMU includes multiple hierarchical page tables, each containing page table entries that can be addressed via VA;

[0020] Figure 5A An exemplary in-memory TLB register is illustrated, which includes a memory address field configured to store a memory address pointing to an in-memory TLB in system memory;

[0021] Figure 5B The illustration shows an exemplary in-memory TLB entry in the system memory's in-memory TLB.

[0022] Figure 6 It is a diagram. Figure 3 A flowchart illustrating an exemplary process in which the MMU in the memory management system of the processor translates a VA into a PA and accesses the process-specific TLB in system memory to translate the VA into a PA.

[0023] Figure 7A and Figure 7B It contains leaf table entries and can be included. Figure 3 A schematic diagram of other multi-level page tables in the system memory of the memory management system used to convert VA to PA;

[0024] Figure 8 This is a schematic diagram of an exemplary in-memory TLB for caching entries from multi-level page tables;

[0025] Figure 9 This is a block diagram of an exemplary processor-based system, including a processor having one or more CPUs and a memory management system including at least one MMU provided in the CPU and a memory management system including an MMU TLB and page tables for VA to PA translation, wherein the memory management system is further configured to include process-specific in-memory TLBs in system memory, and the system memory is configured to store cached page table entries in the page tables for VA to PA translation in the event of an MMU TLB miss, including but not limited to... Figure 2 The processor and Figure 3 The memory management system in [the system]. Detailed Implementation

[0026] The aspects disclosed herein include, in processor-based systems, a process-specific translation lookahead buffer (mTLB) in memory used to enhance the Memory Management Unit (MMU) TLB for translating virtual addresses (VA) to physical addresses (PA). A processor-based system includes a processor having one or more central processing units (CPUs), each CPU configured to execute computer software instructions for a process. The processor-based system also includes a memory system comprising main physical memory addressable via PA. The processor is a virtual memory system that employs virtual addressing to make the available memory space greater than the amount of physical memory space in the main system memory of the processor-based system. In some examples, a shared or dedicated MMU is provided for each CPU for VA translation to PA. The MMU is associated with a system-in-memory TLB (“MMU TLB”) and page tables (which are memory circuits). System memory is memory addressable entirely by the PA space of the processor-based system. The MMU TLB is a cache memory associated with the MMU and is configured as a page table entry in the cache page table to avoid the need for a full traversal of the page table when the MMU TLB contains page table entries for VA to PA translations.

[0027] In the exemplary aspects disclosed herein, to enhance the MMU TLB to reduce the need to traverse page tables or perform full page table traversals to translate VA to PA, processor-based systems also support in-memory TLBs allocated in system memory. In this regard, in response to an MMU TLB miss for a VA-to-PA translation, the in-memory TLB is accessed to determine whether the page table entry for the VA-to-PA translation is contained in the in-memory TLB. If the page table entry for the VA-to-PA translation is contained in the in-memory TLB, the page table entry in the in-memory TLB is used to perform the VA-to-PA translation. In this way, additional page table entries for the VA-to-PA translation can be cached without expanding the size of the MMU TLB. The size of the in-memory TLB can be adjusted to provide a higher hit rate if desired. If the page table entry for the VA-to-PA translation is not contained in the in-memory TLB, the MMU traverses its page tables to perform the VA-to-PA translation.

[0028] In the examples disclosed herein, a dedicated in-memory TLB is supported in system memory for each process in the processor and is not shared across processes; therefore, a cache page table entry for one process does not supersede a cache page table entry for another process. In this regard, each CPU in the processor supports storing a pointer address to the in-memory TLB in system memory, allowing the MMU in the CPU to access the dedicated in-memory TLB corresponding to a specific process. In the examples disclosed herein, the dedicated in-memory TLB can also be supported for use by the operating system kernel and / or hypervisor that oversees the virtualization of guest processes executing on the host CPU. When a process is scheduled to execute in the CPU, the in-memory TLB address stored for that process can be loaded into the in-memory TLB register in the CPU. This allows the MMU's page table traverser circuitry to access the dedicated in-memory TLB for use by the executing process performing a VA to PA translation in the event of a TLB miss by the MMU. If a TLB miss occurs, the MMU's page table traverser circuitry can traverse the page table. Supporting a dedicated in-memory TLB for each process also allows different-sized in-memory TLBs to be allocated to different processes, if desired, for example, based on their memory access patterns and the number of process threads sharing the in-memory TLB. In another example, the in-memory TLB in system memory is directly memory-mapped to memory addresses, which can also simplify cache page table entry replacement strategies.

[0029] In other examples, the in-memory TLB can be configured to cache page table entries at different levels in the page table into the MMU TLB. In another example, the in-memory TLB can be configured to cache only hierarchical page table entries at certain levels in the page table into the MMU TLB. For example, the in-memory TLB associated with a given MMU can be configured to cache page table entries from page tables at higher levels than those cached in the MMU TLB to improve performance. Therefore, if a TLB hit occurs on any cached non-leaf page table entry in the MMU TLB, the page table traverser circuitry will only need to traverse the lower-level page table to convert the VA to PA. If a TLB miss occurs in the MMU TLB, the page table traverser circuitry can query the in-memory TLB for the matching page table entry to convert the VA to PA.

[0030] Before discussing examples of process-specific mTLBs used to enhance the MMU TLB for converting VA to PA in processor-based systems, let's first discuss... Figure 2 The discussion includes exemplary processor-based systems with one or more CPUs.

[0031] In this regard, Figure 2This is a diagram of an exemplary processor-based system 200 including processor 202, which is configured to issue memory requests (i.e., data read and data write requests) to a memory system 204 including cache memory 206 and system memory 208. System memory 208 is memory that can be fully addressed through the PA space of the processor-based system 200. For example, system memory 208 may be dynamic random access memory (DRAM) provided in a separate DRAM chip. Processor 202 includes one or more corresponding CPUs 210(0)-210(N), where “N” is a positive integer representing the number of CPUs included in processor 202. Processor 202 may be packaged in an integrated circuit (IC) chip 212. The cache memory system 206 includes one or more cache memories 214(1)-214(X) located at different levels in the processor-based system 200 and logically situated between the CPUs 210(0)-210(N) and the system memory 208, where “X” is a positive integer representing the number of CPUs included in the processor 202. The memory controller 216 controls access to the system memory 208. For example, the CPUs 210(0)-210(N), acting as requesting devices, can issue a data request 218 to read data in response to a processing load instruction. The data request 218 includes the target address of the data to be read from memory. Using CPU 210(0) as an example, if the requested data is not in the private cache memory 214(1) (i.e., a cache miss 214(1)), the private cache memory 214(1) can be considered as a first-level (L1) cache memory. In this example, the private cache memory 214(1) sends the data request 218 to the shared cache memory 214(X) shared with all CPUs 210(0)-210(N) via the interconnect bus 220. The shared cache memory 214(X) can be a third-level (3) cache memory. The requested data in the data request 218 is eventually completed either in the cache memory 214(1)-214(X) or in the system memory 208—if it is not included in any cache memory 214(1)-214(X).

[0032] Figure 2The processor-based system 200 is configured to support virtual addressing. In this respect, the operating system executing a process on processor 202 can use virtual memory as a virtual memory system by issuing VAs in memory access requests. In the virtual memory system, each process is given the impression that there are more memory addresses (i.e., VAs) available in memory system 204 for retrieving and storing data compared to the PAs in system memory 208. When a process requests access to data in memory system 204, the process provides a memory address, which is a VA. The VA must then be mapped to the actual PA in memory system 204 where the data is to be stored or retrieved. In this respect, Figure 2 Each CPU 210(0)-210(N) in processor 202 may include or have an associated MMU 222(0)-220(N) used to convert VA to PA.

[0033] Figure 3 This is a schematic diagram of an exemplary memory management system 300, which includes... Figure 2 The processor 202 includes an MMU circuit 302 associated with CPUs 210(0)-210(N) in the system memory 202, which translates VA to PA in response to memory access requests issued by the associated corresponding CPUs 210(0)-210(N). The memory management system 300 includes page tables 304 and an MMU TLB 306 in the system memory 208, which the MMU circuit 302 accesses to translate VA to PA. Page table 304 is a memory circuit that includes multiple page table entries 308(0)-308(E), which are indexable based on VA to provide information for translating from PA to VA. In response to a TLB miss and an in-memory TLB miss (discussed below), in response to a computer software instruction executed by the corresponding CPU 210(0)-210(N) to determine whether there is a page table entry 308(0)-308(E) containing information to convert VA to PA, page table 304 is accessed or “traversed” by page table traverser circuit 309 in MMU circuit 302 based on the incoming VA. If so, a “page table hit” 310 is issued by page table 304, and MMU circuit 302 provides the PA for the memory access request to MMU TLB 306. The converted PA is also written to MMU TLB 306 as a “TLB write” 312. If page table entries 308(0)-308(E) in page table 304 do not contain information to convert VA to PA, page table 304 issues a “page table miss” 314, and a memory management fault and trap occurs or an exception is delivered to the operating system for handling. Page table 304 may include multiple page table levels that must be "traversed" by page table traverser circuit 309 to convert incoming VA to PA.

[0034] To improve the performance of converting VA to PA, the VA converted by accessing page table 304 and the PA information generated by the issued "page table hit" 310 are also cached (i.e., written) in MMU TLB 306. MMU TLB 306 is a cache memory, which in this example is a faster memory than page table 304. MMU TLB 306 has multiple MMU TLB entries 318(0)-318(T), each configured to store the PA associated with a given VA. The VA stored in MMU TLB entries 318(0)-318(T) is a tag that can be compared with the incoming VA in the received memory access request before accessing page table 304 to determine whether any MMU TLB entries 318(0)-318(T) with the converted PA exist in MMU TLB 306. If so, a "TLB Hits" 320 is issued by MMU TLB 306 without traversing page table 304, and MMU circuit 302 provides the PA in the hit MMU TLB entries 318(0)-318(T) for the memory access request. If the incoming VA in the received memory access request does not exist in any MMU TLB entries 318(0)-318(T) in MMU TLB 306, a "TLB Miss" 322 is issued, and the VA can be used to traverse page table 304 to convert the incoming VA to PA, as described above.

[0035] When the workload is Figure 2 When executing on CPUs 210(0)-210(N) in processor 202, multiple processes and the operating system kernel compete for access to the MMU TLB 306. As workload pressure on memory system 204 increases, the MMU TLB 306 may begin to thrash, meaning that TLB misses and the resulting evictions and insertions occur frequently, which degrades performance. In the exemplary aspects disclosed herein, in order to enhance the MMU TLB 306 to reduce the number of page table 304 traversals for converting VA to PA, Figure 3The memory management system 300 also supports in-memory TLBs 324(0)-324(I) allocated in system memory 208. In response to a TLB miss on MMU TLB 306 for a VA to PA translation, in-memory TLBs 324(0)-324(I) can be accessed to determine if a page table entry exists in the in-memory TLB entry of the accessed in-memory TLB 324(0)-324(I) to translate the VA to its PA. Each in-memory TLB 324(0)-324(I) contains multiple in-memory TLB entries 326(0)(0)-326(I)(B), each of which is configured to cache page table entries 308(0)-308(E) in page table 304. If page table entries 308(0)-308(E) used for VA to PA translation are included in in-memory TLB entries 326(0)(0)-326(I)(B) in the accessed in-memory TLBs 324(0)-324(I), then such page table entries 308(0)-308(E) in the accessed in-memory TLBs 324(0)-324(I) are used to perform VA to PA translation. In this way, additional page table entries used for VA to PA translation can be cached without expanding the size of the MMU TLB 306. For a given memory size, the more abundant and cheaper system memory 208 is allocated to in-memory TLBs 324(0)-324(I). If the page table entry used for the VA to PA conversion is not included in the memory TLB 324(0)-324(I) accessed by the part, then the MMU circuit 302 causes the page table traverser circuit 309 to traverse the page table 304 as previously discussed above to perform the VA to PA conversion.

[0036] This will be discussed in more detail below. Figure 3 The memory management system 300 is configured to support each in-memory TLB 324(0)-324(I) in the allocated system memory 208, dedicated to a specific process executing on CPUs 210(0)-210(N) and therefore not shared between different processes. For example, in-memory TLB 324(0) is dedicated to one process executing on CPUs 210(0)-210(N), while in-memory TLB 324(X) is assigned to different processes executing on CPUs 210(0)-210(N). In this respect, Figure 2Each CPU 210(00-210(N)) in processor 202 supports storing the address of in-memory TLB 324(0)-324(I) in system memory 208 allocated to the corresponding process, such that page table entries in in-memory TLB entries 326(0)(0)-326(0)(B) cached in in-memory TLB 324(0) do not supersede page table entries in in-memory TLB entries 326(0)(0)-326(0)(B) in in-memory TLB 324(I). In this way, in-memory TLB 324(0)-324(I) is not shared across processes. In-memory TLB 324(0)-324(I) can be shared among multiple CPUs 210(0)-210(N) because multiple CPUs 210(0)-210(N) can execute the same process. As an example, a dedicated in-memory TLB can also be supported for monitoring on the host CPU. The operating system kernel and / or hypervisor in the virtualized processor 202 of the client processes executing on 210(0)-210(N).

[0037] When a process is scheduled to execute in CPUs 210(0)-210(N), the in-memory TLB address stored for that process can be loaded into the MMU circuitry 302 associated with CPUs 210(0)-210(N). This allows the MMU circuitry 302 to access dedicated in-memory TLBs 324(0)-324(I) for executing a process performing a VA-to-PA translation in the event of a TLB miss at MMU TLB 306 and a TLB hit at in-memory TLBs 324(0)-324(I). This avoids the need for page table traverser circuitry 309 to traverse page table 304. If a miss occurs at in-memory TLBs 324(0)-324(I) for the executed process, then page table traverser circuitry 309 can traverse page table 304 as previously discussed. If desired, the memory management system 300, which supports process-specific in-memory TLBs 324(0)-324(I), can also allow different sizes of in-memory TLBs 324(0)-324(I) to be allocated to different processes. As an example, it might be desirable to provide different sizes of in-memory TLBs 324(0)-324(I) based on the memory access patterns of the respective processes and the number of process threads sharing the in-memory TLBs 324(0)-324(I). In another example, the in-memory TLBs 324(0)-324(I) located in system memory 208 allow the in-memory TLBs 324(0)-324(I) to be directly memory-mapped to memory addresses, which can also simplify cache page table entry replacement strategies. The examples discussed below explain this in more detail... Figure 3The operation of an MMU circuit such as MMU circuit 302 in CPU 210(0) accesses the memory TLB 324(0)-324(I)-210(N) of a given process executing in CPU 210(0) to convert the VA in a memory access request issued as a result of the execution of the process into PA.

[0038] In this non-restrictive example, by Figure 2 The processor-based System 200 supports 64-bit VA memory addresses. In this respect, Figure 4A The illustration shows an exemplary bit format of an exemplary VA 400 supported by a processor-based system 200, illustrating bit assignment of bits 63-0. Bits 63-48 are free bits, which are unused or can be reserved for additional functionality. The address space of the VA 400 is 48 bits, spanning bits 47-0, for supporting 2D operations in a processor-based system. 48 One virtual memory location. Bits of the VA 400 can be used to index the page table, which can be used as... Figure 3 Page table 304 in the memory management system 300. Figure 4B The diagram shows that it can be used Figure 3 An exemplary page table 402 is provided in the MMU circuit 302, wherein page table 402 includes four (4) levels of hierarchical page tables 404(3)-404(0), each level containing page table entries addressable by VA400. Each page table entry in the hierarchical page tables 404(3)-404(0) is either a leaf page table entry or a non-leaf page table entry. Leaf page table entries are not used to further access another page table entry and can be directly associated with a memory page in the physical memory of system memory 208, while non-leaf page table entries are used to further access another page table entry to obtain the PA of a memory page in system memory 208 and can be cached in this example.

[0039] Continue to refer to Figure 4B The hierarchical page tables 404(3)-404(0) in page table 402 are organized to provide a basic page size of 4 kilobytes (KB), with 512 page table entries in each hierarchical page table 404(3)-404(0) (i.e., addressable with 9 bits), supporting a 39-bit VA 400 address space. In this example, hierarchical page table 404(3) contains page table entries 408(3)(0)-408(3)(511) and is designed not to be cached. Figure 3 The TLB 324(0)-324(I) is in memory. The second-level page table 404(2) is in the second level in page table 402 and is indexed by the second-level index 406(2) in bits 38-30 of VA 400. The page table entries of the second-level page table 404(2) are 512 or 29 Each of the entries 408(2)(0)-408(2)(511) points to one of the “X” first hierarchical page tables 404(1)(0)-404(X), which is then indexed by the first hierarchical index 406(1) in bits 29-21 of VA 400. The page table entries (512 or 2) of the first hierarchical page tables in each of the first hierarchical page tables 404(1)(0)-404(1)(X) are... 9 The entries 408(1)(0)(0)-408(1)(X)(511) (i.e., the number of entries 0-X in the first hierarchical page table at level (1), and the number of entries 0-511 in each hierarchical page table) point to one of the 0th hierarchical page tables 404(0)(0)-404(0)(Y), which is then indexed by the 0th level index 406(0) in bits 20-12 of VA 400. In this example, the page table entries 408 accessed by the hierarchical page tables 404(2), 404(1)(0)-404(1)(X), and 404(0)(0)-404(0)(Y) in the page table 402 are identified. Figure 2 The 4KB page PA in system memory 208 of the processor-based system 200. The offset bit of PA in VA 104 is the offset in VA 400, which in this example is in bits 11-0 of VA 400.

[0040] As an example, which will be discussed in more detail below, Figure 3 The memory management system 300 can be configured to cache hierarchical page tables 404(2), 404(1)(0)-404(1)(X), and 404(0)(0)-404(0)(Y) at different levels in different memory structures. For example, page table entries 408(2)(0)-408(2)(511) of the second hierarchical page table 404(2) can be cached in the in-memory TLB 324(0)-324(I), while page table entries 408(1)(0)(0)-408(1)(X)(511) of the first hierarchical page table 404(1)(0)-404(1)(X) can be cached in the memory TLB 324(0)-324(I). Figure 3 In the MMU circuit 302, in the MMU TLB 306. Page table entries 408(0)(0)(0)-408(0)(Y)(511)(0)-404(0)(Y) in the 0th level page table 404(0) are leaf page table entries that can be cached in the MMU TLB 306.

[0041] As discussed above, it is possible to... Figure 2 Each process executed in the CPUs 210(0)-210(N) of the processor 202 provides Figure 3The memory management system 300 contains dedicated in-memory TLBs 324(0)-324(I). Therefore, in this example, when a process's thread is scheduled to execute on CPUs 210(0)-210(N) in processor 202, a mechanism is provided to indicate that a specific in-memory TLB 324(0)-324(I) is allocated to that process in system memory 208, so that MMU circuitry 302 can know where in system memory 208 to access the in-memory TLB 324(0)-324(I) dedicated to that process. In this regard, CPUs 210(0)-210(N) 3 may include in-memory TLB registers containing memory address fields 324(0)-324(I) configured to store a memory address pointing to a PA in system memory 208 into the in-memory TLB corresponding to the currently executing process in CPUs 210(0)-210(N). An example of this in-memory TLB register 500 is... Figure 5A The diagram is shown in the image. Figure 5A As shown, the in-memory TLB register 500 includes a memory address field 502 configured to store the physical address of the in-memory TLB 324(0)-324(I) corresponding to the currently executing process on CPU 210(0)-210(N). For a host, such as a host management program, running directly on CPU 210(0)-210(N), the memory address field 502 can be the host PA. For a client running directly on CPU 210(0)-210(N), the memory address field 502 can be the client PA. Also in this example, the in-memory TLB register 500 includes a TLB entry count field 504 configured to store the number of in-memory TLB entries 326(0)(0)-324(I)(B) in the included in-memory TLB 324(0)-324(I). This allows in-memory TLBs 324(0)-324(I) to know the size of the number of in-memory TLB entries 326(0)(0)-324(I)(B) allocated in in-memory TLBs 324(0)-324(I) identified by the memory address in memory address field 502. In this example, the in-memory TLB register 500 also includes a cache level field 506 in the page table, configured to store a number indicating which level in the hierarchical page table 404 of page table 402 in Figure 4 is cached in in-memory TLBs 324(0)-324(I) identified in memory address field 502. Also in this example, the in-memory TLB register 500 includes a cache level field 508 in the MMU TLB, configured to store a number indicating which level in the hierarchical page table 404 of page table 402 is cached in MMU TLB 306.

[0042] Figure 5B The illustration shows an exemplary in-memory TLB entry 326, which, as an example, represents... Figure 3 The architecture of in-memory TLB entries 326(0)(0)-326(I)(B) in in-memory TLBs 324(0)-324(I) is shown. As illustrated, in-memory TLB entry 326 includes a leaf or non-leaf page table entry cache field 510, which is configured to store leaf or non-leaf page table entries in in-memory TLB entry 326. In-memory TLB entry 326 also includes a lock indicator 512, which is configured to store a lock state when in-memory TLB entry 326 is in a locked or unlocked state. For example, a "0" bit can indicate an unlocked state, while a "1" bit can indicate a locked state. As discussed below, the lock indicator 512 can be edited by the MMU circuitry 302 to indicate whether a given in-memory TLB entry 326 in in-memory TLBs 324(0)-324(I) is being used, in case two page table traversers are configured to compete for access to read or write the same in-memory TLB entry 326 in in-memory TLBs 324(0)-324(I). The in-memory TLB entry 326 also includes a VA tag field 514, which is configured to store the VA corresponding to the in-memory TLB entry 326. The MMU circuitry 302 can use this VA to compare with an incoming VA to be converted to a PA to determine whether the in-memory TLB entry 326 is suitable for converting a VA to its PA. In this example, the in-memory TLB entry 326 also includes a generation number field 516 configured to store a generation number. As will be discussed in more detail below, the generation number stored in the generation number field 516 may be used to determine whether the in-memory TLB entry 326 is valid and to provide a method for invalidating the in-memory TLB entry 326.

[0043] Figure 6 It's a diagram. Figure 3 A flowchart of an exemplary process 600 of the MMU circuit 302 in the memory management system 300, which converts VA to PA and accesses process-specific in-memory TLBs 324(0)-324(I) in system memory 208 to convert VA to PA. Combined with Figure 3 The memory management system 300 and Figure 4B Let's discuss this using page 402. Figure 6In process 600, the MMU circuit 302 receives a memory access request for VA 400 based on computer software instructions executed for the processes in CPUs 210(0)-210(N) (block 602). The MMU circuit 302 determines whether the MMU TLB 306 contains MMU TLB entries 318(0)-318(T) that contain page table entries corresponding to VA 400 (block 604). If MMU TLB 306 contains an MMU TLB entry 318(0)-318(T) that contains a page table entry corresponding to VA 400 (block 604), then this is an MMU TLB hit, and MMU circuit 302 uses the PA stored in the MMU TLB entry 318(0)-318(T) corresponding to VA 400 to convert VA 400 into its PA (block 606), and the process ends (block 616). However, if MMU TLB 306 does not contain MMU TLB entries 318(0)-318(T) (block 604) containing the page table entry corresponding to VA 400, this is an MMU TLB miss, and MMU circuit 302 then determines whether VA 400 in the VA tag field 514 of the in-memory TLB entries 326(0)(0))-324(I)(B) stored in the in-memory TLBs 324(0)-324(I) allocated to the process matches VA 400 of the memory access request (block 608). As discussed above, MMU circuit 302 can use the memory address in the memory address field 502 of the in-memory TLB register 500 to access the corresponding in-memory TLBs 324(0)-324(I) for the process.

[0044] If the VA in the VA tag field 514 of the in-memory TLB entries 326(0)(0)-326(I)(B) in the in-memory TLBs 324(0)-324(I) allocated to the process matches the VA 400 of the memory access request, then the MMU circuit 302 uses the contents of the matching in-memory TLB entries 326(0)(0)-326(I)(B) (block 608). This is an in-memory TLB hit. If the in-memory TLB entries 326(0)(0)-326(I)(B) contain a leaf table entry, then the MMU circuit 302 converts VA 400 to PA based on the fact that the accessed page table entry in the in-memory TLB entries 326(0)(0)-326(I)(B) has a VA in the VA tag field 514 that matches VA 400 (block 610). If in-memory TLB entries 326(0)(0)-326(I)(B) contain non-leaf page table entries, then page table traverser circuit 309 uses the non-leaf page table entries to traverse page table 304. Otherwise, for an in-memory TLB miss, if the VA in the VA tag field 514 of in-memory TLB entries 326(0)(0)-324(I)(B) stored in in-memory TLBs 324(0)-324(I) allocated to the process does not match the VA 400 of the memory access request (block 608), this is an in-memory TLB miss, and MMU circuit 302 performs a page table traversal. MMU circuit 302 causes page table traverser circuit 309 to access hierarchical page tables 404(3)-404(0) in page table 402 indexed by memory access request VA 400 (block 612) and convert VA 400 into PA contained in page table entries in hierarchical page tables 404(3)-404(0) corresponding to VA 400 (block 614), and the process ends (block 616).

[0045] As an example, suppose we can... Figure 4B The basic page size determined in page table 402 is 4KB, and each intermediate hierarchical page table 404(3)-404(0) has 512 entries. It is also assumed that... Figure 5AThe in-memory TLB register 500, discussed in this paper, for in-memory TLBs 324(0)-324(I) has its memory address in system memory 208 in its memory address field 502, 256 TLB entries in the TLB entry count field 504, a cache level of level 2 in in-memory TLBs 324(0)-324(I) in the cache level field 506 (bitmap represented as "100"), and a cache level of level 1 in MMU TLB 306 in the cache level field 508 (bitmap represented as "010"). In this example, level 0 leaf page table entries 408(0)(0)(0)-408(0)(Y)(511) in level 0 page tables 404(0)(0)-404(0)(Y) point to 4KB memory pages. The first-level leaf page table entries 408(1)(0)(0)-408(1)(0)(511) in the first-level page table 404(1)(0)-404(1)(X) point to a 2MB memory page. The second-level leaf page table entries 408(2)(0)(0)-408(2)(0)(511) in the second-level page table 404(2)(0)-404(2)(511) point to a 1 gigabyte (GB) memory page. The first-level non-leaf page table entries 408(1)(0)(0)-408(1)(0)(511) in the first-level page table 404(1)(0)-404(1)(X) point to the zero-level page table 404(0)(0)-404(0)(Y). The second-level non-leaf page table entries 408(2)(0)-408(2)(511) in the second-level page tables 404(2)(0)-404(2)(511) point to the first-level page tables 404(1)(0)-404(1)(X). In this example, leaf page table entries can always be cached in MMU TLB 306, non-leaf page table entries 408(1)(0)(0)-408(1)(0)(511) can be cached in MMUTLB 306, and leaf and non-leaf second-level page table entries 408(2)(0)-408(2)(511) can be cached in in-memory TLB 324(0)-324(I).

[0046] In this example, the span of a single in-memory TLB entry 326(0)(0)-326(I)(B) is 1GB. For a given incoming VA 400 to be converted to PA, MMU circuit 302 calculates the index into in-memory TLB 324(0)-324(I) for the current process of VA 400 as follows. This index is (VA / 1GB)%256. If an in-memory TLB miss occurs (e.g., Figure 6If the page table traverser circuit 309 traverses the page table 402 from the top level (block 608) and finds the leaf page table entry 408 for VA 400, then the leaf page table entry 408 is written to the MMU TLB 306. If the leaf page table entry 408 corresponding to VA 400 is higher than the second-level page table 404(2), no further caching is performed. If the leaf page table entry 408 corresponding to VA 400 is located in the second-level page table 404(2), it is cached in the memory TLB 324(0)-324(I) and the MMU TLB 306. If the leaf page table entry 408 corresponding to VA 400 is in page table 404(1) or 404(0) of level 1 or level 0, then the non-leaf page table entry 408 in page table 404(2) of level 2 is cached in in-memory TLB 324(0)-324(I) and MMU TLB 306. When page table entry 408 is cached in in-memory TLB 324(0)-324(I) as in-memory TLB entry 326(0)(0)-326(I)(B), the VA bit of VA 400 is truncated to the 1GB boundary and stored in the VA tag field 514 of in-memory TLB entry 326(0)(0)-326(I)(B). The current generation number, which will be discussed in more detail below, is stored in the generation number field 516 of in-memory TLB entry 326(0)(0)-326(I)(B). In this way, it is possible to precisely control which page table levels are cached in the MMU TLB 306 for the current process and are cached in in-memory TLB entries 326(0)(0)-326(I)(B).

[0047] As discussed above, when an MMU TLB hit occurs (e.g., in...) Figure 6 In block 606 of the MMU TLB, this means that a leaf page table entry 408 for VA 400 has been found in MMU TLB 306, and page table traversal of page table 402 is not required. If leaf page table entry 408 has been evicted from MMU TLB 306, but a first-level page table entry still exists in MMU TLB 306, then page table traverser circuit 309 can traverse page table 402 starting from first-level page table entry 408. If no first-level page table entry is found in MMU TLB 306, then MMU circuit 302 queries in-memory TLBs 324(0)-324(I) for the current process. If an in-memory TLB hit occurs, then MMU circuit 302 traverses from the second-level page table entries stored in in-memory TLBs 324(0)-324(I).

[0048] The MMU circuit 302 converts VA 400 to PA. Figure 6Additional functions and variations of process 600 can be executed. For example, in response to an MMU TLB miss (e.g., Figure 6 In block 604), MMU circuit 302 can be configured to read the VA in the VA tag field 514 of the in-memory TLB entry 326(0)(0)-324(I)(B) of the accessed in-memory TLB 324(0)-324(I). If the lock indicator 512 in the in-memory TLB entry 326(0)(0)-324(I)(B) indicates a locked state, this means that another process is using the same in-memory TLB entry 326(0)(0)-324(I)(B), and this is considered an in-memory TLB miss to perform page table 402 traversal (e.g., Figure 6 (blocks 612 and 614 in the memory). However, if the lock indicator 512 in the in-memory TLB entries 326(0)(0)-324(I)(B) indicates an unlocked state, the MMU circuit 302 can set the lock indicator 512 to a locked state. For example, a compare and swap (CAS) instruction can be executed on the VA tag field 514 in the accessed in-memory TLB entries 326(0)(0)-324(I)(B) to set its lock indicator 512 to a locked state. If the CAS instruction fails, this is considered an in-memory TLB miss to perform a page table 402 traversal (e.g., Figure 6 (Blocks 612 and 614 in the middle).

[0049] MMU circuit 302 can then check the VA in the VA tag field 514 of the accessed memory TLB entries 326(0)(0)-324(I)(B) in the locked state (e.g., in...). Figure 6 In block 608, it determines whether the VA in the VA tag field 514 matches the VA 400 of the memory access request. If they do not match (e.g., from...), Figure 6 If the path to block 608 is not found, then this is considered a memory TLB miss, and proceed to block 612 to perform a page table 402 traversal (e.g., ...). Figure 6 (Blocks 612 and 614 in the memory). The lock indicator 512 of the accessed memory TLB entries 326(0)(0)-324(I)(B) is set to the unlocked state. However, if the VA in the VA tag field 514 of the accessed memory TLB entries 326(0)(0)-324(I)(B) in the locked state matches the VA 400 of the memory access request (e.g., from...). Figure 6If block 608 is the path, then MMU circuit 302 can check the generation number in generation number field 516 of in-memory TLB entries 326(0)(0)-324(I)(B) to determine if the generation number is stale. As will be discussed in more detail below, one method to invalidate stale in-memory TLB entries 326(0)(0)-324(I)(B) is, for example, if the VA to PA mapping has not changed in the operating system, update the generation number in generation number field 516 of in-memory TLB entries 326(0)(0)-326(I)(B) to invalidate them, so that their generation number is not current. Stale in-memory TLB entries 326(0)(0)-326(I)(B) are considered in-memory TLB misses. However, if the VA in the VA tag field 514 of the accessed in-memory TLB entry 326(0)(0)-326(I)(B) in the locked state in block 608 matches the VA 400 of the memory access request, and the generation number in the generation number field 516 of the accessed in-memory TLB entry 326(0)(0)-326(I)(B) is not stale, then the in-memory TLB entry 326(0)(0)-326(I)(B) can be read and used to convert VA 400 into PA from the second hierarchical page table 404(2), and then used as the start PA to traverse page table 304 (e.g., Figure 6 Block 610 in the MMU TLB). PA is also written back to MMU TLB entries 318(0)-318(T) in MMU TLB 306, and the process ends (e.g., Figure 6 (Block 616 in the middle).

[0050] If an MMU TLB miss and an in-memory TLB miss occur (e.g., from...), Figure 6 If the paths to blocks 604 and 608 are not valid, then page table traverser circuit 309 traverses page table 402, as previously discussed (e.g., ...). Figure 6 (Blocks 612 and 614 in the table). If page table entry 408 found on page table 402 for VA 400 does not need to be cached in in-memory TLB entries 326(0)(0)-326(I)(B), then the process ends (e.g., Figure 6(Block 616 in the memory). Otherwise, unless already locked, the lock indicator 512 in the in-memory TLB entries 326(0)(0)-326(I)(B) is set. If not already locked, the VA in the VA tag field 514 of the available in-memory TLB entries 326(0)(0)-326(I)(B) is set to a new VA value from the instruction being executed (which includes memory accesses found from the traversal of page table 402) and the lock indicator 512 is set to locked by executing a CAS instruction on the VA tag field 514. If the CAS instruction fails, the process ends (e.g., Figure 6 (Block 616 in the memory). Otherwise, the current generation number is written to the generation number field 516 of the in-memory TLB entries 326(0)(0)-326(I)(B), and the page table entry 408 found from the traversal of page table 402 is written to the in-memory TLB entries 326(0)(0)-326(I)(B). Then the lock indicator 512 is reset to the unlocked state. Memory barriers may be required during these steps to ensure that updates are viewed in the correct order.

[0051] If the lock indicator 512 in in-memory TLB entries 326(0)(0)-326(I)(B) indicates a locked state, this means that another process is editing the same in-memory TLB entries 326(0)(0)-326(I)(B), and this is considered an in-memory TLB miss to perform a page table 402 traversal (e.g., Figure 6 (Blocks 612 and 614 in the code). This process ends (block 616) because the page table traversal of page table 304 has been completed at this point.

[0052] Other organization of the page table can be used as Figure 3 Page table 304 in the MMU circuit 302. For example, Figure 7A Another example of a multi-level page table 700 is illustrated, which can be included as page table 304. Figure 3The MMU circuit 302 converts VA 400 into a pointer to a 2MB physical memory page. For example, a three-level hierarchical page table 702(3)-702(1) is provided. The following caching scheme can be used. Page table entries 704(1)(0)-704(1)(511) in the first hierarchical page table 702(1) can be leaf page table entries that are always cached in the MMU TLB 306. Page table entries 704(2)(0)-704(2)(511) in the second hierarchical page table 702(2) are cached in the in-memory TLB 324(0)-324(I). Page table entries 704(3)(0)-704(3)(511) in the third-level page table 702(3) are at a higher level than page table entries in the in-memory TLB entries 326(0)(0)-326(I)(B) cached in the in-memory TLB 324(0)-324(I), and therefore page table entries 704(3)(0)-704(3)(511) are not cached.

[0053] Figure 7B Another example of a multi-level page table 705 is illustrated, which can be included as page table 304. Figure 3 The MMU circuit 302 converts VA 400 into a page pointing to 1GB of physical memory. For example, a two-level hierarchical page table 706(3)-706(2) is provided. The following caching scheme can be used. Leaf page table entries 708(2)(0)-708(2)(511) in the second hierarchical page table 706(2) are always cached in the MMU TLB 306. Leaf page table entries 708(2)(0)-708(2)(511) in the second hierarchical page table 706(2) are cached in the in-memory TLB 324(0)-324(I). Page table entries 708(3)(0)-708(3)(511) in the third-level page table 706(3) are at a higher level than page table entries 326(0)(0)-326(I)(B) in the in-memory TLB 324(0)-324(I), therefore page table entries 708(3)(0)-708(3)(511) are not cached.

[0054] If the cache page table level field 506 in the in-memory TLB register 500 in Figure 5 specifies that more than one page level should be cached in the identified in-memory TLBs 324(0)-324(I), then the in-memory TLBs 324(0)-324(I) can... Figure 2In the processor-based system 200, the system memory 208 is split or divided into multiple parts such that VA is mapped to the split in-memory TLB entries 326(0)(0)-326(I)(B). When the in-memory TLBs 324(0)-324(I) are split into multiple levels, the MMU circuit 302 needs to perform a search from lowest to highest or in parallel within each level of the in-memory TLBs 324(0)-324(I). This is in Figure 8 The example is shown below. Figure 8 As shown, a 512-entry in-memory TLB 324 can be split into corresponding top and bottom in-memory TLBs 324(T) and 324(B), each with 256 in-memory TLB entries 326(0)-326(255) and 326(256)-326(511). For example, a first hierarchical page table entry can be cached in the top in-memory TLB 324(T), while a second hierarchical page table entry can be cached in the bottom in-memory TLB 324(B). In the event of an MMU TLB miss for MMU TLB 306, MMU circuit 302 will first search for a matching first hierarchical page table entry in the in-memory TLB entries 326(0)-326(255) of the top in-memory TLB 324(T). If no match is found, the MMU circuit 302 will then search for a matching second hierarchical page table entry in the in-memory TLB entries 326(256)-326(511) in the bottom in-memory TLB 324(B).

[0055] It may also be necessary or desirable to provide a mechanism to invalidate MMU TLB entries 318(0)-318(T) in MMU TLB 306 and in-memory TLB entries 326(0)(0)-326(I)(B) in in-memory TLB 324(0)-324(I) (when they are no longer valid) so that incorrect VA to PA translations are not performed. For example, when in Figure 2When the operating system kernel executing in CPUs 210(0)-210(N) of processor 202 performs an operation to change the VA to PA mapping in system memory 208, the VA to PA mapping may change. For example, the operating system kernel may perform functions that change the VA to PA mapping, such as unmapping, remapping, permission changes, protection changes, and other miscellaneous changes. Essentially, when the attributes of the VA to PA mapping change, it may be necessary to invalidate MMU TLB entries 318(0)-318(T) in MMU TLB 306 and / or in-memory TLB entries 326(0)(0)-326(I)(B) in in-memory TLB 324(0)-324(I). In-memory TLBs 324(0)-324(I) are extensions of MMUTLB 306, and therefore any invalidation of MMU TLB entries 318(0)-318(T) will also need to be performed on in-memory TLB entries 326(0)(0)-326(I)(B) in MMU TLB 306.

[0056] For example, Figure 3 The MMU circuit 302 can receive a failure indicator for the executing process and / or, for example, from the operating system kernel to request the failure of a TLB entry. This is an internal failure request because the failure request is initiated from the process of the CPU 210(0)-210(N) with MMU circuit 302 and / or the operating system kernel. In response to receiving a failure indicator for a process, MMU circuit 302 can be configured to flush one or more in-memory TLB entries 326(0)(0)-326(I)(B) of in-memory TLBs 324(0)-324(I) allocated to that process based on any VA-PA remapping.

[0057] As another example, with Figure 2 Take, for example, the case where a process is executing on the operating system kernel of CPUs 210(0)-210(N) in processor 202. This process has assigned in-memory TLBs 324(0)-324(I), as previously discussed. A pointer to the memory address of in-memory TLBs 324(0)-324(I) in system memory 208 is stored in... Figure 5AIn the in-memory TLB register 500, as previously discussed. When the process's thread is context-switched to CPU 210(0)-210(N), the memory addresses of in-memory TLBs 324(0)-324(I) in system memory 208 are loaded into in-memory TLB register 500 so that MMU circuit 302 and its page table traverser circuit 309 can access in-memory TLBs 324(0)-324(I) for performing VA to PA translation in the event of a TLB miss on MMU TLB 306. For this example, assume that the operating system kernel unmaps the memory address range from the memory address space addressed by the process. This means that page table entries in the unmapped address range of in-memory TLB entries 326(0)(0)-326(I)(B) stored in in-memory TLBs 324(0)-324(I) may now become invalid. Several scenarios are possible. For example, if these page table entries affected by the unmapping are cached in MMU TLB entries 318(0)-318(T) for the process, and are leaf or non-leaf page table entries, then MMU TLB entries 318(0)-318(T) in MMU TLB 306 can be flushed without flushing in-memory TLB entries 326(0)(0)-326(I)(B) in in-memory TLB 324(0)-324(I). However, if these page table entries affected by the unmapping are cached in in-memory TLB entries 326(0)(0)-326(I)(B) for the process, then these page table entries in in-memory TLB entries 326(0)(0)-326(I)(B) in in-memory TLB 324(0)-324(I) are flushed to invalidate them. Failure may involve a process that simply writes a "0" to in-memory TLB entries 326(0)(0)-326(I)(B) to invalidate it. Additionally, the VA tag field 514 in in-memory TLB entries 326(0)(0)-326(I)(B) can be written with a 0 as a way to invalidate page table entries in in-memory TLB entries 326(0)(0)-326(I)(B). If the unmapped page table entry is at a higher level than the page table entries cached in in-memory TLB 324(0)-324(I) for that process, this means there may be page table entries cached from lower table circuit levels in in-memory TLB 324(0)-324(I) that are overwritten by the affected page table entry. In this case, all of these page table entries in in-memory TLB 324(0)-324(I) will be invalidated. As an option, the operating system kernel can perform a failure by directly writing to the page table entries in the in-memory TLB entries 326(0)(0)-326(I)(B) in the in-memory TLB 324(0)-324(I), without requiring the MMU circuit 302 to perform this task.As an alternative, the operating system kernel can schedule tasks for MMU circuit 302 to perform invalidation. For example, by erasing or zeroing the memory address in the memory address field of the process structure, the operating system kernel can invalidate the entire in-memory TLB 324(0)-324(I) for the process. The operating system kernel can then erase or zero the memory address in the memory address field 502 of the in-memory TLB register 500 in the current CPU 210(0)-210(N) running the process. The operating system kernel can issue a cross-call command to zero out the in-memory TLB registers on other CPUs 210(0)-210(N) running the same process. The scheduled task can also invalidate the entire in-memory TLB 324(0)-324(I) for the process by erasing or zeroing, for example, the memory address in the memory address field 502 of the in-memory TLB register 500. For a running thread, the operating system kernel can issue a cross-call command to other CPUs 210(0)-210(N) to erase the memory address in the memory address field 502 of the on-memory TLB register 500 in each CPU 210(0)-210(N) that points to the remapped address space corresponding to the on-memory TLB 324(0)-324(I) of the process. Once the operating system kernel has taken steps to ensure that the on-memory TLB 324(0)-324(I) to be invalidated is not used, the operating system kernel can schedule the invalidated on-memory TLB 324(0)-324(I) via a background task—if desired.

[0058] As an example, a process that can be executed by the operating system kernel to invalidate in-memory TLB entries 326(0)(0)-326(I)(B) in in-memory TLBs 324(0)-324(I) is as follows. The first step is to invalidate page table entries in page table 304. The next step is to invalidate in-memory TLB entries 326(0)(0)-326(I)(B) in in-memory TLBs 324(0)-324(I) so that the invalidation is globally visible in processor 202. This prevents future traversals from loading in-memory TLB entries 326(0)(0)-326(I)(B) using invalidated page table entries. The VA tag field 514 of the page table entries for the in-memory TLB entries 326(0)(0)-326(I)(B) to be invalidated is read, and the lock indicator 512 is read to determine whether the in-memory TLB entries 326(0)(0)-326(I)(B) are being accessed by another MMU or process. Once the lock indicator 512 is in the unlocked state, a CAS instruction is used to set the lock indicator 512 to the locked state. The page table entries in the page table entry cache field 510 are invalidated. The VA in the VA tag field 514 can also be invalidated, such as by storing all zeros in the VA tag field 514. The lock indicator 512 is then reset to the unlocked state.

[0059] It may also be necessary to implement a mechanism to externally invalidate MMU TLB entries 318(0)-318(T) in MMU TLB 306 and in-memory TLB entries 326(0)(0)-326(I)(B) in in-memory TLB 324(0)-324(I) (when they are no longer valid) so that incorrect VA to PA translations are not performed. For example, in Figure 2The host hypervisor executing in processor 202 can optionally capture guest memory accesses. It can do this by removing access permissions from the host page table that translates a guest process PA into a host process PA. In this scenario, all guest page table entries in MMU TLB 318(0)-318(T) in MMU TLB 306 (which caches page entries in the host page table) and in-memory TLB 326(0)(0)-326(I)(B) in in-memory TLB 324(0)-324(I) may need to be invalidated. However, there may be many in-memory TLBs 324(0)-324(I) in both the guest process and the guest operating system. As previously discussed, an external invalidation mechanism can be implemented using generation numbers. For example, the hypervisor can maintain a set of generation numbers, one for each guest operating system. As previously discussed, in-memory TLB entries 326(0)(0)-326(I)(B) have a generation number field 516. Therefore, when MMU circuit 302 caches page table entries in in-memory TLB entries 326(0)(0)-326(I)(B) of in-memory TLB 324(0)-324(I), a copy of the current client generation number is stored in the generation number field 516 of the cached in-memory TLB entries 326(0)(0)-326(I)(B). Therefore, when MMU circuit 302 matches in-memory TLB entries 326(0)(0)-326(I)(B) of in-memory TLB 324(0)-324(I) for a given VA 400 to be converted, the generation number stored in the generation number field 516 of the matched in-memory TLB entries 326(0)(0)-326(I)(B) is checked to see if it is the current one. If it is not current, the page table entry in the matching in-memory TLB entry 326(0)(0)-326(I)(B) is not used by the MMU circuit 302, which effectively means it is invalid. When the host hypervisor wants to invalidate all in-memory TLB entries 326(0)(0)-326(I)(B) in the in-memory TLB 324(0)-324(I) for the guest operating system, the host hypervisor can simply increment the generation number stored in the generation number field 516 of all in-memory TLB entries 326(0)(0)-326(I)(B) to invalidate them.

[0060] It may also be desirable to dynamically change the size of in-memory TLBs 324(0)-324(I) to improve the performance of VA-PA translation for a particular process. For example, a mechanism may be needed to allow the operating system kernel to dynamically change the size of in-memory TLBs 324(0)-324(I) for a process if memory access requests for a process do not achieve the desired access time performance. However, multiple threads of the same process can access the same in-memory TLBs 324(0)-324(I) simultaneously. Therefore, as an example, the operating system kernel may be configured to resize the in-memory TLBs 324(0)-324(I) by first invalidating (e.g., zeroing) the memory address in memory address field 502 on the current CPU 210(0)-210(N) of the in-memory TLBs 324(0)-324(I) to be resized and in the process. For a running thread, the operating system kernel can be configured to send cross-call commands to other CPUs 210(0)-210(N), which will cause the other CPUs 210(0)-210(N) to invalidate the memory address field 502 in the in-memory TLB register 500 of the process targeting in-memory TLB 324(0)-324(I), thereby effectively preventing the MMU circuit 302 in CPUs 210(0)-210(N) from using the in-memory TLB 324(0)-324(I) to be resized for VA to PA translation. Since the operating system kernel can determine that the in-memory TLBs 324(0)-324(I) of the process to be resized will not be used by the threads of that process, the operating system kernel can allocate a new in-memory TLB 324(0)-324(I) for that process in system memory 208, initiate in-memory TLB entries 326(0)(0)-324(I)(B), and set the in-memory TLB register 500 corresponding to the resized in-memory TLB 324(0)-324(I) to allow the MMU circuit 302 to use the resized in-memory TLB 324(0)-324(I) for VA to PA conversion. A malicious client may also be able to forge in-memory TLB entries 326(0)(0)-324(I)(B) in in-memory TLB 324(0)-324(I). In special circumstances, when the host management program requires a client process to traverse the entire page table, the host management program can disable the in-memory TLBs 324(0)-324(I) corresponding to the client process. During normal operation later, the in-memory TLBs 324(0)-324(I) can be re-enabled. If the forgery occurs during normal operation of the client host, it will only affect the client process and not other client or host processes.

[0061] Figure 9This is a block diagram of an exemplary processor-based system 900 including processor 902, which may include a memory management system 904 with a dedicated mTLB 906 for enhancing the MMU TLB for converting VA to PA, including but not limited to... Figure 3 The memory management system 300 and its Figures 4A-5B and Figures 7A-8 The processor-based system 900 may be one or more circuits included in an electronic board such as a printed circuit board (PCB), a server, a personal computer, a desktop computer, a laptop computer, a personal digital assistant (PDA), a computing board, a mobile device, or any other device, and may represent, for example, a server or a user's computer. In this example, the processor-based system 900 includes a processor 902. The processor 902 represents one or more general-purpose processing circuits, such as a microprocessor, a central processing unit, etc. More specifically, the processor 902 may be an EDGE instruction set microprocessor, or other processor implementing an instruction set that supports explicit consumer naming for conveying the produced value generated by the execution of producer instructions. The processor 902 is configured to execute processing logic in instructions for performing the operations and steps discussed herein. In this example, the processor 902 includes an instruction cache 908 for temporary, fast-access memory storage of instructions accessible to the memory management system 904. Instructions fetched or prefetched from memory such as system memory 910 via system bus 912 are stored in the instruction cache 908. The memory management system 904 is configured to process instructions fetched into the instruction cache 908 and process the instructions for execution.

[0062] Processor 902 and system memory 910 are coupled to system bus 912 and can interconnect peripheral devices included in processor-based system 900. It is well known that processor 902 communicates with these other devices via system bus 912 by exchanging address, control, and data information. For example, processor 902 can transmit bus transaction requests to memory controller 914 in system memory 910 (as an example of a slave device). Although in Figure 9 Not shown, but multiple system buses 912 may be provided, each forming a different architecture. In this example, the memory controller 914 is configured to provide memory access requests to the memory array 916 in the system memory 910. The memory array 916 includes an array of storage bit cells for storing data. As a non-limiting example, the system memory 910 may be a read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (such as synchronous DRAM (SDRAM)), and static memory (e.g., flash memory, static random access memory (SRAM), etc.).

[0063] Other devices can be connected to system bus 912. For example... Figure 9 As illustrated, these devices may, as an example, include system memory 910, external cache memory 917 as part of a cache memory system 918 that may include lower-level cache memory (all accessible by processor 902), one or more input devices 918, one or more output devices 920, modem 922, and one or more display controllers 924. The input devices 918 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. The output devices 920 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. Modem 922 may be any device configured to allow data exchange to and from network 926. Network 926 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), and bluetext. TM Networks and the Internet. Modem 922 can be configured to support any type of communication protocol desired. Processor 902 can also be configured to access multiple display controllers 924 via system bus 912 to control information sent to one or more displays 928. The multiple displays 928 can include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, etc.

[0064] Figure 9 The processor-based system 900 may include a set of instructions 930 that will be executed by the processor 902 for any application desired according to the instructions. The instructions 930 may be stored in system memory 910, the processor 902, and / or instruction cache 908, as an example of a non-transitory computer-readable medium 932. The instructions 930 may also reside wholly or at least partially in system memory 910 and / or within the processor 902 during their execution. The instructions 930 may also be transmitted or received over a network 926 via a modem 922, such that the network 926 includes the computer-readable medium 932.

[0065] Although computer-readable medium 932 is shown as a single medium in the exemplary embodiments, the term "computer-readable medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store a set or more sets of instructions. The term "computer-readable medium" should also be understood to include any medium capable of storing, encoding, or carrying a set of instructions for execution by a processing device and causing the processing device to perform any one or more methods of the embodiments disclosed herein. Therefore, the term "computer-readable medium" should include, but is not limited to, solid-state storage, optical media, and magnetic media.

[0066] The embodiments disclosed herein include various steps. These steps may be formed by hardware components or may be embodied in machine-executable instructions that can be used to cause a general-purpose or special-purpose processor programmed with these instructions to perform the steps. Alternatively, these steps may be performed by a combination of hardware and software.

[0067] The embodiments disclosed herein may be provided as a computer program product or software, which may include a machine-readable medium (or computer-readable medium) having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to the embodiments disclosed herein. A machine-readable medium includes any mechanism for storing or transmitting information in a machine-readable (e.g., computer-readable) form. For example, machine-readable media include: machine-readable storage media (e.g., ROM, random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.); and so on.

[0068] Unless otherwise explicitly stated and apparent from the foregoing discussion, it should be understood that throughout the description, discussions using terms such as “processing,” “computing,” “determining,” and “displaying” refer to the actions and processes of a computer system or similar electronic computing device that manipulate data and memory represented as physical (electronic) quantities within computer system registers and transform them into other data similarly represented as physical quantities within computer system memory or registers or other such information storage, transmission, or display devices.

[0069] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various systems can be used with programs based on the teachings herein, or it can be demonstrated that constructing more specialized devices to perform the desired method steps is convenient. The necessary structures for various such systems will emerge from the above description. Furthermore, the embodiments described herein are not described with reference to any particular programming language. It should be understood that the teachings of the embodiments described herein can be implemented using a variety of programming languages.

[0070] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits, and algorithms described in connection with the embodiments disclosed herein can be implemented as electronic hardware, stored in memory or another computer-readable medium and executed by a processor or other processing device, or a combination of both. As an example, components of the distributed antenna system described herein can be used in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How this functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the entire system. Those skilled in the art can implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as departing from the scope of these embodiments.

[0071] The various illustrative logic blocks, modules, and circuits described in conjunction with the embodiments disclosed herein can be implemented or performed using a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. Furthermore, the controller can be a processor. The processor can be a microprocessor, but alternatively, the processor can be any conventional processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0072] The embodiments disclosed herein can be embodied in hardware and instructions stored in hardware, and can reside in, for example, RAM, flash memory, ROM, electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor such that the processor can read information from the storage medium and write information to the storage medium. Alternatively, the storage medium can be integrated into the processor. The processor and storage medium can reside in an ASIC. The ASIC can reside in a remote station. Alternatively, the processor and storage medium can reside as discrete components in a remote station, base station, or server.

[0073] It should also be noted that the operational steps described in any exemplary embodiment herein are described to provide examples and discussion. The described operations can be performed in many different orders besides the order illustrated. Furthermore, the operations described in a single operational step can actually be performed in multiple different steps. Additionally, one or more operational steps discussed in the exemplary embodiments can be combined. Those skilled in the art will also understand that information and signals can be represented using any of a variety of technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0074] Unless otherwise expressly stated, any method described herein is not intended to be construed as requiring its steps to be performed in a particular order. Therefore, if a method claim does not actually describe the order in which its steps are followed, or if the claims or specification do not otherwise specifically state that these steps will be limited to a particular order, then no particular order is to be inferred.

[0075] It will be apparent to those skilled in the art that various modifications and variations can be made without departing from the spirit or scope of the invention. Since modifications, combinations, sub-combinations, and variations of the disclosed embodiments in conjunction with the spirit and essence of the invention will be apparent to those skilled in the art, the invention should be construed as including all contents within the scope of the appended claims and their equivalents.

Claims

1. A memory management system in a central processing unit (CPU), wherein the CPU is a processor in a processor-based system, comprising: Page tables, in the system memory of the processor-based system, include multiple hierarchical page tables, each hierarchical page table including multiple page table entries, the multiple page table entries being addressable by different hierarchical indexes of virtual address VA, and the multiple page table entries being configured to store the physical address PA associated with the VA; The Memory Management Unit (MMU) Translation Backup Buffer (TLB) includes multiple MMU TLB entries, each of which is configured to store cached page table entries from the multiple page table entries. An in-memory TLB, in the system memory, comprises multiple in-memory TLB entries, each in-memory TLB entry being configured to store cached page table entries from the multiple page table entries; Page table traverser circuitry is configured to access multiple page table entries in the multiple hierarchical page tables based on the VA; and The MMU circuit is configured as follows: The system receives memory access requests, including requests for VA, based on computer software instructions executed for processes in the CPU. Determine whether any of the multiple MMU TLB entries in the MMU TLB contain a page table entry that includes a PA corresponding to the request VA; And in response to determining that the MMU TLB does not contain an MMU TLB entry that includes the page table entry corresponding to the PA of the request VA: Determine whether the VA in the first in-memory TLB entry of the plurality of in-memory TLB entries stored in the in-memory TLB allocated to the process in the CPU matches the requested VA; In response to determining that the VA stored in the first in-memory TLB entry matches the request VA, the request VA is converted to a PA based on the first in-memory TLB entry; And in response to determining that the VA stored in the first memory TLB entry does not match the requested VA, the page table traverser circuit: Based on the request VA, access the multiple hierarchical page tables in the page table; The request VA is converted into the first PA contained in the first page table entry of the plurality of hierarchical page tables corresponding to the request VA; Write the first page table entry in at least one of the hierarchical page tables in the page table corresponding to the request VA to the first MMU TLB entry in the MMU TLB; And in response to writing the first page table entry to the first MMU TLB entry in the MMU TLB: In response to the first page table entry in the at least one hierarchical page table being in the highest-level page table of the plurality of hierarchical page tables: The first page table entry is not written to the in-memory TLB entry in the in-memory TLB.

2. The memory management system of claim 1, wherein the MMU circuitry is further configured to, in response to determining that the VA stored in the first memory TLB entry matches the requested VA: Write the first in-memory TLB entry to the MMU TLB entry in the MMU TLB.

3. The memory management system of claim 1, wherein the MMU circuitry is further configured to, in response to determining that the MMU TLB contains an MMU TLB entry including the page table entry comprising the PA corresponding to the requested VA: The request VA is converted into the PA in the page table entry contained in the MMU TLB entry.

4. The memory management system of claim 3, wherein the MMU circuitry is configured to, in response to determining that the MMU TLB contains an MMU TLB entry, the MMU TLB entry containing a page table entry as a leaf page table entry: The request VA is converted into the PA in the page table entry contained in the MMU TLB entry.

5. The memory management system according to claim 3, wherein: The MMU circuitry is configured to, in response to determining that the MMU TLB contains an MMU TLB entry that includes a page table entry as a non-leaf page table entry, cause the page table traverser circuitry to: Based on the non-leaf page table entry in the MMU TLB entry, access the next hierarchical page table entry among the plurality of hierarchical page tables in the page table; And convert the requested VA into a PA contained in the page table entry in the next hierarchical page table.

6. The memory management system of claim 1, wherein the MMU circuitry is further configured to, in response to writing a second page table entry stored in one of the plurality of hierarchical page tables in the page table corresponding to the request VA to a second in-memory TLB entry in the in-memory TLB: Write the second page table entry to the second MMU TLB entry in the MMU TLB.

7. The memory management system of claim 1, wherein the MMU circuitry is further configured to, in response to determining that the VA stored in the first memory TLB entry does not match the requested VA: Write the third page table entry from one of the plurality of hierarchical page tables stored in the page table corresponding to the request VA to the in-memory TLB entry in the in-memory TLB.

8. The memory management system according to claim 1, wherein: Each of the plurality of in-memory TLB entries in the in-memory TLB also includes a lock indicator field, which is configured to store a lock indicator indicating a lock status. The MMU circuitry is also configured to, in response to determining that the TLB MMU does not contain an MMU TLB entry that includes the page table entry corresponding to the PA of the request VA: Determine whether the lock indicator in the lock indicator field of the first memory TLB entry indicates the lock status; And in response to the lock indicator in the lock indicator field of the first in-memory TLB entry indicating the lock status, the request VA is not converted to the PA based on the first in-memory TLB entry.

9. The memory management system of claim 8, wherein the MMU circuitry is further configured to: In response to the lock indicator in the lock indicator field of the first in-memory TLB entry indicating an unlocked state, the request VA is not converted to the PA based on the first in-memory TLB entry: The lock indicator in the lock indicator field of the first memory TLB entry will be set to the locked state; Determine whether the VA stored in the first stored TLB entry matches the requested VA; And in response to determining that the VA stored in the first memory TLB entry matches the requested VA: Based on the first in-memory TLB entry, the request VA is converted into the PA; And the lock indicator in the lock indicator field of the first memory TLB entry is set to the unlocked state.

10. The memory management system of claim 1, wherein the MMU circuitry is further configured to: Receive a failure indicator for the process; and In response to receiving the failure indicator for the process, and in response to the in-memory TLB entry containing a page table entry, flush the in-memory TLB entry in the in-memory TLB allocated to the process.

11. The memory management system according to claim 1, wherein: Each of the plurality of in-memory TLB entries in the in-memory TLB also includes a generation number field configured as a storage generation number; Furthermore, the MMU circuit is configured to, in response to determining that the VA stored in the first in-memory TLB entry does not match the requested VA: Write the second page table entry and the current generation number to the second in-memory TLB entry in the in-memory TLB.

12. The memory management system of claim 11, wherein the MMU circuitry is further configured to, in response to determining that the MMU TLB does not contain an MMU TLB entry that includes the page table entry comprising the PA corresponding to the requested VA: Determine whether the generation number in the generation number field of the first in-memory TLB entry in the in-memory TLB allocated to the process matches the current generation number; And in response to determining that the generation number stored in the generation number field of the first in-memory TLB entry does not match the current generation number, the MMU circuitry is further configured to cause the page table traverser circuitry to: Based on the request VA, access the multiple hierarchical page tables in the page table; And convert the requested VA into the first PA contained in the first page table entry.

13. The memory management system according to claim 1, in: The page table includes: A leaf-level paging table, comprising multiple leaf-level paging entries, which are addressable through the leaf level of the VA and configured to store a PA associated with the VA; A first hierarchical page table includes a plurality of first hierarchical page table entries, which are addressable through the first hierarchy of the VA, and each of the plurality of first hierarchical page table entries is configured to store the address of a leaf page table entry in the leaf hierarchical page table; and The second hierarchical page table includes a plurality of second hierarchical page table entries, which are addressable through the second hierarchy of the VA and each of the plurality of second hierarchical page table entries is configured to store the address of a first hierarchical page table entry in the first hierarchical page table; The in-memory TLB includes the plurality of in-memory TLB entries, each in-memory TLB entry being configured to store a second hierarchical page table entry from the second hierarchical page table; and The MMU TLB includes the plurality of MMU TLB entries, each MMU TLB entry being configured to store a first hierarchical page table entry from the first hierarchical page table.

14. The memory management system according to claim 1, in: The page table includes: A leaf-level paging table, comprising multiple leaf-level paging entries, which are addressable through the leaf level of the VA and configured to store a PA associated with the VA; And a first hierarchical page table, including a plurality of first hierarchical page table entries, the plurality of first hierarchical page table entries being addressable through the first hierarchy of the VA and each of the plurality of first hierarchical page table entries being configured to store the address of a leaf page table entry in the leaf hierarchical page table; The in-memory TLB includes the plurality of in-memory TLB entries, each in-memory TLB entry being configured to store a first hierarchical page table entry from the first hierarchical page table; The MMU TLB includes the plurality of MMU TLB entries, each MMU TLB entry being configured to store a first hierarchical page table entry from the first hierarchical page table.

15. The memory management system according to claim 1, in: The page table includes: A leaf-level paging table, comprising multiple leaf-level paging entries, which are addressable through the leaf level of the VA and configured to store a PA associated with the VA; And a first hierarchical page table, including a plurality of first hierarchical page table entries, the plurality of first hierarchical page table entries being addressable through the first hierarchy of the VA and each of the plurality of first hierarchical page table entries being configured to store the address of a leaf page table entry in the leaf hierarchical page table; And the in-memory TLB includes: The first in-memory TLB includes a first plurality of in-memory TLB entries, each of the first plurality of in-memory TLB entries being configured to store a first hierarchical page table entry from the first hierarchical page table. And a second in-memory TLB, including a second plurality of in-memory TLB entries, each of the second plurality of in-memory TLB entries being configured to store a second hierarchical page table entry from a second hierarchical page table.

16. The memory management system of claim 1, further comprising an in-memory TLB register, the in-memory TLB register being configured to store a memory address pointing to the in-memory TLB in the system memory of the processor-based system. The MMU circuit is also configured to: Based on the memory address corresponding to the process in the in-memory TLB address register corresponding to the request VA, access the first in-memory TLB entry in the in-memory TLB allocated to the process.

17. The memory management system of claim 1, comprising a system memory including multiple in-memory TLBs, each allocated to a process.

18. A method for translating a virtual address VA to a physical address PA in a central processing unit (CPU) of a processor-based system, comprising: The system receives memory access requests, including requests for VA, based on computer software instructions executed for processes in the CPU. It is determined that the MMU TLB entries in the MMU TLB, which includes multiple Memory Management Unit (MMU) Translation Back Buffer (TLB) entries, do not contain page table entries that include the PA corresponding to the requested VA, and each of the multiple MMU TLB entries is configured to store a page table entry for storing the cache among the multiple page table entries; The page table entries are contained in a page table comprising multiple hierarchical page tables, each hierarchical page table comprising multiple page table entries, the multiple page table entries being addressable via a VA and configured to store a PA associated with the VA; And in response to determining that the MMU TLB does not contain an MMU TLB entry that includes the page table entry corresponding to the PA of the request VA: The VA stored in the first in-memory TLB entry of a plurality of in-memory TLB entries in the system memory of the processor-based system, which is allocated to the process in the system memory of the processor-based system, does not match the requested VA; In response to determining that the VA stored in the first in-memory TLB entry matches the request VA, the request VA is converted to a PA based on the first in-memory TLB entry; And in response to determining that the VA stored in the first in-memory TLB entry does not match the requested VA, the page table traverser circuit: Based on the request, VA accesses at least one of the plurality of hierarchical page tables; The request VA is converted into the first PA contained in the first page table entry of the plurality of hierarchical page tables corresponding to the request VA; Write the first page table entry in the plurality of hierarchical page tables in the page table corresponding to the request VA to the first MMU TLB entry in the MMU TLB; And in response to writing the first page table entry to the first MMU TLB entry in the MMU TLB: In response to the first page table entry in the plurality of hierarchical page tables being in the highest-level page table of the plurality of hierarchical page tables: The first page table entry is not written to the in-memory TLB entry in the in-memory TLB.

19. The method of claim 18, further comprising, in response to determining that the VA stored in the first in-memory TLB entry matches the requested VA: Write the first in-memory TLB entry to the MMU TLB entry in the MMU TLB.

20. The method of claim 18, further comprising, in response to determining that the MMU TLB contains an MMU TLB entry including the page table entry comprising the PA corresponding to the request VA: The request VA is converted into the PA in the page table entry contained in the MMU TLB entry.

21. A processor-based system, comprising: System memory; A processor comprising one or more central processing units (CPUs), each CPU being configured to execute computer instructions and one or more processes in an operating system software program; A memory management system, located within one or more CPUs, includes: Page tables, in system memory, include multiple hierarchical page tables, each hierarchical page table including multiple page table entries, the multiple page table entries being addressable by different hierarchical indexes of virtual address VA and the multiple page table entries being configured to store the physical address PA associated with the VA; The Memory Management Unit (MMU) Translation Backup Buffer (TLB) includes multiple MMU TLB entries, each of which is configured to store cached page table entries from the multiple page table entries. An in-memory TLB, in the system memory, comprises multiple in-memory TLB entries, each in-memory TLB entry being configured to store cached page table entries from multiple page table entries; Page table traversal circuitry, the page table traversal circuitry being configured to access page table entries in the plurality of hierarchical page tables in the page table based on the VA; And the MMU circuit is configured as follows: The system receives a memory access request, including a request for VA, based on computer software instructions executed for the processes of the one or more processes in the one or more CPUs. Determine whether the MMU TLB entry in the MMU TLB contains a page table entry that includes a PA corresponding to the request VA; In response to determining that the MMU TLB does not contain an MMU TLB entry that includes the page table entry corresponding to the PA of the request VA: Determine whether the VA stored in the first in-memory TLB entry of the process in the system memory allocated to the processor-based system matches the requested VA; And in response to determining that the VA stored in the first in-memory TLB entry matches the requested VA, the requested VA is converted to a PA based on the first in-memory TLB entry; And in response to determining that the VA stored in the first memory TLB entry does not match the requested VA, the page table traverser circuit: Based on the request VA, access the multiple hierarchical page tables in the page table; The request VA is converted into the first PA contained in the first page table entry of one of the plurality of hierarchical page tables corresponding to the request VA; Write the first page table entry in one of the hierarchical page tables in the page table corresponding to the request VA to the first MMU TLB entry in the MMU TLB; And in response to writing the first page table entry to the first MMU TLB entry in the MMU TLB: In response to the first page table entry in one hierarchical page table being in the highest-level page table of the plurality of hierarchical page tables: The first page table entry is not written to the in-memory TLB entry in the in-memory TLB.

22. The processor-based system of claim 21, wherein each of the one or more CPUs is configured to execute the computer instructions in the operating system software to: It is determined that the VA-to-PA mapping of the system memory has been changed for an executed process, the VA-to-PA mapping including one or more VAs mapped to one or more PAs; In response to determining that the VA-to-PA mapping of the system memory has been changed for the executed process: Determine whether one or more page table entries corresponding to the VA in the VA-to-PA mapping for the executed process consist only of leaf page table entries; In response to determining that the page table entry corresponding to the VA in the VA-to-PA mapping for the executed process consists not only of leaf page table entries: Determine whether one or more page table entries corresponding to the VA in the VA-to-PA mapping for the executed process are included in one or more in-memory TLB entries corresponding to the VA in the VA-to-PA mapping for the executed process; And in response to determining that one or more page table entries corresponding to the page table entry in the VA-to-PA mapping for the executed process are included in one or more entries in the in-memory TLB entry corresponding to the VA in the VA-to-PA mapping for the executed process: Flush one or more entries in the in-memory TLB entry corresponding to the VA in the VA-to-PA mapping for the executed process.

23. The processor-based system of claim 22, wherein each of the one or more CPUs is further configured to, in response to determining that one or more page table entries corresponding to the page table entry in the VA-to-PA mapping for the executed process consist only of leaf page table entries, execute the computer instructions in the operating system software program to: Flush one or more entries in the MMU TLB that correspond to the VA in the VA to PA mapping.

24. The processor-based system of claim 22, wherein each of the one or more CPUs is further configured to, in response to determining that the one or more page table entries corresponding to the page table entries in the VA-to-PA mapping for the executed process consist not only of leaf page table entries, execute the computer instructions in the operating system software program to: Determine whether one or more page table entries corresponding to the VA in the VA-to-PA mapping for the executed process are in a hierarchical page table above the page hierarchy of the in-memory TLB; In response to determining that one or more page table entries corresponding to the VA in the VA-to-PA mapping for the executed process are in the hierarchical page table above the page hierarchy of the in-memory TLB: Flush one or more entries of the in-memory TLB entry corresponding to the VA in the VA-to-PA mapping for the executed process; One or more entries in the MMU TLB that correspond to the VA in the VA-to-PA mapping are flushed; And flushing one or more page table entries in the page table that correspond to the VA in the VA-to-PA mapping.

25. The processor-based system of claim 24, further comprising a plurality of in-memory TLB address registers, each in-memory TLB address register corresponding to a corresponding process in the one or more processes, and each in-memory TLB register being configured to store a memory address pointing to a corresponding in-memory TLB in the system memory allocated to the corresponding process; in: The MMU circuit is further configured to access the first in-memory TLB entry in the in-memory TLB allocated to the process based on the in-memory TLB address in the in-memory TLB address register of the plurality of in-memory TLB address registers. The CPU is further configured to, in response to determining that one or more page table entries corresponding to the page table entry in the VA-to-PA mapping for the executed process are in the hierarchical page table above the page hierarchy of the in-memory TLB: Erase the memory address in one or more of the plurality of memory TLB address registers corresponding to the executed process in the CPU.

26. The processor-based system of claim 25, wherein the CPU is further configured to, in response to determining that one or more page table entries corresponding to the page table entry in the VA-to-PA mapping for the executed process are in the hierarchical page table located above the page hierarchy of the in-memory TLB: A cross-call command is issued to another CPU among the one or more CPUs, causing the other CPU to erase the memory address in one or more of the plurality of in-memory TLB address registers corresponding to the executed process that points to the corresponding in-memory TLB allocated to the executed process.

27. The processor-based system according to claim 22, wherein: Each of the plurality of in-memory TLB entries in the in-memory TLB allocated to the process also includes a generation number field configured to store a generation number; And the MMU circuitry is configured to, in response to determining that the VA stored in the first in-memory TLB entry does not match the requested VA: Write the second page table entry and the current generation number to the second memory TLB entry; And in response to determining that the MMU TLB does not contain an MMU TLB entry that includes the page table entry corresponding to the PA of the request VA: Determine whether the generation number in the generation number field of the first in-memory TLB entry in the in-memory TLB allocated to the process matches the current generation number; And in response to determining that the generation number stored in the generation number field of the first memory TLB entry does not match the current generation number, the MMU circuit is further configured to cause the page table traverser circuit to: Based on the request VA, access the multiple hierarchical page tables in the page table; And convert the requested VA into the first PA contained in the first page table entry; The CPU is further configured such that, in response to determining that one or more page table entries corresponding to the page table entry in the VA-to-PA mapping for the executed process are included in one or more entries in the in-memory TLB entry corresponding to the VA in the VA-to-PA mapping for the executed process: Change the current generation number.

28. The processor-based system of claim 22, further comprising a plurality of in-memory TLB address registers, each in-memory TLB address register corresponding to a corresponding process in the one or more processes, and each in-memory TLB register being configured to store a memory address pointing to a corresponding in-memory TLB in the system memory allocated to the corresponding process; in, The CPU is further configured to dynamically adjust the allocation size of the target in-memory TLB in the system memory by being configured to: Erase the memory address pointing to the target TLB from one or more of the plurality of on-memory TLB address registers corresponding to the target on-memory TLB to be resized; And issue a cross-call command to other CPUs among the one or more CPUs, so that the other CPUs erase the memory address pointing to the target in-memory TLB in one or more of the plurality of in-memory TLB address registers corresponding to the target in-memory TLB to be resized.

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