A chip stacking structure and a manufacturing method thereof

Abstract

A chip stacking structure and a manufacturing method thereof. Among them, the chip stacking structure includes a first wafer (100) and a second wafer (200). An exposed first bonding pad (133) is provided on the first redistribution layer (130) of the first wafer (100). The first redistribution layer (130) and the first bonding pad (133) of the first wafer (100) are directly bonded to the passive surface (220) of the second wafer (200) without preparing an additional dielectric layer on the bonding surface, reducing the thickness after the first wafer (100) and the second wafer (200) are stacked, making the size of the chip package smaller, thinner and lighter. Moreover, the thermal resistance after the first wafer (100) and the second wafer (200) are directly stacked is smaller, improving the heat dissipation performance of the chip. In addition, the second wafer (200) is further provided with a through-silicon via (233) connected to the first bonding pad (133), enabling the first wafer (100) and the second wafer (200) to be directly electrically interconnected through the through-silicon via (233) with high connection reliability. The provided method for manufacturing the above chip stacking structure has simple process steps and does not have the problem of etching selectivity ratio, greatly improving the feasibility.

Description

Technical Field

[0001] This application relates to the technical field of chip packaging, and particularly to a chip stacking structure and a manufacturing method thereof. Background Art

[0002] Chip packaging, also known as integrated circuit packaging, is a process of placing the produced wafer Die on a substrate that serves as a carrier, leading out the pins, and then fixing and packaging them into a whole. Among them, three-dimensional integrated circuit (3D IC) packaging technology is a packaging technology that vertically stacks multiple layers of wafers in three-dimensional space to form a single integrated whole. The 3D IC packaging technology can address the problem of the physical limitations of semiconductor manufacturing processes by electrons and materials, and save chip space.

[0003] Currently, in 3D IC packaging technology, to achieve vertical stacking of chips, generally an additional dielectric layer needs to be prepared on the mutually contacting surfaces of two wafers, and the two wafers are integrated together through silicon fusion bonding of the dielectric layer. Then, through-silicon vias that penetrate the wafers and the dielectric layer are prepared to electrically connect the two wafers. Generally, the thickness of the additional dielectric layer for bonding prepared for each wafer can reach 1 micron to 5 microns. Therefore, the stacking of every two layers of wafers will increase the thickness of the chip by an additional 2 microns to 10 microns. When the number of stacked wafer layers increases, the additional thickness of the chip will also increase accordingly, ultimately making the packaging size of the chip larger. Summary of the Invention

[0004] This application provides a chip stacking structure and a manufacturing method thereof, which can reduce the stacking thickness of the chip, improve the electrical connection reliability and heat dissipation performance of the wafer, and have a simple manufacturing process.

[0005] To achieve the above object, the following technical solutions may be adopted in this application:

[0006] In a first aspect, this application provides a chip stacking structure, which includes: a first wafer, on the active surface of the first wafer, a first redistribution layer is provided; a plurality of first bonding pads, the plurality of first bonding pads are exposed on the surface of the first redistribution layer parallel to the first wafer, and the plurality of first bonding pads are electrically connected to the metal wiring of the first redistribution layer; a second wafer, the second wafer is stacked with the first wafer, and the passive surface of the second wafer is bonded to the first redistribution layer and the plurality of first bonding pads; the second wafer is provided with a plurality of through-silicon vias, and one end of each through-silicon via located on the passive surface of the second wafer is connected to at least one of the plurality of first bonding pads.

[0007] The chip stacking structure provided by this application includes a first wafer and a second wafer. The first redistribution layer of the first wafer is provided with an exposed first bonding pad. The first redistribution layer and the first bonding pad of the first wafer are directly bonded to the passive surface of the second wafer, without the need to prepare an additional dielectric layer on the bonding surface, reducing the thickness after the first wafer and the second wafer are stacked, making the size of the chip package smaller, thinner and lighter.

[0008] Combined with the first aspect, in a possible design, the structure further includes: a plurality of second bonding pads, the plurality of second bonding pads are exposed on the surface of the first redistribution layer parallel to the first wafer, the plurality of second bonding pads are bonded to the passive surface of the second wafer, and the plurality of second bonding pads are electrically connected to the metal wiring of the first redistribution layer. According to the above structure, the first redistribution layer and the first bonding pad of the first wafer are directly bonded to the passive surface of the second wafer, making the thermal resistance between the first wafer and the second wafer smaller, and heat can be directly transferred between the first wafer and the second wafer; moreover, the second bonding pad can also be used as a heat conduction structure between the wafers in this application, which can further reduce the thermal resistance between the wafers, improve the heat transfer efficiency between the wafers, and improve the heat dissipation performance after chip packaging.

[0009] Combined with the first aspect, in a possible design, the active surface of the second wafer is provided with a second redistribution layer, the second redistribution layer is provided with a plurality of metal pad disks, and the plurality of metal pad disks are electrically connected to the metal wiring of the second redistribution layer; one end of each through-silicon via located on the active surface of the second wafer is connected to at least one of the plurality of metal pad disks. Thus, the through-silicon via is directly connected to the first bonding pad and the metal pad disk, without the need to penetrate the dielectric layer, avoiding the problem of etching selectivity ratio and improving the electrical connection reliability between the first wafer and the second wafer.

[0010] Combined with the first aspect, in a possible design, each through-silicon via is filled with a metal filler, and the metal filler is used to electrically connect the first bonding pad it connects to the metal pad disk.

[0011] Combined with the first aspect, in a possible design, the metal filler is formed by sputtering a seed layer connected to the first bonding pad on the inner surface of the through-silicon via and performing metal electroplating on the surface of the seed layer.

[0012] Combined with the first aspect, in a possible design, the passive surface of the second wafer is provided with a first dielectric layer, and the passive surface of the second wafer is bonded to the first redistribution layer, the plurality of first bonding pads and the plurality of second bonding pads through the first dielectric layer. The first dielectric layer can be prepared using a high thermal conductivity material, such as silicon carbide, diamond, graphene or silicon nitride, etc., to reduce the thermal resistance between the first wafer and the second wafer and improve the heat dissipation performance after chip packaging.

[0013] Second aspect, the present application provides a method for manufacturing a chip stacking structure, the method comprising: preparing a first redistribution layer and a plurality of first bonding pads on an active surface of a first wafer, the plurality of first bonding pads being exposed on a surface of the first redistribution layer parallel to the first wafer, and the plurality of first bonding pads being electrically connected to metal wirings of the first redistribution layer; bonding a passive surface of a second wafer to the first redistribution layer and the plurality of first bonding pads; etching the second wafer to form a plurality of through-silicon vias, and one end of each through-silicon via located on the passive surface of the second wafer being connected to at least one of the plurality of first bonding pads.

[0014] In the method for manufacturing a chip stacking structure provided by the present application, the first redistribution layer of the first wafer and the passive surface of the second wafer are directly bonded, so there is no need to prepare an additional dielectric layer on the bonding surface or use solder balls, and the thickness after stacking the first wafer and the second wafer can be reduced by at least the thickness of the additional dielectric layer, making the size of the chip package smaller, thinner and lighter.

[0015] In combination with the second aspect, in a possible design, preparing the first redistribution layer and the plurality of first bonding pads on the active surface of the first wafer includes: preparing a first redistribution layer with a thickness greater than a preset target thickness and a plurality of first bonding pads hidden in the first redistribution layer on the active surface of the first wafer; thinning the first redistribution layer to the target thickness by material removal processing, so that the plurality of first bonding pads are exposed on a surface of the first redistribution layer parallel to the first wafer. Since the first bonding pads in the present application do not need to be connected to solder balls, during the material removal process, there is no need to precisely control the depth of the dish in the process, and only the swelling margin needs to be retained, thereby improving the feasibility of process control and reducing the production cost.

[0016] In combination with the second aspect, in a possible design, the method further includes: preparing a plurality of second bonding pads hidden in the first redistribution layer on the active surface of the first wafer, and when the first redistribution layer is thinned to the target thickness, the plurality of second bonding pads are exposed on the surface of the first redistribution layer. According to the above method, the first redistribution layer and the first bonding pads of the first wafer are directly bonded to the passive surface of the second wafer, so that the thermal resistance between the first wafer and the second wafer is smaller, and heat can be directly transferred between the first wafer and the second wafer; moreover, the second bonding pads can also be used as a heat conduction structure between the wafers in the present application, which can further reduce the thermal resistance between the wafers, improve the heat transfer efficiency between the wafers, and improve the heat dissipation performance after chip packaging.

[0017] In combination with the second aspect, in a possible design, a plurality of through-silicon vias are etched in the second wafer, and one end of each through-silicon via located on the passive surface of the second wafer is connected to at least one of the plurality of first bonding pads, including: determining the projection positions of at least one first bonding pad on the active surface of the second wafer; etching a through-silicon via perpendicular to the active surface of the second wafer from the projection position towards the first bonding pad until the through-silicon via contacts at least one first bonding pad. Thus, in the method provided in this application, no additional dielectric etching is generated during the etching of the through-silicon vias, only the silicon of the wafer body is etched, and there is no need to select an etching selectivity ratio for different materials, avoiding the problems of fin-shaped etching topography and drum-shaped etching topography formed in the dielectric layer due to inappropriate etching selectivity ratio, ensuring the continuity of the seed layer and the metal filler, and improving the connection reliability between the first wafer and the second wafer.

[0018] In combination with the second aspect, in a possible design, the method further includes: preparing a second redistribution layer on the active surface of the second wafer, the second redistribution layer being provided with a plurality of metal pad disks, and the plurality of metal pad disks being electrically connected to the metal wiring of the second redistribution layer; one end of each through-silicon via located on the active surface of the second wafer is connected to at least one of the plurality of metal pad disks. Thus, the through-silicon vias are directly connected to the first bonding pads and the metal pad disks without passing through the dielectric layer, improving the electrical connection reliability between the first wafer and the second wafer.

[0019] In combination with the second aspect, in a possible design, the method further includes: forming a seed layer connected to the first bonding pad on the inner surface of the through-silicon via by surface sputtering; performing metal electroplating on the surface of the seed layer to form a metal filler, and the metal filler electrically connects the first bonding pad and the metal pad disk. According to the above method, the through-silicon vias do not need to pass through the dielectric layer during etching, and no fin-shaped etching topography and drum-shaped etching topography are generated due to the problem of etching selectivity ratio. Therefore, the seed layer on the inner surface of the through-silicon via can have good coverage continuity, enabling the metal filler to continuously and fully fill the through-silicon via, ensuring that the metal filler can form a reliable electrical connection between the first wafer and the second wafer.

[0020] In combination with the second aspect, in a possible design, bonding and connecting the passive surface of the second wafer to the first redistribution layer and the plurality of first bonding pads includes: preparing a first dielectric layer on the passive surface of the second wafer; bonding and connecting the first dielectric layer to the first redistribution layer, the first bonding pad, and the second bonding pad. The first dielectric layer can be prepared using a high thermal conductivity material, such as silicon carbide, diamond, graphene, or silicon nitride, etc. to reduce the thermal resistance between the first wafer and the second wafer and improve the heat dissipation performance after chip packaging.

[0021] In a third aspect, the present application provides an electronic device, which includes a printed circuit board (PCB) and at least one computer chip disposed on the printed circuit board. Among them, some or all of the at least one computer chip has a chip stacking structure as in the first aspect and any of its design manners. Description of the Drawings

[0022] Figure 1 is a schematic diagram of a chip stacking structure;

[0023] Figure 2 schematic diagrams of fin-shaped etching topography and drum-shaped etching topography;

[0024] Figure 3 is a schematic diagram of another chip stacking structure;

[0025] Figure 4 is an exploded view of the chip stacking structure provided in Embodiment 1 of the present application;

[0026] Figure 5 is a cross-sectional view of the stacked state of the first wafer and the second wafer;

[0027] Figure 6 is an exploded view of another chip stacking structure provided in Embodiment 1 of the present application;

[0028] Figure 7 is a cross-sectional view of the stacked state of the first wafer and the second wafer;

[0029] Figure 8 is an exploded view of another chip stacking structure provided in Embodiment 1 of the present application;

[0030] Figure 9 is an exploded view of a multi-layer chip stacking structure shown in the embodiments of the present application;

[0031] Figure 10 is a cross-sectional view of a multi-layer chip stacking structure shown in the embodiments of the present application;

[0032] Figure 11 is a schematic diagram of the structure of an integrated chip shown in the embodiments of the present application;

[0033] Figure 12 is a schematic diagram of step S101 of a method for manufacturing a chip stacking structure provided in Embodiment of the present application;

[0034] Figure 13 is a schematic diagram of step S101 of a method for manufacturing a chip stacking structure provided in Embodiment of the present application;

[0035] Figure 14It is a schematic diagram of step S102 of a method for manufacturing a chip stacking structure provided by an embodiment of the present application;

[0036] Figure 15 It is a schematic diagram of step S103 of a method for manufacturing a chip stacking structure provided by an embodiment of the present application;

[0037] Figure 16 It is a schematic diagram of step S104 of a method for manufacturing a chip stacking structure provided by an embodiment of the present application;

[0038] Figure 17 It is a schematic diagram of step S102 of a method for manufacturing a chip stacking structure provided by an embodiment of the present application. Detailed implementation manners

[0039] Hereinafter, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of this embodiment, unless otherwise specified, the meaning of "a plurality" is two or more.

[0040] Chips are important components in various electronic devices, and the product performance of electronic devices largely depends on the performance of the chips. In order to adapt to the rapid development of technologies such as graphics computing, neural network (NN), artificial intelligence (AI), cloud computing, and high-performance computing cluster (HPCC), in recent years, the process technology of chips has been continuously improved, the number of transistors has been continuously increased, and the performance of the chips has thus been continuously enhanced, and the operating power consumption has also increased accordingly. However, due to the development trend of electronic devices towards high performance, multi-function, high reliability, high integration, miniaturization, and lightness and thinness, the integration degree of electronic devices is getting higher and higher, and the space inside the body is becoming increasingly precious. This makes various chips need to have both high performance and a small volume at the same time, and such requirements pose challenges to chip packaging.

[0041] Chip packaging, also known as integrated circuit packaging, is a process of placing the produced wafer Die on a substrate that serves as a carrier, leading out the pins, and then fixing and packaging them into a whole. In the embodiments of this application, the wafer can also be called a bare die, bare chip, or bare wafer, which is a small piece of unencapsulated integrated circuit body made of semiconductor material, and the established functions of the integrated circuit are realized on this small piece of semiconductor. Currently, in order to improve the integration of chips and reduce the chip volume, some relatively advanced chip packaging methods have been proposed. Among them, the three-dimensional integrated circuit (3D IC) packaging technology is a packaging technology that vertically integrates multiple layers of wafers in three-dimensional space to form a single integrated whole. The 3D IC packaging technology can address the problem that the semiconductor manufacturing process is physically limited by electrons and materials, and saves chip space.

[0042] In the 3D IC packaging technology, a stacked structure can be first formed between the vertically arranged multiple layers of wafer Dies through methods such as fusion bonding (FB), and then, electrical interconnection between different layers of wafers can be achieved through technologies such as wire bond (WB) or through silicon via (TSV). Finally, the above stacked structure is encapsulated, and the packaged chip can be obtained.

[0043] Among them, silicon fusion bonding is a low-cost 3D stacking method applicable to the 3D IC packaging technology. The silicon fusion bonding process is simple and has a fast production speed, and can obtain a 3D stacked structure with small parasitic capacitance, high integration density, and small short-channel effect, and is particularly suitable for the SOI (silicon on insulator) structure of low-voltage and low-power circuits.

[0044] Among them, through silicon via, also known as silicon via hole, is a vertical electrical connection technology that penetrates the device layer of the silicon wafer. Specifically, through silicon via is a through hole that connects the upper and lower sides of the wafer, and a conductor (i.e., via metal) is poured into the through hole to form a conductive connection. The poured conductor can be determined according to its specific process, such as conductive materials copper, tungsten, and polysilicon, and the silicon via conductive material is isolated from the substrate by an insulating layer (usually silicon dioxide).

[0045] Figure 1 It is a schematic diagram of a chip stacked structure. As Figure 1 shown, the chip stacked structure includes an upper wafer 10 and a lower wafer 20 that are stacked on top of each other. Among them, the active surface ( Figure 1 the upper surface of the upper wafer 10 in Figure 1On the upper surfaces of the lower wafers 20 respectively, redistribution layers 11 and 21 are fabricated. On the passive surface of the upper wafer 10 ( Figure 1 On the lower surface of the upper wafer 10) and on the surface of the redistribution layer 21 of the lower wafer 20, additional dielectric layers 12 and 22 are fabricated respectively. The upper wafer 10 and the lower wafer 20 are bonded together by silicon fusion bonding through the dielectric layers 12 and 22 to achieve stacking. In addition, this stacked structure further includes through-silicon vias 30 that penetrate the bulk silicon of the upper wafer 10 and the dielectric layers 12 and 22, enabling electrical interconnection between the upper wafer 10 and the lower wafer 20. Solder balls 13 are provided on the redistribution layer of the upper wafer 10, and these solder balls 13 are used to form electrical connections with an external substrate or a printed circuit board (PCB).

[0046] Here, it should be supplemented and explained that the active surface of a wafer refers to the surface of the wafer that has active devices, and the surface of the wafer that does not have active devices is called the passive surface. For example Figure 1 The lower surface of the upper wafer 10 and the lower surface of the lower wafer 20 in Figure 1 both belong to passive surfaces; a redistribution layer (RDL) refers to a metal wiring pattern formed on the wafer surface by depositing metal layers and dielectric layers to achieve re-layout of the I / O ports of the chip. The redistribution layer is usually deposited on the active surface of the wafer. For example, in

[0047] Figure 1 In the structure shown, the redistribution layer 21 of the lower wafer 20 is deposited on the active surface of the lower wafer 20, and the redistribution layer 11 of the upper wafer 10 is deposited on the active surface of the upper wafer 10. To achieve silicon fusion bonding between the upper wafer 10 and the lower wafer 20 in the structure shown, additional dielectric layers 12 and 22 are fabricated on the passive surface of the upper wafer 10 and the redistribution layer 21 of the lower wafer 20. The thickness of these dielectric layers 12 and 22 can currently reach 1 μm to 5 μm, which will increase the thickness of the stacked chip. Especially when the number of wafer stacking layers of the chip is relatively large, the increase in thickness caused by these dielectric layers 12 and 22 is more obvious. For example, currently, the number of wafer stacking layers of 3D NAND flash memory can reach 96 layers or even 128 layers, resulting in a very obvious increase in thickness brought by the dielectric layer, which is very unfavorable for the thinness and lightness of the chip. And, since silicon fusion bonding requires meeting certain surface flatness and roughness requirements, before silicon fusion bonding the dielectric layer, it is also necessary to precisely perform chemical mechanical polishing (CMP) on the surface of the dielectric layer, which increases additional process steps and costs and reduces the packaging efficiency.

[0048] In addition, since Figure 1The silicon through - via 30 of the shown structure penetrates the bulk silicon of the upper wafer 10 and the dielectric layers 12 and 22. Therefore, when fabricating the silicon through - via 30, not only the bulk silicon of the upper wafer 10 needs to be etched, but also the dielectric layers 12 and 22 need to be etched. Generally speaking, if only the wafer bulk silicon is etched, the Bosch process can be used; among them, the Bosch process, namely deep reactive ion etching (DRIE), is a high aspect - ratio silicon etching technology based on fluorine - based gases. It alternately switches the etching gas and the passivation gas, so that the reactive ion etching process continuously deposits an anti - etching layer or side - wall passivation layer on the side walls of the etched holes. The etching gas of the Bosch process is sulfur hexafluoride SF6, and the passivation gas is perfluorocyclobutane C4F8. C4F8 can form fluorocarbon - based polymer in the plasma, and this polymer can deposit on the silicon surface to prevent the reaction of fluorine ions with silicon. However, the gases used in deep reactive ion etching only have etching or passivation effects on silicon, while the dielectric layer is generally an oxide or a nitride. Therefore, if the wafer bulk silicon and the dielectric layer need to be etched, the Bosch process cannot be used, and only reactive ion etching (RIE) can be used. However, since it is difficult to select a suitable etching selectivity for the wafer bulk silicon and the dielectric layer, even if the reactive ion etching process is adopted, due to the inappropriate etching selectivity, fin - type (Fin) etching topography and drum - type etching topography as shown in Figure 2 will be formed in the dielectric layer. The fin - type etching topography and drum - type etching topography will cause the side - wall shape of the etched hole to fluctuate greatly, affecting the coverage continuity of the seed layer during the preparation of the silicon through - via. The discontinuous coverage of the seed layer will cause the subsequent filling failure of the core metal of the through - hole, resulting in the electrical interconnection failure between the stacked wafers.

[0049] Moreover, Figure 1 The shown chip - stacking structure requires the dielectric layers 12 and 22 to completely cover the upper wafer 10 and the lower wafer 20, making the upper wafer 10 and the lower wafer 20 have a large thermal resistance, which hinders the heat transfer. And the silicon through - via 30 is only distributed in a small part of the wafer, having a very limited effect on the heat dissipation of the wafer. Therefore, Figure 1 such a structure may also cause heat - dissipation problems in the chip, affecting the chip performance.

[0050] Figure 3 is a schematic diagram of another chip - stacking structure. As shown in Figure 3 , this chip - stacking structure includes an upper wafer 10 and a lower wafer 20 stacked on each other. The active surface of the upper wafer 10 ( Figure 3 the upper surface of the upper wafer in Figure 3A large number of metal pads 14 and 24 are prepared on the upper surface of the lower wafer in []. The positions of the metal pads 14 on the upper wafer 10 and the metal pads 24 on the lower wafer correspond to each other and are connected by solder balls 40 to achieve the stacked interconnection of the upper wafer 10 and the lower wafer 20. In order to enable the solder balls 40 to accurately connect the metal pads 14 on the upper wafer 10 and the metal pads 24 on the lower wafer 20, Figure 3 In the preparation of the stacked structure shown, it is necessary to strictly control the position accuracy of the metal pads 14 and 24, and strictly control the accuracy of the dish profile formed by the metal pads 14 and 24 during chemical mechanical polishing (CMP). The production process is difficult and the feasibility is relatively low. Moreover, since the wafers are interconnected by the solder balls 40, due to the limitation of the diameter of the solder balls 40, there is a limit to the spacing between the wafers and the pad pitch between the metal pads 14 and 24, and it cannot be further reduced, resulting in Figure 3 The height and horizontal dimensions of the chip stacked structure shown are relatively large, increasing the size of the chip after subsequent packaging.

[0051] It can be seen that various chip stacked structures currently adopted in the 3D IC packaging technology of chips generally have the problems of large stacked thickness and unsatisfactory heat dissipation performance.

[0052] The embodiment of the present application provides a chip stacked structure and a manufacturing method thereof to solve the technical problems existing in the above-mentioned various solutions. It should be noted that the chip stacked structure described in the embodiment of the present application can have multiple different forms and can be realized in various ways. The chip stacked structure and manufacturing method discussed below are only some preferred embodiments for illustrating the feasibility of the structure described in the embodiment of the present application, and do not limit the protection scope of the embodiment of the present application. Implementing the stacked packaging structure described in the embodiment of the present application by other methods or sequences is also within the protection scope of the embodiment of the present application.

[0053] Embodiment 1

[0054] The embodiment 1 of the present application provides a chip stacked structure, which can be applied to the 3D IC packaging technology of chips to reduce the chip stacked thickness and improve the chip heat dissipation performance. Figure 4 is an exploded view of the chip stacked structure provided by the embodiment 1 of the present application. As Figure 4 shown, the chip stacked structure includes:

[0055] A first wafer 100 and a second wafer 200, the first wafer 100 and the second wafer 200 are stacked up and down. The first wafer 100 and the second wafer 200 can be, for example, silicon wafers made of silicon material. Both the first wafer 100 and the second wafer 200 include an active surface and a passive surface. Among them, the active surface 110 of the first wafer 100 is in Figure 4corresponding to the upper surface of the first wafer 100, the passive surface 120 of the first wafer 100 is in Figure 4 corresponding to the lower surface of the first wafer 100, the active surface 210 of the second wafer 200 is in Figure 4 corresponding to the upper surface of the second wafer 200, the passive surface 220 of the second wafer 200 is in Figure 4 corresponding to the lower surface of the second wafer 200, the active surface 110 of the first wafer 100 and the passive surface 220 of the second wafer 200 are disposed opposite to each other.

[0056] A first redistribution layer 130 is disposed on the active surface 110 of the first wafer 100. The first redistribution layer 130 includes a dielectric layer 131 and metal wirings 132. Among them, the dielectric layer 131 covers the active surface 110 of the first wafer 100. The dielectric layer 131 serves as an insulating material between the metal wirings 132 and can be prepared using a polarizable insulator material. For example, on the active surface 110 of the first wafer 100, materials such as silicon dioxide are deposited by plasma-enhanced chemical vapor deposition (PECVD) to form the dielectric layer 131. The metal wirings 132, as leads of the I / O ports of the chip, shuttle through the dielectric layer 131. The metal wirings 132 can be implemented using copper or other metal materials. For example, a pattern film for etching the metal wirings 132 is etched on the dielectric layer 131 using the damascene process, and then metal fillers are used to form the metal wirings 132, or the metal wirings 132 are prepared on the dielectric layer 131 by electroplating. It is easy to understand that since a chip usually has multiple I / O ports, therefore, the metal wirings 132 in the embodiments of the present application include multiple metal wires of each I / O port lead.

[0057] In the embodiments of the present application, the first redistribution layer 130 is further provided with a plurality of first bonding pads 133. The first bonding pads 133 are exposed on the surface of the first redistribution layer 130 parallel to the first wafer 100, that is: the first bonding pads 133 are disposed facing the passive surface 220 of the second wafer 200. The plurality of first bonding pads 133 are electrically connected to the metal wirings 132 of the first redistribution layer 130. The first bonding pads 133 can be implemented using copper or other metal materials and are prepared together with the first redistribution layer 130 using the damascene or electroplating method. It should be added that due to the requirements of the wafer circuit design, the first redistribution layer 130 may include one or more layers of metal wirings 132, and each layer of metal wirings 132 may be connected to the first bonding pads 133. Therefore, Figure 4 the first bonding pads 133 marked can be understood as including only one first bonding pad 133, or can be understood as including a stack of multiple first bonding pads 133.

[0058] Further, as shown in Figure 4 , the active surface 210 of the second wafer 200 is provided with a second redistribution layer 230. The second redistribution layer 230 is composed of a dielectric layer 231 and metal wirings 232. The implementation manners of the dielectric layer 231 and the metal wirings 232 of the second redistribution layer 230 may refer to those of the dielectric layer 131 and the metal wirings 132 of the first redistribution layer 130. It is easy to understand that, according to different integrated circuit designs of the wafers, the dielectrics and metal wirings of the first redistribution layer 130 and the second redistribution layer 230 may be implemented in the same way or in different ways, such as different layouts of the metal wirings, etc. The implementation manners of the second redistribution layer 230 are not elaborated in the embodiments of the present application.

[0059] Further, as shown in Figure 4 , the second wafer 200 is further provided with a plurality of through-silicon vias 233, and the plurality of through-silicon vias 233 penetrate from the active surface 210 of the second wafer 200 to the passive surface 220 of the second wafer 200. The second redistribution layer 230 of the second wafer 200 is further provided with a plurality of metal pad disks 234, and the plurality of metal pad disks are electrically connected to the metal wirings 232 in the second redistribution layer 230. The metal pad disks 234 may be implemented using copper or other metal materials, for example, prepared in the second redistribution layer 230 by using the damascene process or electroplating method. It should be added that, due to the requirements of the wafer circuit design, the second redistribution layer 230 may include one or more layers of metal wirings 232, and each layer of metal wirings 232 may be connected with metal pad disks 234. Therefore, Figure 4 the metal pad disk 234 marked in

[0060] Figure 5 is a cross-sectional view of the stacked state of the first wafer and the second wafer. As shown in Figure 5 , the passive surface 220 of the second wafer 200 is bonded to the first redistribution layer 130 of the first wafer 100, so that the first wafer 100 and the second wafer 200 are stacked. A special feature of the embodiments of the present application is that the first bonding pad 133 is exposed on the surface of the first redistribution layer 130, so that the first bonding pad 133 can also be bonded to the passive surface 220 of the second wafer 200. Therefore, the "bonding connection between the passive surface 220 of the second wafer 200 and the first redistribution layer 130 of the first wafer 100" in the embodiments of the present application actually means the bonding connection between the passive surface 220 of the second wafer 200 and the first redistribution layer 130 of the first wafer 100 and a plurality of first bonding pads 133.

[0061] Further, as shown in Figure 5As shown, one end of each through-silicon via 233 located on the active surface 210 of the second wafer 200 is connected to at least one metal pad 234, and one end of each through-silicon via 233 located on the passive surface 220 of the second wafer 200 is connected to at least one first bonding pad 133. The through-silicon via 233 is also filled with a metal filler 235, such as electroplated copper, etc. The metal filler 235 can be obtained by sputtering a seed layer connected to the first bonding pad 133 on the inner surface of the through-silicon via 233 and then performing metal electroplating on the surface of the seed layer. The metal filler 235 is used to electrically connect the metal pad 234 at one end of the through-silicon via 233 and the first bonding pad 133 at the other end of the through-silicon via 233, realizing the electrical interconnection between the first wafer 100 and the second wafer 200.

[0062] It should be added that if the second wafer 200 is the uppermost wafer of the chip, then the second redistribution layer 230 as Figure 5 shown can also be provided with solder balls 236. Through these solder balls 236, the packaged chip can be connected to an external substrate or a printed circuit board, enabling the chip to form an electrical connection with the external substrate or printed circuit board PCB.

[0063] The chip stacking structure provided by the embodiment of the present application directly bonds and connects the first redistribution layer 130 on the active surface 110 of the first wafer 100 and the passive surface 220 of the second wafer 200. Therefore, there is no need to prepare an additional dielectric layer on the bonding surface or use solder balls, which can reduce the thickness of the chip after stacking the first wafer 100 and the second wafer 200 by at least the thickness generated by the above-mentioned additional dielectric layer and solder balls, making the size of the packaged chip smaller, thinner and lighter. Moreover, after eliminating the additional dielectric layer, the thermal resistance after stacking the first wafer 100 and the second wafer 200 is reduced, which is beneficial to the transfer of heat between the wafers and improves the heat dissipation performance of the chip. In addition, the first redistribution layer 130 of the first wafer 100 is also provided with an exposed first bonding pad 133, and the second wafer 200 is also provided with a through-silicon via 233 connected to the first bonding pad 133, enabling the first wafer 100 and the second wafer 200 to be directly electrically interconnected through the through-silicon via 233 without the need to rely on solder balls or etching the dielectric layer. Therefore, the structure is simple, the process steps are simplified, and the connection reliability is high.

[0064] In an alternative embodiment, as Figure 6As shown in the figure, the chip stacking structure provided by the embodiment of the present application further includes: a plurality of second bonding pads 134. The second bonding pads 134 are exposed on the surface of the first redistribution layer 130 parallel to the active surface 110 of the first wafer 100, that is: the second bonding pads 134 are arranged facing the passive surface 220 of the second wafer 200. The above-mentioned plurality of second bonding pads 134 are electrically connected to the metal wiring 132 of the first redistribution layer 130. The second bonding pads 134 can be implemented using copper or other metal materials, and are prepared together with the first redistribution layer 130 by damascene or electroplating methods.

[0065] Figure 7 is a cross-sectional view of the stacked state of the first wafer and the second wafer. As Figure 7 shown, since the second bonding pads 134 are exposed on the surface of the first redistribution layer 130, the second bonding pads 134 can also be bonded to the passive surface 220 of the second wafer 200. Therefore, in the embodiment of the present application, "the passive surface 220 of the second wafer 200 is bonded and connected to the first redistribution layer 130 of the first wafer 100" can also be that the passive surface 220 of the second wafer 200 is bonded and connected to the first redistribution layer 130 of the first wafer 100, a plurality of first bonding pads 133 and a plurality of second bonding pads 134.

[0066] In the embodiment of the present application, the first bonding pads 133 and the second bonding pads 134 can be the same bonding pads or different bonding pads. The main difference between the two is that the first bonding pads 133 are used to connect to the through-silicon vias 233 of the second wafer 200, so that the first wafer 100 and the second wafer 200 are electrically interconnected; while the second bonding pads 134 are only connected to the passive surface 220 of the second wafer 200 and not connected to the through-silicon vias 233. Therefore, the second bonding pads 134 are used as a thermal conduction structure between the wafers in the embodiment of the present application, which can further reduce the thermal resistance between the wafers, improve the heat transfer efficiency between the wafers, and improve the heat dissipation performance after chip packaging.

[0067] In one embodiment, as Figure 8 shown, a first dielectric layer 237 is further provided on the passive surface 220 of the second wafer 200 in the embodiment of the present application. When the first dielectric layer 237 is provided on the passive surface 220 of the second wafer 200, in the embodiment of the present application, "the passive surface 220 of the second wafer 200 is bonded and connected to the first redistribution layer 130 of the first wafer 100" can also be that the first dielectric layer 237 of the second wafer 200 is bonded and connected to the first redistribution layer 130 of the first wafer 100, a plurality of first bonding pads 133 and a plurality of second bonding pads 134.

[0068] In the embodiments of the present application, the first dielectric layer 237 can be prepared using a high thermal conductivity material, such as silicon carbide, diamond, graphene, or silicon nitride, etc., to reduce the thermal resistance between the first wafer 100 and the second wafer 200 and improve the heat dissipation performance after chip packaging.

[0069] It should be added that a chip packaged using 3D IC technology may include two or more layers of wafers stacked on top of each other, and the stacking structure of the first wafer 100 and the second wafer 200 shown in the embodiments of the present application can be the stacking structure adopted by any two adjacent layers of wafers in the chip. In a chip with multiple layers of wafers, any two adjacent layers of wafers can adopt the same or different stacking structures. For example, all adjacent two layers of wafers adopt the stacking structure such as that of the first wafer 100 and the second wafer 200, or only some adjacent two layers of wafers adopt the stacking structure such as that of the first wafer 100 and the second wafer 200. These structural designs do not exceed the protection scope of the embodiments of the present application.

[0070] Figure 9 and Figure 10 are an exploded view and a cross-sectional view of a multi-layer chip stacking structure shown in the embodiments of the present application.

[0071] As Figure 9 and Figure 10 shown, the chip stacking structure includes: multiple layers of wafers stacked on top of each other, such as wafer wafer1, wafer wafer2, wafer wafer3,..., wafer wafer N. Among them, any two adjacent wafers can be used as the first wafer and the second wafer in the embodiments of the present application and have the stacking structure of the first wafer and the second wafer in the embodiments of the present application.

[0072] Exemplarily, wafer wafer1 can be implemented as the first wafer, and the redistribution layer RDL1 of wafer wafer1 can correspondingly be implemented as the first redistribution layer; wafer wafer2 can be implemented as the second wafer corresponding to wafer wafer1, and the redistribution layer RDL2 of wafer wafer2 can correspondingly be implemented as the second redistribution layer. The passive surface 322 of wafer wafer2 is bonded to the redistribution layer RDL1 of wafer wafer1, multiple first bonding pads 133, and multiple second bonding pads 134. Multiple through-silicon vias 233 are provided on wafer wafer2. One end of each through-silicon via 233 is connected to at least one of the multiple first bonding pads 133 of wafer wafer1, and the other end is connected to the metal wiring 132 of the redistribution layer RDL2 of wafer wafer2 to achieve electrical interconnection between wafer wafer1 and wafer wafer2.

[0073] Exemplarily, wafer 2 can be implemented as the first wafer, and the redistribution layer RDL2 of wafer 2 can accordingly be implemented as the first redistribution layer; wafer 3 can be implemented as the second wafer corresponding to wafer 2, and the redistribution layer RDL3 of wafer 3 can accordingly be implemented as the second redistribution layer. The passive surface 332 of wafer 3 is bonded to the redistribution layer RDL2 of wafer 2, a plurality of first bonding pads 133, and a plurality of second bonding pads 134. Wafer 3 is provided with a plurality of through-silicon vias 233. One end of each through-silicon via 233 is connected to at least one of the plurality of first bonding pads 133 of wafer 2, and the other end is connected to the metal wiring 132 of the redistribution layer RDL3 of wafer 3, realizing the electrical interconnection between wafer 2 and wafer 3.

[0074] For other wafers, for example, the stacking structure of wafer m and wafer m + 1 (m is a natural number, m + 1 ≤ N) can also be referred to Figure 9 and Figure 10 the stacking structure shown. Wherein, when wafer m is implemented as the first wafer, wafer m + 1 can be implemented as the second wafer, and this is not elaborated in the embodiments of the present application.

[0075] Figure 9 and Figure 10 The chip stacking structure shown can be applied to stacked dynamic random access memory (stacked DRAM), 3D NAND flash memory, and other chips that require stacking and packaging of wafers.

[0076] Among them, stacked DRAM can be, for example, high-bandwidth memory (HBM). When Figure 9 and Figure 10 the chip stacking structure shown is applied to HBM, it can effectively reduce the wafer stacking thickness of HBM, enable HBM to stack more wafers under the same thickness, and enable HBM to provide higher bandwidth and larger capacity in a smaller volume; Figure 9 and Figure 10 the chip stacking structure shown can also improve the heat dissipation performance of HBM, which is beneficial to increasing the frequency of HBM and enabling HBM to exhibit higher performance.

[0077] When Figure 9 and Figure 10When the shown chip stacking structure is applied to 3D NAND flash memory, it can effectively reduce the wafer stacking thickness of 3D NAND flash memory, enabling 3D NAND flash memory to stack more wafers at the same thickness. For example, it can stack from the existing 96-layer and 128-layer wafers to more layers, allowing 3D NAND flash memory to provide a larger capacity in a smaller volume. Figure 9 and Figure 10 The shown chip stacking structure can also improve the heat dissipation performance of 3D NAND flash memory, which is beneficial to improving the continuous read and write performance of 3D NAND flash memory.

[0078] It should be added that, as Figure 10 shown, in the stacking structure of multiple wafers, the redistribution layer RDL N of the topmost wafer waferN can be provided with solder balls 236. Through these solder balls 236, the packaged chip can be integrated onto an external substrate or a printed circuit board, enabling the chip to form an electrical connection with the external substrate or printed circuit board PCB.

[0079] Figure 11 is a schematic structural diagram of an integrated chip shown in an embodiment of the present application. The integrated chip includes a substrate and at least one chip. Among them, a part of the chips (hereinafter referred to as chip 1) can have Figure 9 and Figure 10 the shown chip stacking structure, and another part of the chips (hereinafter referred to as chip 2) can have other forms of chip stacking structures. Among them, chip 1 can form an electrical connection with the substrate 238 through the solder balls 236. Chip 2 can include multiple wafers, and these multiple wafers can be packaged using the chip stacking structure provided by the embodiment of the present application, or can also be packaged using other chip stacking structures, such as connection structures like an interposer 239.

[0080] As an example, Figure 11 the shown integrated chip can be a graphics processing unit (GPU). Among them, chip 1 can be the video memory chip of the graphics processor, such as an HBM video memory chip, and chip 2 can be the system on chip (SOC) of the graphics processor. At least one system chip and multiple HBM video memory chips can be included in a graphics processor. The chip stacking structure provided by the embodiment of the present application can enable the HBM video memory chip to provide higher bandwidth and larger capacity in a smaller volume, which is beneficial to improving the performance of the graphics processor.

[0081] Embodiment 2

[0082] Embodiment 2 of the present application provides a method for manufacturing a chip stacking structure, which can be used to manufacture the chip stacking structures of Embodiment 1 and its various embodiments of the present application. The method may include the following steps S101 to step S104:

[0083] Step S101, prepare a first redistribution layer and a plurality of first bonding pads on the active surface of the first wafer. The plurality of first bonding pads are exposed on the surface of the first redistribution layer parallel to the first wafer, and the plurality of first bonding pads are electrically connected to the metal wiring of the first redistribution layer.

[0084] The first redistribution layer includes a dielectric layer and metal wiring. Among them, the dielectric layer can be formed by depositing materials such as silicon dioxide on the active surface of the first wafer using the PECVD method; the metal wiring can be prepared together with the first bonding pads. For example, use the damascene process to etch the metal wiring and the pattern film for the first bonding pads on the dielectric layer, and then fill the metal to form the metal wiring and the first bonding pads, or use electroplating to prepare the metal wiring and the first bonding pads on the dielectric layer. It should be noted that the finally prepared first bonding pads need to be exposed on the surface of the first redistribution layer.

[0085] To obtain the first bonding pads exposed on the surface of the first redistribution layer, step S101 can be implemented through steps S201 to step S202 as Figure 12 shown:

[0086] Step S201, prepare a first redistribution layer 130 with a thickness greater than a preset target thickness H on the active surface 110 of the first wafer 100, and a plurality of first bonding pads 133 hidden in the first redistribution layer 130.

[0087] Among them, the target thickness H refers to the thickness of the first redistribution layer determined during chip design. The target thickness H can be determined according to design rules, and the design rules can be parameters provided by semiconductor manufacturers, for example, to ensure that the target thickness H meets the parameter requirements for manufacturing.

[0088] In the first redistribution layer 130 with a thickness greater than the target thickness H, both the metal wiring 132 and the first bonding pads 133 are hidden in the dielectric layer 131 of the first redistribution layer 130. Among them, the first bonding pads 133 have a certain depth in the direction perpendicular to the active surface 110 of the first wafer 100, and the distance L between the end of the first bonding pads 133 far from the active surface 110 and the active surface 110 is greater than the target thickness H.

[0089] Step S202, through material removal processing, thin the first redistribution layer 130 to the target thickness H, so that a plurality of first bonding pads 133 are exposed on the surface of the first redistribution layer 130 parallel to the first wafer 100.

[0090] In a specific implementation, the CMP process can be used to remove materials from the first redistribution layer 130, thinning the first redistribution layer 130 to a target thickness, and then changing the first bonding pad 133 from the hidden state after step S201 to an exposed state. During the CMP process, an oxide layer may be generated on the exposed surface of the first bonding pad 133. Therefore, after CMP, chemical cleaning or plasma cleaning can be used to remove the oxide layer. Among them, the chemical cleaning method is, for example, formic acid cleaning, and the plasma cleaning method is, for example, argon plasma cleaning, which will not be elaborated here.

[0091] In addition, during the CMP process, the first bonding pad 133 is subject to the dish effect and forms a dish-shaped profile dish on the exposed surface. Since the material of the first bonding pad 133 is different from that of its surrounding dielectric 131, the dish-shaped profile will form a shallow groove, which can be used as the expansion margin for metal creep and plastic deformation during the subsequent bonding process. It should be added that since the first bonding pad 133 in the embodiment of the present application does not need to be connected to the solder ball, during the CMP process, it is not necessary to precisely control the depth of the dish in the process, as long as the expansion margin is retained. Therefore, the method of the embodiment of the present application improves the feasibility of process control and reduces the production cost.

[0092] In an implementable embodiment, an exposed second bonding pad is further provided on the surface of the first redistribution layer. Then, in order to fabricate the second bonding pad, step S101 can also be implemented through Figure 13 the steps S301 and S302 shown below:

[0093] Step S301, prepare a first redistribution layer 130 with a thickness greater than the preset target thickness H on the active surface 110 of the first wafer 100, as well as a plurality of first bonding pads 133 and a plurality of second bonding pads 134 hidden in the first redistribution layer 130.

[0094] In the first redistribution layer 130 with a thickness greater than the target thickness H, the metal wiring 132, the first bonding pad 133, and the second bonding pad 134 are all hidden in the dielectric layer 131 of the first redistribution layer 130. Among them, the first bonding pad 133 and the second bonding pad 134 both have a certain depth in the direction perpendicular to the active surface 110 of the first wafer 100, and the distance between the ends of the first bonding pad 133 and the second bonding pad 134 far from the active surface 110 and the active surface 110 is greater than the target thickness H.

[0095] Step S302, through material removal processing, thin the first redistribution layer 130 to the target thickness H, so that a plurality of first bonding pads 133 and a plurality of second bonding pads 134 are exposed on the surface of the first redistribution layer 130 parallel to the first wafer 100.

[0096] In the embodiments of the present application, the first bonding pad 133 and the second bonding pad 134 may be the same bonding pad or different bonding pads. The main difference between the two is that the first bonding pad 133 is used to connect to the through-silicon via of the second wafer, enabling electrical interconnection between the first wafer 100 and the second wafer; while the second bonding pad 134 is only connected to the passive surface of the second wafer and not to the through-silicon via. Therefore, the second bonding pad 134 is used as a heat conduction structure between the wafers in the embodiments of the present application, which can reduce the thermal resistance between the wafers, improve the heat transfer efficiency between the wafers, and improve the heat dissipation performance after chip packaging.

[0097] Step S102: Bond the passive surface of the second wafer to the first redistribution layer and a plurality of first bonding pads.

[0098] In a specific implementation, as Figure 14 shown, the passive surface 220 of the second wafer 200 and the first redistribution layer 130 can be first activated, and then the passive surface 220 of the second wafer 200 is connected to the first redistribution layer 130 by means of silicon fusion bonding. Since the first redistribution layer 130 is also provided with the exposed first bonding pad 133, the first bonding pad 133 can also be bonded to the passive surface 220 of the second wafer 200. Additionally, if the first redistribution layer is also provided with the exposed second bonding pad 134, then the second bonding pad 134 can also be bonded to the passive surface 220 of the second wafer 200. Therefore, the connection method between the first wafer 100 and the second wafer 200 in the embodiments of the present application is between silicon fusion bonding and hybrid bonding.

[0099] Step S103: Etch a plurality of through-silicon vias in the second wafer, and one end of each through-silicon via located on the passive surface of the second wafer is connected to at least one of the plurality of first bonding pads.

[0100] In a specific implementation, as Figure 15As shown, the projection position of the through-silicon via 233 can be determined on the active surface 210 of the second wafer 200 according to the position of the first bonding pad 133; then, perpendicular to the active surface 210 of the second wafer 200, the through-silicon via 233 is etched from the determined projection position towards the first bonding pad 133. During the etching process, by controlling the etching depth, the bottom of the through-silicon via 233 can be gradually moved closer to the first bonding pad 133 until the first bonding pad 133 is exposed; next, a seed layer connected to the first bonding pad 133 is sputtered on the inner surface of the through-silicon via 233; finally, metal electroplating is performed on the surface of the seed layer to prepare the metal filler 235 for realizing electrical interconnection between the first wafer 100 and the second wafer 200. In the method of the embodiment of the present application, no additional dielectric etching is generated during the etching of the through-silicon via 233, only the wafer body silicon is etched, and there is no need to select an etching selectivity for different materials, avoiding the problems of fin-shaped etching topography and drum-shaped etching topography formed in the dielectric layer due to inappropriate etching selectivity, ensuring the continuity of the seed layer and the metal filler 235, and improving the connection reliability between the first wafer 100 and the second wafer 200.

[0101] In the embodiment of the present application, the through-silicon via 233 can be prepared by different processes such as via-first, via-middle, or via-last; among them, the via-first process means preparing the through-silicon via 233 before preparing the second redistribution layer of the second wafer 200, the via-middle process means preparing the through-silicon via 233 during the preparation of the second redistribution layer; the via-last process means preparing the through-silicon via 233 after preparing the second redistribution layer; the embodiment of the present application does not specifically limit the manufacturing process of the above through-silicon via 233.

[0102] Step S104, a second redistribution layer is prepared on the active surface of the second wafer. The second redistribution layer is provided with a plurality of metal pad disks, and the plurality of metal pad disks are electrically connected to the metal wiring of the second redistribution layer; one end of each through-silicon via located on the active surface of the second wafer is connected to at least one of the plurality of metal pad disks.

[0103] As Figure 16As shown, the second rewiring layer 230 is composed of a dielectric layer 231 and a metal wiring 232. The dielectric layer 231 can be formed by depositing materials such as silicon dioxide on the active surface 210 of the second wafer 200 using the PECVD method; the metal wiring 232 can be prepared together with the metal pad 234, for example, a Damascus process is used to etch a pattern for the metal wiring 232 and the metal pad 234 on the dielectric layer 231, and then a metal filler is formed to form the metal wiring 232 and the metal pad 234, or the metal wiring 232 and the metal pad 234 are prepared on the dielectric layer by electroplating. It should be noted that the metal pad 234 finally prepared needs to be connected to the metal filler 235 prepared in step S103. At this point, the first bonding pad 133 is electrically connected to the metal pad 234 through the metal filler 235, so that the first wafer 100 and the second wafer 200 establish an electrical interconnection channel.

[0104] It should be noted that if the second wafer 200 is the topmost wafer of the chip, the second redistribution layer 230 may be provided with solder balls 236, through which the packaged chip may be mounted on an external substrate or printed circuit board, so that the chip is electrically connected to the external substrate or printed circuit board PCB.

[0105] The manufacturing method of the chip stacking structure of the embodiment of the present application directly bonds the first rewiring layer 130 of the first wafer 100 and the passive surface 220 of the second wafer 200, so there is no need to prepare an additional dielectric layer or use solder balls on the bonding surface, which can reduce the thickness of the first wafer 100 and the second wafer 200 after stacking by at least the thickness generated by the additional dielectric layer and solder balls, so that the size of the chip after packaging is smaller and thinner. In addition, after the additional dielectric layer is omitted, the thermal resistance of the first wafer 100 and the second wafer 200 after stacking is reduced, which is conducive to the transfer of heat between the wafers and improves the heat dissipation performance of the chip. In addition, the first rewiring layer 130 of the first wafer 100 is also provided with an exposed first bonding pad 133, and the second wafer 200 is also provided with a silicon through hole 233 connected to the first bonding pad 133, so that the first wafer 100 and the second wafer 200 can be directly electrically interconnected through the silicon through hole 233, without the need for solder balls and etching dielectric layers, so the structure is simple, the process steps are simplified, and the connection reliability is high.

[0106] In an alternative embodiment, Figure 17As shown, a first dielectric layer 237 may also be fabricated on the passive surface 220 of the second wafer 200. When the first dielectric layer 237 is fabricated on the passive surface 220 of the second wafer 200, step S102 is specifically implemented as follows: the first dielectric layer 237 of the second wafer 200 is bonded to the redistribution layer 130, the first bonding pad 133, and the second bonding pad 134 of the first wafer 100. The first dielectric layer 237 may be fabricated using a highly thermally conductive material, such as silicon carbide, diamond, graphene, or silicon nitride, etc., to reduce the thermal resistance between the first wafer 100 and the second wafer 200 and improve the heat dissipation performance after chip packaging.

[0107] In the example of this application, steps S101 to S104 are used as the basic steps to fabricate a double-layer chip stack structure. It is easy to understand that the above basic steps may also be executed in whole or in part repeatedly, or executed repeatedly in a combined or split manner to fabricate a multi-layer chip stack structure, and these implementation manners do not exceed the protection scope of the embodiments of this application.

[0108] The embodiments of this application also provide a computer chip, which includes but is not limited to a central processing unit (CPU), a graphics processing unit (GPU), a system on chip (SOC), a 3D NAND chip, a stacked dynamic random access memory (stacked DRAM), and a high-bandwidth memory (HBM), etc. The above computer chip may include, for example, a substrate and multiple wafers packaged on the substrate, where some or all of the multiple wafers include the chip stack structure of one of the embodiments of this application.

[0109] The embodiments of this application also provide an electronic device, which includes but is not limited to a graphics card, a solid-state drive (SSD), a USB flash drive, a mobile phone, a personal computer, a server, a workstation, etc. The electronic device includes at least one printed circuit board (PCB) and at least one computer chip disposed on the at least one printed circuit board, where some or all of the at least one computer chip include the chip stack structure of one of the embodiments of this application.

Claims

1. A chip stacking structure, characterized in that, Comprising: A first wafer, on the active surface of which a first redistribution layer is provided; A plurality of first bonding pads, which are exposed on the surface of the first redistribution layer parallel to the first wafer, and the plurality of first bonding pads are electrically connected to the metal wirings of the first redistribution layer; A second wafer, which is stacked with the first wafer, and the passive surface of the second wafer is bonded to the first redistribution layer and the plurality of first bonding pads; the second wafer is provided with a plurality of through-silicon vias, and the first end of each through-silicon via located on the passive surface of the second wafer is connected to at least one of the plurality of first bonding pads; A plurality of second bonding pads, which are exposed on the surface of the first redistribution layer parallel to the first wafer, and the plurality of second bonding pads are bonded to the passive surface of the second wafer, and the plurality of second bonding pads are electrically connected to the metal wirings of the first redistribution layer; A first dielectric layer is provided on the passive surface of the second wafer, and the passive surface of the second wafer is bonded to the first redistribution layer, the plurality of first bonding pads and the plurality of second bonding pads through the first dielectric layer.

2. The chip stacking structure according to claim 1, wherein A second redistribution layer is provided on the active surface of the second wafer, and the second redistribution layer is provided with a plurality of metal pad disks, and the plurality of metal pad disks are electrically connected to the metal wirings of the second redistribution layer; one end of each through-silicon via located on the active surface of the second wafer is connected to at least one of the plurality of metal pad disks.

3. The chip stacking structure according to claim 2, wherein Each through-silicon via is filled with a metal filler, and the metal filler is used to electrically connect the first bonding pad it is connected to and the metal pad disk.

4. The chip stacking structure according to claim 3, wherein The metal filler is obtained by sputtering a seed layer connected to the first bonding pad on the inner surface of the through-silicon via and performing metal electroplating on the surface of the seed layer.

5. A manufacturing method of a chip stacking structure, characterized in that, Comprising: Preparing a first redistribution layer and a plurality of first bonding pads on the active surface of the first wafer, the plurality of first bonding pads are exposed on the surface of the first redistribution layer parallel to the first wafer, and the plurality of first bonding pads are electrically connected to the metal wirings of the first redistribution layer; Bonding the passive surface of the second wafer to the first redistribution layer and the plurality of first bonding pads; Etching the second wafer to form a plurality of through-silicon vias, and one end of each through-silicon via located on the passive surface of the second wafer is connected to at least one of the plurality of first bonding pads; Preparing a plurality of second bonding pads hidden in the first redistribution layer on the active surface of the first wafer, and when the first redistribution layer is thinned to a target thickness, the plurality of second bonding pads are exposed on the surface of the first redistribution layer; The bonding the passive surface of the second wafer to the first redistribution layer and the plurality of first bonding pads includes: preparing a first dielectric layer on the passive surface of the second wafer; Bond the first dielectric layer to the first redistribution layer, the first bonding pad, and the second bonding pad.

6. The method according to claim 5, characterized in that, Preparing a first redistribution layer and a plurality of first bonding pads on the active surface of the first wafer includes: Preparing the first redistribution layer with a thickness greater than a preset target thickness and the plurality of first bonding pads hidden within the first redistribution layer on the active surface of the first wafer; Thin the first redistribution layer to the target thickness by material removal processing, exposing the plurality of first bonding pads parallel to the surface of the first wafer in the first redistribution layer.

7. The method according to claim 5, characterized in that Etching a plurality of through-silicon vias in the second wafer, with one end of each through-silicon via located on the passive surface of the second wafer connected to at least one of the plurality of first bonding pads, includes: Determine the projection positions of at least one first bonding pad on the active surface of the second wafer; Etch the through-silicon vias perpendicular to the active surface of the second wafer starting from the projection positions in the direction of the first bonding pads until the through-silicon vias contact the at least one first bonding pad.

8. The method according to any one of claims 5 to 7, characterized in that Further includes: Preparing a second redistribution layer on the active surface of the second wafer, the second redistribution layer being provided with a plurality of metal pad disks, the plurality of metal pad disks being electrically connected to the metal wiring of the second redistribution layer; one end of each through-silicon via located on the active surface of the second wafer is connected to at least one of the plurality of metal pad disks.

9. The method according to claim 8, characterized in that Further includes: Form a seed layer connected to the first bonding pad on the inner surface of the through-silicon via by surface sputtering; Perform metal electroplating on the surface of the seed layer to form metal fillers, and the metal fillers electrically connect the first bonding pad to the metal pad disk.

10. An electronic device, characterized in that, Includes a printed circuit board PCB and at least one computer chip disposed on the printed circuit board, and part or all of the at least one computer chip has the chip stack structure according to any one of claims 1-4.

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