Ferroelectric memory devices containing two-dimensional charge carrier channels and methods of making the same

Abstract

A ferroelectric memory device includes a two-dimensional electron gas channel, a gate electrode, and a ferroelectric element between the gate electrode and the two-dimensional electron gas channel.

Description

[0001] Related applications

[0002] This application claims priority to U.S. Non-Provisional Application No. 16 / 798,643 and U.S. Non-Provisional Application No. 16 / 798,686, filed on February 24, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to the field of semiconductor devices, and more specifically to ferroelectric memory devices employing two-dimensional charge-carrying gas channels and methods for manufacturing the same. Background Technology

[0004] Ferroelectric memory devices are memory devices containing ferroelectric materials for storing information. The ferroelectric material acts as the memory material in the memory device. Depending on the polarity of the electric field applied to the ferroelectric material, the dipole moment of the ferroelectric material is programmed with two different orientations (e.g., "up" or "down" polarization positions based on atomic positions in the crystal lattice, such as oxygen and / or metal atom positions) to store information in the ferroelectric material. The different orientations of the dipole moment of the ferroelectric material can be detected by the electric field generated by the dipole moment. For example, the orientation of the dipole moment can be detected by measuring the current flowing through a semiconductor channel adjacent to the ferroelectric material in a field-effect transistor ferroelectric memory device. Summary of the Invention

[0005] According to one aspect of this disclosure, a ferroelectric memory device includes a two-dimensional electron gas channel, a gate electrode, and a ferroelectric element located between the gate electrode and the two-dimensional electron gas channel.

[0006] According to another aspect of this disclosure, a method for forming a single three-dimensional memory device is provided, the method comprising: forming an alternating stack of insulating layers and spacer material layers over a substrate, wherein the spacer material layers are formed as conductive layers or subsequently replaced by conductive layers; forming a memory opening through the alternating stack; forming a ferroelectric memory element at the periphery of the memory opening at each layer of the spacer material layers; and forming a two-dimensional electron gas channel directly on the ferroelectric memory element in the memory opening.

[0007] According to another aspect of this disclosure, a memory device is provided, the memory device comprising: at least one cell layer stack located above a substrate, wherein the cell layer stack includes a metal source layer, a channel-level insulating layer, a metal drain layer, and a device isolation-level insulating layer; and a plurality of memory openings extending vertically through the at least one cell layer stack; and memory opening filling structures located within a corresponding one of the plurality of memory openings, wherein each of the memory opening filling structures includes a tubular ferroelectric dielectric layer and at least one two-dimensional cylindrical electron gas channel, the at least one two-dimensional cylindrical electron gas channel extending vertically between the metal source layer and the metal drain layer of the at least one cell layer stack.

[0008] According to another aspect of this disclosure, the memory device includes: a two-dimensional electron gas channel located on a substrate; a source region and a drain region located at the end portions of the two-dimensional electron gas channel; a two-dimensional van der Waals ferroelectric material layer located on the two-dimensional electron gas channel and comprising a ferroelectric material selected from CuInP2S6, a-In2Se3, g-SbP, g-SbAs, or a group IV monochalcogenide material having the MX form, wherein M is selected from Ge, Sn, or Pb, and X is selected from S, Se, or Te; and at least one gate electrode located above the two-dimensional van der Waals ferroelectric material layer.

[0009] According to another aspect of this disclosure, a ferroelectric memory device includes: a channel; a gate electrode; a ferroelectric element located between the gate electrode and the channel, wherein the ferroelectric element includes a two-dimensional van der Waals ferroelectric material layer comprising a ferroelectric material selected from CuInP2S6, a-In2Se3, g-SbP, g-SbAs, or a group IV monochalcogenide material having the MX form, wherein M is selected from Ge, Sn, or Pb, and X is selected from S, Se, or Te; and a first interface dielectric layer located between the ferroelectric element and the gate electrode.

[0010] According to one aspect of this disclosure, a ferroelectric memory device comprises a two-dimensional semiconductor material layer having a band gap of at least 1.1 eV and a thickness of at least one of one to five monolayers of semiconductor material; or includes a two-dimensional charge carrier layer; a source contact contacting a first portion of the two-dimensional semiconductor material layer; a drain contact contacting a second portion of the two-dimensional semiconductor material layer; a ferroelectric memory element located between the source and drain contacts and adjacent to a first surface of the two-dimensional semiconductor material layer; and a conductive gate electrode located adjacent to the ferroelectric memory element.

[0011] According to another aspect of this disclosure, a method for operating a ferroelectric memory device is provided. The polarization direction of the ferroelectric memory element can be programmed by applying a positive bias voltage or a negative bias voltage relative to a two-dimensional semiconductor material layer to a conductive gate electrode. The polarization direction of the ferroelectric memory element can be sensed by measuring the magnitude of the current between the source and drain contacts at a read voltage between the source and drain contacts.

[0012] According to another aspect of this disclosure, a method of manufacturing a ferroelectric memory device includes forming a two-dimensional semiconductor material layer; forming a ferroelectric memory element directly on a first surface of the two-dimensional semiconductor material layer; forming a conductive gate electrode on the ferroelectric memory element; forming a source contact on a first end portion of the two-dimensional semiconductor material layer; and forming a drain contact on a second end portion of the two-dimensional semiconductor material layer. Attached Figure Description

[0013] Figure 1 It is a perspective view of a metal-ferroelectric semiconductor structure.

[0014] Figure 2A yes Figure 1 Potential diagram of the first polarization state of the metal-ferroelectric semiconductor structure.

[0015] Figure 2B yes Figure 1 Potential diagram of the second polarization state of the metal-ferroelectric semiconductor structure.

[0016] Figure 3 This is a graph showing the variation of the electrostatic potential at the interface between the ferroelectric material portion and the metal portion with the ferroelectric thickness of the metal-ferroelectric semiconductor structure with two selected ferroelectric polarization densities.

[0017] Figure 4 It is a graph showing how conductivity varies with the Fermi level of a two-dimensional general-purpose semiconductor material.

[0018] Figure 5 This is a graph showing the density of per atom per electron volt of pristine graphene and fluorinated graphene calculated within a tight-binding model.

[0019] Figure 6 This is a graph showing how conductivity varies with the Fermi level of pristine graphene and fluorinated graphene calculated within the tight-binding model.

[0020] Figure 7 This is a first exemplary structure according to a first embodiment of the present disclosure.

[0021] Figure 8 This is a second exemplary structure according to a second embodiment of the present disclosure.

[0022] Figure 9 This is a third exemplary structure according to a third embodiment of the present disclosure.

[0023] Figure 10A This is a vertical cross-sectional view of a fourth exemplary structure according to a fourth embodiment of the present disclosure.

[0024] Figure 10B yes Figure 10A A schematic perspective view of the fourth exemplary structure.

[0025] Figure 11 The calculated density per atom per electron volt of hexagonal boron nitride is shown based on density function theory (DFT) and hybridization function.

[0026] Figure 12 The calculated density of molybdenum disulfide per atom per electron volt state is shown based on density function theory (DFT) and hybridization function.

[0027] Figure 13A This is a graph showing how the conductivity of hexagonal boron nitride varies with polarization calculated within the tight-binding model.

[0028] Figure 13B This is a graph showing how the electrical conductivity of fluorinated graphene changes with polarization calculated within the tight-binding model.

[0029] Figure 13C This is a graph showing how the conductivity of molybdenum disulfide varies with polarization calculated within a tight-binding model.

[0030] Figure 13D This is a graph showing how the conductivity of single germanium varies with polarization calculated within a tight-binding model.

[0031] Figure 14 This is a schematic diagram of a ferroelectric memory device according to an embodiment of the present disclosure.

[0032] Figure 15 This is a vertical cross-sectional view of a fifth exemplary structure after the formation of a field-effect transistor and a semiconductor material layer, according to a fifth embodiment of the present disclosure.

[0033] Figure 16 This is a vertical cross-sectional view of a fifth exemplary structure following the alternating stacking of insulating and sacrificial material layers, according to a fifth embodiment of this disclosure.

[0034] Figure 17 This is a vertical cross-sectional view of a fifth exemplary structure after the formation of the reverse stepped dielectric material portion, according to a fifth embodiment of the present disclosure.

[0035] Figure 18AThis is a vertical cross-sectional view of a fifth exemplary structure after the formation of the memory opening and the support opening, according to a fifth embodiment of the present disclosure.

[0036] Figure 18B It is along Figure 18A A top view of the fifth exemplary structure in the vertical plane A-A'.

[0037] Figures 19A to 19J This is a sequential vertical cross-sectional view of the memory opening during the formation of the first exemplary memory opening filling structure, according to a fifth embodiment of the present disclosure.

[0038] Figure 19K It is an alternative construction to the first exemplary memory opening-filling structure according to the fifth embodiment of this disclosure.

[0039] Figure 20A This is a diagram illustrating the compositional variations in a tubular ferroelectric dielectric layer according to a fifth embodiment of the present disclosure.

[0040] Figure 20B This is a band diagram of the tubular ferroelectric dielectric layer during an erasure operation, according to the fifth embodiment of this disclosure.

[0041] Figure 20C This is a strip diagram of the tubular ferroelectric dielectric layer during programming operation according to the fifth embodiment of this disclosure.

[0042] Figures 21A to 21C This is a sequential vertical cross-sectional view of the memory opening during the formation of the second exemplary memory opening filling structure, according to a sixth embodiment of the present disclosure.

[0043] Figure 21D This is an alternative implementation of the second exemplary structure according to the sixth embodiment of this disclosure.

[0044] Figure 22A This is a vertical cross-sectional view of a memory opening including a third exemplary memory opening filling structure according to a seventh embodiment of the present disclosure.

[0045] Figure 22B This is a vertical cross-sectional view of a memory opening, including an alternative construction of a third exemplary memory opening filling structure, according to a seventh embodiment of this disclosure.

[0046] Figure 23 This is a vertical cross-sectional view of a fourth exemplary structure after the formation of a memory stack structure, according to an eighth embodiment of the present disclosure.

[0047] Figure 24A This is a vertical cross-sectional view of a fourth exemplary structure after the formation of the back-side groove, according to the eighth embodiment of this disclosure.

[0048] Figure 24B yes Figure 24A A partial perspective top view of the fourth exemplary structure. Vertical plane A-A' is... Figure 24A The plane of the vertical cross-sectional view.

[0049] Figure 25 This is a vertical cross-sectional view of a fourth exemplary structure after the formation of the back recess, according to an embodiment of the present disclosure.

[0050] Figure 26A This is a vertical cross-sectional view of a fourth exemplary structure after the formation of a conductive layer, according to an eighth embodiment of the present disclosure.

[0051] Figure 26B yes Figure 26A An enlarged view of the area surrounding the memory opening filling structure in an alternative embodiment of the fourth exemplary structure.

[0052] Figure 26C yes Figure 26A An enlarged view of the area surrounding the memory opening filling structure in another alternative embodiment of the fourth exemplary structure.

[0053] Figure 27 This is a vertical cross-sectional view of a fourth exemplary structure after the formation of the back-side contact through-hole structure, according to the eighth embodiment of this disclosure.

[0054] Figure 28A This is a vertical cross-sectional view of a fourth exemplary structure after the formation of an additional contact via structure, according to the eighth embodiment of this disclosure.

[0055] Figure 28B yes Figure 28A A partial perspective top view of the fourth exemplary structure. Vertical plane A-A' is... Figure 28A The plane of the vertical cross-sectional view.

[0056] Figure 29 This is a vertical cross-sectional view of a fifth exemplary structure, according to a ninth embodiment of the present disclosure, after forming multiple instances of a unit layer including a source level sacrificial layer, a channel level insulating layer, a drain level sacrificial layer, and a device isolation level insulating layer, and after forming an insulating cap layer over a substrate.

[0057] Figure 30 This is a vertical cross-sectional view of a fifth exemplary structure after the formation of a stepped surface and a reverse stepped dielectric material portion, according to a ninth embodiment of this disclosure.

[0058] Figure 31 This is a vertical cross-sectional view of a fifth exemplary structure after the array of memory openings is formed, according to a ninth embodiment of the present disclosure.

[0059] Figure 32 This is a vertical cross-sectional view of a fifth exemplary structure after the formation of the channel-level recess, according to a ninth embodiment of the present disclosure.

[0060] Figure 33 This is a vertical cross-sectional view of a fifth exemplary structure after the formation of a two-dimensional electron gas channel, according to a ninth embodiment of the present disclosure.

[0061] Figure 34A This is a vertical cross-sectional view of a fifth exemplary structure after the formation of the memory opening filling structure, according to a ninth embodiment of the present disclosure.

[0062] Figure 34B yes Figure 34A A vertical cross-sectional view of the fifth exemplary structure.

[0063] Figure 35A This is a vertical cross-sectional view of a fifth exemplary structure after the formation of the back-side groove, according to a ninth embodiment of the present disclosure.

[0064] Figure 35B yes Figure 35A A vertical cross-sectional view of the fifth exemplary structure.

[0065] Figure 36 This is a vertical cross-sectional view of a fifth exemplary structure after the formation of the active stage back recess, according to the ninth embodiment of this disclosure.

[0066] Figure 37 This is a vertical cross-sectional view of a fifth exemplary structure after the formation of the source and drain layers, according to a ninth embodiment of this disclosure.

[0067] Figure 38A This is a vertical cross-sectional view of a fifth exemplary structure after the formation of the contact via structure, according to a ninth embodiment of this disclosure.

[0068] Figure 38B yes Figure 38A A vertical cross-sectional view of the fifth exemplary structure.

[0069] Figure 39 This is a vertical cross-sectional view of the first construction of the sixth exemplary structure according to the tenth embodiment of this disclosure.

[0070] Figure 40 This is a vertical cross-sectional view of the second construction of the sixth exemplary structure according to the tenth embodiment of this disclosure.

[0071] Figure 41 This is a vertical cross-sectional view of the third construction of the sixth exemplary structure according to the tenth embodiment of this disclosure.

[0072] Figure 42 This is a vertical cross-sectional view of the fourth construction of the sixth exemplary structure according to the tenth embodiment of this disclosure.

[0073] Figure 43 This is a top-down view of the fifth construction of the sixth exemplary structure according to the tenth embodiment of this disclosure. Detailed Implementation

[0074] As discussed above, embodiments of this disclosure relate to ferroelectric memory devices employing two-dimensional electron gas (“2DEG”) channels, methods of operation thereof, and methods of fabrication thereof. In some embodiments, a two-dimensional semiconductor material layer comprising five monolayers or less (such as one to four monolayers of atoms of a semiconductor material) comprises a 2DEG channel layer. The ferroelectric states of the ferroelectric memory element induce orders of magnitude changes in conductivity within the channel. In some embodiments, the ferroelectric memory device may be formed in a three-dimensional memory array having a tubular ferroelectric dielectric layer.

[0075] The accompanying drawings are not to scale. Unless explicitly described or otherwise clearly indicated that no element is repeated, multiple instances of an element may be repeated where only a single instance is shown. Identical reference numerals refer to identical or similar elements. Unless otherwise expressly stated, elements with the same reference numerals are presumed to have the same material composition. Serial numbers such as “first,” “second,” and “third” are used only to identify similar elements and may be used differently throughout the specification and claims of this disclosure. The term “at least one” element refers to all possibilities, including the possibility of a single element and the possibility of multiple elements.

[0076] As used herein, a first element located "on" a second element may be located on the outer side or the inner side of the surface of the second element. As used herein, if there is physical contact between the surface of the first element and the surface of the second element, the first element is "directly" located on the second element. As used herein, if there is a conductive path consisting of at least one conductive material between the first element and the second element, the first element is "electrically connected" to the second element. As used herein, a "prototype" structure or a "process" structure refers to a transient structure in which at least one component is subsequently modified in terms of shape or composition.

[0077] As used herein, a “layer” refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper overlay structure, or may have a range smaller than that of the lower or upper overlay structure. Furthermore, a layer may be a region of uniform or non-uniform continuous structure whose thickness is less than that of the first continuous structure. For example, a layer may be positioned between the top and bottom surfaces of the first continuous structure or between any pair of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, or may have one or more layers on, above, and / or below it. As used herein, a “layer stack” refers to a stack of layers. As used herein, a “line” or “line structure” refers to a layer having a primary direction of extension (i.e., having the direction along which the layers extend the most).

[0078] As used herein, a "field-effect transistor" refers to any semiconductor device having a semiconductor channel through which current flows at a current density modulated by an external electric field. As used herein, an "active region" refers to the source region or drain region of a field-effect transistor. A "top active region" refers to the active region of a field-effect transistor located above another active region of the same transistor. A "bottom active region" refers to the active region of a field-effect transistor located below another active region of the same transistor.

[0079] As used in this article, "semiconductor material" refers to a material with a conductivity of 1.0 × 10⁻⁶ m / s. -6 S / m to 1.0×10 5 Materials with electrical conductivity in the range of S / m. As used herein, "semiconductor material" refers to a material having an electrical conductivity in the absence of electrical dopants in the presence of S / m. -6 Materials with electrical conductivity ranging from S / m to 1.0 S / m can be produced when appropriately doped with electrical dopants, exhibiting conductivity ranging from 1.0 S / m to 1.0 × 10⁻⁶. 5 Doped materials with conductivity in the range of S / m. As used herein, “electrical dopant” refers to a p-type dopant that adds holes to the valence band of the band structure, or an n-type dopant that adds electrons to the conduction band of the band structure. As used herein, “conductive material” refers to a material with conductivity greater than 1.0 × 10⁻⁶ S / m. 5 Materials with a conductivity of S / m. As used herein, "insulating material" or "dielectric material" refers to a material with a conductivity of less than 1.0 × 10⁻⁶ S / m. -6 Materials with an electrical conductivity of S / m. As used herein, "heavily doped semiconductor material" refers to a material doped with an electrically conductive agent at a sufficiently high atomic concentration to become a conductive material (i.e., having a conductivity greater than 1.0 × 10⁻⁶). 5 Semiconductor materials with a conductivity of S / m. "Doped semiconductor materials" can be heavily doped semiconductor materials, or can include those exhibiting a conductivity of 1.0 × 10⁻⁶ S / m.-6 S / m to 1.0×10 5 Semiconductor materials with electrical dopant concentrations (i.e., p-type and / or n-type dopant) in the range of S / m. "Intrinsic semiconductor material" refers to a semiconductor material that is not doped with electrical dopant. Therefore, a semiconductor material can be semiconductor or conductive, and can be intrinsic or doped. A doped semiconductor material can be semiconductor or conductive, depending on the atomic concentration of the electrical dopant present therein.

[0080] As used herein, “metallic material” refers to a conductive material that includes at least one metallic element. All conductivity measurements were performed under standard conditions. As used herein, “ferroelectric material” refers to any material that exhibits spontaneous polarization that can be reversed by the application of an external electric field.

[0081] refer to Figure 1 This illustrates a metal-ferroelectric semiconductor structure according to an embodiment of the present disclosure. In the ferroelectric memory device described below, the metal-ferroelectric semiconductor structure includes: a metal portion comprising a gate electrode 50, a ferroelectric material portion comprising a gate dielectric / ferroelectric memory element 20, and a semiconductor portion comprising a semiconductor channel 40.

[0082] refer to Figure 2A and Figure 2B , showing Figure 1 Potential diagram of the polarization states of a metal-ferroelectric semiconductor structure. Figure 2A Show Figure 1 The first polarization state of the metal-ferroelectric semiconductor structure is described, wherein the ferroelectric polarization vector P points in a positive polarization direction from the metal portion (such as gate electrode 50) to the semiconductor portion (such as semiconductor channel 40). In this case, positive ferroelectric charges exist on the side of the ferroelectric material portion (such as gate dielectric 20) at the interface with the semiconductor portion (such as semiconductor channel 40), and negative ferroelectric charges exist on the side of the ferroelectric material portion (such as gate dielectric 20) at the interface with the metal portion (such as gate electrode 50). The ferroelectric charges induce screening charges within the metal portion and the semiconductor portion. Screening charges are mobile charges (such as electrons or holes) that reduce the electric field caused by the ferroelectric charges within the ferroelectric material portion. Positive screening charges accumulate within the metal portion (such as gate electrode 50), and negative screening charges accumulate within the semiconductor portion (such as semiconductor channel 40).

[0083] Figure 2B Show Figure 1The second polarization state of the metal-ferroelectric semiconductor structure is described, where the ferroelectric polarization vector P points in a direction from the semiconductor portion (such as the semiconductor channel 40) to the metal portion (such as the gate electrode 50). In this case, negative ferroelectric charges exist on the side of the ferroelectric material portion (such as the gate dielectric 20) at the interface with the semiconductor portion (such as the semiconductor channel 40), and positive ferroelectric charges exist on the side of the ferroelectric material portion (such as the gate dielectric 20) at the interface with the metal portion (such as the gate electrode 50). The ferroelectric charges induce screening charges within the metal portion and the semiconductor portion. Negative screening charges accumulate within the metal portion (such as the gate electrode 50), and positive screening charges accumulate within the semiconductor portion (such as the semiconductor channel 40).

[0084] The screening potential at the interface between the ferroelectric material and the metallic part can be controlled by switching the polarization direction of the ferroelectric material part. The electrostatic potential V varies with the distance x from the interface between the metallic and ferroelectric material parts. c (x) decays with a characteristic decay distance, referred to as the Thomas-Fermi sieve length. If the x-axis is chosen such that the x-coordinate is positive within the ferroelectric material portion with thickness d and within the semiconductor material portion, then the electrostatic potential V in the metallic and semiconductor material portions... c (x) is governed by the following equation:

[0085]

[0086] Where λ is the Thomas-Fermi sieve length within the corresponding material portion.

[0087] The screening length λ of the metal portion (such as the gate electrode 50) is greater than that of the metal portion. l In cases where the material is much thicker, and if the semiconductor material portion (such as the semiconductor channel 40) is thinner, the electrostatic potential V of the semiconductor material portion... c The solution to (x) (i.e., x>d) is given as follows:

[0088]

[0089] Where d is the thickness of the ferroelectric material portion, P is the ferroelectric polarization of the ferroelectric material portion, ε0 is the vacuum permittivity, ε is the relative permittivity of the ferroelectric material portion (i.e., the ratio of the permittivity of the ferroelectric material portion to the vacuum permittivity), and λ l It is the Thomas-Fermi sieve length of the metallic portion, λ r λ' is the Thomas-Fermi screening length of the semiconductor material portion, l is the thickness of the semiconductor material portion, and λ' l Given from the following:

[0090]

[0091] According to one aspect of this disclosure, the electrostatic potential in the interface region of the semiconductor material portion near the ferroelectric material portion can be controlled by reversing the ferroelectric polarization within the ferroelectric material portion. For Figure 2A The positive polarization direction shown indicates that the selected charge brings the Fermi level into the conduction band of the semiconductor material. For Figure 2B As shown, the negative polarization direction filters the charge, causing the Fermi level to shift toward the band gap. Therefore, by reversing the ferroelectric polarization direction, the Fermi level moves between its position in the semiconductor band gap and its position in one of the bands (e.g., the conduction band or valence band), resulting in a significant difference between the resistive (e.g., resistivity or resistance) states of the device.

[0092] According to one aspect of this disclosure, the semiconductor material portion comprises a two-dimensional semiconductor material that provides high conductivity in a two-dimensional plane parallel to the interface between the semiconductor material portion and the ferroelectric material portion. As used herein, a two-dimensional semiconductor material refers to a semiconductor material with a thickness of 1 to 5 monolayers (such as 2 to 3 monolayers of atoms of a semiconductor material), and / or the semiconductor material contains a two-dimensional charge carrier gas, such as a two-dimensional electron gas. In one embodiment, the two-dimensional semiconductor material has a lateral extent of quantum mechanical modification of induced band structure along one direction. In one embodiment, the two-dimensional semiconductor material may have a lateral direction of less than 10 nm along one direction, which is referred to herein as the thickness direction of the two-dimensional semiconductor material.

[0093] According to one aspect of this disclosure, the semiconductor material portion includes a two-dimensional semiconductor material layer having a thickness of 1 to 5 monolayers and a band gap of at least 1 eV (such as at least 1.15 eV, for example, 1.15 eV to 5.65 eV). Alternatively, the two-dimensional semiconductor material layer may include a two-dimensional charge carrier gas (such as a two-dimensional electron gas) layer and a band gap of at least 1 eV (such as at least 1.15 eV, for example, 1.15 eV to 5.65 eV). As used herein, a two-dimensional charge carrier gas refers to a collection of charge carriers in a quantum confinement that provides enhanced conductivity in a direction perpendicular to the direction of the quantum confinement. For example, a two-dimensional electron gas is a two-dimensional charge carrier gas.

[0094] In one embodiment, the semiconductor material portion comprises a two-dimensional semiconductor material selected from the following: hexagonal boron nitride having a band gap of 5.62 eV, fluorinated graphene having a band gap of 2.93 eV, molybdenum disulfide having a band gap of 2.24 eV, and single germanium having a band gap of 1.16 eV. The list of possible candidates for two-dimensional semiconductor materials is not limited to the aforementioned materials.

[0095] Figure 3 V is the electrostatic potential at the interface between the ferroelectric material part and the metal part. c (0) Calculated within the Thomas-Fermi model Figure 1 The graph shows the variation of the ferroelectric thickness d in the metal-ferroelectric semiconductor structure. Based on this model, the electrostatic potential V at the interface between the ferroelectric material portion and the semiconductor portion is... c (0) is given by the following:

[0096]

[0097] The first curve 310 corresponds to a ferroelectric polarization of 20 μC / cm. 2 In this case, the relative permittivity of the ferroelectric material portion is 90, the Thomas-Fermi sieve length of the metallic portion is 0.2 nm, and the Thomas-Fermi sieve length of the semiconductor material portion is also 0.2 nm. The second curve 320 corresponds to a ferroelectric polarization of 40 μC / cm. 2 In this case, the relative permittivity of the ferroelectric material portion is 90, the Thomas-Fermi sieve length of the metallic portion is 0.2 nm, and the Thomas-Fermi sieve length of the semiconductor material portion is also 0.2 nm. An electrostatic potential greater than 1.0 V and / or greater than 1.5 V and / or greater than 2.0 V can be generated at the interface between the ferroelectric material portion and the metallic portion through the ferroelectric polarization effect.

[0098] Figure 4 This is a graph showing the conductivity as a function of the Fermi level of a hypothetical two-dimensional semiconductor material (e.g., for a single layer of semiconductor material). Because... Figure 4 The calculations employed a simple model based on a two-dimensional semiconductor material with a tightly bonded dual-band Hamiltonian structure. This two-dimensional semiconductor material was then used in… Figure 1 When the semiconductor material portion of a device is used, it is possible to switch the state of the two-dimensional semiconductor material between a conductive and insulating state by reversing the direction of ferroelectric polarization, such as... Figure 2A and Figure 2B As shown in the diagram. In other words, Figure 1 The shift of the Fermi level in a device can be sufficient to provide two different resistance states, such as a higher resistance state and a lower resistance state, which can be, for example, a conductive state and an insulating state.

[0099] According to the embodiments of this disclosure, conductivity is related to Figure 4 The functional dependence of the Fermi level shown can be physically represented by any suitable two-dimensional semiconductor material, such as hexagonal boron nitride, fluorinated graphene, molybdenum disulfide, or germanium mononitride.

[0100] Table 1 below shows the calculated band gap and conduction band in-situ energy for various materials that can be used in the ferroelectric memory devices of this disclosure. The band gap value is calculated from the first-principles electronic structure based on the hybridization function, and the in-situ energy is fitted tightly to reproduce the calculated band structure.

[0101] Table 1: Bandgap and conduction band in-situ energy of two-dimensional semiconductor materials

[0102] Two-dimensional semiconductor materials Band gap (eV) Conduction band potential energy (eV) Hexagonal BN 5.62 6.81 <![CDATA[MoS2]]> 2.24 5.12 Fluorinated graphene 2.93 5.465 single germanium 1.16 4.58

[0103] A list of other suitable highly stable two-dimensional semiconductor materials and their band gaps calculated in the DFT are shown in Table 2. It is known that the DFT underestimates the band gap value, therefore the actual band gap is expected to be larger.

[0104] Table 2: Bandgap of Additional Two-Dimensional Semiconductor Materials

[0105]

[0106]

[0107]

[0108]

[0109] Primitive graphene (i.e., graphene without defects or dopants) is an electrical conductor lacking a band gap, while fluorinated graphene is a semiconductor with a band gap. Figure 5 This is a graph showing the density of states per carbon atom per electron volt for pristine graphene and fluorinated graphene. A close-binding model is used for calculating the density per energy state. Curve 510 represents the density of states per carbon atom per electron volt for pristine graphene. Curve 520 represents the density of states per carbon atom per electron volt for fluorinated graphene. Pristine graphene provides a non-zero density of states at all energies except zero, and therefore does not provide the voltage at which pristine graphene becomes an insulator. Fluorinated graphene provides an energy band with a zero density of states, and therefore provides the voltage range for fluorinated graphene to act as an insulator.

[0110] refer to Figure 6 The calculated conductivity of pristine graphene and fluorinated graphene was plotted as a function of Fermi energy. Curve 610 represents the conductivity of pristine graphene, and curve 620 represents the conductivity of fluorinated graphene. Fluorinated graphene provides an energy range in which conductivity is negligible, and it acts as an insulating material for Fermi levels of 0.5 eV or lower. In contrast, pristine graphene does not provide an energy range in which it can act as an insulating material.

[0111] The atomic percentage of fluorine in fluorinated graphene can range from 0.1% to 60%, such as 0.5% to 50%, including a range of 0.1% to 0%. Therefore, fluorinated graphene can contain, but is not limited to, fluorinated graphene with a carbon-to-fluorine ratio of approximately 1:1. The position and width of the zero-density band in fluorinated graphene vary with the atomic concentration of fluorine atoms within the fluorinated graphene.

[0112] Therefore, in Figure 1 Switching between insulating and conductive states within the device is possible for fluorinated graphene semiconductor materials, which serve as the semiconductor component. Other semiconductor materials with sufficient band gaps (such as molybdenum disulfide, hexagonal boron nitride, or single germanium) can be used instead. Figure 1 Fluorinated graphene in devices.

[0113] Figure 7 A first exemplary structure 180 according to a first embodiment of the present disclosure is shown. The first ferroelectric memory device 180 includes a transistor 95 containing a semiconductor channel 40. The semiconductor channel 40 may be configured to provide a two-dimensional charge carrier layer (such as a 2DEG layer) or a semiconductor material selected from fluorinated graphene, hexagonal boron nitride, molybdenum disulfide, monogermanium, or similar two-dimensional materials having a sufficient band gap. The semiconductor channel 40 may consist only of the two-dimensional charge carrier layer, or the semiconductor channel may also contain additional semiconductor material in addition to the two-dimensional charge carrier layer. The two-dimensional charge carrier layer may be located in a two-dimensional Euclidean plane. In one embodiment, the semiconductor channel 40 may have a thickness in the range of 0.3 nm to 10 nm, such as in the range of 0.6 nm to 5 nm. The two-dimensional charge carrier layer serves as a channel within the transistor 95 (e.g., a ferroelectric memory cell) of the first ferroelectric memory device 180.

[0114] Ferroelectric memory element 21 is positioned adjacent to semiconductor channel 40, such as on the surface of semiconductor channel (i.e., on the surface of the two-dimensional charge carrier layer). Ferroelectric memory element 21 serves as the gate dielectric 20 within transistor 95 of the first ferroelectric memory device 180. Ferroelectric memory element 21 is in contact with a first surface of semiconductor channel 40. Ferroelectric memory element 21 comprises and / or is substantially composed of at least one ferroelectric material, such as barium titanate (e.g., BaTiO3; BT), calcium staborite (e.g., Ca2B6O3), etc. 11 ·5H2O), bismuth titanate (such as Bi 12 TiO 20 Bi4Ti3O 12 Or Bi2Ti2O7), barium europium titanate, ferroelectric polymers, germanium telluride, anhydrous potassium magnesium sulfate (such as M2M) '2(SO4)3, where M is a monovalent metal and M' is a divalent metal, lead, scandium, tantalum (such as Pb(Sc)3), x Ta 1-x Lead titanate (such as PbTiO3; PT), lead zirconate titanate (such as Pb(Zr,Ti)O3; PZT), lithium niobate (such as LiNbO3; LN, (LaAlO3)), and polyvinylidene fluoride (CH2CF2). n Potassium niobate (such as KNbO3), sodium tartrate (such as KNaC4H4O6·4H2O), potassium oxytitanium phosphate (such as KO5PTi), sodium bismuth titanate (such as Na 0.5 Bi 0.5 TiO3 or Bi 0.5 Na 0.5 TiO3), lithium tantalate (such as LiTaO3(LT)), lead lanthanum titanate (such as (Pb,La)TiO3(PLT)), lead lanthanum zirconium titanate (such as (Pb,La)(Zr,Ti)O3(PLZT)), ammonium dihydrogen phosphate (such as NH4H2PO4(ADP)), or potassium dihydrogen phosphate (such as KH2PO4(KDP)). In one embodiment, the ferroelectric memory element 21 comprises and / or is substantially composed of a ferroelectric dielectric material.

[0115] A front-side conductive gate electrode 51 is located directly on the ferroelectric memory element 21 on the opposite side of the semiconductor channel 40. The front-side conductive gate electrode 51 serves as the gate electrode 50 of the transistor 95 of the first ferroelectric memory device 180. The conductive gate electrode 51 is in contact with the ferroelectric memory element 21. The conductive gate electrode 51 may comprise a metallic material and / or be substantially composed of a metallic material, such as an elemental metal (Ti, Ta, or W), an intermetallic alloy of at least two elemental metals, a metal semiconductor compound (such as a metal silicide), or a conductive metal alloy of at least one elemental metal (such as Ti, Ta, or W) and a nonmetallic element (such as nitrogen and / or oxygen, such as TiN or WN).

[0116] Source contact 42 contacts a first portion of semiconductor channel 40, and drain contact 44 contacts a second portion of semiconductor channel. Ferroelectric memory element 21 is located between source contact 42 and drain contact 44. Source contact 42 and drain contact 44 may comprise and / or be substantially composed of corresponding metal contact materials. The metal contact material may be a metal semiconductor compound, a conductive metal nitride, an elemental metal, or an intermetallic alloy. In one embodiment, the metal material that can be used for the conductive gate electrode 51 may also be used for source contact 42 and drain contact 44.

[0117] In one embodiment, the two-dimensional charge carrier layer is located within 10 nm of the two-dimensional Euclidean plane, which is included at the interface between the semiconductor channel 40 and the ferroelectric memory element 21.

[0118] For example, a transistor 95 of the first exemplary structure 180 can be formed by forming a semiconductor channel 40 above a substrate 10, forming a ferroelectric memory element 21 directly on a first surface of the semiconductor channel 40, forming a conductive gate electrode 51 on the ferroelectric memory element 21, forming a source contact 42 on a first portion of the semiconductor channel 40, and forming a drain contact 44 on a second portion of the semiconductor channel 40. The substrate 10 has a planar top surface 11 that contacts the bottom surface of the semiconductor channel 40. Figure 7 In the embodiment shown, the direction between the semiconductor channel 40 and the conductive gate electrode 51 is perpendicular to the planar top surface 11 of the substrate 10. Alternatively, in Figure 8 In the implementation shown, transistor 95 can be relative to Figure 7 The transistor 95 shown is rotated 90 degrees so that the orientation between the semiconductor channel 40 and the conductive gate electrode 51 is parallel to the plane of the planar top surface 11 of the substrate 10. The substrate 10 may include any suitable supporting substrate, such as a semiconductor wafer, an insulating substrate, or a conductive substrate having an insulating layer above its planar top surface 11.

[0119] During programming, a variable gate bias voltage V can be applied relative to the semiconductor channel 40. g A polarization of the ferroelectric memory element 21 is programmed by applying a conductive gate electrode 51. During sensing, a source-drain bias voltage is applied between the source contact 42 and the drain contact 44 (e.g., across the source and drain contacts) and by applying a gate sensing bias voltage to the conductive gate electrode 51. The sensing circuitry 584 measures the source-drain current while applying the source-drain bias voltage between the source contact 42 and the drain contact 44 (e.g., across the source and drain contacts).

[0120] refer to Figure 8 According to a second embodiment of the present disclosure, a second exemplary structure 180 can be provided with a back-side ferroelectric memory element 22 in contact with a second surface of the semiconductor channel 40 to... Figure 7A first exemplary structure 180 is derived. The back-side ferroelectric memory element 22 is an additional ferroelectric material portion that serves as an additional gate dielectric 20. The back-side ferroelectric memory element 22 is located on a second surface of the semiconductor channel 40, which is parallel to and on the opposite side of the first surface of the semiconductor channel 40. The back-side ferroelectric memory element 22 may have the same thickness as the ferroelectric memory element 21 and may contain any ferroelectric material that can be used in the ferroelectric memory element 21.

[0121] A conductive back-side gate electrode 52 is disposed on the back-side ferroelectric memory element 22. The conductive back-side gate electrode 52 may contact the back-side ferroelectric memory element 22. The conductive back-side gate dielectric 52 may contain any material suitable for use with the conductive gate electrode 51. A conductive path connects the conductive back-side gate electrode to the conductive gate electrode, thereby electrically shorting the conductive back-side gate electrode 52 to the conductive gate electrode 51.

[0122] In one embodiment, the polarization of the ferroelectric memory element 21 and the polarization of the back-side ferroelectric memory element 22 can point in opposite directions. Therefore, the polarization of the ferroelectric memory element 21 and the back-side ferroelectric memory element 22 can point towards the semiconductor channel 40 in a first ferroelectric memory state, and the polarization of the ferroelectric memory element 21 and the back-side ferroelectric memory element 22 can point away from the semiconductor channel 40 in a second ferroelectric memory state. Thus, positive ferroelectric charge exists in the ferroelectric memory element 21 and the back-side ferroelectric memory element 22 near the interface with the semiconductor channel 40 in the first ferroelectric memory state, which induces negative screening charge (moving electrons) in a two-dimensional charge carrier layer near the interface with the ferroelectric memory element 21 and the back-side ferroelectric memory element 22. Alternatively, if a semiconductor layer is used instead of the two-dimensional charge carrier layer, the induced charge will be used to deflect the Fermi energy and change the conductivity state of the semiconductor layer. Similarly, negative ferroelectric charges exist in the ferroelectric memory element 21 and the back-side ferroelectric memory element 22 near the interface with the semiconductor channel 40 in the second ferroelectric memory state, and the second ferroelectric memory state induces positive screening charges (holes, i.e., no electrons) in the two-dimensional charge carrier layer near the interface with the ferroelectric memory element 21 and the back-side ferroelectric memory element 22. When a voltage is applied to the front-side conductive gate electrode 51, the second exemplary structure 180 can be operated by applying the same voltage (e.g., a voltage pulse of the same polarity) to the conductive back-side gate electrode 52.

[0123] The thickness of the semiconductor channel 40 in the second exemplary structure 180 may be the same as the thickness of the semiconductor channel in the first exemplary structure 180. Alternatively, the thickness of the semiconductor channel 40 in the second exemplary structure 180 may be in the range of 1.0 times to 2.0 times the thickness of the semiconductor channel 40 in the first exemplary structure 180. The increased thickness window of the semiconductor channel 40 in the second exemplary structure 180 is due to the dual-gate construction, in which screening charges are induced in an additive manner by two different ferroelectric polarizations.

[0124] The transistor 95 of the second exemplary structure 180 can be formed by modifying the method used to form the transistor 95 of the first exemplary structure 180. In addition to the processing steps for forming the various components of the first exemplary structure 180, the back-side ferroelectric memory element 22 can also be formed on the second surface of the semiconductor channel 40, and the conductive back-side gate electrode 52 can be formed on the back-side ferroelectric memory element 22.

[0125] In one embodiment, the transistor 95 of the second exemplary structure 180 may be supported by a substrate 10 having a planar top surface 11 that is perpendicular to the plane of the interface between the semiconductor channel 40 and the ferroelectric memory element 21 and parallel to the direction of the current in the semiconductor channel 40 (i.e., the direction between the source contact 42 and the drain contact 44) during sensing operation.

[0126] Alternatively, Figure 8 The transistor 95 shown can be rotated 90 degrees to have the same characteristics as... Figure 7 The structure is similar to that shown in the diagram. In this alternative structure, a conductive back-side gate electrode 52 is formed above the substrate 10, a back-side ferroelectric memory element 22 is formed above the conductive back-side gate electrode 52, a semiconductor channel 40 is formed above the back-side ferroelectric memory element 22, a ferroelectric memory element 21, a source contact 42, and a drain contact 44 are formed above the semiconductor channel 40, and a front-side conductive gate electrode 51 is formed above the ferroelectric memory element 21.

[0127] refer to Figure 9The image shows a transistor 95 with a third exemplary structure according to an embodiment of the present disclosure, which is derived from the first exemplary structure 180 by forming a back-side contact electrode 53 directly on the second surface of the semiconductor channel 40. A two-dimensional semiconductor material layer 40G within the semiconductor channel 40 is explicitly shown. The two-dimensional semiconductor material layer 40G described above may include the entire semiconductor channel 40 or only a portion of the semiconductor channel 40. The two-dimensional semiconductor material layer 40G may have a band gap of at least 1.1 eV, may include a thickness of 1 to 5 monolayers of semiconductor material, and / or may include a two-dimensional charge carrier gas layer. The second surface of the semiconductor channel 40 is located on the opposite side of the first surface of the semiconductor channel 40. Therefore, the back-side contact electrode 53 may contact the second surface of the semiconductor channel 40. The back-side contact electrode 53 may apply a back-side bias voltage to the semiconductor channel 40 during programming of the ferroelectric polarization of the ferroelectric memory element 21. Optionally, the front gate contact 81 and / or the back gate contact 83 may be formed on the conductive gate electrode 51 and the back contact electrode 53, respectively, to facilitate the application of the bias voltage used during operation of the transistor 95 of the third exemplary structure. In an alternative embodiment, Figure 9 The layers 51 and / or 53 shown may include a gate insulating layer, and the contacts 81 and / or 83 may respectively include a front conductive gate electrode and a back contact electrode (e.g., a back gate).

[0128] refer to Figure 10A and Figure 10B This illustrates a transistor 95 with a fourth exemplary structure according to a fourth embodiment of the present disclosure. In the transistor 95 of the fourth exemplary structure, the ferroelectric memory element 20 and / or the gate electrode 50 may have a tubular configuration surrounding the semiconductor channel 40. In other words, the gate electrode 50 may be a wound gate electrode 54 wound around the ferroelectric memory element 20, which may be a wound ferroelectric memory element 23. The wound ferroelectric memory element 23 is wound (i.e., surrounds) the semiconductor channel 40.

[0129] In this embodiment, the semiconductor channel 40 can be a vertical pillar or a vertical shell surrounding the vertical pillar, the vertical pillar extending longitudinally perpendicular to the planar top surface 11 of the substrate 10, such as... Figure 10B As shown in the diagram. The wound ferroelectric memory element 23 may be an inner shell wound (i.e., surrounding) the semiconductor channel 40. The wound gate electrode 54 is wound around the middle portion of the wound ferroelectric memory element 23. Source contacts and drain contacts (42, 44) contact opposite ends of the semiconductor channel 40 on opposite sides of the wound gate electrode 54. The source contacts and drain contacts (42, 44) may also be wound around the semiconductor channel 40, or they may contact only a portion of the outer periphery of the semiconductor channel 40.

[0130] Generally, the various ferroelectric memory devices 180 of the embodiments of this disclosure can be operated by programming the polarization direction of the ferroelectric memory element 21, applying a positive or negative bias voltage to the conductive gate electrode 51 relative to the semiconductor channel 40, and sensing the polarization direction of the ferroelectric memory element 21 by sensing the magnitude of the current between the source contact 42 and the drain contact 44 while applying a read voltage (i.e., measuring the bias voltage) between the source contact 42 and the drain contact 44. If a back-side ferroelectric memory element 22 is included, the ferroelectric polarization direction of the back-side ferroelectric memory element 22 is opposite to the ferroelectric polarization direction of the ferroelectric memory element 21. The thickness and / or material composition of the back-side ferroelectric memory element 22 may be the same as or different from the thickness and / or material composition of the ferroelectric memory element 21. In other words, the polarizations of the ferroelectric memory element 21 and the back-side ferroelectric memory element 22 are antiparallel to each other and are flipped simultaneously during programming.

[0131] If a conductive back-side gate electrode 52 is included, the voltage applied to the conductive back-side gate electrode 52 may be the same as the voltage applied to the front-side conductive gate electrode 51. A read voltage may be applied to the conductive gate electrode 51 while sensing the polarization direction of the ferroelectric memory element 21, and optionally sensing the polarization direction of the back-side ferroelectric memory element 22.

[0132] The devices of the embodiments of this disclosure offer advantages over ferroelectric primitive graphene memory elements based on tunneling resistors (TERs), which exhibit poor polarization retention and require a thicker ferroelectric barrier to stabilize polarization. However, the thicker barrier results in a lower tunneling current and thus significantly reduces the signal (e.g., read current) in TER-based devices. In contrast, the read current does not flow through the ferroelectric material in the devices of the embodiments of this disclosure. Therefore, a thicker ferroelectric layer can be used in the devices of the embodiments of this disclosure without reducing the read current, and the polarization retention problem is reduced or overcome in the devices of the embodiments of this disclosure, compared to prior art TER-based devices.

[0133] To avoid being bound by a specific theory and to demonstrate the advantages of the devices according to the embodiments of this disclosure, the inventors calculated the on / off ratio of ferroelectric polarization control over the bandgap of a semiconductor in a finite-size nanostructure at room temperature. The inventors developed a quantum mechanical calculation based on the conductivity of ballistic electron transport via a finite-size semiconductor attached to a ferroelectric material and two metal contacts. The inventors' calculations are based on the green function form within a two-band tightly bound Hamiltonian model. In contrast, first-principles electronic structure calculations are used to obtain the density of states and bandgap of two-dimensional semiconductor materials.

[0134] Specifically, Figure 1The structure is modeled using a rectangular device size of 10nm × 5nm (i.e., the area of ​​each interface between adjacent layers). The thickness d of the ferroelectric material portion is 5nm, and the distance between the ferroelectric material portion and each metal contact is 1nm. The electrostatic potential in the semiconductor material portion below the ferroelectric material portion is controlled by reversing the ferroelectric polarization.

[0135] The inventor's simulation results Figure 11 , Figure 12 and Figures 13A to 13D As shown in the figure. The accuracy of conductivity simulations is limited by numerical precision. Below 10 -2 (Ohm·m) -1 The conductivity value is outside the range of reliable numerical accuracy, and therefore, the calculation is limited to the range of ferroelectric polarization, resulting in a conductivity value of at least 10. -2 (Ohm·m) -1 .

[0136] refer to Figure 11 This paper presents the calculated density per atom per electron volt for hexagonal boron nitride. This calculation is based on density function theory (DFT) and hybridization functions.

[0137] refer to Figure 12 This paper presents the calculated density per atom per electron volt for molybdenum disulfide. This calculation is based on density function theory (DFT) and hybridization functions.

[0138] Figures 13A to 13D The transistor 95, illustrating a ferroelectric memory device according to an embodiment of this disclosure, has a calculated conductivity (in 10⁻⁶) at room temperature (20 degrees Celsius). 7 A graph showing how ferroelectric polarization changes (in units of / Ohm m). Figure 13A The calculated conductivity is shown for the case where the ferroelectric memory element is composed of hexagonal boron nitride. Figure 13B The calculated conductivity is shown for the case where the ferroelectric memory element is composed of fluorinated graphene. Figure 13C The calculated conductivity is shown for the case where the ferroelectric memory element is composed of molybdenum disilicide. Figure 13D The calculated conductivity is shown for the case where the ferroelectric memory element is composed of a single germanium element.

[0139] Figures 13A to 13D The conductivity of all semiconductor channels in the embodiments of this disclosure increases (or decreases) exponentially with ferroelectric polarization in the positive (or negative) direction. This allows the calculated conductivity σ(P) to be fitted to a fitting function that includes ferroelectric polarization P as a variable. Furthermore, the on / off ratio (i.e., the ratio of conductivity in the on state to conductivity in the off state) can be fitted to a function with another variable P.max Another fitting function is given, where the variable is the maximum value of the ferroelectric polarization required to push the Fermi level of the two-dimensional semiconductor into the conduction band. The functional forms of σ(P) and ON / OFF are given below:

[0140] σ(P)=σ0e aP ,and

[0141]

[0142] Where σ0 = σ(P = 0) is the conductivity of the semiconductor channel under the paraelectric condition. Table 3 lists the best-fit values ​​for σ(P) and the ON / OFF fitting parameters.

[0143] Ferroelectric materials <![CDATA[Optimal value of a (in cm 2 / μC)]]> <![CDATA[P max (in μC / cm) 2 (as a unit) Hexagonal BN 0.61 75 <![CDATA[MoSi2]]> 0.49 30 Fluorinated graphene 0.50 40 single germanium 0.44 10

[0144] While defect states can limit the practical ON / OFF ratio, various two-dimensional semiconductor materials offer generally high ON / OFF ratios. Simulations show that higher ON / OFF ratios are likely to be associated with wider bandgap two-dimensional semiconductor materials, and thicker ferroelectric materials can be used in conjunction with such two-dimensional semiconductor materials. Higher operating voltages are expected to increase the thickness of the ferroelectric material in the ferroelectric memory device 180 of the embodiments of this disclosure.

[0145] According to one aspect of this disclosure, the ferroelectric memory array may include an array of memory cells (e.g., transistors) 95 of embodiments of this disclosure. See also Figure 14 A schematic diagram of a ferroelectric memory array including transistors 95 in an array configuration is shown. The ferroelectric memory array can be configured as a random access memory device 501. As used herein, a "random access memory device" means a memory device that includes memory cells that allow random access, i.e., access to any selected memory cell based on a command to read the contents of a selected memory cell.

[0146] The random access memory device 501 of this disclosure includes a memory array region 550 containing an array of corresponding ferroelectric memory cells 180 located at the intersection of word lines (which may include a first electrical conductor 30 as shown or a second electrical conductor 90 in an alternative configuration) and bit lines (which may include a second electrical conductor 90 as shown or a first electrical conductor 30 in an alternative configuration). For example, word lines 30 may be electrically connected to and / or may include gate electrodes 50 of transistors 95 in the array, while bit lines 90 may be electrically connected to and / or may include source or drain contacts (42, 44) of transistors 95 in the array.

[0147] Random access memory device 501 may also include a row decoder 560 connected to the word lines, a sensing circuitry 570 (e.g., a sensing amplifier and other bit line control circuitry) connected to the bit lines, a column decoder 580 connected to the bit lines, and a data buffer 590 connected to the sensing circuitry. Multiple instances of ferroelectric memory cells (e.g., ferroelectric memory transistors) 95 are provided to form an array configuration of random access memory device 501. Thus, each ferroelectric memory cell in the ferroelectric memory cell 95 may be a two-terminal device including a corresponding first electrode and a corresponding second electrode. It should be noted that the location and interconnection of the components are illustrative, and the components may be arranged in different configurations. Furthermore, the ferroelectric memory cell 95 may be manufactured as a discrete device, i.e., a single isolated device.

[0148] Embodiments of this disclosure provide a non-volatile memory element with ferroelectrically controlled conductivity based on a two-dimensional semiconductor material or a two-dimensional charge carrier layer (such as a 2DEG layer 40G). Information can be written and stored by applying an electrical pulse that reverses the ferroelectric polarization and thereby induces surface charges in the semiconductor or the two-dimensional charge carrier layer. Information can be read by measuring the resistance of the semiconductor channel including the two-dimensional charge carrier layer.

[0149] Compared to previously known three-terminal ferroelectric-graphene structures, the devices of the embodiments of this disclosure provide a significant increase in the resistance difference of the two-dimensional semiconductor material layer by replacing the gapless pristine graphene (i.e., zero bandgap) with a two-dimensional semiconductor material layer, which may have a bandgap of at least 1.1 eV. Compared to previously known two-terminal vertical tunnel junction devices, the devices of the embodiments of this disclosure greatly improve the stability of ferroelectric polarization because the thickness of the ferroelectric material portion can be increased without signal loss. The devices of the embodiments of this disclosure are non-volatile memory devices capable of non-volatilely storing information, which is not provided by high electron mobility transistors (HEMTs) or heterojunction field-effect transistors (HFETs) known in the art. Because the in-plane geometry allows for low-current operation during the sensing step, the devices of the embodiments of this disclosure enable low-power sensing.

[0150] refer to Figure 15This illustration shows a fifth exemplary structure according to a fifth embodiment of the present disclosure, which can be used, for example, to fabricate a device structure containing a vertical NAND memory device. The fifth exemplary structure includes a substrate, which may be a semiconductor substrate. The substrate may include a substrate semiconductor layer 109. The substrate semiconductor layer 109 is a semiconductor material layer and may include at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, and / or other semiconductor materials known in the art. The substrate may have a main surface 7, which may be, for example, the topmost surface of the substrate semiconductor layer 109. The main surface 7 may be a semiconductor surface. In one embodiment, the main surface 7 may be a single-crystal semiconductor (e.g., silicon) surface. For example, the substrate may be a single-crystal silicon wafer. Optionally, at least one doped well (not explicitly shown) may be formed within the substrate semiconductor layer 109.

[0151] At least one semiconductor device 700 of the peripheral circuit system may be formed on a portion of the substrate semiconductor layer 109. The at least one semiconductor device may include, for example, a field-effect transistor. For example, at least one shallow trench isolation structure 120 may be formed by etching a portion of the substrate semiconductor layer 109 and depositing a dielectric material therein. A gate dielectric layer, at least one gate conductor layer, and a gate cap dielectric layer may be formed over the substrate semiconductor layer 109 and may subsequently be patterned to form at least one gate structure (150, 152, 154, 158), each of which may include a gate dielectric 150, a gate electrode (152, 154), and a gate cap dielectric. The gate electrodes (152, 154) may include a stack of a first gate electrode portion 152 and a second gate electrode portion 154. At least one gate spacer 156 may be formed around at least one gate structure (150, 152, 154, 158) by depositing and anisotropically etching a conformal dielectric layer. An active region 130 may be formed in the upper portion of the substrate semiconductor layer 109, for example, by introducing ions that use at least one gate structure (150, 152, 154, 158) as a mask structure. Additional masks may be used as needed. The active region 130 may include the source and drain regions of a field-effect transistor. Optionally, a first dielectric pad 161 and a second dielectric pad 162 may be formed. Each of the first and second dielectric pads (161, 162) may include a silicon oxide layer, a silicon nitride layer, and / or a dielectric metal oxide layer. In an illustrative example, the first dielectric pad 161 may be a silicon oxide layer, and the second dielectric pad 162 may be a silicon nitride layer. At least one semiconductor device of the peripheral circuitry system may contain driver circuitry for a memory device to be subsequently formed, which may include at least one NAND device.

[0152] A dielectric material such as silicon oxide may be deposited over the at least one semiconductor device and subsequently planarized to form a planarized dielectric layer 170. In one embodiment, the planarized top surface of the planarized dielectric layer 170 may be coplanar with the top surface of the dielectric pads (161, 162). Subsequently, the planarized dielectric layer 170 and the dielectric pads (161, 162) may be removed from a region to physically expose the top surface of the substrate semiconductor layer 109.

[0153] Optional semiconductor material layer 110 can be formed on the top surface of substrate semiconductor layer 109 by depositing a single-crystal semiconductor material (e.g., by selective epitaxy). The deposited semiconductor material can be the same as or different from the semiconductor material of substrate semiconductor layer 109. The deposited semiconductor material can be any material that can be used for substrate semiconductor layer 109 as described above. The single-crystal semiconductor material of semiconductor material layer 110 can be epitaxially aligned with the single-crystal structure of substrate semiconductor layer 109. The portion of the deposited semiconductor material above the top surface of planarized dielectric layer 170 can be removed, for example, by chemical mechanical planarization (CMP). In this case, semiconductor material layer 110 can have a top surface coplanar with the top surface of planarized dielectric layer 170. Semiconductor material layer 110 can be doped with p-type dopant or n-type dopant. The doping type of semiconductor material layer 110 is referred to herein as the first conductivity type. In the absence of semiconductor material layer 110, substrate semiconductor layer can be doped with p-type dopant or n-type dopant, and the doping type of substrate semiconductor layer 109 is referred to herein as the first conductivity type. In one implementation, the first conductivity type may be p-type.

[0154] refer to Figure 16 Alternating stacks of insulating layer 132 and spacer material layers may be formed over a substrate, which may include optional semiconductor material layer 110 and substrate semiconductor layer 109. The spacer material layers may be formed as conductive layers or as sacrificial material layer 142 subsequently replaced by conductive layers.

[0155] In one embodiment, an alternating stack of a plurality of first material layers (which may be insulating layers 132) and second material layers (which are spacer material layers located between the first material layers 132 and may be sacrificial material layers 142) is formed above the top surface of the substrate. For example, an alternating stack of a plurality of first material layers and second material layers may be formed on the top surface of a semiconductor material layer 110. As used herein, a “material layer” means a layer comprising a material throughout its entirety. As used herein, an alternating plurality of fifth elements and second elements refers to a structure in which instances of fifth elements and instances of second elements alternate. Each instance of a fifth element that is not the end element of an alternating plurality of elements is adjacent to two instances of a second element on both sides, and each instance of a second element that is not the end element of an alternating plurality of elements is adjacent to two instances of a fifth element at both ends. The fifth elements may have the same thickness therebetween or may have different thicknesses. The second elements may have the same thickness therebetween or may have different thicknesses. The alternating plurality of first material layers and second material layers may begin with an instance of a first material layer or an instance of a second material layer, and may end with an instance of a first material layer or an instance of a second material layer. In one implementation, instances of the fifth element and instances of the second element may be formed in units that are periodically repeated within alternating plurality of elements.

[0156] Each first material layer includes a first material, and each second material layer includes a second material different from the first material. In one embodiment, each first material layer may be an insulating layer 132, and each second material layer may be a sacrificial material layer. In this case, the stack may include alternating plurality of insulating layers 132 and sacrificial material layers 142, and constitute a prototype stack including alternating layers of insulating layers 132 and sacrificial material layers 142. As used herein, a "prototype" structure or "in-process" structure refers to a transient structure in which at least one component therein is subsequently modified in terms of shape or composition.

[0157] The alternating stacking of multiple layers is referred to herein as an alternating stack (132, 142). In one embodiment, the alternating stack (132, 142) may include an insulating layer 132 made of a first material and a sacrificial material layer 142 made of a second material, which is different from the material of the insulating layer 132. The first material of the insulating layer 132 may be at least one insulating material. Thus, each insulating layer 132 may be an insulating material layer. Insulating materials that can be used for the insulating layer 132 include, but are not limited to, silicon oxide (including doped or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicon glass (OSG), spin-coated dielectric materials, dielectric metal oxides (e.g., alumina, hafnium oxide, etc.) and their silicates, which are commonly referred to as high dielectric constant (high k) dielectric oxides, dielectric metal oxynitrides and their silicates, and organic insulating materials. In one embodiment, the first material of the insulating layer 132 may be silicon oxide and / or organosilicon glass.

[0158] The second material of the sacrificial material layer 142 is a sacrificial material that can be selectively removed from the first material of the insulating layer 132. As used herein, the removal of the first material is "selective" for the second material if the removal process removes the first material at a rate at least twice the removal rate of the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process of the first material relative to the second material.

[0159] The sacrificial material layer 142 may comprise an insulating material, a semiconductor material, or a conductive material. A second material of the sacrificial material layer 142 may subsequently be replaced with a conductive electrode, which may, for example, serve as the control gate electrode of a vertical NAND device. Non-limiting examples of the second material include silicon nitride, amorphous semiconductor materials (such as amorphous silicon), and polycrystalline semiconductor materials (such as polycrystalline silicon). In one embodiment, the sacrificial material layer 142 may be a spacer material layer comprising silicon nitride or a semiconductor material comprising at least one of silicon and germanium. Alternatively, a permanent conductive layer may be used instead of the sacrificial material layer 142. The permanent conductive layer may comprise a conductive material such as a metal, polycrystalline silicon, or a metal silicide (e.g., NiSi). In this case, the permanent conductive layer is not replaced with a different material and serves as the control gate electrode of the vertical NAND device.

[0160] In one embodiment, the insulating layer 132 may comprise silicon oxide, and the sacrificial material layer may comprise a silicon nitride sacrificial material layer. The first material of the insulating layer 132 may be deposited, for example, by chemical vapor deposition (CVD). For instance, if silicon oxide is used for the insulating layer 132, tetraethyl orthosilicate (TEOS) may be used as a precursor material for the CVD process. The second material that may form the sacrificial material layer 142 is, for example, CVD or atomic layer deposition (ALD).

[0161] The thickness of the insulating layer 132 and the sacrificial material layer 142 can range from 20 nm to 50 nm, and smaller and larger thicknesses can be used for each insulating layer 132 and each sacrificial material layer 142. The number of repetitions of the insulating layer 132 to sacrificial material layer (e.g., control gate electrode or sacrificial material layer) 142 pair can range from 2 to 1,024, and is typically in the range of 8 to 256, but larger repetitions are also possible. The top gate electrode and bottom gate electrode in the stack can be used as select gate electrodes. In one embodiment, each sacrificial material layer 142 in the alternating stack (132, 142) can have a substantially uniform thickness that remains constant within each respective sacrificial material layer 142.

[0162] Optionally, an insulating cap layer 70 may be formed over the alternating stacks (132, 142). The insulating cap layer 70 comprises a dielectric material different from that of the sacrificial material layer 142. In one embodiment, the insulating cap layer 70 may comprise a dielectric material that can be used for the insulating layer 132 as described above. The insulating cap layer 70 may have a greater thickness than each of the insulating layers 132. The insulating cap layer 70 may be deposited, for example, by chemical vapor deposition. In one embodiment, the insulating cap layer 70 may be a silicon oxide layer.

[0163] refer to Figure 17 A stepped cavity may be formed within a stepped region 300, and optionally within a peripheral device region 200. The stepped cavity may have various stepped surfaces such that the horizontal cross-sectional shape of the stepped cavity gradually changes with vertical distance from the top surface of the substrate (109, 110). In one embodiment, the stepped cavity may be formed by repeatedly performing a set of processing steps. The set of processing steps may include, for example, a first type of etching process and a second type of etching process, wherein the first type of etching process vertically increases the cavity depth by one or more levels, and the second type of etching process laterally extends the area to be vertically etched in a subsequent first type of etching process. As used herein, a “level” of a structure comprising alternating multiple layers is defined as the relative position of a pair of first and second material layers within the structure.

[0164] After the stepped cavity is formed, the remaining peripheral portions of the alternating stacks (132, 142) may have stepped surfaces. As used herein, a “stepped surface” refers to a set of surfaces comprising at least two horizontal surfaces and at least two vertical surfaces, such that each horizontal surface abuts a first vertical surface extending upward from a first edge of the horizontal surface and a second vertical surface extending downward from a second edge of the horizontal surface. A “stepped cavity” refers to a cavity having stepped surfaces.

[0165] A reverse stepped dielectric portion 65 (i.e., an insulating filler portion) can be formed in a stepped cavity by depositing a dielectric material therein. For example, a dielectric material such as silicon oxide can be deposited in the stepped cavity. Excess portions of the deposited dielectric material can be removed, for example, from above the top surface of the insulating cap layer 70 by chemical mechanical planarization (CMP). The remaining portion of the deposited dielectric material filling the stepped cavity constitutes the reverse stepped dielectric portion 65. As used herein, a “reverse stepped” element refers to an element having a stepped surface and a horizontal cross-sectional area that monotonically increases with vertical distance from the top surface of the substrate on which the element is situated. If silicon oxide is used for the reverse stepped dielectric portion 65, the silicon oxide of the reverse stepped dielectric portion 65 may or may not be doped with dopants such as B, P, and / or F.

[0166] refer to Figure 18A and Figure 18B A photolithographic material stack (not shown), including at least a photoresist layer, may be formed over an insulating cap layer 70 and alternating stacks (132, 142), and may be photolithographically patterned to form openings therein. The pattern in the photolithographic material stack may be transferred through the insulating layer 70 and across the entire alternating stack (132, 142) by at least one anisotropic etching using the patterned photolithographic material stack as an etching mask. The portion of the alternating stack (132, 142) below the opening in the patterned photolithographic material stack is etched to form a memory opening 49. In other words, the pattern in the patterned photolithographic material stack is transferred through the alternating stack (132, 142) to form a memory opening 49 extending through the alternating stack (132, 142). The chemical properties of the anisotropic etching process used to etch the material through the alternating stack (132, 142) may be alternately used to optimize the etching of the first and second materials in the alternating stack (132, 142). Anisotropic etching can be, for example, a series of reactive ion etchings. The sidewalls of the memory opening 49 can be substantially vertical or can be tapered. The patterned photolithography material stack can then be removed, for example, by ashing.

[0167] In one embodiment, after the top surface of the semiconductor material layer 110 is physically exposed at the bottom of each memory opening 49, over-etching of the semiconductor material layer 110 may optionally be performed. Over-etching may be performed before or after the removal of the photolithography material stack. In other words, the recessed surface of the semiconductor material layer 110 may be vertically offset from the unprocessed top surface of the semiconductor material layer 110 by a recess depth. The recess depth may be, for example, in the range of 1 nm to 50 nm, but smaller and larger recess depths may also be used. Over-etching is optional and may be omitted. If over-etching is not performed, the bottom surface of each memory opening 49 may be coplanar with the top surface of the semiconductor material layer 110. Each memory opening in the memory openings 49 may include a sidewall (or multiple sidewalls) extending substantially perpendicular to the top surface of the substrate. The region forming the array of memory openings 49 is referred to herein as a device region. The substrate semiconductor layer 109 and the semiconductor material layer 110 together constitute a substrate (109, 110), which may be a semiconductor substrate. Alternatively, the semiconductor material layer 110 may be omitted, and the memory opening 49 may extend to the top surface of the substrate semiconductor layer 109.

[0168] Various embodiments of this disclosure can be used to form a memory stack structure in each memory opening of the memory opening. Figures 19A to 19K This illustration shows sequential vertical cross-sectional views of memory openings within a fifth exemplary structure during the formation of a fifth exemplary memory opening filling structure, according to a fifth embodiment of the present disclosure. The formation of the exemplary memory opening filling structure may be achieved through... Figure 18A and Figure 18B Execution is performed within each of the memory opening 49 and the support opening 19 in the fifth exemplary structure shown.

[0169] refer to Figure 19A , showing Figure 18A and Figure 18B The memory opening 49 in the fifth exemplary structure. The memory opening 49 extends through the insulating cap layer 70, alternately stacked (132, 142), and optionally extends into the upper portion of the semiconductor material layer 110. The recess depth of the bottom surface of each memory opening relative to the top surface of the semiconductor material layer 110 can range from 0 nm to 30 nm, but a greater recess depth is also possible. Optionally, the sacrificial material layer 142 can be partially laterally recessed, for example by isotropic etching, to form a lateral recess (not shown).

[0170] refer to Figure 19BAn optional pedestal channel portion 111 may be formed at the bottom portion of each memory opening 49, for example, by selective epitaxy. Each pedestal channel portion 111 includes a single-crystal semiconductor material epitaxially aligned with the single-crystal semiconductor material of the semiconductor material layer 110. In one embodiment, the pedestal channel portion 111 may be doped with ions of the same conductivity type as the semiconductor material layer 110. In one embodiment, the top surface of each pedestal channel portion 111 may be formed above a horizontal plane including the top surface of the sacrificial material layer 142. In this case, at least one source-select gate electrode may then be formed by replacing each sacrificial material layer 142 located below the horizontal plane including the top surface of the pedestal channel portion 111 with a corresponding conductive material layer. The pedestal channel portion 111 may be a portion of a transistor channel extending between a source region subsequently formed in the substrate (109, 110) and a drain region subsequently formed in the upper portion of the memory opening 49. A cavity 49' exists in the unfilled portion of the memory opening 49 above the pedestal channel portion 111. In one embodiment, the substrate channel portion 111 may comprise monocrystalline silicon. In one embodiment, the substrate channel portion 111 may be doped with a first conductivity type, the first conductivity type being the same as the conductivity type of the semiconductor material layer 110 to which the substrate channel portion contacts. If the semiconductor material layer 110 is absent, the substrate channel portion 111 may be formed directly on the substrate semiconductor layer 109, which may be doped with the first conductivity type.

[0171] Optionally, the ferroelectric side interface dielectric layer can be formed by conformally depositing the dielectric material into the memory opening, as will be discussed below. Figure 26B To elaborate further. The ferroelectric side interface dielectric layer (if present) comprises a dielectric material that improves the interface quality and enhances the ferroelectric properties of the ferroelectric material layer and gate electrode subsequently formed by replacing the sacrificial material layer 142 with a conductive layer. The ferroelectric side interface dielectric layer 1 comprises hafnium aluminum oxide, hafnium oxide, or aluminum oxide. The thickness of the channel side interface dielectric layer can range from 1 nm to 2 nm.

[0172] refer to Figure 19CAt least one ferroelectric dielectric layer (504, 506) may be formed in each memory opening in memory opening 49, in each support opening in support opening 19, and over insulating cap layer 70. If an optional ferroelectric side interface dielectric layer is present in the openings (19, 49), at least one ferroelectric dielectric layer (504, 506) may be formed directly on the ferroelectric side interface dielectric layer. At least one ferroelectric dielectric layer (504, 506) may comprise any ferroelectric dielectric material. In one embodiment, at least one ferroelectric dielectric layer (504, 506) comprises only one ferroelectric dielectric layer 504. The ferroelectric dielectric layer may comprise hafnium oxide (such as hafnium oxide containing at least one dopant selected from Al, Zr, and Si and having a ferroelectric non-centrosymmetric orthorhombic phase), zirconium oxide, hafnium zirconium oxide, bismuth ferrite, barium titanate (such as BaTiO3; BT), calcium staborite (such as Ca2B6O3), etc. 11 ·5H2O), bismuth titanate (such as Bi4Ti3O) 12 ), barium europium titanate, ferroelectric polymers, germanium telluride, anhydrous potassium magnesium sulfate (such as M2M), ' 2(SO4)3, where M is a monovalent metal and M' is a divalent metal, lead, scandium, tantalum (such as Pb(Sc)3), x Ta 1-x Lead titanate (such as PbTiO3; PT), lead zirconate titanate (such as Pb(Zr,Ti)O3; PZT), lithium niobate (such as LiNbO3; LN, (LaAlO3)), and polyvinylidene fluoride (CH2CF2). n Potassium niobate (such as KNbO3), sodium tartrate (such as KNaC4H4O6·4H2O), potassium oxytitanium phosphate (such as KO5PTi), sodium bismuth titanate (such as Na 0.5 Bi 0.5 TiO3 or Bi 0.5 Na 0.5 TiO3), lithium tantalate (such as LiTaO3(LT)), lead lanthanum titanate (such as (Pb,La)TiO3(PLT)), lead lanthanum zirconium titanate (such as (Pb,La)(Zr,Ti)O3(PLZT)), ammonium dihydrogen phosphate (such as NH4H2PO4(ADP)) or potassium dihydrogen phosphate (such as KH2PO4(KDP)).

[0173] In another embodiment, at least one ferroelectric dielectric layer (504, 506) comprises a first ferroelectric dielectric layer 504 deposited first and a second dielectric layer 506 (which may be a ferroelectric dielectric layer or a non-ferroelectric dielectric layer) deposited on the first ferroelectric dielectric layer 504. The first ferroelectric dielectric layer 504 is also referred to as the outer ferroelectric dielectric layer, and the second dielectric layer 506 is also referred to as the inner dielectric layer, which may be a ferroelectric or non-ferroelectric dielectric layer. Each of the at least one ferroelectric dielectric layer (504, 506) can be deposited by a corresponding conformal deposition process, such as atomic layer deposition (ALD) or chemical vapor deposition (CVD). In this embodiment, at least one ferroelectric dielectric layer (504, 506) may include a layer stack configured to reduce electron tunneling from the channel to at least one ferroelectric dielectric layer (504, 506) and improve the quality of the interface with the channel to be deposited in subsequent steps. In this configuration, the first ferroelectric dielectric layer 504 may have a first bandgap energy, and the second dielectric layer 506 may have a second bandgap energy greater than the first bandgap energy to reduce electron tunneling from the channel into layer 504. For example, both dielectric layers may comprise hafnium aluminum oxide, which may optionally be doped with zirconium. The first ferroelectric dielectric layer 504 may have a greater thickness and a higher hafnium to aluminum atom ratio than the second dielectric layer 506. In this configuration, the hafnium-rich first ferroelectric dielectric layer 504 can be used to store data based on its ferroelectric state, while the aluminum-rich second dielectric layer 506 can be used to improve the interface with the channel and reduce electron tunneling from the channel into layer 504. If the aluminum atom fraction of the second dielectric layer 506 is sufficiently high, this layer may lose its ferroelectric properties and serve as an interface layer to improve the quality of the interface with the channel. Alternatively, layer 506 may be a ferroelectric dielectric layer.

[0174] In the illustrative example, the first ferroelectric dielectric layer 504 may have Hf 1.5(1-α-β) Zr 1.5β Al 2α The material composition of O3, wherein α is in the range of 0.01 to 0.2 (such as 0.025 to 0.05), and β is in the range of 0 to 0.2. The second dielectric layer 506 may have Hf 1.5γ Zr 1.5δ Al 2(1-γ-δ) The material composition of O3, wherein γ is in the range of 0 to 0.2 (e.g., 0.05 to 0.15) and δ is in the range of 0 to 0.2. For example, the first ferroelectric dielectric layer 504 may be hafnium oxide with an aluminum molar fraction of 0.05 to 0.08 (i.e., aluminum-doped orthorhombic ferroelectric hafnium oxide), while the second dielectric layer 506 may have an aluminum molar fraction of 0.6 to 1 (i.e., it may consist substantially of non-ferroelectric aluminum oxide or hafnium-doped aluminum oxide).

[0175] The thickness of the first ferroelectric dielectric layer 504 can be in the range of 6 nm to 16 nm, such as in the range of 8 nm to 12 nm. The thickness of the second dielectric layer 506 can be in the range of 0.5 nm to 3 nm (such as 1 nm to 2 nm), but smaller and larger thicknesses are also possible.

[0176] When using an aluminum-doped hafnium oxide layer for the first ferroelectric dielectric layer 504 and the second dielectric layer 506, the molar fraction of aluminum atoms in each of the first ferroelectric dielectric layer 504 and the second dielectric layer 506 can be provided by adjusting the cycle ratio of the hafnium deposition cycle to the aluminum deposition cycle. For the deposition of the first ferroelectric dielectric layer 504, the cycle ratio can be in the range of 20:1 to 10:1, and for the deposition of the second dielectric layer 506, the cycle ratio can be in the range of 1:1.5 to 1:10.

[0177] A sacrificial cover layer 508 may be formed over at least one ferroelectric dielectric layer (504, 506). The sacrificial cover layer 508 comprises a thin layer of sacrificial material that protects at least one ferroelectric dielectric layer (504, 506) during subsequent anisotropic etching processes and may be selectively removed from at least one ferroelectric dielectric layer (504, 506). For example, the sacrificial cover layer 508 may comprise amorphous silicon and may have a thickness in the range of 1 nm to 5 nm. A thermal annealing process (such as rapid thermal annealing (RTA)) at a temperature of at least 1,000 degrees Celsius for 1 to 2 seconds may be performed to induce crystallization of at least one ferroelectric dielectric layer (504, 506), thereby inducing ferroelectricity in at least one ferroelectric dielectric layer (504, 506).

[0178] refer to Figure 19D An anisotropic etching process can be performed to remove horizontal portions of the sacrificial cover material layer 508 and at least one ferroelectric dielectric layer (504, 506). The anisotropic etching process may include a reactive ion etching process comprising a first step having an etching chemical substance for etching the material of the sacrificial cover material layer 508, and a second step having an etching chemical substance for etching the material of at least one ferroelectric dielectric layer (504, 506). The central portion of each substrate channel portion 111 can be laterally recessed by the anisotropic etching process. A tubular ferroelectric dielectric layer 500, including the cylindrical remainder of the first ferroelectric dielectric layer 504 and the cylindrical remainder of the second ferroelectric dielectric layer 506, may be formed in each memory opening 49 and each support opening 19 after anisotropic etching of the first ferroelectric dielectric layer 504 and the second ferroelectric dielectric layer 506.

[0179] refer to Figure 19EThe sacrificial cover material layer 508 can be selectively removed from at least one ferroelectric dielectric layer (504, 506) using an isotropic etching process. For example, the sacrificial cover material layer 508 can be selectively removed from at least one ferroelectric dielectric layer (504, 506) using a wet etching process employing thermal trimethyl-2-hydroxyethyl ammonium hydroxide (“thermal TMY”) or tetramethyl ammonium hydroxide (TMAH).

[0180] refer to Figure 19F A two-dimensional electron gas (“2DEG”) channel layer (such as a metal dichalcogenide layer 60L) is deposited on the physically exposed surfaces of the substrate channel portion 111, the tubular ferroelectric layer 500, and the insulating cap layer 70. In one embodiment, the metal dichalcogenide in the metal dichalcogenide layer 60L may comprise transition metal dichalcogenides, i.e., dichalcogenides of transition metals. For example, the transition metal dichalcogenide may comprise Mo. 1-x W x S 2-y Se y , where x is a number in the range of 0 (and including 0) to 1 (and including 1), and y is a number in the range of 0 (and including 0) to 2 (and including 2). Therefore, transition metal dichalcogenides may include MoS2, WS2, MoSe2, WSe2, or ternary or quaternary alloys thereof.

[0181] In one embodiment, the metal dichalcogenide layer 60L may have a Mo 1-x W x S 2-y Se y The thickness ranges from one to five monolayers. In one embodiment, the metal dichalcogenide layer 60L may have a Mo thickness ranging from 0.6 nm to 4 nm. 1-x W x S 2-y Se y The thickness is substantially uniform within the range. In one embodiment, the metal dichalcogenide layer 60L may have a Mo... 1-x W x S 2-y Se y The thickness ranges from one to three monolayers. Within this thickness range, the metal dichalcogenide layer 60L can provide a two-dimensional electron gas with quantum confinement (i.e., quantum confinement in the direction of the thickness of the metal dichalcogenide layer 60L) in the radial direction of the memory opening. When the base channel portion 111 is formed at the lower end of the memory opening, the metal dichalcogenide layer 60L can be formed directly on the top surface of the base channel portion.

[0182] In one embodiment, the two-dimensional electron gas channel layer 60L of Mo1-x W x S 2-y Se y The material can be obtained through Mo 1-x W x O y The alloy (i.e., molybdenum oxide, tungsten oxide, or molybdenum-tungsten oxide) film is deposited and sulfided (e.g., sulfided) directly on the tubular ferroelectric dielectric layer 500, wherein x ranges from 0 to 1 and y ranges from 2 to 3. 1-x W x O y Alloy films can be deposited using a supercycle atomic layer deposition (ALD) process, where one supercycle consists of n MoO atoms. x Deposition cycles and m WO3 deposition cycles, as described, for example, in J. Song et al., *Nature Communications*, 6:7817 (2015). Mo 1-x W x O y Alloy thin film sulfidation to form Mo 1-x W x S 2-y Se y Materials can be produced by one or two stepwise annealings in a chalcogenide environment (e.g., containing sulfur and / or selenium). For example, to form Mo... 1-x W x S2 thin films can be used to deposit Mo at temperatures ranging from 600 to 850°C in an environment containing argon and H2S. 1-x W x O y The alloy film is annealed for 30 to 60 minutes. Optionally, a second annealing step using rapid heat treatment (RTP) at a higher temperature of 950 to 1050 °C or furnace annealing for 15 to 30 minutes in the same environment may also be performed after the initial annealing.

[0183] MoO can be controlled x To optimize Mo's performance, the ALD cycle ratio between atomic layer deposition and WO3 was used. 1-x W x S 2-y Se y The composition and number of atomic layers in an alloy. Mo 1-x W x S 2-y Se y The band gap of an alloy can be precisely controlled as a function of the composition and number of layers of each corresponding alloy. Mo 1-x W x S 2-y Se yVertical composition control (VCC) multilayer stacks can be formed using a sequential supercycle atomic layer deposition process. For example, for each supercycle, five consecutive supercycles with different cycle ratios of atomic layer deposition steps can be performed. VCC Mo synthesized using this method... 1-x W x S 2-y Se y Multilayer stacking can have better performance than transferring Mo alone. 1-x W x S 2- y Se y VCC Mo manufactured in a single layer 1-x W x S 2-y Se y Stronger interlayer coupling within multilayer stacks.

[0184] Therefore, in one embodiment, the two-dimensional electron gas channel layer 60L can be formed by performing multiple consecutive cycles of molybdenum oxide layer deposition and tungsten oxide layer deposition, followed by sulfidation at a high temperature.

[0185] The metal dichalcogenide material of the two-dimensional electron gas channel layer 60L can be deposited as a crystalline semiconductor material or an amorphous semiconductor material, which can then be annealed to convert into the crystalline semiconductor material As used herein. "Crystal material" refers to a single-crystal or polycrystalline material. In one embodiment, the metal dichalcogenide material of the two-dimensional electron gas channel layer 60L can be formed as or can be converted into a polycrystalline material during the annealing process. The two-dimensional semiconductor channel material of the two-dimensional electron gas channel layer 60L is formed directly on the physically exposed surface of the tubular ferroelectric dielectric layer 500.

[0186] Non-single-crystal semiconductor films can be crystallized to varying degrees. For example, polycrystalline semiconductor films are composed of “grains.” Within each grain, the material is in a crystalline phase. That is, within each grain, the crystal structure is oriented in the same way. However, the crystal orientation can differ in different grains. As used herein, polycrystalline semiconductor materials include nanocrystals, microcrystals, or even larger crystals. The terminology depends on the grain size. Nanocrystals have a size of approximately one nanometer (1 × 10⁻⁶). -9 Average grain size ranges from one micrometer (m) to hundreds of nanometers. Microcrystals have an average grain size of one micrometer (1 × 10⁻⁶ m). -6 The average grain size ranges from several meters to hundreds of micrometers. Therefore, polycrystalline semiconductor materials can have a higher atomic number than amorphous semiconductor materials. Consequently, the defect state density of polycrystalline semiconductor films is lower than that of amorphous semiconductor films.

[0187] refer to Figure 19GOptionally, a channel-side interface dielectric layer 522 is formed on the inner sidewall of the two-dimensional electron gas channel layer 60L. The channel-side interface dielectric layer 522 comprises a dielectric material that improves interface quality and reduces the trap density of the two-dimensional electron gas channel layer 60L at the interface with the channel-side interface dielectric layer 522, thereby improving the charge carrier mobility in the two-dimensional electron gas channel layer 60L. In one embodiment, the channel-side interface dielectric layer 522 comprises hafnium aluminum oxide, hafnium oxide, or aluminum oxide. The thickness of the channel-side interface dielectric layer 522 can be in the range of 1 nm to 2 nm.

[0188] refer to Figure 19H Dielectric core 62 is formed within each cavity 49' laterally surrounded by a channel-side interface dielectric layer 522. For example, a dielectric material, such as silicon oxide or organosilicon glass, can be deposited in each cavity 49' by conformal deposition methods such as low-pressure chemical vapor deposition (LPCVD) or by self-planarization deposition processes such as spin coating.

[0189] The horizontal portions of the dielectric material, the optional channel-side interface dielectric layer 522 (if present), and the two-dimensional electron gas channel layer 60L can be removed from above the top surface of the insulating cap layer 70 using a planarization process. Planarization processes can be employed, such as by dip etching or chemical mechanical planarization. Each remaining portion of the two-dimensional electron gas channel layer 60L constitutes a two-dimensional electron gas channel 60 extending through the memory opening and located within the tubular ferroelectric dielectric layer 500. Each remaining portion of the dielectric material constitutes a dielectric core 62 located within the two-dimensional electron gas channel 60 and the optional channel-side interface dielectric layer 522.

[0190] refer to Figure 19I The top surface of the remaining portion of the dielectric core layer may be recessed, for example, by recess etching to a certain depth to form a recessed region within each memory opening 49, the depth being between the top surface and the bottom surface of the insulating cap layer 70. The top surface of the dielectric core 62 lies between a first horizontal plane including the top surface of the insulating cap layer 70 and a second horizontal plane including the bottom surface of the insulating cap layer 70.

[0191] refer to Figure 19J The doped semiconductor drain portion 630 can be formed by depositing doped semiconductor material in each recessed region above the dielectric core 62. The doped semiconductor drain portion 630 is a drain region containing doped semiconductor material. The doped semiconductor material can be, for example, doped polysilicon or doped compound semiconductor material. In one embodiment, the atomic concentration of the dopant of the second conductivity type in the doped semiconductor material can be 1.0 × 10⁻⁶. 19 / cm 3 Up to 2.0×10 21 / cm 3Within the range, but smaller and larger atomic concentrations can also be used. Dopant can be introduced in situ during growth and / or ex-situ after growth by ion implantation.

[0192] Excess of the deposited semiconductor material can be removed from the top surface of the insulating cap layer 70, for example, by chemical mechanical planarization (CMP) or recess etching, to form a doped semiconductor drain portion 630 embedded within the two-dimensional electron gas channel 60. In one embodiment, the top surface of the doped semiconductor drain portion 630 may be coplanar with the top surface of the insulating cap layer 70. In one embodiment, the top surfaces of the doped semiconductor drain portion 630, the optional channel side interface dielectric layer 522, the two-dimensional electron gas channel 60, and the tubular ferroelectric dielectric layer 500 may be coplanar with the top surface of the insulating cap layer 70. The doped semiconductor drain portion 630, including the portion of the doped semiconductor material, may be formed directly on the sidewall of the two-dimensional electron gas channel 60.

[0193] Due to the two-dimensional or pseudo-two-dimensional properties of the two-dimensional electron gas channel 60, a two-dimensional electron gas can be formed within the two-dimensional electron gas channel 60. The two-dimensional electron gas can be a cylindrically confined electron gas. As used herein, "cylindrical confinement" refers to two-dimensional confinement where the global topology of the two-dimensional space is homogeneous with respect to the sidewall surfaces of a cylinder. Quantum confinement (e.g., quantization) of electrons occurs within the channel. Electron currents can flow vertically with high mobility in the cylindrically confined electron gas.

[0194] Each successive combination of the tubular ferroelectric dielectric layer 500 and the two-dimensional electron gas channel 60 within the memory opening 49 constitutes a memory stack structure 55. The collection of all material portions filling the memory opening 49 constitutes a memory opening filling structure 58. Figure 19J A first exemplary memory opening-fill structure 58 is shown, which includes an optional base channel portion 111, a memory stack structure 55, an optional channel-side interface dielectric layer 522, a dielectric core 62, and a drain region 63.

[0195] refer to Figure 19K An alternative embodiment of the first exemplary memory aperture filling structure 58 is shown. An alternative embodiment of the first exemplary memory aperture filling structure 58 can be achieved by implanting ions (such as n-type dopants) into the upper portion of the two-dimensional electron gas channel 60. Figure 19I structure or Figure 3The structure of J is derived. The implanted upper portion of the two-dimensional electron gas channel 60 is transformed into a doped cyclic metal disulfide portion referred to herein as a cyclic doped metal disulfide drain portion 631. Each drain region 63 may include a set of cyclic doped metal disulfide drain portions 631 and doped semiconductor drain portions 630. In one embodiment, it is possible to... Figure 19I After the processing steps and Figure 19J Ion implantation is performed prior to the processing steps. In another embodiment, it can be performed... Figure 19J Ion implantation is performed after the processing steps. In this case, the doped semiconductor drain portion 630 can be directly formed on the inner sidewall of the annular doped metal dichalcogenide drain portion 631 as another component of the drain region 63.

[0196] Generally, a vertical stack of ferroelectric memory elements can be formed at the periphery of each memory opening 49 at each layer of the spacer material layer (which may be the sacrificial material layer 142). The ferroelectric memory elements can be formed by conformal deposition and anisotropic etching of at least one ferroelectric dielectric layer (504, 506). The ferroelectric memory element includes a corresponding portion of a tubular ferroelectric dielectric layer 500 located at the corresponding layer of the sacrificial material layer 142. A two-dimensional electron gas channel 60 is formed within each tubular ferroelectric dielectric layer 500. A dielectric core 62 may be formed within each two-dimensional electron gas channel 60.

[0197] refer to Figure 20A The diagram illustrates the compositional variation of the tubular ferroelectric dielectric layer 500 as a function of the radial distance R from the vertical axis passing through the geometric center of the memory opening filling structure 58. The interface between the sacrificial material layer 142 and the tubular ferroelectric dielectric layer 500 corresponds to the interface between the gate electrode to be formed subsequently and the ferroelectric memory element. The interface between the tubular ferroelectric dielectric layer 500 and the two-dimensional electron gas channel 60 corresponds to the interface between the ferroelectric memory element and the semiconductor channel of the transistor. The portion of the tubular ferroelectric dielectric layer 500 including the first ferroelectric dielectric layer 504 may have Hf. 1.5(1-α-β) Zr 1.5β Al 2α The material composition of O3, wherein α is in the range of 0.01 to 0.2 and β is in the range of 0 to 0.2. The portion of the tubular ferroelectric dielectric layer 500 including the second dielectric layer 506 may have Hf. 1.5γ Zr 1.5δ Al 2(1-γ-δ) The material composition of O3 includes γ in the range of 0.05 to 0.2 and δ in the range of 0 to 0.2. Therefore, the first ferroelectric dielectric layer 504 includes a first hafnium aluminum oxide or hafnium zirconium aluminum oxide layer, and the second dielectric layer 506 includes a second hafnium aluminum oxide or hafnium zirconium aluminum oxide layer having a higher aluminum concentration than the first hafnium aluminum oxide or hafnium zirconium aluminum oxide layer.

[0198] refer to Figure 20B and Figure 20C The following is a strip diagram of the tubular ferroelectric dielectric layer 500, showing the following case: wherein the first ferroelectric dielectric layer 504 has Hf 1.35 Al 0.2 The material composition is O3, and the second dielectric layer 506 has a material composition with a higher aluminum to hafnium atomic ratio compared to the first ferroelectric dielectric layer 504. For example... Figure 20B As shown, for an exemplary gate bias voltage of 4 to 8V applied during the erase operation, electron tunneling from the two-dimensional electron gas channel 60 to the first ferroelectric dielectric layer 504 can occur due to Hf in the second dielectric layer 506. 1.35 Al 0.2 O3 decreases due to its wider bandwidth.

[0199] like Figure 20C As shown, for an exemplary gate bias voltage of -4 to -8V applied during program operation, hole tunneling from the two-dimensional electron gas channel 60 to the first ferroelectric dielectric layer 504 can also occur due to Hf in the second dielectric layer 506. 1.35 Al 0.2 O3 decreases due to its wider bandwidth.

[0200] Figures 21A to 21C The process for forming a second exemplary memory opening-fill structure according to the sixth embodiment is shown. (Reference) Figure 21A , Figure 19I The first exemplary memory opening-fill structure can be modified by forming a ring-shaped doped metal disulfide drain portion 631. The ring-shaped doped metal disulfide drain portion 631 can be formed, for example, by implanting ions into the upper portion of the two-dimensional electron gas channel 60 using an ion implantation process or a plasma doping process. The upper portion of the two-dimensional electron gas channel 60 is transformed into the ring-shaped doped metal disulfide drain portion 631. Therefore, the ring-shaped doped metal disulfide drain portion 631 contacts the upper end of the remaining portion of the two-dimensional electron gas channel 60. The ring-shaped doped metal disulfide drain portion 631 is a component of the drain region.

[0201] refer to Figure 21BThe metal material layer can be directly deposited on the annular doped metal disulfide drain portion 631. The metal material layer may include and / or may consist of: a nickel layer, a nickel silicide layer, a heavily N+ doped polysilicon layer, a stack of titanium and gold layers, or a stack of nickel and gold layers. In an illustrative example, the stack of titanium layer 632 and gold layer 634 can be directly deposited on the annular doped metal disulfide drain portion 631. Titanium layer 632 may be substantially composed of titanium and may have a thickness ranging from 1 nm to 30 nm, but smaller and larger thicknesses are also possible. Gold layer 634 may be substantially composed of gold and may have a thickness ranging from 1 nm to 30 nm, but smaller and larger thicknesses are also possible. A recessed region may exist above the dielectric core 62 and within the sidewalls of the stack of titanium layer 632 and gold layer 634.

[0202] refer to Figure 21C Doped semiconductor materials (such as N-doped polysilicon) can be deposited within the recessed region. This can be achieved using methods similar to those used in... Figure 19J The same deposition method is used in the processing steps to deposit the doped semiconductor material to form the doped semiconductor drain portion 630. In one embodiment, the atomic concentration of the dopant of the second conductivity type in the doped semiconductor material can be 1.0 × 10⁻⁶. 19 / cm 3 Up to 2.0×10 21 / cm 3 Within the range, but smaller and larger atomic concentrations can also be used. Dopant can be introduced in situ during growth and / or ex-situ after growth by ion implantation.

[0203] The portions of the doped semiconductor material, gold layer 634, and titanium layer 632 located above a horizontal plane including the top surface of the insulating cap layer 70 can be removed by a planarization process, which may include at least one recess etching and / or chemical mechanical planarization. Each remaining portion of the doped semiconductor material is a doped semiconductor drain region 630. Each remaining portion of the gold layer 634 may include a cylindrical portion and a horizontal bottom portion. Each remaining portion of the titanium layer 632 may include a cylindrical portion and a horizontal bottom portion. Each drain region 63 may include an annular doped metal dichalcogenide drain portion 631, a titanium layer 632 contacting the annular doped metal dichalcogenide drain portion 631, a gold layer 634 contacting the titanium layer 632, and a doped semiconductor drain portion 630, the doped semiconductor drain portion being embedded within and laterally surrounded by the stack of titanium layers 632 and gold layers 634. Thus, the doped semiconductor drain portion 630 is formed within a cavity laterally surrounded by the stack of titanium layers 632 and gold layers 634. A second exemplary memory opening filling structure 58 is disposed within each memory opening 49.

[0204] refer to Figure 21DAn alternative embodiment of the second exemplary memory opening-fill structure 58 can be derived from the second exemplary memory opening-fill structure 58 by omitting the formation of the cyclic doped metal dichalcogenide drain portion 631. In this case, the titanium layer 632 can be formed directly on the sidewall of the two-dimensional electron gas channel 60. The doped semiconductor drain portion 630 can be formed by in-situ doping of the deposited semiconductor material.

[0205] refer to Figure 22A This illustrates a memory opening 49 including a third exemplary memory opening filling structure 58 according to a seventh embodiment. The third exemplary memory opening filling structure 58 can be operated from... Figure 21B The second exemplary memory aperture filling structure 58 is derived by selecting the thicknesses of the titanium layer 632 and the gold layer 634 such that the entire cavity above the dielectric core 62 is filled with a stack of titanium layers 632 and gold layers 634, and using a planarization process to remove a portion of the stack of titanium layers 632 and gold layers 634 from above a horizontal plane including the top surface of the insulating cap layer 70. In this case, each drain region 63 may include a ring-shaped doped metal dichalcogenide drain portion 631, titanium layer 632, and gold layer 634.

[0206] refer to Figure 22B This illustrates an alternative embodiment of the third exemplary memory aperture filling structure 58, which can be achieved by omitting the formation of the cyclic doped metal dichalcogenide drain portion 631. Figure 22A A third exemplary memory opening-filling structure 58 is derived. In this case, the titanium layer 632 can be formed directly on the sidewall of the two-dimensional electron gas channel 60.

[0207] Multiple instances of any of the exemplary memory opening filling structures 58 described above can be formed in Figure 18A and 18B In the fifth exemplary structure shown. Figure 23 A fourth exemplary structure is shown, including multiple instances of an exemplary memory opening filling structure 58. The fourth exemplary structure may be... Figure 19J , Figure 19K , Figure 21C , Figure 21D , Figure 22A or Figure 22B Any of the exemplary memory opening-filling structures.

[0208] refer to Figure 24A and Figure 24BThe contact-level dielectric layer 73 may be formed over the alternating stacks (132, 142) of the insulating layer 132 and the sacrificial material layer 142, as well as over the memory aperture filling structure 58 and the support pillar structure 24. The contact-level dielectric layer 73 contains a dielectric material different from that of the sacrificial material layer 142. For example, the contact-level dielectric layer 73 may contain silicon oxide. The contact-level dielectric layer 73 may have a thickness in the range of 50 nm to 500 nm, but smaller and larger thicknesses are also possible.

[0209] A photoresist layer (not shown) may be applied over the contact-level dielectric layer 73 and photolithographically patterned to form openings in regions between clusters of the memory stack structure 55. The pattern in the photoresist layer may be transferred through the contact-level dielectric layer 73, alternating stacks (132, 142), and / or reverse stepped dielectric material portions 65 by anisotropic etching to form back-side trenches 79, which extend at least vertically from the top surface of the contact-level dielectric layer 73 to the top surface of the substrate (109, 110) and laterally through the memory array region 1100 and the stepped region 300.

[0210] In one embodiment, the back-side trenches 79 may extend laterally along a first horizontal direction hd1 and may be laterally spaced from each other along a second horizontal direction hd2, the second horizontal direction being perpendicular to the first horizontal direction hd1. The memory stack structure 55 may be arranged in rows extending along the first horizontal direction hd1. Drain selection level isolation structures 72 may extend laterally along the first horizontal direction hd1. Each back-side trench 79 may have a uniform width that remains constant along the longitudinal direction (i.e., along the first horizontal direction hd1). Each drain selection level isolation structure 72 may have a uniform vertical cross-sectional profile along a vertical plane perpendicular to the first horizontal direction hd1, the uniform vertical cross-sectional profile not changing with translation along the first horizontal direction hd1. Multiple rows of the memory stack structure 55 may be located between adjacent pairs of back-side trenches 79 and drain selection level isolation structures 72, or between adjacent pairs of drain selection level isolation structures 72. In one embodiment, the back-side trenches 79 may include source contact openings in which source contact via structures may subsequently be formed. The photoresist layer can be removed, for example, by ashing.

[0211] A dopant of a second conductivity type can be implanted into the portion of the semiconductor material layer 110 below the back trench 79 to form a source region 61. The atomic concentration of the dopant of the second conductivity type in the source region 61 can be 5.0 × 10⁻⁶. 19 / cm 3 Up to 2.0×10 21 / cm 3Within the range, but smaller and larger atomic concentrations can also be used. The surface portion of the semiconductor material layer 110 extending between each source region 61 and the adjacent memory opening-fill structure 58 includes a horizontal semiconductor channel 59.

[0212] refer to Figure 25 An etchant can be introduced into the back trench 79, for example, using an etching process, which selectively etches a second material of the sacrificial material layer 142 relative to a first material of the insulating layer 132. A back recess 143 is formed in the volume from which the sacrificial material layer 142 is removed. The removal of the second material of the sacrificial material layer 142 can be selective for the first material of the insulating layer 132, the material of the reverse stepped dielectric portion 65, the semiconductor material of the semiconductor material layer 110, and the material of the outermost layer of the annular ferroelectric dielectric layer 500. In one embodiment, the sacrificial material layer 142 may comprise silicon nitride, and the materials of the insulating layer 132 and the reverse stepped dielectric portion 65 may be selected from silicon oxide and dielectric metal oxides.

[0213] The etching process for selectively removing the second material from the outermost layer of the first material and the annular ferroelectric dielectric layer 500 can be a wet etching process using a wet etching solution, or a vapor-phase (dry) etching process in which the etchant is introduced into the back trench 79 in a vapor phase. For example, if the sacrificial material layer 142 comprises silicon nitride, the etching process can be a wet etching process that immerses the exemplary structure in a wet etching bath comprising phosphoric acid, which selectively etches silicon nitride for silicon oxide, silicon, and various other materials used in the art. When the back recess 143 is present within the volume previously occupied by the sacrificial material layer 142, the support pillar structure 24, the reverse stepped dielectric material portion 65, and the memory opening filling structure 58 provide structural support.

[0214] Each back-side recess 143 may be a laterally extending cavity having a lateral dimension greater than the vertical extent of the cavity. In other words, the lateral dimension of each back-side recess 143 may be greater than the height of the back-side recess 143. A plurality of back-side recesses 143 may be formed in a volume of a second material from which the sacrificial material layer 142 is removed. The memory openings forming the memory stack structure 55 are referred herein as front openings or front cavities, in contrast to the back-side recesses 143. In one embodiment, the memory array region 1100 includes a single three-dimensional NAND string array having a plurality of device levels disposed above a substrate (109, 110). In this case, each back-side recess 143 may define space for accommodating a corresponding word line of the single three-dimensional NAND string array.

[0215] Each of the plurality of back-side recesses 143 may extend substantially parallel to the top surface of the substrate (109, 110). The back-side recesses 143 may be vertically defined by the top surface of the underlying insulating layer 132 and the bottom surface of the covering insulating layer 132. In one embodiment, each back-side recess 143 is designed to always have a uniform height.

[0216] The optional substrate channel portion 111 and the physically exposed surface portions of the semiconductor material layer 110 can be converted into dielectric material portions by thermal conversion and / or plasma conversion of the semiconductor material into a dielectric material. For example, thermal conversion and / or plasma conversion can be used to convert the surface portions of each substrate channel portion 111 into tubular dielectric spacers 116, and each physically exposed surface portion of the semiconductor material layer 110 into planar dielectric portions 616. In one embodiment, each tubular dielectric spacer 116 may be topologically homeomorphic to a torus, i.e., generally toroidal. As used herein, a device is topologically homeomorphic to a torus if the shape of the device can be stretched sustainably without destroying holes or forming new holes in the shape of the torus. The tubular dielectric spacer 116 comprises a dielectric material containing the same semiconductor elements as the substrate channel portion 111, and additionally contains at least one nonmetallic element, such as oxygen and / or nitrogen, such that the material of the tubular dielectric spacer 116 is a dielectric material. In one embodiment, the tubular dielectric spacer 116 may comprise a dielectric oxide, dielectric nitride, or dielectric oxynitride of the semiconductor material of the base channel portion 111. Similarly, each planar dielectric portion 616 comprises a dielectric material containing the same semiconductor elements as the semiconductor material layer and additionally containing at least one nonmetallic element, such as oxygen and / or nitrogen, such that the material of the planar dielectric portion 616 is a dielectric material. In one embodiment, the planar dielectric portion 616 may comprise a dielectric oxide, dielectric nitride, or dielectric oxynitride of the semiconductor material of the semiconductor material layer 110. Dopants in the drain region 63 and source region 61 may be activated during the annealing process forming the planar dielectric portion 616 and the tubular dielectric spacer 116. Alternatively, an additional annealing process may be performed to activate ions in the drain region 63 and source region 61.

[0217] refer to Figure 26AAt least one metallic material can be deposited in the backside recess 143 using at least one conformal deposition process. The at least one metallic material may include, for example, a metal barrier layer or metal filler material. The metal barrier layer comprises a conductive metallic material that can serve as a diffusion barrier layer and / or adhesion promoter layer for the subsequently deposited metal filler material. The metal barrier layer may comprise a conductive metal nitride material, such as TiN, TaN, WN, or a stack thereof; or may comprise a conductive metal carbide material, such as TiC, TaC, WC, or a stack thereof. In one embodiment, the metal barrier layer can be deposited using a conformal deposition process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). The thickness of the metal barrier layer can range from 2 nm to 8 nm, such as 3 nm to 6 nm, but smaller and larger thicknesses are also possible. In one embodiment, the metal barrier layer may consist substantially of a conductive metal nitride such as TiN.

[0218] A metal filler layer is then deposited over the metal barrier layer using a conformal deposition method, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof. In one embodiment, the metal filler layer may consist substantially of at least one elemental metal. The at least one elemental metal of the metal filler layer may be selected from, for example, tungsten, cobalt, ruthenium, titanium, and tantalum. In one embodiment, the metal filler layer may consist substantially of a single elemental metal. In one embodiment, the metal filler layer may be deposited using a fluorine-containing precursor gas such as WF6. In one embodiment, the metal filler layer may be a tungsten layer including a residual amount of fluorine atoms as impurities. The metal filler layer is spaced from the insulating layer 132 and the memory opening filling structure 58 by a metal barrier layer that prevents fluorine atoms from diffusing therefrom.

[0219] Multiple conductive layers 146 may be formed in multiple back-side recesses 143, and a continuous conductive material layer may be formed on the sidewalls of each back-side trench 79 and above the contact-level dielectric layer 73. Each conductive layer 146 includes a portion of a metal barrier layer and a portion of a metal filler layer located between a pair of vertically adjacent dielectric material layers (such as a pair of insulating layers 132). The continuous conductive material layer includes a continuous portion of the metal barrier layer and a continuous portion of the metal filler layer located in the back-side trench 79 or above the contact-level dielectric layer 73.

[0220] Each sacrificial material layer 142 may be replaced by a conductive layer 146. A back cavity exists in the portion of each back trench 79 that is not filled with a continuous conductive material layer. Tubular dielectric spacers 116 laterally surround the base channel portion 111. When forming the conductive layer 146, the bottommost conductive layer 146 laterally surrounds each tubular dielectric spacer 116.

[0221] The deposited metallic material of the continuous conductive material layer is etched back from the sidewalls of each back trench 79 and from above the contact-level dielectric layer 73, for example, by isotropic wet etching, anisotropic dry etching, or a combination thereof. Each remaining portion of the deposited metallic material in the back recess 143 constitutes a conductive layer 146. Each conductive layer 146 may be a conductive line structure. Therefore, the sacrificial material layer 142 is replaced by the conductive layer 146. The planar dielectric portion 616 can be removed during the removal of the continuous conductive material layer. A back cavity exists within each back trench 79.

[0222] Each intermediate conductive layer 146 can serve as a combination of multiple control gate electrodes and word lines located on the same level, the word lines being electrically interconnected (i.e., electrically shorted) with the multiple control gate electrodes located on the same level. The multiple control gate electrodes within each conductive layer 146 are control gate electrodes of a vertical memory device comprising a memory stack structure 55. In other words, each conductive layer 146 can be a word line serving as a common control gate electrode for multiple vertical memory devices.

[0223] At least one topmost conductive layer 146 may serve as a drain-side selected gate electrode (SGD). At least one bottommost conductive layer 146 may serve as a source-side selected gate electrode (SGS). Optionally, at least one conductive layer 146 located between the SGD and the word line may include a drain-side dummy word line to mitigate the impact on drain-side edge memory cells in the memory string. Optionally, at least one additional conductive layer 146 located between the SGS and the word line may include a source-side dummy word line to mitigate the impact on source-side edge memory cells in the memory string.

[0224] refer to Figure 26B and Figure 26C This illustrates an alternative embodiment of a region surrounding a memory opening filling structure 58 containing a ferroelectric side interface dielectric layer 530, which can be derived from... Figure 26A The fourth exemplary structure shown is derived. Figure 26B In one embodiment, a ferroelectric side interface dielectric layer 530 is formed in the memory opening 49 before the tubular ferroelectric dielectric layer 500 is formed. Figure 26CIn one embodiment, prior to the formation of the conductive layer 146, the ferroelectric side interface dielectric layer 530 is formed directly on the back-side recess 143 on the physically exposed cylindrical outer wall section of the tubular ferroelectric dielectric layer 500 of each memory opening-filling structure 58, and directly on the physically exposed horizontal surface of the insulating layer 132 and the insulating cap layer. The ferroelectric side interface dielectric layer 530 contains a dielectric material that improves interface quality and enhances the ferroelectric properties of the tubular ferroelectric dielectric layer 500 and the conductive layer 146. The ferroelectric side interface dielectric layer 530 contains hafnium aluminum oxide, hafnium oxide, or aluminum oxide. The thickness of the channel-side interface dielectric layer 522 can be in the range of 1 nm to 2 nm.

[0225] refer to Figure 27 An insulating material layer can be formed in the back trench 79 and over the contact-level dielectric layer 73 using a conformal deposition process. Exemplary conformal deposition processes include, but are not limited to, chemical vapor deposition and atomic layer deposition. The insulating material layer comprises an insulating material such as silicon oxide, silicon nitride, dielectric metal oxide, organosilicon glass, or a combination thereof. In one embodiment, the insulating material layer may comprise silicon oxide. The insulating material layer can be formed, for example, by low-pressure chemical vapor deposition (LPCVD) or atomic layer deposition (ALD). The thickness of the insulating material layer can range from 1.5 nm to 60 nm, but smaller and larger thicknesses are also possible.

[0226] Anisotropic etching is performed to remove horizontal portions of the insulating material layer from above the contact-level dielectric layer 73 and from the bottom of each back-side trench 79. Each remaining portion of the insulating material layer constitutes an insulating spacer 74. A back-side cavity exists within the volume surrounded by each insulating spacer 74. The top surface of the semiconductor material layer 110 may be physically exposed at the bottom of each back-side trench 79.

[0227] The upper portion of the semiconductor material layer 110 extending between the source region 61 and the plurality of base channel portions 111 constitutes a horizontal semiconductor channel 59 for a plurality of field-effect transistors. The horizontal semiconductor channel 59 is connected to a plurality of metal dichalcogenide channels 60 via corresponding base channel portions 111. The horizontal semiconductor channel 59 contacts the source region 61 and the plurality of base channel portions 111. Each source region 61 is formed in the upper portion of the substrate (109, 110). Semiconductor channels (59, 111, 60) extend between each source region 61 and a corresponding set of drain regions 63. The semiconductor channels (59, 111, 60) comprise a two-dimensional electron gas channel 60 of a memory stack structure 55.

[0228] A back-side contact via structure 76 may be formed in each back-side cavity. Each contact via structure 76 may fill a corresponding back-side cavity. The contact via structure 76 may be formed by depositing at least one conductive material in the remaining unfilled volume (i.e., the back-side cavity) of the back-side trench 79. For example, at least one conductive material may include a conductive pad 76A and a conductive filler portion 76B. The conductive pad 76A may include a conductive metal pad, such as TiN, TaN, WN, TiC, TaC, WC, alloys thereof, or stacks thereof. The thickness of the conductive pad 76A may range from 3 nm to 30 nm, but smaller and larger thicknesses are also possible. The conductive filler portion 76B may include a metal or metal alloy. For example, the conductive filler portion 76B may contain W, Cu, Al, Co, Ru, Ni, alloys thereof, or stacks thereof.

[0229] At least one conductive material can be planarized using a contact-level dielectric layer 73 covering the alternating stacks (132, 146) as a terminating layer. If a chemical mechanical planarization (CMP) process is used, the contact-level dielectric layer 73 can be used as a CMP terminating layer. Each remaining continuous portion of at least one conductive material in the back-side trench 79 constitutes a back-side contact via structure 76. The back-side contact via structure 76 extends through the alternating stacks (132, 146) and contacts the top surface of the source region 61.

[0230] refer to Figure 28A and Figure 28B Additional contact via structures (88, 86, 8P) may be formed through the contact-level dielectric layer 73 and optionally through the reverse stepped dielectric portion 65. For example, a drain contact via structure 88 may be formed through the contact-level dielectric layer 73 on each drain region 63. A word line contact via structure 86 may be formed on the conductive layer 146 through the contact-level dielectric layer 73 and through the reverse stepped dielectric portion 65. A peripheral device contact via structure 8P may be formed directly on the corresponding node of the peripheral device through the reverse stepped dielectric portion 65.

[0231] Referring to all embodiments of this disclosure, the ferroelectric memory device includes a two-dimensional electron gas channel 60, a gate electrode (46, 146), and ferroelectric memory elements (21, 22, 23, 500) located between the gate electrode and the two-dimensional electron gas channel.

[0232] Each of the second to fourth exemplary structures disclosed herein may include alternating stacks of an insulating layer 132 and a conductive layer 146 (one of which includes the gate electrode mentioned above) above a substrate (109, 110), a memory opening 49 extending vertically through the alternating stacks, a two-dimensional electron gas channel 60 located inside the memory opening, a ferroelectric memory element (e.g., a portion of layer 500) located between the channel 60 and the conductive layer 146, and a dielectric core 62 surrounded by the channel.

[0233] In one embodiment, the two-dimensional electron gas channel 60 includes a metal dichalcogenide channel. In one embodiment, the ferroelectric memory element includes a tubular ferroelectric dielectric layer 500 extending vertically through portions of alternately stacked conductive layers 146.

[0234] In one embodiment, the tubular ferroelectric dielectric layer 500 includes: a first ferroelectric dielectric layer 504 having a first bandgap energy; and a second dielectric layer 506 having a second bandgap energy greater than the first bandgap energy and located between the first ferroelectric dielectric layer 504 and a metal dichalcogenide channel.

[0235] In one embodiment, the first ferroelectric dielectric layer 504 comprises a first hafnium aluminum oxide or hafnium zirconium aluminum oxide layer; and the second dielectric layer 506 comprises a second hafnium aluminum oxide or hafnium zirconium aluminum oxide layer having a higher aluminum concentration than the first hafnium aluminum oxide or hafnium zirconium aluminum oxide layer. In one embodiment, the first ferroelectric dielectric layer 504 has Hf 1.5(1-α-β) Zr 1.5β Al 2α The material composition of O3, wherein α is in the range of 0.01 to 0.2 and β is in the range of 0 to 0.2; and the second dielectric layer 506 has Hf 1.5γ Zr 1.5δ Al 2(1-γ-δ) The material composition of O3, wherein γ is in the range of 0.05 to 0.2 and δ is in the range of 0 to 0.2.

[0236] In one embodiment, the metal dichalcogenide channel has a thickness ranging from one to five monolayers. In one embodiment, the metal dichalcogenide channel comprises Mo... 1-x W x S 2-y Se y The material is composed of x in the range of 0 to 1, and y is independent of x and in the range of 0 to 2.

[0237] In one embodiment, the substrate (109, 110) includes a semiconductor material layer 110. The bottom end of a metal dichalcogenide channel is electrically connected to the semiconductor material layer. In one embodiment, a single three-dimensional memory device includes a pedestal channel portion 111 located at the bottom end of a memory opening 49 and epitaxially aligned with the semiconductor material layer 110, wherein the metal dichalcogenide channel contacts the top surface of the pedestal channel portion 111.

[0238] In one embodiment, a single three-dimensional memory device includes a drain region 63 contacting the upper end of a metal disulfide channel. In one embodiment, the drain region 63 includes a ring-shaped doped metal disulfide drain portion 631. In one embodiment, the drain region 63 further includes a stack of nickel layers, nickel silicide layers, N+ doped polysilicon layers, titanium layers, and gold layers, or a stack of nickel and gold layers, such as a stack of titanium layers 632 and gold layers 634 embedded within the ring-shaped doped metal disulfide drain portion 631; and a doped semiconductor drain portion 630 embedded within the stack of titanium layers 632 and gold layers 634. The drain region 63 includes a doped semiconductor drain portion 630 contacting the inner sidewall of the ring-shaped doped metal disulfide drain portion 631. In one embodiment, the drain region 63 includes a stack of titanium layers 632 and gold layers 634; and the titanium layer 632 contacts the sidewall of the metal disulfide channel.

[0239] In one embodiment, the ferroelectric memory element is in direct contact with the conductive layer 146. In one embodiment, the memory device of this disclosure may be a single three-dimensional memory device comprising a vertical NAND device located above a substrate (109, 110), and the conductive layer 146 may include or be electrically connected to a corresponding word line of the vertical NAND device. The substrate (109, 110) may include a silicon substrate. The vertical NAND device may include a single three-dimensional NAND string array located above the silicon substrate. At least one memory cell in a first device level of the three-dimensional NAND string array is located above another memory cell in a second device level of the three-dimensional NAND string array. The silicon substrate may contain an integrated circuit including driving circuitry for positioning memory devices thereon.

[0240] A single three-dimensional NAND string array may include multiple metal dichalcogenide (MDA) channels. At least one end portion of each MDA channel extends substantially perpendicular to the top surface of the substrate (109, 110). In one embodiment, the multiple MDA channels may be connected in parallel to a common horizontal semiconductor channel portion, which is a portion of the semiconductor material layer 110 extending between the source region 61 and the base channel portion 111. The single three-dimensional NAND string array may include multiple memory elements (e.g., memory cells including portions of a tubular ferroelectric dielectric layer 500 present within each memory stack structure 55). Each memory element may be positioned adjacent to a corresponding MDA channel among the multiple MDA channels (i.e., two-dimensional electron gas channels 60). The single three-dimensional NAND string array may include multiple control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate (109, 110).

[0241] Two-dimensional metal dichalcogenide channels can have a thickness of no more than five atomic layers, and even more preferably no more than three atomic layers. Such thin metal dichalcogenide materials exhibit characteristics of providing two-dimensional channels with high charge carrier mobility. For example, MoS2 channels can have a thickness of up to approximately 200 cm⁻¹. 2 The field-confined mobility is / Vs. This is more than an order of magnitude higher than the field-confined mobility in a conventional polysilicon channel.

[0242] Higher electron mobility transport can be advantageously used to increase the on-current of the memory stack and increase the signal-to-noise ratio during read operations. Low leakage and low gate-induced drain leakage (“GIDL”) result in lower power consumption and less program and read interference. Lower leakage, (and therefore) better boost and less program interference result in lower power consumption. Alternatively, the operating voltage can be reduced, thereby reducing power consumption.

[0243] According to another aspect of this disclosure, any of the ferroelectric memory elements of this disclosure, such as ferroelectric memory element 21, back-side ferroelectric memory element 22, wound ferroelectric memory element 23, and / or ferroelectric dielectric layer 504, may comprise a two-dimensional van der Waals ferroelectric material. This material provides a van der Waals heterostructure with a two-dimensional electron gas channel 60. Due to the two-dimensional characteristics of the material therein, such structures can provide an ideal insulator / semiconductor interface without dangling bonds (with reduced dangling bonds) and improve device reliability. The smaller thickness of the ferroelectric memory element and semiconductor channel improves device scalability. Simultaneously, the higher mobility of the two-dimensional semiconductor channel provides higher cell current and enhanced performance. The thickness of the two-dimensional ferroelectric material can range from a single monolayer to five monolayers.

[0244] Non-limiting examples of two-dimensional ferroelectric materials include CuInP2S6, a-In2Se3, g-SbP, g-SbAs and group IV monochalcogenides having the MX form, wherein M is selected from Ge, Sn or Pb, and X is selected from S, Se or Te.

[0245] For example, α-In2Se3 is a ferroelectric material with a van der Waals structure that retains ferroelectric properties in a single monolayer with a thickness of about 1 nm, retains ferroelectric properties in a multilayer structure, and has a rhombic R3m structure that is non-centrosymmetric and supports polarization that can be switched by an external electric field.

[0246] In another example, γ-SbX (X = As, P) can be formed as a van der Waals two-dimensional ferroelectric film having a single monolayer or a thickness of 2 to 3 monolayers. Based on first-principles calculations, the ferroelectric memory device of this disclosure employing γ-SbX (X = As, P) is expected to exhibit approximately 3.80 × 10⁻⁶ Ω·cm. -10 Cm -1 (For γ-SbAs) or 3.47 × 10 -10 Cm -1 Excellent two-dimensional ferroelectricity (for γ-SbP). Furthermore, γ-SbX (X = As, P) can operate at extremely high temperatures. For example, the ferroelectricity of monolayer γ-SbAs or γ-SbP remains good over temperature ranges up to 600K or 700K. Therefore, γ-SbX can be used as a robust ferroelectric material in two-dimensional ferroelectric-two-dimensional semiconductor heterostructures to form various non-volatile memory devices of this disclosure, which may include three-dimensional NAND memory devices or three-dimensional NOR memory devices.

[0247] In yet another example, the two-dimensional van der Waals ferroelectric material may comprise CuInP2S6 (CIPS). In one example, CIPS can be deposited via chemical vapor deposition or conformal atomic layer deposition, for example, using a precursor of the corresponding stoichiometric element. The thickness of the CIPS can range from 2 nm to 6 nm. The deposited film can be annealed at a high temperature ranging from 650°C to 750°C for a duration ranging from 10 minutes to 30 minutes.

[0248] In one embodiment, an optional ferroelectric-side interface dielectric layer 530 may be formed between the gate or word line and the two-dimensional van der Waals ferroelectric material. The ferroelectric-side interface dielectric layer 530 may comprise aluminum oxide. For example, if the two-dimensional van der Waals ferroelectric material is used... Figure 28A The ferroelectric dielectric layer 504 in the three-dimensional NAND device shown can be deposited in the back recess 143 on the dielectric intermediate layer before the conductive layer 146 is deposited. Figure 25The ferroelectric side interface dielectric layer 530 is formed inside the back side recess 143 shown in the figure, such as Figure 26A As shown. Therefore, it can form with Figure 26C A structure similar to that of [other structures]. Alternatively, the tubular ferroelectric dielectric layer 500 can be formed as [a structure similar to [other structures]. Figure 26B Prior to a structure similar to the one described above, a ferroelectric side interface dielectric layer 530 may be formed in the memory opening 49.

[0249] refer to Figure 29 This illustrates a fifth exemplary structure according to a ninth embodiment of the present disclosure, the fifth exemplary structure being available from... Figure 15 The fifth exemplary structure is derived. In this case, the semiconductor material layer 110 may or may not be used. An insulating substrate may be used instead of the substrate semiconductor layer 109. At least one instance of a cell layer stack including a device isolation level insulating layer 332, a source level sacrificial layer 342, a channel level insulating layer 232, and a drain level sacrificial layer 442 may be formed over the substrate semiconductor layer 109. Multiple instances of cell layer stacks may be formed over the substrate. The total number of cell layer stacks may be in the range of 1 to 512, such as 2 to 128, but fewer and more cell layer stacks may also be used.

[0250] Each source-level sacrificial layer 342 and each drain-level sacrificial layer 442 contains sacrificial material that can selectively remove the material of the device isolation level insulating layer 332 and the channel level insulating layer 232. Furthermore, each channel level insulating layer 232 contains a material in an etchant that provides a high etch rate, the etchant selectively etching each device isolation level insulating layer 332 for each source-level sacrificial layer 342 and each drain-level sacrificial layer 442.

[0251] In one embodiment, a vertical stack including multiple instances of cell layer stacks can be derived from the alternating stacks (132, 142) of the fifth exemplary structure by employing each odd-numbered (e.g., counting from the bottom with an integer 1) sacrificial material layer 142 as a source-level sacrificial layer 342, employing each even-numbered sacrificial material layer 142 as a drain-level sacrificial layer 442, and by modifying the material composition of each even-numbered insulating layer 132 to provide a higher etchant etch rate than each odd-numbered insulating layer 132. In this case, the odd-numbered insulating layer 132 in the fifth exemplary structure can be a device isolation level insulating layer 332 in the fifth exemplary structure, and the even-numbered insulating layer 132 in the fifth exemplary structure can be a channel level insulating layer 232.

[0252] Alternatively, the positions of the source-level sacrificial layer 342 and the drain-level sacrificial layer 442 can be reversed. In this case, each odd-numbered (e.g., counting from the bottom with an integer 1) sacrificial material layer 142 in the fifth exemplary structure can be used as the source-level sacrificial layer 342 in the fifth exemplary structure, and each even-numbered sacrificial material layer 142 can be used as the drain-level sacrificial layer 442 in the fifth exemplary structure.

[0253] In the illustrative example, the source-level sacrificial layer 342 and the drain-level sacrificial layer 442 may comprise silicon nitride, the device isolation-level insulating layer 332 may comprise undoped silicate glass (such as TEOS oxide), and the channel-level insulating layer 232 may comprise doped silicate glass (such as borosilicate glass, borophosphosilicate glass, or fluorosilicate glass) or organosilicon glass. In this case, the channel-level insulating layer 232 may have an etch rate in 100:1 diluted hydrofluoric acid that is at least 5 times (such as 10 to 1,000 times) that of undoped silicate glass.

[0254] Generally, at least one instance of a cell layer stack may be formed over a substrate. The cell layer stack, from bottom to top or from top to bottom, may include a device isolation level insulating layer 332, a source level sacrificial layer 342, a channel level insulating layer 232, and a drain level sacrificial layer 442. In one embodiment, at least one instance of a cell layer stack comprises a vertical stack of multiple instances of a cell layer stack. An insulating cap layer 70 may be formed over at least one instance of the cell layer stack.

[0255] refer to Figure 30 Executable Figure 17 The processing steps are to form a stepped surface and a reverse stepped dielectric material portion 65.

[0256] refer to Figure 31 Executable Figure 18A and Figure 18B The processing steps are used to form the memory opening 49 and the support opening 19. The formation of the drain selection stage isolation structure 72 can be omitted.

[0257] refer to Figure 32An isotropic etching process is performed, which etches at a higher rate than the material of the device isolation layer 332 and selectively etches the material of the channel insulating layer 232 for the materials of the source sacrificial layer 342 and the drain sacrificial layer 442. If the source sacrificial layer 342 and the drain sacrificial layer 442 contain silicon nitride, if the device isolation layer 332 contains undoped silicate glass, and if the channel insulating layer 232 contains doped silicate glass, a wet etching process using diluted hydrofluoric acid (such as 100:1 diluted hydrofluoric acid) can be performed to selectively laterally recess the cylindrical sidewall sections of the channel insulating layer 232 for the source sacrificial layer 342, the drain sacrificial layer 442, and the device isolation layer 332.

[0258] The channel level recess 249 is formed by selectively laterally recessing the channel level insulating layer 232 for each source level sacrificial layer 342, each drain level sacrificial layer 442, and each device isolation level insulating layer 332. The channel level recess 249 is formed at each layer of the channel level insulating layer 232 around each memory opening 49 and around each support opening 19. The channel level recess 249 includes cylindrical voids from which material of the channel level insulating layer 232 is removed. In one embodiment, the lateral recess distance of the isotropic etching process is selected within the range of one to five monolayers of the subsequently deposited two-dimensional electron gas channel material.

[0259] refer to Figure 33 The two-dimensional electron gas channel 60 can be formed within the volume of the channel-level recess 249 by depositing a metal dichalcogenide layer with a thickness ranging from one to five monolayers, and by anisotropically etching the portion of the metal dichalcogenide layer located outside the volume of the channel-level recess 249. The metal dichalcogenide layer can be deposited using any of the methods described above. After the anisotropic etching process, each remaining cylindrical portion of the metal dichalcogenide layer constitutes the two-dimensional electron gas channel 60, which can be a cylindrical two-dimensional electron gas channel. A vertical stack of two-dimensional cylindrical electron gas channels 60 can be formed within each memory opening 49.

[0260] In one embodiment, each of the two-dimensional cylindrical electron gas channels 60 comprises a metal dichalcogenide channel. In one embodiment, each of at least one two-dimensional cylindrical electron gas channel within each memory opening 49 has a lateral thickness ranging from one to five monolayers and includes a two-dimensional electron gas therein. In one embodiment, each of at least one two-dimensional cylindrical electron gas channel within each memory opening 49 comprises a metal dichalcogenide channel. 1-x W xS 2-y Se y The material is composed of x in the range of 0 to 1, and y is independent of x and in the range of 0 to 2.

[0261] refer to Figure 34A and Figure 34B The tubular ferroelectric dielectric layer 500 can be formed by conformally depositing at least one ferroelectric dielectric material on the physically exposed sidewalls of the two-dimensional cylindrical electron gas channel 60, the source sacrificial layer 342, the drain sacrificial layer 442, and the device isolation insulating layer 332. The tubular ferroelectric dielectric layer 500 can be formed above the inner cylindrical sidewall of the two-dimensional cylindrical electron gas channel 60.

[0262] The tubular ferroelectric dielectric layer 500 may include any of the constructions described above and may be formed in any of the manner described above. In one embodiment, the tubular ferroelectric dielectric layer 500 may include a stack of a first ferroelectric dielectric layer 504 and a second dielectric layer 506, such that the second dielectric layer 506 is deposited directly on the inner cylindrical sidewall of the vertically stacked two-dimensional cylindrical electron gas channels 60 in each memory opening 49, and the first ferroelectric dielectric layer 504 is deposited on the second dielectric layer 506. The thickness and material composition of the second dielectric layer 506 may be the same as in the previously described embodiments. The thickness and material composition of the first ferroelectric dielectric layer 504 may be the same as in the previously described embodiments.

[0263] In one embodiment, each tubular ferroelectric dielectric layer 500 includes a first ferroelectric dielectric layer 504 having a first bandgap energy, and a second dielectric layer 506 having a second bandgap energy greater than the first bandgap energy and located within the same memory opening 49 between the first ferroelectric dielectric layer 504 and the two-dimensional electron gas channel 60. In one embodiment, the first ferroelectric dielectric layer 504 includes a first hafnium aluminum oxide or hafnium zirconium aluminum oxide layer; and the second dielectric layer 506 includes a second hafnium aluminum oxide or hafnium zirconium aluminum oxide layer having a higher aluminum concentration than the first hafnium aluminum oxide or hafnium zirconium aluminum oxide layer. In one embodiment, the first ferroelectric dielectric layer 504 may have Hf 1.5(1-α-β) Zr 1.5β Al 2α The material composition of O3, wherein α is in the range of 0.01 to 0.2 and β is in the range of 0 to 0.2, and the second dielectric layer 506 may have Hf 1.5γ Zr 1.5δ Al 2(1-γ-δ) The material composition of O3, wherein γ is in the range of 0.05 to 0.2 and δ is in the range of 0 to 0.2.

[0264] In another embodiment, each tubular ferroelectric dielectric layer 500 includes a two-dimensional van der Waals ferroelectric material layer comprising a ferroelectric material selected from CuInP2S6, a-In2Se3, g-SbP, g-SbAs, or a group IV monochalcogenide material having the MX form, wherein M is selected from Ge, Sn, or Pb, and X is selected from S, Se, or Te.

[0265] The ferroelectric side interface dielectric layer 530 may optionally be formed by conformal deposition of a dielectric material. The ferroelectric side interface dielectric layer 530 (if present) contains a dielectric material that improves interface quality. The ferroelectric side interface dielectric layer 530 contains hafnium aluminum oxide, hafnium oxide, or aluminum oxide. The thickness of the ferroelectric side interface dielectric layer 530 may be in the range of 1 nm to 2 nm.

[0266] Word lines 546 may be formed above the inner cylindrical sidewall of a tubular ferroelectric dielectric layer 500 within each memory opening 49 (e.g., formed on the ferroelectric side interface dielectric layer 530 if layer 530 is omitted, or formed directly on the tubular ferroelectric dielectric layer 500). Word lines 546 may extend vertically through each source sacrificial layer 342 and each drain sacrificial layer 442 within at least one instance of the unit layer stack. Word lines may comprise metallic materials such as titanium nitride, tantalum nitride, tungsten nitride, titanium, tantalum, tungsten, molybdenum, ruthenium, cobalt, copper, or any other transition metal element or alloy thereof. Word lines 546 may be formed by conformal deposition of at least one metallic material. The lateral thickness of each word line 546 may range from 6 nm to 100 nm, but smaller and larger thicknesses are also possible.

[0267] Where cavities exist in each memory opening 49 after the word line 546 has been formed, dielectric material can be deposited in the remaining volume of the memory opening 49. For example, silicon oxide can be deposited in the cavities within the memory opening 49 using a conformal deposition process. Excess portions of the dielectric material, the metallic material of the word line 546, the optional ferroelectric side interface dielectric layer 530, and the tubular ferroelectric dielectric layer 500 can be removed from above a horizontal plane including the top surface of the insulating cap layer 70 using a planarization process. The planarization process may include chemical mechanical planarization (CMP) and / or recess etching processes. Each remaining portion of the dielectric material constitutes a dielectric core 62.

[0268] The collection of all material portions filling the memory opening 49 constitutes the memory opening filling structure 358. The collection of all material portions filling the support opening 19 constitutes the support pillar structure 324. Each memory opening filling structure 358 and each support pillar structure 324 may include a vertical stack of a two-dimensional cylindrical electron gas channel 60, a tubular ferroelectric dielectric layer 500, an optional ferroelectric side interface dielectric layer 530, a word line 546, and an optional dielectric core 62.

[0269] refer to Figure 35A and Figure 35B Executable Figures 24A to 24B The processing steps are to form the contact-level dielectric layer 73 and the back-side trench 79.

[0270] refer to Figure 36 An isotropic etching process can be performed to selectively etch the source-level sacrificial layer 342 and the drain-level sacrificial layer 442 for the device isolation-level insulating layer 332 and the channel-level insulating layer 232. For example, if the source-level sacrificial layer 342 and the drain-level sacrificial layer 442 contain silicon nitride, if the device isolation-level insulating layer 332 contains undoped silicate glass, and if the channel-level insulating layer 232 contains doped silicate glass, a wet etching process using thermal phosphoric acid can be performed to etch the source-level sacrificial layer 342 and the drain-level sacrificial layer 442. Active stage back-side recesses (343, 443) are formed in the volume from which the source-level sacrificial layer 342 and the drain-level sacrificial layer 442 are removed. The active stage back side recess (343, 443) includes a source stage back side recess 343 formed in the volume from which the source stage sacrificial layer 342 is removed, and a drain stage back side recess 443 formed in the volume from which the drain stage sacrificial layer 442 is removed.

[0271] refer to Figure 37 Executable Figure 26A and Figure 26B The processing steps involve depositing at least one conductive material in the active stage backside recess (343, 443) and removing excess portions of the at least one conductive material from inside the backside trench 79 and above the contact stage dielectric layer 73. The at least one conductive material may include a metal nitride pad (346A, 446A) comprising a metal nitride material (such as TiN, TaN, and / or WN) and a metal filler portion (346B, 446B) comprising a metal filler material, which may comprise an elemental metal (such as W, Mo, Ru, Co, Cu, or any other transition metal) or an intermetallic alloy. A metal source layer 346 is formed in each source stage backside recess 343, and a metal drain layer 446 is formed in each drain stage backside recess 443. Each metal source layer 346 may include a source stage metal nitride pad 346A and a source stage metal filler portion 346B. Each metal drain layer 446 may include a drain-level metal nitride liner 446A and a drain-level metal filler portion 446B.

[0272] Each source-level sacrificial layer 342 and each drain-level sacrificial layer 442 may be replaced by a metal source layer and a metal drain layer, respectively. Each metal source layer 346 and each metal drain layer 446 may be directly formed on the annular horizontal surface of a corresponding subset of the two-dimensional cylindrical electron gas channel 60, the corresponding subset being directly located on one of the corresponding channel-level insulating layers 232. In one embodiment, each metal source layer 346 and each metal drain layer 446 may be directly formed on the annular horizontal surface of all two-dimensional cylindrical electron gas channels 60, the annular horizontal surface contacting the same channel-level insulating layer 232 between adjacent pairs of back-side trenches 79.

[0273] refer to Figure 38A and Figure 38B Dielectric material can be deposited in the back trench 79 to form dielectric wall structures 376. Contact via structures (588, 583, 585, 8P) can be formed through the contact-level dielectric layer 73 and optionally through the reverse stepped dielectric material portion 65. For example, word line contact via structure 588 can be formed through the contact-level dielectric layer 73 on each word line 546. Source contact via structure 583 can be formed on the metal source layer 346 through the contact-level dielectric layer 73 and through the reverse stepped dielectric material portion 65. Drain contact via structure 585 can be formed on the metal drain layer 446 through the contact-level dielectric layer 73 and through the reverse stepped dielectric material portion 65. Peripheral device contact via structure 8P can be formed directly on the corresponding node of the peripheral device through the reverse stepped dielectric material portion 65.

[0274] In an alternative embodiment, instead of replacing the source-level sacrificial layer 342 and drain-level sacrificial layer 442 with corresponding metal source layer 346 and metal drain layer 446, the power and drain layers (346, 446) are formed as a portion of the initial unit layer stack (232, 332, 346, 446). In this alternative embodiment, each power and drain layer may comprise a heavily doped polysilicon layer. If desired, a thinner (e.g., 1 nm to 2 nm thick) optional metal interface improvement layer may be formed in contact with the heavily doped polysilicon layer.

[0275] Each two-dimensional cylindrical electron gas channel 60 is located between and contacts a vertically adjacent pair of metal source layers 346 and metal drain layers 446. Each two-dimensional cylindrical electron gas channel 60 is controlled by a gate electrode, which includes an adjacent portion of a word line 546. The word lines 546 are independently controlled. A portion of the tubular ferroelectric dielectric layer 500 located adjacent to a set of two-dimensional cylindrical electron gas channels 60 can be independently programmed to provide a two-dimensional ferroelectric NOR array. The vertical stacking of two-dimensional ferroelectric NOR arrays located between adjacent pairs of dielectric wall structures 376 constitutes a three-dimensional ferroelectric NOR array.

[0276] Referring to all structures relating to the fifth exemplary structure of this disclosure, a memory device is provided, the memory device comprising at least one cell layer stack located above a substrate, wherein the cell layer stack includes a metal source layer 346, a channel-level insulating layer 232, a metal drain layer 446, and a device isolation insulating layer 332; a plurality of memory openings 49 extending vertically through the at least one cell layer stack (346, 232, 436, 332); and memory opening filling structures 358 located within a corresponding one of the plurality of memory openings 49, wherein each memory opening filling structure 358 includes a tubular ferroelectric dielectric layer 500 and at least one two-dimensional cylindrical electron gas channel 60 extending vertically between the metal source layer 346 and the metal drain layer 446 of the at least one cell layer stack (346, 232, 436, 332).

[0277] In one embodiment, each channel-level insulating layer 232 contacts the outer cylindrical sidewall of the corresponding two-dimensional cylindrical electron gas channel 60.

[0278] In one embodiment, the tubular ferroelectric dielectric layer 500 contacts the cylindrical surface of each metal source layer in the metal source layer 346 and the cylindrical surface of each metal drain layer in the metal drain layer 446.

[0279] In one embodiment, word lines 546 may be formed above the inner cylindrical sidewalls of tubular ferroelectric dielectric layers 500 within each memory opening 49. Word lines 546 may extend vertically through each metal source layer 346 and each metal drain layer 446 within at least one unit layer stack (346, 232, 436, 332).

[0280] In one embodiment, at least one cell layer stack (346,232,436,332) comprises a vertical stack of multiple cell layer stacks (346,232,436,332).

[0281] In one embodiment, each of at least one two-dimensional cylindrical electron gas channel 60 comprises a metal dichalcogenide channel.

[0282] In one embodiment, each of at least one two-dimensional cylindrical electron gas channel 60 has a lateral thickness ranging from one to five monolayers and includes a two-dimensional electron gas therein; and each of at least one two-dimensional cylindrical electron gas channel 60 includes a Mo 1-x W x S 2-y Se yThe material constitutes and / or is substantially composed of said material, wherein x is in the range of 0 to 1, and y is independent of x and is in the range of 0 to 2. In one embodiment, the tubular ferroelectric dielectric layer 500 includes a two-dimensional van der Waals ferroelectric material layer comprising a ferroelectric material selected from CuInP2S6, a-In2Se3, g-SbP, g-SbAs, or a group IV monochalcogenide material having the MX form, wherein M is selected from Ge, Sn, or Pb, and X is selected from S, Se, or Te.

[0283] refer to Figure 39 This illustration shows a first configuration of a sixth exemplary structure according to a tenth embodiment of the present disclosure. The sixth exemplary structure includes a semiconductor substrate 709, which includes a semiconductor material layer. The semiconductor material layer may comprise a single-crystal semiconductor material layer or a polycrystalline semiconductor material. The semiconductor substrate 709 may comprise at least one elemental semiconductor material, such as silicon, germanium, or a silicon-germanium alloy; or may comprise a compound semiconductor material, such as a III-V compound semiconductor material or a II-V compound semiconductor material.

[0284] A two-dimensional electron gas channel layer 60L may be formed on the top surface of the semiconductor substrate 709. The two-dimensional electron gas channel layer 60L may contain any of the materials used in the two-dimensional electron gas channel layer 60L described above, and may have the same thickness as the two-dimensional electron gas channel layer 60L described above.

[0285] A stack of layers, including a two-dimensional van der Waals ferroelectric material layer 740, an optional ferroelectric side interface dielectric layer 530, and a gate electrode material layer 746, can be sequentially deposited over a two-dimensional electron gas channel layer 60L and can be photolithographically patterned to form a gate stack. The two-dimensional van der Waals ferroelectric material layer 740 is formed on the two-dimensional electron gas channel 60. The two-dimensional van der Waals ferroelectric material layer 740 may have the same thickness and material composition as any of the two-dimensional van der Waals ferroelectric material layers described above. In one embodiment, the two-dimensional van der Waals ferroelectric material layer 740 comprises and / or is substantially composed of: a ferroelectric material selected from CuInP2S6, a-In2Se3, g-SbP, g-SbAs, or a group IV monochalcogenide material having the MX form, wherein M is selected from Ge, Sn, or Pb, and X is selected from S, Se, or Te.

[0286] The ferroelectric side interface dielectric layer 530 may have the same material composition and the same thickness as in the previously described embodiments. In one embodiment, the ferroelectric side interface dielectric layer 530 comprises and / or is substantially composed of hafnium aluminum oxide, hafnium oxide, or aluminum oxide, and contacts the two-dimensional van der Waals ferroelectric material layer 740 and the gate electrode 746.

[0287] The remaining patterned portion of the gate electrode material layer includes a gate electrode 746, which may contain a doped semiconductor material or at least one metal material, such as a metal nitride material (e.g., TiN, TaN, and / or WN); and / or at least one elemental metal or intermetallic alloy.

[0288] The gate electrode 746 can be used as a mask to implant dopant into the end portion of the two-dimensional electron gas channel layer 60L and the lower portion of the semiconductor substrate 709 to form source region 732 and drain region 738. Each of the source region 732 and drain region 738 may include a corresponding doped portion of the two-dimensional electron gas channel layer 60L and a doped portion of the semiconductor substrate 709. The portions of the two-dimensional electron gas channel layer 60L that do not belong to source region 732 or drain region 738 constitute the two-dimensional electron gas channel 60.

[0289] A planarized dielectric layer 760 comprising a dielectric material (such as silicon oxide and / or silicon nitride) may be deposited over the gate electrode 746 and may be planarized to provide a planar top surface. Contact via structures (782, 785, 788) may be formed through the planarized dielectric layer 760. The contact via structures (782, 785, 788) may include a source contact via structure 782 contacting the top surface of the source region 732, a drain contact via structure 788 contacting the top surface of the drain region 738, and a gate contact via structure 785 contacting the top surface of the gate electrode 746.

[0290] refer to Figure 40 This illustrates a second configuration of the sixth exemplary structure, which can be achieved by replacing the semiconductor substrate 701 with an insulating substrate 719. Figure 39 The first construction of the sixth exemplary structure shown is derived. In this case, the source region 732 and the drain region 738 can be confined within the two-dimensional electron gas channel layer 60L.

[0291] refer to Figure 41 The diagram illustrates a third configuration of the sixth exemplary structure, which can be achieved by forming a channel-side interface dielectric layer 522. Figure 40 The second construction of the sixth exemplary structure shown is derived. The channel-side interface dielectric layer 522 may have the same material composition and the same thickness as in the previously described embodiments. The channel-side interface dielectric layer 522 may comprise and / or may be substantially composed of: hafnium aluminum oxide, hafnium oxide, or aluminum oxide, and may contact the substrate (such as insulating substrate 719) and the two-dimensional electron gas channel 60.

[0292] refer to Figure 42The fourth configuration of the sixth exemplary structure can be derived from any of the first, second, and third configurations of the sixth exemplary structure by forming a plurality of gate stacks (740, 530, 746) arranged along the direction connecting the source region 732 and the drain region 738 instead of a single gate stack (740, 530, 746) above the two-dimensional electron gas channel 60. The gate electrode 746 can be independently controlled to provide a NAND ferroelectric memory string.

[0293] refer to Figure 43 The fifth configuration of the sixth exemplary structure can be derived from the first, second, and third configurations of the sixth exemplary structure by forming a plurality of gate stacks (740, 530, 746) arranged perpendicular to the direction connecting the source region 732 and the drain region 738, instead of a single gate stack (740, 530, 746) above the two-dimensional electron gas channel 60. The gate electrode 746 can be independently controlled to provide a NOR ferroelectric memory string. The two-dimensional electron gas channel 60 may include a plurality of channel regions (C1, C2, C3) connected in a parallel manner between the source region 732 and the drain region 738.

[0294] Referring to all the figures relating to the sixth exemplary structure, a memory device is provided, the memory device comprising: a two-dimensional electron gas channel 60 on a substrate; (709, 719); a source region 732 and a drain region 738 at the end portions of the two-dimensional electron gas channel 60; a two-dimensional van der Waals ferroelectric material layer 740 on the two-dimensional electron gas channel 60 and comprising a ferroelectric material selected from CuInP2S6, a-In2Se3, g-SbP, g-SbAs, or a group IV monochalcogenide material having the MX form, wherein M is selected from Ge, Sn, or Pb, and X is selected from S, Se, or Te; and at least one gate electrode 746 above the two-dimensional van der Waals ferroelectric material layer 740.

[0295] In one embodiment, the memory device includes a ferroelectric side interface dielectric layer 530 comprising hafnium oxide, hafnium oxide, or aluminum oxide, and contacting a two-dimensional van der Waals ferroelectric material layer 740 and at least one gate electrode 746.

[0296] In one embodiment, substrate 709 includes a semiconductor material layer; and source region 732 and drain region 738 include corresponding doped portions of semiconductor material layer 709. In another embodiment, substrate 719 includes a dielectric material.

[0297] In one embodiment, source region 732 and drain region 738 include corresponding portions of two-dimensional electron gas channel layer 60L, the corresponding portions containing the material of two-dimensional electron gas channel 60 and additionally containing dopant atoms; source contact via structure 782 contacts the top surface of source region 732; and drain contact via structure 788 contacts the top surface of drain region 738.

[0298] In one embodiment, at least one gate electrode 746 includes a plurality of gate electrodes 746, and the plurality of gate electrodes 746 are arranged along a direction connecting the source region 732 and the drain region 738 to provide a NAND memory device, or arranged along a direction perpendicular to the direction connecting the source region 732 and the drain region 738 to provide a NOR memory device.

[0299] Generally, compared to existing ferroelectric memory devices, the various embodiments of this disclosure provide ferroelectric memory devices with superior device characteristics. For example, the two-dimensional channel has an improved interface with the ferroelectric material, while having fewer or no dangling bonds. The improved interface quality increases device reliability. This interface is further improved if a two-dimensional van der Waals ferroelectric material is used. In addition, the smaller thickness of both the two-dimensional channel and the ferroelectric material improves device scalability, while the higher mobility of the two-dimensional channel generates higher cell currents, and thus results in better device performance.

[0300] While specific preferred embodiments have been mentioned above, it will be understood that this disclosure is not limited thereto. Those skilled in the art will appreciate that various modifications can be made to the disclosed embodiments, and such modifications are intended to fall within the scope of this disclosure. In cases where embodiments employing specific structures and / or constructions are shown in this disclosure, it should be understood that this disclosure can be practiced with any other functionally equivalent compatible structures and / or constructions, provided that such substitutions are not expressly prohibited or otherwise considered impossible by those skilled in the art. All publications, patent applications, and patents cited herein are incorporated herein by reference in their entirety.

Claims

1. A unitary three-dimensional memory device, comprising: an alternating stack of insulating layers and conductive layers over a substrate; a memory opening vertically extending through the alternating stack; a two-dimensional electron gas channel inside the memory opening; a dielectric core surrounded by the channel; and a plurality of ferroelectric memory elements between the channel and the conductive layers, wherein the two-dimensional electron gas channel comprises a metallic chalcogenide channel, wherein: the ferroelectric memory elements comprise portions of a tubular ferroelectric dielectric layer vertically extending through the conductive layers of the alternating stack; and the tubular ferroelectric dielectric layer comprises: a first ferroelectric dielectric layer having a first band gap energy; and a second dielectric layer having a second band gap energy greater than the first band gap energy and located between the first ferroelectric dielectric layer and the metallic chalcogenide channel.

2. The unitary three-dimensional memory device of claim 1, wherein: the first ferroelectric dielectric layer comprises a first hafnium aluminum oxide or hafnium zirconium aluminum oxide layer; and the second dielectric layer comprises a second hafnium aluminum oxide or hafnium zirconium aluminum oxide layer having a higher aluminum concentration than the first hafnium aluminum oxide or hafnium zirconium aluminum oxide layer.

3. The unitary three-dimensional memory device of claim 1, wherein the metallic chalcogenide channel has a thickness in a range from 1 monolayer to 5 monolayers and comprises the two-dimensional electron gas therein.

5. The unitary three-dimensional memory device of claim 1, wherein:

4. The unit three-dimensional memory device of claim 3, wherein the metal dichalcogenide channel comprises a material having Mo 1-x W x S 2-y Se y consisting of, wherein x is in a range of 0 to 1, and y is independent of x and in a range of 0 to 2. the substrate comprises a semiconductor material layer; and a bottom end of the metallic chalcogenide channel is electrically connected to the semiconductor material layer.

6. The unitary three-dimensional memory device of claim 1, further comprising a drain region contacting an upper end of the metallic chalcogenide channel.

7. The unitary three-dimensional memory device of claim 6, wherein the drain region comprises a ring-shaped doped metallic chalcogenide drain portion.

8. The unitary three-dimensional memory device of claim 6, the drain region comprises a doped semiconductor drain portion.

9. The unitary three-dimensional memory device of claim 6, wherein the drain region comprises a stack of a nickel layer, a nickel silicide layer, an N+ doped polysilicon layer, a titanium layer, and a gold layer, or a stack of a nickel layer and a gold layer.

10. A ferroelectric memory device, comprising: a two-dimensional electron gas channel; a gate electrode; and a ferroelectric element between the gate electrode and the two-dimensional electron gas channel, wherein the ferroelectric element comprises a two-dimensional van der Waals ferroelectric element.

11. The ferroelectric memory device of claim 10, wherein the ferroelectric element comprises a portion of a two-dimensional van der Waals ferroelectric material layer selected from CuInP2S6, a-In2Se3, g-SbP, g-SbAs, or a group IV monochalcogenide material having a formula MX, where M is selected from Ge, Sn, or Pb, and X is selected from S, Se, or Te.

12. A method of forming a unitary three-dimensional memory device, comprising: forming an alternating stack of insulating layers and spacer material layers over a substrate, wherein the spacer material layers are formed as or subsequently replaced by conductive layers; forming a memory opening through the alternating stack; ​ ​ forming a ferroelectric memory element at each level of the spacer material layers at a periphery of the memory opening; and forming a two-dimensional electron gas channel directly on the ferroelectric memory element in the memory opening, wherein the ferroelectric memory element comprises a two-dimensional van der Waals ferroelectric element.

13. A method of forming a single three-dimensional memory device, comprising: forming an alternating stack of insulating layers and spacer material layers over a substrate, wherein the spacer material layers are formed as, or are subsequently replaced by, electrically conductive layers; forming a memory opening through the alternating stack; forming a ferroelectric memory element at each level of the spacer material layers at a periphery of the memory opening; and forming a two-dimensional electron gas channel directly on the ferroelectric memory element in the memory opening, wherein: the two-dimensional electron gas channel comprises a metallic dichalcogenide channel having a thickness in a range from 1 monolayer to 5 monolayers, and includes a two-dimensional electron gas therein, and The metal dichalcogenide channel comprises a material having Mo 1-x W x S 2-y Se y comprising a material wherein x is in a range of 0 to 1 and y is independent of x and in a range of 0 to 2, wherein the metal dichalcogenide channel is formed by atomic layer deposition of a metal oxide layer comprising molybdenum oxide, tungsten oxide, or molybdenum tungsten oxide, followed by chalcogenization of the metal oxide layer.

14. A memory device, comprising: at least one unit layer stack over a substrate, wherein the at least one unit layer stack comprises a metallic source layer, a channel level insulating layer, a metallic drain layer, and a device isolation level insulating layer; a plurality of memory openings vertically extending through the at least one unit layer stack; and a memory opening fill structure within a respective one of the plurality of memory openings, wherein each of the memory opening fill structures comprises a tubular ferroelectric dielectric layer and at least one two-dimensional electron gas channel vertically extending between the metallic source layer and the metallic drain layer of the at least one unit layer stack.

15. The memory device of claim 14, wherein the channel level insulating layer contacts an outer cylindrical sidewall of a respective one of the at least one two-dimensional electron gas channel.

16. The memory device of claim 14, wherein the tubular ferroelectric dielectric layer contacts a cylindrical surface of the metallic source layer and a cylindrical surface of the metallic drain layer.

17. The memory device of claim 14, wherein each of the memory opening fill structures comprises a word line over an inner cylindrical sidewall of the tubular ferroelectric dielectric layer and vertically extending through each metallic source layer and each metallic drain layer within the at least one unit layer stack.

18. The memory device of claim 14, wherein the at least one unit layer stack comprises a vertical stack of a plurality of the at least one unit layer stack.

19. The memory device of claim 14, wherein the tubular ferroelectric dielectric layer comprises: a first ferroelectric dielectric layer having a first bandgap energy; and a second dielectric layer having a second bandgap energy greater than the first bandgap energy and located between the first ferroelectric dielectric layer and the two-dimensional electron gas channel.

20. The memory device of claim 19, wherein: the first ferroelectric dielectric layer comprises a first hafnium aluminum oxide or hafnium zirconium aluminum oxide layer; and the second dielectric layer comprises a second hafnium aluminum oxide or hafnium zirconium aluminum oxide layer having a higher aluminum concentration than the first hafnium aluminum oxide or hafnium zirconium aluminum oxide layer.

21. The memory device of claim 14, wherein the tubular ferroelectric dielectric layer comprises a two-dimensional van der Waals ferroelectric material layer comprising a ferroelectric material selected from CuInP2S6, a-In2Se3, g-SbP, g-SbAs, or a group-IV monochalcogenide material having the formula MX, where M is selected from Ge, Sn, or Pb, and X is selected from S, Se, or Te.

22. The memory device of claim 14, wherein the at least one two-dimensional electron gas channel comprises a metallic dichalcogenide channel.

23. The memory device of claim 22, wherein: the at least one two-dimensional electron gas channel has a lateral thickness in a range from 1 monolayer to 5 monolayers, and comprises the two-dimensional electron gas therein; and The at least one two-dimensional electron gas channel comprises a material having Mo 1-x W x S 2-y Se y comprising a material wherein x is in the range of 0 to 1 and y is independent of x and in the range of 0 to 2.

24. A memory device, comprising: a two-dimensional electron gas channel on a substrate; a source region and a drain region at terminal portions of the two-dimensional electron gas channel; a two-dimensional van der Waals ferroelectric material layer on the two-dimensional electron gas channel and comprising a ferroelectric material selected from CuInP2S6, a-In2Se3, g-SbP, g-SbAs, or a group-IV monochalcogenide material having the formula MX, where M is selected from Ge, Sn, or Pb, and X is selected from S, Se, or Te; and at least one gate electrode over the two-dimensional van der Waals ferroelectric material layer.

25. The memory device of claim 24, further comprising a channel-side interface dielectric layer comprising hafnium aluminum oxide, hafnium oxide, or aluminum oxide contacting the substrate and the two-dimensional electron gas channel.

26. The memory device of claim 24, further comprising a ferroelectric-side interface dielectric layer comprising hafnium aluminum oxide, hafnium oxide, or aluminum oxide contacting the two-dimensional van der Waals ferroelectric material layer and the at least one gate electrode.

27. The memory device of claim 24, wherein: the substrate comprises a semiconductor material layer; and the source region and the drain region comprise respective doped portions of the semiconductor material layer.

28. The memory device of claim 24, wherein: the source region and the drain region comprise respective portions of the two-dimensional electron gas channel layer, the respective portions comprising material of the two-dimensional electron gas channel and additionally comprising dopant atoms; a source contact via structure contacts a top surface of the source region; and a drain contact via structure contacts a top surface of the drain region.

29. The memory device of claim 24, wherein the at least one gate electrode comprises a plurality of gate electrodes arranged along a direction connecting the source region and the drain region to provide a NAND memory device, or along a direction perpendicular to the direction connecting the source region and the drain region to provide a NOR memory device.

30. A ferroelectric memory device, comprising: a channel; a gate electrode; a ferroelectric element between the gate electrode and the channel, wherein the ferroelectric element comprises a layer of a two-dimensional van der Waals ferroelectric material comprising a ferroelectric material selected from CuInP2S6, a-In2Se3, g-SbP, g-SbAs, or a Group IV monochalcogenide material having the formula MX, wherein M is selected from Ge, Sn, or Pb, and X is selected from S, Se, or Te; and a first interfacial dielectric layer between the ferroelectric element and the gate electrode.

31. The ferroelectric memory device of claim 30, wherein the first interfacial dielectric layer comprises hafnium aluminum oxide, hafnium oxide, or aluminum oxide.

32. The ferroelectric memory device of claim 30, wherein the memory device comprises a single three-dimensional memory device comprising: an alternating stack of insulating layers and conductive layers over a substrate, wherein the gate electrode comprises one of the conductive layers; a memory opening extending vertically through the alternating stack, wherein the channel comprises a two-dimensional electron gas channel inside the memory opening; a ferroelectric memory element between the channel and the conductive layer, wherein the ferroelectric element comprises one of the ferroelectric elements; and a dielectric core surrounded by the channel.

33. The ferroelectric memory device of claim 32, further comprising a second interfacial dielectric layer contacting the two-dimensional electron gas channel and the dielectric core, and comprising hafnium aluminum oxide, hafnium oxide, or aluminum oxide.

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