Pixel structure

Abstract

A pixel structure has a penetration area and a reflection area, comprising a substrate, a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, a flat layer, a pixel electrode and a reflection electrode. The first metal layer is arranged on the substrate and includes a plurality of first patterned areas and a first storage electrode. The first insulating layer is arranged on the substrate and covers the first metal layer. The second metal layer is arranged on the first insulating layer and includes a plurality of second patterned areas and a second storage electrode. The second insulating layer is arranged on the first insulating layer and covers the second metal layer. The flat layer is arranged on the second insulating layer. The pixel electrode is electrically connected to the second metal layer through a contact window penetrating the second insulating layer and the flat layer. The reflection electrode is arranged on the pixel electrode and includes a plurality of third patterned areas. The plurality of third patterned portions substantially correspond to the area where the plurality of first patterned areas and the plurality of second patterned areas overlap in the normal direction of the substrate to define a penetration area.

Description

Technical Field

[0001] The present invention relates to a pixel structure, and in particular to a pixel structure for a semi-transmissive display panel. Background Art

[0002] In the existing semi-transmissive display panel, the method of defining the transmission area is to select a specific area so that the reflective electrode, the first metal layer and the second metal layer are removed in this specific area; however, the first metal layer used to form the first storage electrode and the second metal layer used to form the second storage electrode will be removed due to this method of defining the transmission area, resulting in a reduction in their area. Therefore, this method of defining the transmission area will cause the storage capacitance in a pixel structure of the display panel to decrease, thereby reducing the voltage stability of the display panel. Summary of the invention

[0003] The present invention is directed to a pixel structure, wherein the storage capacitor of the pixel structure is enhanced to store a larger voltage, thereby having good electrical properties.

[0004] According to an embodiment of the present invention, the pixel structure has a penetration area and a reflection area, and includes a substrate, a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, a flat layer, a pixel electrode and a reflection electrode. The first metal layer is disposed on the substrate and includes a plurality of first patterned areas and a first storage electrode. The first insulating layer is disposed on the substrate and covers the first metal layer. The second metal layer is disposed on the first insulating layer and includes a plurality of second patterned areas and a second storage electrode. The second insulating layer is disposed on the first insulating layer and covers the second metal layer. The flat layer is disposed on the second insulating layer. The pixel electrode is disposed on the flat layer and is electrically connected to the second metal layer through a contact window that penetrates the second insulating layer and the flat layer. The reflection electrode is disposed on the pixel electrode and includes a plurality of third patterned areas. The plurality of third patterned portions substantially correspond to the area where the plurality of first patterned areas and the plurality of second patterned areas overlap in the normal direction of the substrate to define a penetration area.

[0005] In the pixel structure according to the embodiment of the present invention, the transmission area is defined by the reflective electrode.

[0006] In the pixel structure according to the embodiment of the present invention, the above-mentioned transmission area is defined by the first metal layer.

[0007] In the pixel structure according to the embodiment of the present invention, the above-mentioned transmission area is defined by the second metal layer.

[0008] In the pixel structure according to the embodiment of the present invention, the pixel structure further includes a third metal layer disposed between the second insulating layer and the planar layer, wherein the transmission area is defined by the third metal layer.

[0009] In the pixel structure according to the embodiment of the present invention, the transmission area is defined by the reflective electrode and the first metal layer.

[0010] In the pixel structure according to the embodiment of the present invention, the transmission area is defined by the reflective electrode and the second metal layer.

[0011] In the pixel structure according to the embodiment of the present invention, the transmission area is defined by the reflective electrode, the first metal layer, the second metal layer and the third metal layer.

[0012] In the pixel structure according to the embodiment of the present invention, the pixel structure has a first grayscale display area and a second grayscale display area. The first grayscale display area includes a first display block, and the second grayscale display area includes two second display blocks.

[0013] In the pixel structure according to an embodiment of the present invention, the first metal layer used as the first storage electrode when defining multiple first patterned areas has no other areas removed, and the second metal layer used as the second storage electrode when defining multiple second patterned areas has no other areas removed.

[0014] Based on the above, the pixel structure of the present invention does not reduce the area of ​​the first metal layer used to form the first storage electrode and the second metal layer used to form the second storage electrode as the penetration area by making the first metal layer used as the first storage electrode not have other areas removed when defining a plurality of first patterned areas, and the second metal layer used as the second storage electrode not have other areas removed when defining a plurality of second patterned areas. In this case, the storage capacitor in a pixel structure of the display panel of the present invention can be increased and can store a larger voltage, thereby having good electrical properties. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1A FIG. 1 is a schematic top view of a pixel structure according to a first embodiment of the present invention.

[0016] Figure 1B for Figure 1A Schematic diagram of the cross section along the section line AA'.

[0017] Figure 1C FIG. 1 is a schematic diagram of a transmission area and a reflection area of ​​a pixel structure according to a first embodiment of the present invention.

[0018] Figure 2A FIG. 1 is a schematic top view of a pixel structure according to a second embodiment of the present invention.

[0019] Figure 2B FIG. 1 is a schematic diagram of a transmissive region and a reflective region of a pixel structure according to a second embodiment of the present invention.

[0020] Figure 3A FIG. 4 is a schematic top view of a pixel structure according to a third embodiment of the present invention.

[0021] Figure 3B FIG. 1 is a schematic diagram of a transmissive region and a reflective region of a pixel structure according to a third embodiment of the present invention.

[0022] Figure 4A for Figure 3B A schematic cross-sectional view of the first embodiment along the section line BB' in FIG.

[0023] Figure 4B for Figure 3B A schematic cross-sectional view of the second embodiment along the section line BB' in FIG.

[0024] Figure 4C for Figure 3B A schematic cross-sectional view of the third embodiment along the section line BB' in FIG.

[0025] Figure 4D for Figure 3B A schematic cross-sectional view of the fourth embodiment along the section line BB' in FIG.

[0026] Figure 5A for Figure 3B FIG. 1 is an enlarged schematic diagram of the first embodiment of the area X in FIG.

[0027] Figure 5B for Figure 3B FIG. 1 is an enlarged schematic diagram of a second embodiment of an area X in FIG. 1 .

[0028] Figure 5C for Figure 3B FIG. 1 is an enlarged schematic diagram of a third embodiment of an area X in FIG.

[0029] Figure 5D for Figure 3B FIG. 4 is an enlarged schematic diagram of a fourth embodiment of an area X in FIG. DETAILED DESCRIPTION

[0030] The present invention will be described more fully below with reference to the drawings of the present embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thickness of the layers and regions in the drawings are exaggerated for clarity. The same or similar reference numbers represent the same or similar elements, and the following paragraphs will not be repeated one by one. In addition, the directional terms mentioned in the embodiments, such as: up, down, left, right, front or back, etc., are only referenced to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and not to limit the present invention.

[0031] Figure 1A FIG. 1 is a schematic top view of a pixel structure according to a first embodiment of the present invention. Figure 1B for Figure 1A Schematic diagram of the cross section along the section line AA'. Figure 1C FIG. 1 is a schematic diagram of a transmission area and a reflection area of ​​a pixel structure according to a first embodiment of the present invention.

[0032] Please also refer to Figure 1A , Figure 1B as well as Figure 1C The pixel structure 10 of the present embodiment includes a substrate SB, a first metal layer M1, a first insulating layer IL1, a second metal layer M2, a second insulating layer IL2, a pixel electrode PE, and a reflective electrode RE. The substrate SB is, for example, a flexible substrate, which may be a polymer substrate or a plastic substrate, but the present invention is not limited thereto. In other embodiments, the substrate SB may also be, for example, a rigid substrate, which may be a glass substrate, a quartz substrate, or a silicon substrate.

[0033] The first metal layer M1 is, for example, disposed on the substrate SB. The first metal layer M1 is formed, for example, by physical vapor deposition or metal chemical vapor deposition followed by a photolithography and etching process. For example, a first metal material layer (not shown) may be formed on the substrate SB by physical vapor deposition or metal chemical vapor deposition. Then, a patterned photoresist layer (not shown) is formed on the first metal material layer. Thereafter, the first metal material layer is etched using the patterned photoresist layer as a mask to form the first metal layer M1.

[0034] The first metal layer M1 may, for example, include a gate G, a scan line SL, a common electrode line CVL, and a first storage electrode SE1. The scan line SL and the common electrode line CVL extend, for example, in the first direction e1. The gate G is, for example, electrically connected to the corresponding scan line SL to receive a corresponding gate signal. The first storage electrode SE1 may, for example, form a storage capacitor Cst1 with the second metal layer M2 to be introduced later and the first insulating layer IL1 between the two. The common electrode line CVL may, for example, be used to supply a common voltage. The storage capacitor Cst1 may be electrically connected to the common electrode line CVL to receive the common voltage supplied via the common electrode line CVL.

[0035] In the present embodiment, the first metal layer M1 undergoes a lithography and etching process during its formation, so the first metal layer M1 after formation includes a plurality of first patterned portions P1. The plurality of first patterned portions P1 herein refers to portions of the first metal material layer that are etched away, that is, regions where none of the gate G, the scan line SL, the common electrode line CVL, and the first storage electrode SE1 is provided. It is worth mentioning that when the plurality of first patterned portions P1 are defined, no other regions of the first metal layer M1 used as the first storage electrode SE1 are removed, because the patterned portions of the subsequent reflective electrode RE will partially correspond to the plurality of first patterned portions P1 of the first metal layer M1, so that the present embodiment does not need to intentionally remove other regions of the first metal layer M1 used as the first storage electrode SE1.

[0036] The first insulating layer IL1 is, for example, disposed on the substrate SB and covers the first metal layer M1. That is, the first insulating layer IL1 may cover the gate G, the scan line SL, the common electrode line CVL, and the first storage electrode SE1. The first insulating layer IL1 may be formed by, for example, physical vapor deposition or chemical vapor deposition. In the present embodiment, the material of the first insulating layer IL1 may be an inorganic material (for example, silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), an organic material (for example, polyimide resin, epoxy resin, or acrylic resin), or a combination thereof, but the present invention is not limited thereto. The first insulating layer IL1 may be a single-layer structure, but the present invention is not limited thereto. In other embodiments, the first insulating layer IL1 may also be a multi-layer structure.

[0037] The second metal layer M2 is, for example, disposed on the first insulating layer IL1. The second metal layer M2 is formed by, for example, utilizing physical vapor deposition or metal chemical vapor deposition followed by a photolithography and etching process. For example, a second metal material layer (not shown) may be formed on the first insulating layer IL1 by physical vapor deposition or metal chemical vapor deposition. Then, a patterned photoresist layer (not shown) is formed on the second metal material layer. Thereafter, the second metal material layer is etched using the patterned photoresist layer as a mask to form the second metal layer M2.

[0038] The second metal layer M2 may include, for example, a data line DL, a source electrode S, a drain electrode D, and a second storage electrode SE2. The data line DL, for example, extends in a second direction e2 that is orthogonal to the first direction e1. The source electrode S, for example, is electrically connected to the corresponding data line DL to receive a corresponding data signal. The second storage electrode SE2, for example, forms a storage capacitor Cst1 with the first storage electrode SE1 and the first insulating layer IL1 between the first storage electrode SE1 and the second storage electrode SE2. The storage capacitor Cst1 may be used to store a voltage, and the magnitude of the stored voltage may affect the deflection state of the liquid crystal molecules (not shown).

[0039] In the present embodiment, the second metal layer M2 undergoes a lithography and etching process during its formation, so the formed second metal layer M2 includes a plurality of second patterned portions P2. The plurality of second patterned portions P2 here refer to the portions of the second metal material layer that are etched away, that is, the regions where the data line DL, the source S, the drain D, and any of the second storage electrodes SE2 are not provided. It is worth mentioning that when the plurality of second patterned portions P2 are defined, no other regions of the second metal layer M2 used as the second storage electrode SE2 are removed. The reason for this is that the patterned portions of the subsequent reflective electrode RE will partially correspond to the plurality of second patterned portions P2 of the second metal layer M2, so that the present embodiment does not need to intentionally remove other regions of the second metal layer M2 used as the second storage electrode SE2.

[0040] In one embodiment, the pixel structure 10 may further include a semiconductor layer CH. The semiconductor layer CH may be formed, for example, after the first insulating layer IL1 is formed. That is, the semiconductor layer CH is disposed on the first insulating layer IL1, for example.

[0041] The semiconductor layer CH is formed by, for example, a lithography and etching process. For example, a semiconductor material layer (not shown) may be formed on the first insulating layer IL1 by physical vapor deposition or metal chemical vapor deposition. Then, a patterned photoresist layer (not shown) is formed on the semiconductor material layer. Afterwards, the semiconductor material layer is etched using the patterned photoresist layer as a mask to form the semiconductor layer CH. The material of the semiconductor layer CH may be, for example, amorphous silicon, but the present invention is not limited thereto. The material of the semiconductor layer CH may also be, for example, polycrystalline silicon, microcrystalline silicon, single crystal silicon, nanocrystalline silicon or other semiconductor materials or metal oxide semiconductor materials with different lattice arrangements.

[0042] In the present embodiment, the gate G, the source S, the drain D and the semiconductor layer CH may constitute an active device T. The semiconductor layer CH may be, for example, arranged corresponding to the gate G and partially covered by the source S and the drain D. The semiconductor layer CH not covered by the source S and the drain D may serve as a channel layer of the active device T. The active device T may be, for example, any bottom gate thin film transistor known to those skilled in the art. However, although the present embodiment takes a bottom gate thin film transistor as an example, the present invention is not limited thereto. In other embodiments, the active device T may also be, for example, a top gate thin film transistor or other suitable types of thin film transistors.

[0043] The second insulating layer IL2 is, for example, disposed on the first insulating layer IL1 and covers the second metal layer M2. That is, the second insulating layer IL2 may cover the data line DL, the source electrode S, the drain electrode D, and the second storage electrode SE2. The second insulating layer IL2 may be formed by, for example, physical vapor deposition or chemical vapor deposition. In the present embodiment, the material of the second insulating layer IL2 may be an inorganic material (for example, silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), an organic material (for example, polyimide resin, epoxy resin, or acrylic resin), or a combination thereof, but the present invention is not limited thereto. The second insulating layer IL2 may be a single-layer structure, but the present invention is not limited thereto. In other embodiments, the second insulating layer IL2 may also be a multi-layer structure.

[0044] The planar layer PL is, for example, disposed on the second insulating layer IL2. The planar layer PL is formed, for example, by physical vapor deposition or chemical vapor deposition. In the present embodiment, the material of the planar layer PL may be an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stacked layer of at least two of the above materials), an organic material (e.g., a polyimide resin, an epoxy resin, or an acrylic resin), or a combination thereof, but the present invention is not limited thereto. The planar layer PL may be a single-layer structure, but the present invention is not limited thereto. In other embodiments, the planar layer PL may also be a multi-layer structure. The planar layer PL may allow the film layer subsequently formed thereon to have good stability.

[0045] The pixel electrode PE is, for example, disposed on the planar layer PL. The pixel electrode PE is formed, for example, by physical vapor deposition or metal chemical vapor deposition followed by a lithography and etching process. For example, a pixel electrode material layer (not shown) may be formed on the planar layer PL by physical vapor deposition or metal chemical vapor deposition. Next, a patterned photoresist layer (not shown) is formed on the pixel electrode material layer. Afterwards, the pixel electrode material layer is etched using the patterned photoresist layer as a mask to form the pixel electrode PE. The material of the pixel electrode PE may be, for example, a metal oxide conductive material (e.g., indium tin oxide, indium zinc oxide, aluminum tin oxide, aluminum zinc oxide, indium germanium zinc oxide). In one embodiment, the pixel electrode PE is electrically connected to the second metal layer M2 through a contact window H that penetrates the second insulating layer IL2 and the planar layer PL. In detail, the pixel electrode PE is, for example, electrically connected to the drain D of the active element T.

[0046] The reflective electrode RE is, for example, disposed on the pixel electrode PE. The reflective electrode RE is formed by, for example, using a physical vapor deposition method or a metal chemical vapor deposition method and then performing a lithography etching process. For example, a reflective electrode material layer (not shown) may be formed on the pixel electrode PE using a physical vapor deposition method or a metal chemical vapor deposition method. Then, a patterned photoresist layer (not shown) is formed on the reflective electrode material layer. Afterwards, the reflective electrode material layer is etched using the patterned photoresist layer as a mask to form the reflective electrode RE.

[0047] The reflective electrode RE can be formed of a metal material with a reflectivity of ≥ 90%. In this embodiment, the reflective electrode RE is made of aluminum, silver or an alloy thereof, but the present invention is not limited thereto. The reflective electrode RE is used to reflect ambient light or light from a backlight source.

[0048] In the present embodiment, the reflective electrode RE includes a plurality of third patterned portions P3, wherein the plurality of third patterned portions P3 are defined by an area where no metal layer (including at least the first metal layer M1 and the second metal layer M2) is provided, that is, they are defined by an area P12 where a plurality of first patterned areas P1 and a plurality of second patterned areas P2 overlap. In other words, the plurality of third patterned portions P3 of the reflective electrode RE substantially correspond to an area P12 where a plurality of first patterned areas P1 and a plurality of second patterned areas P2 overlap in the normal direction n of the substrate SB, so as to define a penetration region TR. For example, the plurality of third patterned portions P3 of the reflective electrode RE correspond only to the first insulating layer IL1, the second insulating layer IL2 and the planar layer PL in the normal direction n of the substrate SB. Therefore, the plurality of third patterned portions P3 of the reflective electrode RE can be used as the penetration region TR, and the reflective electrode RE itself is used as the reflection region RR. From another perspective, in the transmission region TR, for example, only an insulating layer (including at least the first insulating layer IL1, the second insulating layer IL2 and the planar layer PL) or a transparent electrode (including at least the pixel electrode PE) is disposed, so that the external ambient light or backlight source can pass through. In general, the location of the reflective electrode RE can define the reflective region RR and the transmission region TR.

[0049] Based on this, the pixel structure 10 of the present embodiment is configured such that the plurality of patterned portions P3 of the reflective electrode RE are substantially corresponding to the region where no metal layer is provided in the normal direction n of the substrate SB, so that the area of ​​the first metal layer M1 used to form the first storage electrode SE1 and the second metal layer M2 used to form the second storage electrode SE2 can be used as the transmission region TR without reducing the area. In this case, the storage capacitor in a pixel structure of the display panel of the present invention can be increased and can store a larger voltage, thereby having good electrical properties.

[0050] Figure 2A FIG. 1 is a schematic top view of a pixel structure according to a second embodiment of the present invention. Figure 2B Schematic diagram of the transmissive region and the reflective region of the pixel structure of the second embodiment of the present invention. It must be noted here that: Figure 2A as well as Figure 2B The illustrated embodiments each use Figure 1A as well as Figure 1C The component numbers and partial contents of the embodiments are the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. For the description of the omitted parts, please refer to the description and effects of the above embodiments, and the following embodiments will not be repeated. Figure 2A as well as Figure 2B For at least a portion of the description of the illustrated embodiments that is not omitted, please refer to the subsequent content.

[0051] Please also refer to Figure 2A as well as Figure 2B ,exist Figure 2A as well as Figure 2B In the illustrated embodiment, the pixel structure 20 has a first grayscale display area GS1 and a second grayscale display area GS2. Applying a voltage to the first grayscale display area GS1 or the second grayscale display area GS2 can drive the liquid crystal molecules (not shown) located on the first grayscale display area GS1 or the second grayscale display area GS2 to rotate. In detail, for example, by applying a voltage to the first grayscale display area GS1 or the second grayscale display area GS2, it can be determined whether the liquid crystal molecules corresponding to the first grayscale display area GS1 and the second grayscale display area GS2 are in a bright state (i.e., allowing light to pass through) or in a dark state (i.e., blocking light from passing through). Since the pixel structure 20 of the present embodiment has a first grayscale display area GS1 and a second grayscale display area GS2, the pixel structure 20 includes a first active element T1 and a second active element T2. In some embodiments, the first active device T1 is located on the substrate SB and includes a first gate G1, a first source S1, a first drain D1, and a first semiconductor layer SE1, and the second active device T2 is also located on the substrate SB and includes a second gate G2, a second source S2, a second drain D2, and a second semiconductor layer SE2. In some embodiments, the size of the first active device T1 may be larger than the size of the second active device T2, but the present invention is not limited thereto.

[0052] Figure 3A FIG. 4 is a schematic top view of a pixel structure according to a third embodiment of the present invention. Figure 3B Schematic diagram of the transmission area and the reflection area of ​​the pixel structure of the third embodiment of the present invention. It must be explained here that Figure 3A as well as Figure 3B The illustrated embodiments each use Figure 2A as well as Figure 2BThe component numbers and partial contents of the embodiments are the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. For the description of the omitted parts, please refer to the description and effects of the above embodiments, and the following embodiments will not be repeated. Figure 3A as well as Figure 3B For at least a portion of the description of the illustrated embodiments that is not omitted, please refer to the subsequent content.

[0053] Please also refer to Figure 3A as well as Figure 3B The pixel structure 30 of the present invention has a first grayscale display area GS1 including a first display block GS11 and a second grayscale display area GS2 including two second display blocks GS21 and GS22, so that the pixel structure 30 has three display blocks. The operation mode of the pixel structure 30 of the present embodiment is as follows: when the first active element T1 and the second active element T2 are turned on at the same time, the three display blocks (a first display block GS11 and two second display blocks GS21 and GS22) can be bright, when the first active element T1 is turned off and the second active element T2 is turned on, the two display blocks (two second display blocks GS21 and GS22) can be bright, when the first active element T1 is turned on and the second active element T2 is turned off, one display block (a first display block GS11) can be bright, and when the first active element T1 and the second active element T2 are turned off, the above three display blocks can be dark.

[0054] Figure 4A for Figure 3B A schematic cross-sectional view of the first embodiment along the section line BB' in FIG. Figure 4B for Figure 3B A schematic cross-sectional view of the second embodiment along the section line BB' in FIG. Figure 4C for Figure 3B A schematic cross-sectional view of the third embodiment along the section line BB' in FIG. Figure 4D for Figure 3B A schematic cross-sectional view of the fourth embodiment along the section line BB' in FIG.

[0055] In the embodiments of the present invention, the pixel structures 10, 20, and 30 are configured such that the plurality of patterned portions P3 of the reflective electrode RE substantially correspond to the region without any metal layer in the normal direction n of the substrate SB, so as to define the transmission region TR without reducing the area of ​​the first storage electrode SE1 and the second storage electrode SE2. However, the plurality of patterned portions P3 of the reflective electrode RE substantially correspond to the region without any metal layer, which does not exactly mean that the plurality of patterned portions P3 of the reflective electrode RE completely correspond to the region without any metal layer. That is, in some embodiments, the transmission region TR may be defined by a specific metal layer due to the design of the pixel structures 10, 20, and 30, wherein FIG. 4A to FIG. 4D The metal layer that defines the penetration region TR is shown in more detail. Figure 4A In FIG. 1 , the transmission region TR is defined by the reflective electrode RE. Figure 4B In FIG. 1 , the penetration region TR is defined by the first metal layer M1. Figure 4C In FIG. 1 , the penetration region TR is defined by the second metal layer M2. Figure 4D In the embodiment, the penetration region TR is defined by the third metal layer M3.

[0056] Figure 5A for Figure 3B FIG. 1 is an enlarged schematic diagram of the first embodiment of the area X in FIG. Figure 5B for Figure 3B FIG. 1 is an enlarged schematic diagram of a second embodiment of an area X in FIG. 1 . Figure 5C for Figure 3B FIG. 1 is an enlarged schematic diagram of a third embodiment of an area X in FIG. Figure 5D for Figure 3B FIG. 4 is an enlarged schematic diagram of a fourth embodiment of an area X in FIG.

[0057] Referring to the above-mentioned embodiments, the transmission region TR can be defined by a specific metal layer according to the design of the pixel structures 10, 20, and 30, wherein FIG. 5A to FIG. 5D The metal layer or layers that define the penetration region TR are shown in more detail. Figure 5A In FIG. 1 , the transmission region TR is defined by the reflective electrode RE. Figure 5B In FIG. 1 , the transmission region TR is defined by the reflective electrode RE and the first metal layer M1. Figure 5C In FIG. 1 , the transmission region TR is defined by the reflective electrode RE and the second metal layer M2. Figure 5D In the embodiment, the transmission region TR is defined by the reflective electrode RE, the first metal layer M1, the second metal layer M2 and the third metal layer M3.

[0058] In summary, the pixel structure of the present invention is defined by defining the plurality of third patterned portions of the reflective electrode by an area where no metal layer (at least including the first metal layer and the second metal layer) is provided, that is, it is defined by an area where a plurality of first patterned areas overlap with a plurality of second patterned areas. In other words, the plurality of third patterned portions of the reflective electrode substantially correspond to an area where a plurality of first patterned areas overlap with a plurality of second patterned areas in the normal direction of the substrate to define a penetration area. Based on this, the pixel structure of the present invention can be used as a penetration area without reducing the area of ​​the first metal layer used to form the first storage electrode and the area of ​​the second metal layer used to form the second storage electrode. In this case, the storage capacitor in a pixel structure of the display panel of the present invention can be increased and can store a larger voltage, thereby having good electrical properties.

[0059] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A pixel structure, characterized in that: It has penetrating and reflecting areas, including: substrate; A first metal layer, disposed on the substrate and comprising a plurality of first patterned regions and a first storage electrode; A first insulating layer, disposed on the substrate and covering the first metal layer; A second metal layer, disposed on the first insulating layer and comprising a plurality of second patterned regions and a second storage electrode; A second insulating layer, disposed on the first insulating layer and covering the second metal layer; A planar layer, disposed on the second insulating layer; a pixel electrode electrically connected to the second metal layer through a contact window penetrating the second insulating layer and the planar layer; and a reflective electrode, disposed on the pixel electrode and comprising a plurality of third patterned regions, wherein the plurality of third patterned regions correspond to regions overlapping the plurality of first patterned regions and the plurality of second patterned regions in the normal direction of the substrate to define the penetration region, When defining the plurality of first patterned regions, no other regions of the first metal layer used as the first storage electrode are removed, and when defining the plurality of second patterned regions, no other regions of the second metal layer used as the second storage electrode are removed.

2. The pixel structure according to claim 1, characterized in that: The transmission area is defined by the reflective electrode.

3. The pixel structure according to claim 1, characterized in that: The penetration region is defined by the first metal layer.

4. The pixel structure according to claim 1, characterized in that: The penetration region is defined by the second metal layer.

5. The pixel structure according to claim 1, characterized in that: The invention also includes a third metal layer disposed between the second insulating layer and the planar layer, wherein the penetration area is defined by the third metal layer.

6. The pixel structure according to claim 1, characterized in that: The transmission area is defined by the reflective electrode and the first metal layer.

7. The pixel structure according to claim 1, characterized in that: The transmission area is defined by the reflective electrode and the second metal layer.

8. The pixel structure according to claim 5, characterized in that: The transmission area is defined by the reflective electrode, the first metal layer, the second metal layer and the third metal layer.

9. The pixel structure according to claim 1, characterized in that: It also has a first grayscale display area and a second grayscale display area, wherein the first grayscale display area includes a first display block, and the second grayscale display area includes two second display blocks.

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